1 ;; GCC machine description for Matsushita MN10300
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
3 ;; 2007, 2008 Free Software Foundation, Inc.
4 ;; Contributed by Jeff Law (law@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
27 ;; Condition code settings.
28 ;; none - insn does not affect cc
29 ;; none_0hit - insn does not affect cc but it does modify operand 0
30 ;; This attribute is used to keep track of when operand 0 changes.
31 ;; See the description of NOTICE_UPDATE_CC for more info.
32 ;; set_znv - insn sets z,n,v to usable values; c is unusable.
33 ;; set_zn - insn sets z,n to usable values; v,c are unusable.
34 ;; compare - compare instruction
35 ;; clobber - value of cc is unknown
36 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
37 (const_string "clobber"))
51 (include "predicates.md")
52 (include "constraints.md")
54 ;; ----------------------------------------------------------------------
56 ;; ----------------------------------------------------------------------
60 (define_expand "movqi"
61 [(set (match_operand:QI 0 "general_operand" "")
62 (match_operand:QI 1 "general_operand" ""))]
66 /* One of the ops has to be in a register */
67 if (!register_operand (operand0, QImode)
68 && !register_operand (operand1, QImode))
69 operands[1] = copy_to_mode_reg (QImode, operand1);
73 [(set (match_operand:QI 0 "nonimmediate_operand" "=d*x*a*f,d*x,d*x*a,d*x*a,m,*f,d*x*a")
74 (match_operand:QI 1 "general_operand" "0,I,d*xai,m,d*xa,d*xa*f,*f"))]
76 && (register_operand (operands[0], QImode)
77 || register_operand (operands[1], QImode))"
80 switch (which_alternative)
87 if (GET_CODE (operands[1]) == CONST_DOUBLE)
90 xoperands[0] = operands[0];
91 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
92 output_asm_insn (\"mov %1,%0\", xoperands);
96 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
97 && GET_CODE (operands[1]) == CONST_INT)
99 HOST_WIDE_INT val = INTVAL (operands[1]);
101 if (((val & 0x80) && ! (val & 0xffffff00))
102 || ((val & 0x800000) && ! (val & 0xff000000)))
103 return \"movu %1,%0\";
105 return \"mov %1,%0\";
108 return \"movbu %1,%0\";
111 return \"fmov %1,%0\";
116 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
119 [(set (match_operand:QI 0 "nonimmediate_operand" "=d*a,d,d,!*a,d*a,d,m")
120 (match_operand:QI 1 "general_operand" "0,I,i,i,da,m,d"))]
121 "register_operand (operands[0], QImode)
122 || register_operand (operands[1], QImode)"
125 switch (which_alternative)
134 if (GET_CODE (operands[1]) == CONST_DOUBLE)
137 xoperands[0] = operands[0];
138 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
139 output_asm_insn (\"mov %1,%0\", xoperands);
143 return \"mov %1,%0\";
146 return \"movbu %1,%0\";
151 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
155 (define_expand "movhi"
156 [(set (match_operand:HI 0 "general_operand" "")
157 (match_operand:HI 1 "general_operand" ""))]
161 /* One of the ops has to be in a register */
162 if (!register_operand (operand1, HImode)
163 && !register_operand (operand0, HImode))
164 operands[1] = copy_to_mode_reg (HImode, operand1);
168 [(set (match_operand:HI 0 "nonimmediate_operand" "=d*x*a*f,d*x,d*x*a,d*x*a,m,*f,d*x*a")
169 (match_operand:HI 1 "general_operand" "0,I,d*x*ai,m,d*x*a,d*x*a*f,*f"))]
171 && (register_operand (operands[0], HImode)
172 || register_operand (operands[1], HImode))"
175 switch (which_alternative)
182 if (GET_CODE (operands[1]) == CONST_DOUBLE)
185 xoperands[0] = operands[0];
186 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
187 output_asm_insn (\"mov %1,%0\", xoperands);
191 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
192 && GET_CODE (operands[1]) == CONST_INT)
194 HOST_WIDE_INT val = INTVAL (operands[1]);
196 if (((val & 0x80) && ! (val & 0xffffff00))
197 || ((val & 0x800000) && ! (val & 0xff000000)))
198 return \"movu %1,%0\";
200 return \"mov %1,%0\";
203 return \"movhu %1,%0\";
206 return \"fmov %1,%0\";
211 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
214 [(set (match_operand:HI 0 "nonimmediate_operand" "=d*a,d,d,!*a,d*a,d,m")
215 (match_operand:HI 1 "general_operand" "0,I,i,i,da,m,d"))]
216 "register_operand (operands[0], HImode)
217 || register_operand (operands[1], HImode)"
220 switch (which_alternative)
229 if (GET_CODE (operands[1]) == CONST_DOUBLE)
232 xoperands[0] = operands[0];
233 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
234 output_asm_insn (\"mov %1,%0\", xoperands);
237 return \"mov %1,%0\";
240 return \"movhu %1,%0\";
245 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
249 ;; We use this to handle addition of two values when one operand is the
250 ;; stack pointer and the other is a memory reference of some kind. Reload
251 ;; does not handle them correctly without this expander.
252 (define_expand "reload_insi"
253 [(set (match_operand:SI 0 "register_operand" "=a")
254 (match_operand:SI 1 "impossible_plus_operand" ""))
255 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
259 if (XEXP (operands[1], 0) == stack_pointer_rtx)
261 if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
262 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
263 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
264 emit_move_insn (operands[2],
266 (GET_MODE (XEXP (operands[1], 1)),
267 SUBREG_REG (XEXP (operands[1], 1))));
269 emit_move_insn (operands[2], XEXP (operands[1], 1));
270 emit_move_insn (operands[0], XEXP (operands[1], 0));
274 if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
275 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
276 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
277 emit_move_insn (operands[2],
279 (GET_MODE (XEXP (operands[1], 0)),
280 SUBREG_REG (XEXP (operands[1], 0))));
282 emit_move_insn (operands[2], XEXP (operands[1], 0));
283 emit_move_insn (operands[0], XEXP (operands[1], 1));
285 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
289 (define_insn "pop_pic_reg"
290 [(set (reg:SI PIC_REG)
291 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
295 (define_expand "movsi"
296 [(set (match_operand:SI 0 "general_operand" "")
297 (match_operand:SI 1 "general_operand" ""))]
301 /* One of the ops has to be in a register */
302 if (!register_operand (operand1, SImode)
303 && !register_operand (operand0, SImode))
304 operands[1] = copy_to_mode_reg (SImode, operand1);
308 if (SYMBOLIC_CONST_P (operands[1]))
310 if (GET_CODE (operands[0]) == MEM)
311 operands[1] = force_reg (Pmode, operands[1]);
314 temp = (!can_create_pseudo_p ()
316 : gen_reg_rtx (Pmode));
317 operands[1] = legitimize_pic_address (operands[1], temp);
320 else if (GET_CODE (operands[1]) == CONST
321 && GET_CODE (XEXP (operands[1], 0)) == PLUS
322 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
324 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
325 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
327 operands[1] = expand_binop (SImode, add_optab, temp,
328 XEXP (XEXP (operands[1], 0), 1),
329 (!can_create_pseudo_p ()
331 : gen_reg_rtx (Pmode)),
338 [(set (match_operand:SI 0 "nonimmediate_operand"
339 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,!*y,*f,*f,dxaQ")
340 (match_operand:SI 1 "general_operand"
341 "0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,!*y,axR,0,dxaQi*f,*f"))]
342 "register_operand (operands[0], SImode)
343 || register_operand (operands[1], SImode)"
346 switch (which_alternative)
364 if (GET_CODE (operands[1]) == CONST_DOUBLE)
367 xoperands[0] = operands[0];
368 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
369 output_asm_insn (\"mov %1,%0\", xoperands);
373 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
374 && GET_CODE (operands[1]) == CONST_INT)
376 HOST_WIDE_INT val = INTVAL (operands[1]);
378 if (((val & 0x80) && ! (val & 0xffffff00))
379 || ((val & 0x800000) && ! (val & 0xff000000)))
380 return \"movu %1,%0\";
382 return \"mov %1,%0\";
387 return \"fmov %1,%0\";
392 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none,none_0hit,none_0hit")])
394 (define_expand "movsf"
395 [(set (match_operand:SF 0 "general_operand" "")
396 (match_operand:SF 1 "general_operand" ""))]
400 /* One of the ops has to be in a register */
401 if (!register_operand (operand1, SFmode)
402 && !register_operand (operand0, SFmode))
403 operands[1] = copy_to_mode_reg (SFmode, operand1);
407 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,dx,ax,dx,a,f,dxaQ,daxm,dax")
408 (match_operand:SF 1 "general_operand" "0,0,0,G,G,fdxaQF,f,dax,daxFm"))]
409 "register_operand (operands[0], SFmode)
410 || register_operand (operands[1], SFmode)"
413 switch (which_alternative)
424 return \"fmov %1, %0\";
428 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
429 && GET_CODE (operands[1]) == CONST_INT)
431 HOST_WIDE_INT val = INTVAL (operands[1]);
433 if (((val & 0x80) && ! (val & 0xffffff00))
434 || ((val & 0x800000) && ! (val & 0xff000000)))
435 return \"movu %1,%0\";
437 return \"mov %1,%0\";
442 [(set_attr "cc" "none,none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
444 (define_expand "movdi"
445 [(set (match_operand:DI 0 "general_operand" "")
446 (match_operand:DI 1 "general_operand" ""))]
450 /* One of the ops has to be in a register */
451 if (!register_operand (operand1, DImode)
452 && !register_operand (operand0, DImode))
453 operands[1] = copy_to_mode_reg (DImode, operand1);
457 [(set (match_operand:DI 0 "nonimmediate_operand"
458 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,*f,*f,*f,dxa,*f,Q")
459 (match_operand:DI 1 "general_operand"
460 "0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim,0,*f,dxai,*f,Q,*f"))]
461 "register_operand (operands[0], DImode)
462 || register_operand (operands[1], DImode)"
468 switch (which_alternative)
475 return \"clr %L0\;clr %H0\";
478 if (rtx_equal_p (operands[0], operands[1]))
479 return \"sub %L1,%L0\;mov %L0,%H0\";
481 return \"mov %1,%L0\;mov %L0,%H0\";
490 if (GET_CODE (operands[1]) == CONST_INT)
493 split_double (operands[1], &low, &high);
494 val[0] = INTVAL (low);
495 val[1] = INTVAL (high);
497 if (GET_CODE (operands[1]) == CONST_DOUBLE)
499 if (GET_MODE (operands[1]) == DFmode)
501 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
502 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
504 else if (GET_MODE (operands[1]) == VOIDmode
505 || GET_MODE (operands[1]) == DImode)
507 val[0] = CONST_DOUBLE_LOW (operands[1]);
508 val[1] = CONST_DOUBLE_HIGH (operands[1]);
512 if (GET_CODE (operands[1]) == MEM
513 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
515 rtx temp = operands[0];
517 while (GET_CODE (temp) == SUBREG)
518 temp = SUBREG_REG (temp);
520 gcc_assert (GET_CODE (temp) == REG);
522 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
523 XEXP (operands[1], 0)))
524 return \"mov %H1,%H0\;mov %L1,%L0\";
526 return \"mov %L1,%L0\;mov %H1,%H0\";
529 else if (GET_CODE (operands[1]) == MEM
530 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
531 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
535 xoperands[0] = operands[0];
536 xoperands[1] = XEXP (operands[1], 0);
538 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
544 if ((GET_CODE (operands[1]) == CONST_INT
545 || GET_CODE (operands[1]) == CONST_DOUBLE)
548 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
549 output_asm_insn (\"clr %L0\", operands);
551 output_asm_insn (\"mov %L1,%L0\", operands);
553 else if ((GET_CODE (operands[1]) == CONST_INT
554 || GET_CODE (operands[1]) == CONST_DOUBLE)
555 && (REGNO_REG_CLASS (true_regnum (operands[0]))
557 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
558 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
559 output_asm_insn (\"movu %L1,%L0\", operands);
561 output_asm_insn (\"mov %L1,%L0\", operands);
563 if ((GET_CODE (operands[1]) == CONST_INT
564 || GET_CODE (operands[1]) == CONST_DOUBLE)
567 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
568 output_asm_insn (\"clr %H0\", operands);
570 output_asm_insn (\"mov %H1,%H0\", operands);
572 else if ((GET_CODE (operands[1]) == CONST_INT
573 || GET_CODE (operands[1]) == CONST_DOUBLE)
575 output_asm_insn (\"mov %L0,%H0\", operands);
576 else if ((GET_CODE (operands[1]) == CONST_INT
577 || GET_CODE (operands[1]) == CONST_DOUBLE)
578 && (REGNO_REG_CLASS (true_regnum (operands[0]))
580 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
581 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
582 output_asm_insn (\"movu %H1,%H0\", operands);
584 output_asm_insn (\"mov %H1,%H0\", operands);
592 return \"fmov %L1, %L0\;fmov %H1, %H0\";
594 if (GET_CODE (operands[1]) == MEM
595 && GET_CODE (XEXP (operands[1], 0)) == CONST_INT
596 && (INTVAL (XEXP (operands[1], 0)) & 7) == 0)
597 return \"fmov %D1, %D0\";
599 return \"fmov %L1, %L0\;fmov %H1, %H0\";
601 if (GET_CODE (operands[0]) == MEM
602 && GET_CODE (XEXP (operands[0], 0)) == CONST_INT
603 && (INTVAL (XEXP (operands[0], 0)) & 7) == 0)
604 return \"fmov %D1, %D0\";
606 return \"fmov %L1, %L0\;fmov %H1, %H0\";
614 (ior (lt (symbol_ref "which_alternative") (const_int 2))
615 (eq (symbol_ref "which_alternative") (const_int 12))
616 ) (const_string "none")
617 (eq (symbol_ref "which_alternative") (const_int 2)
618 ) (const_string "clobber")
619 (eq (symbol_ref "which_alternative") (const_int 3)
621 (ne (symbol_ref "rtx_equal_p (operands[0], operands[1])")
622 (const_int 0)) (const_string "clobber")
623 (const_string "none_0hit"))
624 (ior (eq (symbol_ref "which_alternative") (const_int 8))
625 (eq (symbol_ref "which_alternative") (const_int 9))
627 (ne (symbol_ref "mn10300_wide_const_load_uses_clr
629 (const_int 0)) (const_string "clobber")
630 (const_string "none_0hit"))
631 ] (const_string "none_0hit")))])
633 (define_expand "movdf"
634 [(set (match_operand:DF 0 "general_operand" "")
635 (match_operand:DF 1 "general_operand" ""))]
639 /* One of the ops has to be in a register */
640 if (!register_operand (operand1, DFmode)
641 && !register_operand (operand0, DFmode))
642 operands[1] = copy_to_mode_reg (DFmode, operand1);
646 [(set (match_operand:DF 0 "nonimmediate_operand"
647 "=f,dx,ax,dx,f,f,dxa,f,Q,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
648 (match_operand:DF 1 "general_operand"
649 "0,0,0,G,f,dxaF,f,Q,f,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))]
650 "register_operand (operands[0], DFmode)
651 || register_operand (operands[1], DFmode)"
657 switch (which_alternative)
665 return \"clr %L0\;clr %H0\";
670 return \"fmov %L1, %L0\;fmov %H1, %H0\";
673 if (GET_CODE (operands[1]) == MEM
674 && GET_CODE (XEXP (operands[1], 0)) == CONST_INT
675 && (INTVAL (XEXP (operands[1], 0)) & 7) == 0)
676 return \"fmov %D1, %D0\";
678 return \"fmov %L1, %L0\;fmov %H1, %H0\";
681 if (GET_CODE (operands[0]) == MEM
682 && GET_CODE (XEXP (operands[0], 0)) == CONST_INT
683 && (INTVAL (XEXP (operands[0], 0)) & 7) == 0)
684 return \"fmov %D1, %D0\";
686 return \"fmov %L1, %L0\;fmov %H1, %H0\";
689 if (rtx_equal_p (operands[0], operands[1]))
690 return \"sub %L1,%L0\;mov %L0,%H0\";
692 return \"mov %1,%L0\;mov %L0,%H0\";
701 if (GET_CODE (operands[1]) == CONST_INT)
704 split_double (operands[1], &low, &high);
705 val[0] = INTVAL (low);
706 val[1] = INTVAL (high);
708 if (GET_CODE (operands[1]) == CONST_DOUBLE)
710 if (GET_MODE (operands[1]) == DFmode)
712 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
713 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
715 else if (GET_MODE (operands[1]) == VOIDmode
716 || GET_MODE (operands[1]) == DImode)
718 val[0] = CONST_DOUBLE_LOW (operands[1]);
719 val[1] = CONST_DOUBLE_HIGH (operands[1]);
723 if (GET_CODE (operands[1]) == MEM
724 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
726 rtx temp = operands[0];
728 while (GET_CODE (temp) == SUBREG)
729 temp = SUBREG_REG (temp);
731 gcc_assert (GET_CODE (temp) == REG);
733 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
734 XEXP (operands[1], 0)))
735 return \"mov %H1,%H0\;mov %L1,%L0\";
737 return \"mov %L1,%L0\;mov %H1,%H0\";
740 else if (GET_CODE (operands[1]) == MEM
741 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
742 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
746 xoperands[0] = operands[0];
747 xoperands[1] = XEXP (operands[1], 0);
749 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
755 if ((GET_CODE (operands[1]) == CONST_INT
756 || GET_CODE (operands[1]) == CONST_DOUBLE)
759 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
760 output_asm_insn (\"clr %L0\", operands);
762 output_asm_insn (\"mov %L1,%L0\", operands);
764 else if ((GET_CODE (operands[1]) == CONST_INT
765 || GET_CODE (operands[1]) == CONST_DOUBLE)
766 && (REGNO_REG_CLASS (true_regnum (operands[0]))
768 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
769 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
770 output_asm_insn (\"movu %L1,%L0\", operands);
772 output_asm_insn (\"mov %L1,%L0\", operands);
774 if ((GET_CODE (operands[1]) == CONST_INT
775 || GET_CODE (operands[1]) == CONST_DOUBLE)
778 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
779 output_asm_insn (\"clr %H0\", operands);
781 output_asm_insn (\"mov %H1,%H0\", operands);
783 else if ((GET_CODE (operands[1]) == CONST_INT
784 || GET_CODE (operands[1]) == CONST_DOUBLE)
786 output_asm_insn (\"mov %L0,%H0\", operands);
787 else if ((GET_CODE (operands[1]) == CONST_INT
788 || GET_CODE (operands[1]) == CONST_DOUBLE)
789 && (REGNO_REG_CLASS (true_regnum (operands[0]))
791 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
792 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
793 output_asm_insn (\"movu %H1,%H0\", operands);
795 output_asm_insn (\"mov %H1,%H0\", operands);
805 (lt (symbol_ref "which_alternative") (const_int 3)
806 ) (const_string "none")
807 (eq (symbol_ref "which_alternative") (const_int 3)
808 ) (const_string "clobber")
809 (eq (symbol_ref "which_alternative") (const_int 9)
811 (ne (symbol_ref "rtx_equal_p (operands[0], operands[1])")
812 (const_int 0)) (const_string "clobber")
813 (const_string "none_0hit"))
814 (ior (eq (symbol_ref "which_alternative") (const_int 14))
815 (eq (symbol_ref "which_alternative") (const_int 15))
817 (ne (symbol_ref "mn10300_wide_const_load_uses_clr
819 (const_int 0)) (const_string "clobber")
820 (const_string "none_0hit"))
821 ] (const_string "none_0hit")))])
825 ;; ----------------------------------------------------------------------
827 ;; ----------------------------------------------------------------------
829 ;; Go ahead and define tstsi so we can eliminate redundant tst insns
830 ;; when we start trying to optimize this port.
832 [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
834 "* return output_tst (operands[0], insn);"
835 [(set_attr "cc" "set_znv")])
838 [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a")))]
840 "* return output_tst (operands[0], insn);"
841 [(set_attr "cc" "set_znv")])
844 [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
846 "* return output_tst (operands[0], insn);"
847 [(set_attr "cc" "set_znv")])
850 [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a")))]
852 "* return output_tst (operands[0], insn);"
853 [(set_attr "cc" "set_znv")])
856 [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
858 "* return output_tst (operands[0], insn);"
859 [(set_attr "cc" "set_znv")])
861 ;; Ordinarily, the cmp instruction will set the Z bit of cc0 to 1 if
862 ;; its operands hold equal values, but the operands of a cmp
863 ;; instruction must be distinct registers. In the case where we'd
864 ;; like to compare a register to itself, we can achieve this effect
865 ;; with a btst 0,d0 instead. (This will not alter the contents of d0
866 ;; but will have the proper effect on cc0. Using d0 is arbitrary; any
867 ;; data register would work.)
869 ;; Even though the first alternative would be preferable if it can
870 ;; possibly match, reload must not be given the opportunity to attempt
871 ;; to use it. It assumes that such matches can only occur when one of
872 ;; the operands is used for input and the other for output. Since
873 ;; this is not the case, it abort()s. Indeed, such a reload cannot be
874 ;; possibly satisfied, so just mark the alternative with a `!', so
875 ;; that it is not considered by reload.
879 (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
880 (match_operand:SI 1 "nonmemory_operand" "*0,daxi")))]
885 [(set_attr "cc" "compare,compare")])
889 (compare (match_operand:SF 0 "register_operand" "f,f")
890 (match_operand:SF 1 "nonmemory_operand" "f,F")))]
893 [(set_attr "cc" "compare,compare")])
895 ;; ----------------------------------------------------------------------
897 ;; ----------------------------------------------------------------------
899 (define_expand "addsi3"
900 [(set (match_operand:SI 0 "register_operand" "")
901 (plus:SI (match_operand:SI 1 "register_operand" "")
902 (match_operand:SI 2 "nonmemory_operand" "")))]
907 [(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,!*y,!dax")
908 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax")
909 (match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))]
913 switch (which_alternative)
923 return \"add %2,%0\";
926 enum reg_class src1_class, src2_class, dst_class;
928 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
929 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
930 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
932 /* I'm not sure if this can happen or not. Might as well be prepared
933 and generate the best possible code if it does happen. */
934 if (true_regnum (operands[0]) == true_regnum (operands[1]))
935 return \"add %2,%0\";
936 if (true_regnum (operands[0]) == true_regnum (operands[2]))
937 return \"add %1,%0\";
939 /* Catch cases where no extended register was used. These should be
940 handled just like the mn10300. */
941 if (src1_class != EXTENDED_REGS
942 && src2_class != EXTENDED_REGS
943 && dst_class != EXTENDED_REGS)
945 /* We have to copy one of the sources into the destination, then
946 add the other source to the destination.
948 Carefully select which source to copy to the destination; a naive
949 implementation will waste a byte when the source classes are
950 different and the destination is an address register. Selecting
951 the lowest cost register copy will optimize this sequence. */
952 if (REGNO_REG_CLASS (true_regnum (operands[1]))
953 == REGNO_REG_CLASS (true_regnum (operands[0])))
954 return \"mov %1,%0\;add %2,%0\";
955 return \"mov %2,%0\;add %1,%0\";
958 /* At least one register is an extended register. */
960 /* The three operand add instruction on the am33 is a win iff the
961 output register is an extended register, or if both source
962 registers are extended registers. */
963 if (dst_class == EXTENDED_REGS
964 || src1_class == src2_class)
965 return \"add %2,%1,%0\";
967 /* It is better to copy one of the sources to the destination, then
968 perform a 2 address add. The destination in this case must be
969 an address or data register and one of the sources must be an
970 extended register and the remaining source must not be an extended
973 The best code for this case is to copy the extended reg to the
974 destination, then emit a two address add. */
975 if (src1_class == EXTENDED_REGS)
976 return \"mov %1,%0\;add %2,%0\";
977 return \"mov %2,%0\;add %1,%0\";
983 [(set_attr "cc" "set_zn,none_0hit,set_zn,none_0hit,set_zn,none_0hit,set_zn")])
986 [(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,!*y,!dax")
987 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
988 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
992 switch (which_alternative)
1001 return \"add %2,%0\";
1003 /* I'm not sure if this can happen or not. Might as well be prepared
1004 and generate the best possible code if it does happen. */
1005 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1006 return \"add %2,%0\";
1007 if (true_regnum (operands[0]) == true_regnum (operands[2]))
1008 return \"add %1,%0\";
1010 /* We have to copy one of the sources into the destination, then add
1011 the other source to the destination.
1013 Carefully select which source to copy to the destination; a naive
1014 implementation will waste a byte when the source classes are different
1015 and the destination is an address register. Selecting the lowest
1016 cost register copy will optimize this sequence. */
1017 if (REGNO_REG_CLASS (true_regnum (operands[1]))
1018 == REGNO_REG_CLASS (true_regnum (operands[0])))
1019 return \"mov %1,%0\;add %2,%0\";
1020 return \"mov %2,%0\;add %1,%0\";
1025 [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
1027 ;; ----------------------------------------------------------------------
1028 ;; SUBTRACT INSTRUCTIONS
1029 ;; ----------------------------------------------------------------------
1031 (define_expand "subsi3"
1032 [(set (match_operand:SI 0 "register_operand" "")
1033 (minus:SI (match_operand:SI 1 "register_operand" "")
1034 (match_operand:SI 2 "nonmemory_operand" "")))]
1039 [(set (match_operand:SI 0 "register_operand" "=dax,!dax")
1040 (minus:SI (match_operand:SI 1 "register_operand" "0,dax")
1041 (match_operand:SI 2 "nonmemory_operand" "daxi,dax")))]
1045 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1046 return \"sub %2,%0\";
1049 enum reg_class src1_class, src2_class, dst_class;
1051 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
1052 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
1053 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
1055 /* If no extended registers are used, then the best way to handle
1056 this is to copy the first source operand into the destination
1057 and emit a two address subtraction. */
1058 if (src1_class != EXTENDED_REGS
1059 && src2_class != EXTENDED_REGS
1060 && dst_class != EXTENDED_REGS
1061 && true_regnum (operands[0]) != true_regnum (operands[2]))
1062 return \"mov %1,%0\;sub %2,%0\";
1063 return \"sub %2,%1,%0\";
1066 [(set_attr "cc" "set_zn")])
1069 [(set (match_operand:SI 0 "register_operand" "=dax")
1070 (minus:SI (match_operand:SI 1 "register_operand" "0")
1071 (match_operand:SI 2 "nonmemory_operand" "daxi")))]
1074 [(set_attr "cc" "set_zn")])
1076 (define_expand "negsi2"
1077 [(set (match_operand:SI 0 "register_operand" "")
1078 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1082 rtx target = gen_reg_rtx (SImode);
1084 emit_move_insn (target, const0_rtx);
1085 emit_insn (gen_subsi3 (target, target, operands[1]));
1086 emit_move_insn (operands[0], target);
1090 ;; ----------------------------------------------------------------------
1091 ;; MULTIPLY INSTRUCTIONS
1092 ;; ----------------------------------------------------------------------
1094 (define_insn "mulsidi3"
1095 [(set (match_operand:DI 0 "register_operand" "=dax")
1096 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
1097 (sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
1100 [(set_attr "cc" "set_zn")])
1102 (define_insn "umulsidi3"
1103 [(set (match_operand:DI 0 "register_operand" "=dax")
1104 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
1105 (zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
1107 "mulu %1,%2,%H0,%L0"
1108 [(set_attr "cc" "set_zn")])
1110 (define_expand "mulsi3"
1111 [(set (match_operand:SI 0 "register_operand" "")
1112 (mult:SI (match_operand:SI 1 "register_operand" "")
1113 (match_operand:SI 2 "register_operand" "")))]
1118 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1119 (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
1120 (match_operand:SI 2 "nonmemory_operand" "dx,daxi")))]
1124 if (TARGET_MULT_BUG)
1125 return \"nop\;nop\;mul %2,%0\";
1127 return \"mul %2,%0\";
1129 [(set_attr "cc" "set_zn")])
1132 [(set (match_operand:SI 0 "register_operand" "=dx")
1133 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1134 (match_operand:SI 2 "register_operand" "dx")))]
1138 if (TARGET_MULT_BUG)
1139 return \"nop\;nop\;mul %2,%0\";
1141 return \"mul %2,%0\";
1143 [(set_attr "cc" "set_zn")])
1145 (define_insn "udivmodsi4"
1146 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
1147 (udiv:SI (match_operand:SI 1 "general_operand" "0")
1148 (match_operand:SI 2 "general_operand" "dx")))
1149 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
1150 (umod:SI (match_dup 1) (match_dup 2)))]
1154 output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
1156 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1157 return \"divu %2,%0\";
1159 return \"divu %2,%0\;mov mdr,%3\";
1161 [(set_attr "cc" "set_zn")])
1163 (define_insn "divmodsi4"
1164 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
1165 (div:SI (match_operand:SI 1 "general_operand" "0")
1166 (match_operand:SI 2 "general_operand" "dx")))
1167 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
1168 (mod:SI (match_dup 1) (match_dup 2)))]
1172 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1173 return \"ext %0\;div %2,%0\";
1175 return \"ext %0\;div %2,%0\;mov mdr,%3\";
1177 [(set_attr "cc" "set_zn")])
1180 ;; ----------------------------------------------------------------------
1182 ;; ----------------------------------------------------------------------
1184 (define_expand "andsi3"
1185 [(set (match_operand:SI 0 "register_operand" "")
1186 (and:SI (match_operand:SI 1 "register_operand" "")
1187 (match_operand:SI 2 "nonmemory_operand" "")))]
1192 [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
1193 (and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
1194 (match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))]
1198 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1199 return \"extbu %0\";
1200 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1201 return \"exthu %0\";
1202 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1203 return \"add %0,%0\;lsr 1,%0\";
1204 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1205 return \"asl2 %0\;lsr 2,%0\";
1206 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1207 return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1208 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1209 return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1210 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1211 return \"lsr 1,%0\;add %0,%0\";
1212 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1213 return \"lsr 2,%0\;asl2 %0\";
1214 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1215 return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1216 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1217 return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1218 if (REG_P (operands[2]) && REG_P (operands[1])
1219 && true_regnum (operands[0]) != true_regnum (operands[1])
1220 && true_regnum (operands[0]) != true_regnum (operands[2])
1221 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1222 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1223 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1224 return \"mov %1,%0\;and %2,%0\";
1225 if (REG_P (operands[2]) && REG_P (operands[1])
1226 && true_regnum (operands[0]) != true_regnum (operands[1])
1227 && true_regnum (operands[0]) != true_regnum (operands[2]))
1228 return \"and %1,%2,%0\";
1229 if (REG_P (operands[2]) && REG_P (operands[0])
1230 && true_regnum (operands[2]) == true_regnum (operands[0]))
1231 return \"and %1,%0\";
1232 return \"and %2,%0\";
1237 (eq (symbol_ref "which_alternative") (const_int 0)
1238 ) (const_string "none_0hit")
1239 (ne (symbol_ref "GET_CODE (operands[2]) == CONST_INT
1240 && (INTVAL (operands[2]) == 0x7fffffff
1241 || INTVAL (operands[2]) == 0x3fffffff
1242 || INTVAL (operands[2]) == 0x1fffffff
1243 || INTVAL (operands[2]) == 0x0fffffff
1244 || INTVAL (operands[2]) == 0xfffffffe
1245 || INTVAL (operands[2]) == 0xfffffffc
1246 || INTVAL (operands[2]) == 0xfffffff8
1247 || INTVAL (operands[2]) == 0xfffffff0)")
1248 (const_int 0)) (const_string "set_zn")
1249 ] (const_string "set_znv")))])
1252 [(set (match_operand:SI 0 "register_operand" "=dx,dx")
1253 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1254 (match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
1258 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1259 return \"extbu %0\";
1260 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1261 return \"exthu %0\";
1262 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1263 return \"add %0,%0\;lsr 1,%0\";
1264 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1265 return \"asl2 %0\;lsr 2,%0\";
1266 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1267 return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1268 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1269 return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1270 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1271 return \"lsr 1,%0\;add %0,%0\";
1272 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1273 return \"lsr 2,%0\;asl2 %0\";
1274 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1275 return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1276 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1277 return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1278 return \"and %2,%0\";
1283 (eq (symbol_ref "which_alternative") (const_int 0)
1284 ) (const_string "none_0hit")
1285 ;; Shifts don't set the V flag, but bitwise operations clear
1286 ;; it (which correctly reflects the absence of overflow in a
1287 ;; compare-with-zero that might follow). As for the
1288 ;; 0xfffffffe case, the add may overflow, so we can't use the
1290 (ne (symbol_ref "GET_CODE (operands[2]) == CONST_INT
1291 && (INTVAL (operands[2]) == 0x7fffffff
1292 || INTVAL (operands[2]) == 0x3fffffff
1293 || INTVAL (operands[2]) == 0x1fffffff
1294 || INTVAL (operands[2]) == 0x0fffffff
1295 || INTVAL (operands[2]) == 0xfffffffe
1296 || INTVAL (operands[2]) == 0xfffffffc
1297 || INTVAL (operands[2]) == 0xfffffff8
1298 || INTVAL (operands[2]) == 0xfffffff0)")
1299 (const_int 0)) (const_string "set_zn")
1300 ] (const_string "set_znv")))])
1302 ;; ----------------------------------------------------------------------
1304 ;; ----------------------------------------------------------------------
1306 (define_expand "iorsi3"
1307 [(set (match_operand:SI 0 "register_operand" "")
1308 (ior:SI (match_operand:SI 1 "register_operand" "")
1309 (match_operand:SI 2 "nonmemory_operand" "")))]
1314 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1315 (ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
1316 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1320 if (REG_P (operands[2]) && REG_P (operands[1])
1321 && true_regnum (operands[0]) != true_regnum (operands[1])
1322 && true_regnum (operands[0]) != true_regnum (operands[2])
1323 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1324 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1325 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1326 return \"mov %1,%0\;or %2,%0\";
1327 if (REG_P (operands[2]) && REG_P (operands[1])
1328 && true_regnum (operands[0]) != true_regnum (operands[1])
1329 && true_regnum (operands[0]) != true_regnum (operands[2]))
1330 return \"or %1,%2,%0\";
1331 if (REG_P (operands[2]) && REG_P (operands[0])
1332 && true_regnum (operands[2]) == true_regnum (operands[0]))
1333 return \"or %1,%0\";
1334 return \"or %2,%0\";
1336 [(set_attr "cc" "set_znv")])
1339 [(set (match_operand:SI 0 "register_operand" "=dx")
1340 (ior:SI (match_operand:SI 1 "register_operand" "%0")
1341 (match_operand:SI 2 "nonmemory_operand" "dxi")))]
1344 [(set_attr "cc" "set_znv")])
1346 ;; ----------------------------------------------------------------------
1348 ;; ----------------------------------------------------------------------
1350 (define_expand "xorsi3"
1351 [(set (match_operand:SI 0 "register_operand" "")
1352 (xor:SI (match_operand:SI 1 "register_operand" "")
1353 (match_operand:SI 2 "nonmemory_operand" "")))]
1358 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1359 (xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
1360 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1364 if (REG_P (operands[2]) && REG_P (operands[1])
1365 && true_regnum (operands[0]) != true_regnum (operands[1])
1366 && true_regnum (operands[0]) != true_regnum (operands[2])
1367 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1368 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1369 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1370 return \"mov %1,%0\;xor %2,%0\";
1371 if (REG_P (operands[2]) && REG_P (operands[1])
1372 && true_regnum (operands[0]) != true_regnum (operands[1])
1373 && true_regnum (operands[0]) != true_regnum (operands[2]))
1374 return \"xor %1,%2,%0\";
1375 if (REG_P (operands[2]) && REG_P (operands[0])
1376 && true_regnum (operands[2]) == true_regnum (operands[0]))
1377 return \"xor %1,%0\";
1378 return \"xor %2,%0\";
1380 [(set_attr "cc" "set_znv")])
1383 [(set (match_operand:SI 0 "register_operand" "=dx")
1384 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1385 (match_operand:SI 2 "nonmemory_operand" "dxi")))]
1388 [(set_attr "cc" "set_znv")])
1390 ;; ----------------------------------------------------------------------
1392 ;; ----------------------------------------------------------------------
1394 (define_expand "one_cmplsi2"
1395 [(set (match_operand:SI 0 "register_operand" "")
1396 (not:SI (match_operand:SI 1 "register_operand" "")))]
1401 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1402 (not:SI (match_operand:SI 1 "register_operand" "0,0")))]
1405 [(set_attr "cc" "set_znv")])
1408 [(set (match_operand:SI 0 "register_operand" "=dx")
1409 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1412 [(set_attr "cc" "set_znv")])
1414 ;; -----------------------------------------------------------------
1416 ;; -----------------------------------------------------------------
1419 ;; These set/clear memory in byte sized chunks.
1421 ;; They are no smaller/faster than loading the value into a register
1422 ;; and storing the register, but they don't need a scratch register
1423 ;; which may allow for better code generation.
1425 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int 0))]
1430 [(set_attr "cc" "clobber")])
1433 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1))]
1438 [(set_attr "cc" "clobber,none_0hit")])
1441 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1443 (and:SI (subreg:SI (match_dup 0) 0)
1444 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1449 [(set_attr "cc" "clobber,set_znv")])
1452 [(set (match_operand:QI 0 "memory_operand" "=R,T")
1455 (not:QI (match_operand:QI 1 "nonmemory_operand" "i,d"))))]
1460 [(set_attr "cc" "clobber,clobber")])
1463 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1465 (ior:SI (subreg:SI (match_dup 0) 0)
1466 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1471 [(set_attr "cc" "clobber,set_znv")])
1473 (define_expand "iorqi3"
1474 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1475 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
1476 (match_operand:QI 2 "nonmemory_operand" "")))]
1481 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,r")
1482 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
1483 ;; This constraint should really be nonmemory_operand,
1484 ;; but making it general_operand, along with the
1485 ;; condition that not both input operands are MEMs, it
1486 ;; here helps combine do a better job.
1487 (match_operand:QI 2 "general_operand" "i,d,ir")))]
1489 (GET_CODE (operands[2]) != MEM || GET_CODE (operands[1]) != MEM)"
1494 [(set_attr "cc" "clobber,clobber,set_znv")])
1497 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d")
1498 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
1499 ;; This constraint should really be nonmemory_operand,
1500 ;; but making it general_operand, along with the
1501 ;; condition that not both input operands are MEMs, it
1502 ;; here helps combine do a better job.
1503 (match_operand:QI 2 "general_operand" "i,d,id")))]
1504 "GET_CODE (operands[2]) != MEM || GET_CODE (operands[1]) != MEM"
1509 [(set_attr "cc" "clobber,clobber,set_znv")])
1513 (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
1514 (match_operand 1 "const_int_operand" "")
1515 (match_operand 2 "const_int_operand" "")))]
1519 int len = INTVAL (operands[1]);
1520 int bit = INTVAL (operands[2]);
1531 xoperands[0] = operands[0];
1532 xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1533 output_asm_insn (\"btst %1,%0\", xoperands);
1536 [(set_attr "cc" "clobber")])
1540 (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
1541 (match_operand 1 "const_int_operand" "")
1542 (match_operand 2 "const_int_operand" "")))]
1543 "mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
1546 int len = INTVAL (operands[1]);
1547 int bit = INTVAL (operands[2]);
1558 /* If the source operand is not a reg (i.e. it is memory), then extract the
1559 bits from mask that we actually want to test. Note that the mask will
1560 never cross a byte boundary. */
1561 if (!REG_P (operands[0]))
1565 else if (mask & 0xff00)
1566 mask = (mask >> 8) & 0xff;
1567 else if (mask & 0xff0000)
1568 mask = (mask >> 16) & 0xff;
1569 else if (mask & 0xff000000)
1570 mask = (mask >> 24) & 0xff;
1573 xoperands[0] = operands[0];
1574 xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1575 if (GET_CODE (operands[0]) == REG)
1576 output_asm_insn (\"btst %1,%0\", xoperands);
1578 output_asm_insn (\"btst %U1,%A0\", xoperands);
1581 [(set_attr "cc" "clobber")])
1584 [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
1585 (match_operand:SI 1 "const_int_operand" "")))]
1588 [(set_attr "cc" "clobber")])
1593 (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
1594 (match_operand:SI 1 "const_8bit_operand" "")))]
1599 [(set_attr "cc" "clobber")])
1602 ;; ----------------------------------------------------------------------
1603 ;; JUMP INSTRUCTIONS
1604 ;; ----------------------------------------------------------------------
1606 ;; Conditional jump instructions
1608 (define_expand "ble"
1610 (if_then_else (le (cc0)
1612 (label_ref (match_operand 0 "" ""))
1617 (define_expand "bleu"
1619 (if_then_else (leu (cc0)
1621 (label_ref (match_operand 0 "" ""))
1626 (define_expand "bge"
1628 (if_then_else (ge (cc0)
1630 (label_ref (match_operand 0 "" ""))
1635 (define_expand "bgeu"
1637 (if_then_else (geu (cc0)
1639 (label_ref (match_operand 0 "" ""))
1644 (define_expand "blt"
1646 (if_then_else (lt (cc0)
1648 (label_ref (match_operand 0 "" ""))
1653 (define_expand "bltu"
1655 (if_then_else (ltu (cc0)
1657 (label_ref (match_operand 0 "" ""))
1662 (define_expand "bgt"
1664 (if_then_else (gt (cc0)
1666 (label_ref (match_operand 0 "" ""))
1671 (define_expand "bgtu"
1673 (if_then_else (gtu (cc0)
1675 (label_ref (match_operand 0 "" ""))
1680 (define_expand "beq"
1682 (if_then_else (eq (cc0)
1684 (label_ref (match_operand 0 "" ""))
1689 (define_expand "bne"
1691 (if_then_else (ne (cc0)
1693 (label_ref (match_operand 0 "" ""))
1700 (if_then_else (match_operator 1 "comparison_operator"
1701 [(cc0) (const_int 0)])
1702 (label_ref (match_operand 0 "" ""))
1707 if (cc_status.mdep.fpCC)
1708 return \"fb%b1 %0\";
1709 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1710 && (GET_CODE (operands[1]) == GT
1711 || GET_CODE (operands[1]) == GE
1712 || GET_CODE (operands[1]) == LE
1713 || GET_CODE (operands[1]) == LT))
1717 [(set_attr "cc" "none")])
1721 (if_then_else (match_operator 1 "comparison_operator"
1722 [(cc0) (const_int 0)])
1724 (label_ref (match_operand 0 "" ""))))]
1728 if (cc_status.mdep.fpCC)
1729 return \"fb%B1 %0\";
1730 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1731 && (GET_CODE (operands[1]) == GT
1732 || GET_CODE (operands[1]) == GE
1733 || GET_CODE (operands[1]) == LE
1734 || GET_CODE (operands[1]) == LT))
1738 [(set_attr "cc" "none")])
1740 ;; Unconditional and other jump instructions.
1744 (label_ref (match_operand 0 "" "")))]
1747 [(set_attr "cc" "none")])
1749 (define_insn "indirect_jump"
1750 [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1753 [(set_attr "cc" "none")])
1755 (define_expand "builtin_setjmp_receiver"
1756 [(match_operand 0 "" "")]
1761 emit_insn (gen_GOTaddr2picreg ());
1766 (define_expand "casesi"
1767 [(match_operand:SI 0 "register_operand" "")
1768 (match_operand:SI 1 "immediate_operand" "")
1769 (match_operand:SI 2 "immediate_operand" "")
1770 (match_operand 3 "" "") (match_operand 4 "" "")]
1774 rtx table = gen_reg_rtx (SImode);
1775 rtx index = gen_reg_rtx (SImode);
1776 rtx addr = gen_reg_rtx (Pmode);
1778 emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
1779 emit_move_insn (index, plus_constant (operands[0], - INTVAL (operands[1])));
1780 emit_insn (gen_cmpsi (index, operands[2]));
1781 emit_jump_insn (gen_bgtu (operands[4]));
1782 emit_move_insn (index, gen_rtx_ASHIFT (SImode, index, const2_rtx));
1783 emit_move_insn (addr, gen_rtx_MEM (SImode,
1784 gen_rtx_PLUS (SImode, table, index)));
1786 emit_move_insn (addr, gen_rtx_PLUS (SImode, addr, table));
1788 emit_jump_insn (gen_tablejump (addr, operands[3]));
1792 (define_insn "tablejump"
1793 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1794 (use (label_ref (match_operand 1 "" "")))]
1797 [(set_attr "cc" "none")])
1799 ;; Call subroutine with no return value.
1801 (define_expand "call"
1802 [(call (match_operand:QI 0 "general_operand" "")
1803 (match_operand:SI 1 "general_operand" ""))]
1807 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
1809 if (MN10300_GLOBAL_P (XEXP (operands[0], 0)))
1811 /* The PLT code won't run on AM30, but then, there's no
1812 shared library support for AM30 either, so we just assume
1813 the linker is going to adjust all @PLT relocs to the
1815 emit_use (pic_offset_table_rtx);
1816 XEXP (operands[0], 0) = gen_sym2PLT (XEXP (operands[0], 0));
1819 XEXP (operands[0], 0) = gen_sym2PIC (XEXP (operands[0], 0));
1821 if (! call_address_operand (XEXP (operands[0], 0), VOIDmode))
1822 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1823 emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
1827 ;; NB: Mode on match_operand 0 deliberately omitted in
1828 ;; order to be able to match UNSPECs in PIC mode.
1829 (define_insn "call_internal"
1830 [(call (mem:QI (match_operand 0 "call_address_operand" "aS"))
1831 (match_operand:SI 1 "general_operand" "g"))]
1835 if (REG_P (operands[0]))
1836 return \"calls %C0\";
1838 return \"call %C0,[],0\";
1840 [(set_attr "cc" "clobber")])
1842 ;; Call subroutine, returning value in operand 0
1843 ;; (which must be a hard register).
1845 (define_expand "call_value"
1846 [(set (match_operand 0 "" "")
1847 (call (match_operand:QI 1 "general_operand" "")
1848 (match_operand:SI 2 "general_operand" "")))]
1852 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
1854 if (MN10300_GLOBAL_P (XEXP (operands[1], 0)))
1856 /* The PLT code won't run on AM30, but then, there's no
1857 shared library support for AM30 either, so we just assume
1858 the linker is going to adjust all @PLT relocs to the
1860 emit_use (pic_offset_table_rtx);
1861 XEXP (operands[1], 0) = gen_sym2PLT (XEXP (operands[1], 0));
1864 XEXP (operands[1], 0) = gen_sym2PIC (XEXP (operands[1], 0));
1866 if (! call_address_operand (XEXP (operands[1], 0), VOIDmode))
1867 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1868 emit_call_insn (gen_call_value_internal (operands[0],
1869 XEXP (operands[1], 0),
1874 ;; NB: Mode on match_operands 0 and 1 deliberately omitted
1875 ;; in order to be able to match UNSPECs in PIC mode.
1876 (define_insn "call_value_internal"
1877 [(set (match_operand 0 "register_operand" "=dax")
1878 (call (mem:QI (match_operand 1 "call_address_operand" "aS"))
1879 (match_operand:SI 2 "general_operand" "g")))]
1883 if (REG_P (operands[1]))
1884 return \"calls %C1\";
1886 return \"call %C1,[],0\";
1888 [(set_attr "cc" "clobber")])
1890 (define_expand "untyped_call"
1891 [(parallel [(call (match_operand 0 "" "")
1893 (match_operand 1 "" "")
1894 (match_operand 2 "" "")])]
1900 emit_call_insn (gen_call (operands[0], const0_rtx));
1902 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1904 rtx set = XVECEXP (operands[2], 0, i);
1905 emit_move_insn (SET_DEST (set), SET_SRC (set));
1914 [(set_attr "cc" "none")])
1916 ;; ----------------------------------------------------------------------
1917 ;; EXTEND INSTRUCTIONS
1918 ;; ----------------------------------------------------------------------
1920 (define_expand "zero_extendqisi2"
1921 [(set (match_operand:SI 0 "general_operand" "")
1923 (match_operand:QI 1 "general_operand" "")))]
1928 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1930 (match_operand:QI 1 "general_operand" "0,dax,m,0,dax,m")))]
1939 [(set_attr "cc" "none_0hit")])
1942 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1944 (match_operand:QI 1 "general_operand" "0,d,m")))]
1950 [(set_attr "cc" "none_0hit")])
1952 (define_expand "zero_extendhisi2"
1953 [(set (match_operand:SI 0 "general_operand" "")
1955 (match_operand:HI 1 "general_operand" "")))]
1960 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1962 (match_operand:HI 1 "general_operand" "0,dax,m,0,dax,m")))]
1971 [(set_attr "cc" "none_0hit")])
1974 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1976 (match_operand:HI 1 "general_operand" "0,dx,m")))]
1982 [(set_attr "cc" "none_0hit")])
1984 ;;- sign extension instructions
1986 (define_expand "extendqisi2"
1987 [(set (match_operand:SI 0 "general_operand" "")
1989 (match_operand:QI 1 "general_operand" "")))]
1994 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
1996 (match_operand:QI 1 "general_operand" "0,dx,0,dax")))]
2003 [(set_attr "cc" "none_0hit")])
2006 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
2008 (match_operand:QI 1 "general_operand" "0,dx")))]
2013 [(set_attr "cc" "none_0hit")])
2015 (define_expand "extendhisi2"
2016 [(set (match_operand:SI 0 "general_operand" "")
2018 (match_operand:HI 1 "general_operand" "")))]
2023 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
2025 (match_operand:HI 1 "general_operand" "0,dax,0,dax")))]
2032 [(set_attr "cc" "none_0hit")])
2035 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
2037 (match_operand:HI 1 "general_operand" "0,dx")))]
2042 [(set_attr "cc" "none_0hit")])
2044 ;; ----------------------------------------------------------------------
2046 ;; ----------------------------------------------------------------------
2048 (define_expand "ashlsi3"
2049 [(set (match_operand:SI 0 "register_operand" "")
2051 (match_operand:SI 1 "register_operand" "")
2052 (match_operand:QI 2 "nonmemory_operand" "")))]
2057 [(set (match_operand:SI 0 "register_operand" "=dax,dx,!dax")
2059 (match_operand:SI 1 "register_operand" "0,0,dax")
2060 (match_operand:QI 2 "nonmemory_operand" "J,dxi,dax")))]
2064 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1)
2065 return \"add %0,%0\";
2067 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 2)
2070 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 3
2071 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
2072 return \"asl2 %0\;add %0,%0\";
2074 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 4
2075 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
2076 return \"asl2 %0\;asl2 %0\";
2078 if (true_regnum (operands[1]) == true_regnum (operands[0]))
2079 return \"asl %S2,%0\";
2081 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
2082 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
2083 && true_regnum (operands[0]) != true_regnum (operands[2]))
2084 return \"mov %1,%0\;asl %S2,%0\";
2085 return \"asl %2,%1,%0\";
2087 [(set_attr "cc" "set_zn")])
2090 [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
2092 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
2093 (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))]
2101 [(set_attr "cc" "set_zn")])
2103 (define_expand "lshrsi3"
2104 [(set (match_operand:SI 0 "register_operand" "")
2106 (match_operand:SI 1 "register_operand" "")
2107 (match_operand:QI 2 "nonmemory_operand" "")))]
2112 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
2114 (match_operand:SI 1 "register_operand" "0,dax")
2115 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
2119 if (true_regnum (operands[1]) == true_regnum (operands[0]))
2120 return \"lsr %S2,%0\";
2122 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
2123 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
2124 && true_regnum (operands[0]) != true_regnum (operands[2]))
2125 return \"mov %1,%0\;lsr %S2,%0\";
2126 return \"lsr %2,%1,%0\";
2128 [(set_attr "cc" "set_zn")])
2131 [(set (match_operand:SI 0 "register_operand" "=dx")
2133 (match_operand:SI 1 "register_operand" "0")
2134 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
2137 [(set_attr "cc" "set_zn")])
2139 (define_expand "ashrsi3"
2140 [(set (match_operand:SI 0 "register_operand" "")
2142 (match_operand:SI 1 "register_operand" "")
2143 (match_operand:QI 2 "nonmemory_operand" "")))]
2148 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
2150 (match_operand:SI 1 "register_operand" "0,dax")
2151 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
2155 if (true_regnum (operands[1]) == true_regnum (operands[0]))
2156 return \"asr %S2,%0\";
2158 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
2159 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
2160 && true_regnum (operands[0]) != true_regnum (operands[2]))
2161 return \"mov %1,%0\;asr %S2,%0\";
2162 return \"asr %2,%1,%0\";
2164 [(set_attr "cc" "set_zn")])
2167 [(set (match_operand:SI 0 "register_operand" "=dx")
2169 (match_operand:SI 1 "register_operand" "0")
2170 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
2173 [(set_attr "cc" "set_zn")])
2175 ;; ----------------------------------------------------------------------
2177 ;; ----------------------------------------------------------------------
2179 ;; The mn103 series does not have floating point instructions, but since
2180 ;; FP values are held in integer regs, we can clear the high bit easily
2181 ;; which gives us an efficient inline floating point absolute value.
2183 ;; Similarly for negation of a FP value.
2186 (define_expand "absdf2"
2187 [(set (match_operand:DF 0 "register_operand" "")
2188 (abs:DF (match_operand:DF 1 "register_operand" "")))]
2192 rtx target, result, insns;
2195 target = operand_subword (operands[0], 1, 1, DFmode);
2196 result = expand_binop (SImode, and_optab,
2197 operand_subword_force (operands[1], 1, DFmode),
2198 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
2200 gcc_assert (result);
2202 if (result != target)
2203 emit_move_insn (result, target);
2205 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
2206 operand_subword_force (operands[1], 0, DFmode));
2208 insns = get_insns ();
2215 (define_expand "abssf2"
2216 [(set (match_operand:SF 0 "register_operand" "")
2217 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2226 emit_insn (gen_abssf2_am33_2 (operands[0], operands[1]));
2230 target = operand_subword_force (operands[0], 0, SFmode);
2231 result = expand_binop (SImode, and_optab,
2232 operand_subword_force (operands[1], 0, SFmode),
2233 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
2234 gcc_assert (result);
2236 if (result != target)
2237 emit_move_insn (result, target);
2239 /* Make a place for REG_EQUAL. */
2240 emit_move_insn (operands[0], operands[0]);
2245 (define_insn "abssf2_am33_2"
2246 [(set (match_operand:SF 0 "register_operand" "=f,f")
2247 (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
2252 [(set_attr "cc" "none_0hit")])
2254 (define_expand "negdf2"
2255 [(set (match_operand:DF 0 "register_operand" "")
2256 (neg:DF (match_operand:DF 1 "register_operand" "")))]
2260 rtx target, result, insns;
2263 target = operand_subword (operands[0], 1, 1, DFmode);
2264 result = expand_binop (SImode, xor_optab,
2265 operand_subword_force (operands[1], 1, DFmode),
2266 GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
2267 target, 0, OPTAB_WIDEN);
2269 gcc_assert (result);
2271 if (result != target)
2272 emit_move_insn (result, target);
2274 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
2275 operand_subword_force (operands[1], 0, DFmode));
2277 insns = get_insns ();
2284 (define_expand "negsf2"
2285 [(set (match_operand:SF 0 "register_operand" "")
2286 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2295 emit_insn (gen_negsf2_am33_2 (operands[0], operands[1]));
2299 target = operand_subword_force (operands[0], 0, SFmode);
2300 result = expand_binop (SImode, xor_optab,
2301 operand_subword_force (operands[1], 0, SFmode),
2302 GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
2303 target, 0, OPTAB_WIDEN);
2304 gcc_assert (result);
2306 if (result != target)
2307 emit_move_insn (result, target);
2309 /* Make a place for REG_EQUAL. */
2310 emit_move_insn (operands[0], operands[0]);
2314 (define_insn "negsf2_am33_2"
2315 [(set (match_operand:SF 0 "register_operand" "=f,f")
2316 (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
2321 [(set_attr "cc" "none_0hit")])
2323 (define_expand "sqrtsf2"
2324 [(set (match_operand:SF 0 "register_operand" "")
2325 (sqrt:SF (match_operand:SF 1 "register_operand" "")))]
2326 "TARGET_AM33_2 && flag_unsafe_math_optimizations"
2329 rtx scratch = gen_reg_rtx (SFmode);
2330 emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
2331 emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
2336 (define_insn "rsqrtsf2"
2337 [(set (match_operand:SF 0 "register_operand" "=f,f")
2338 (div:SF (match_operand:SF 2 "const_1f_operand" "F,F")
2339 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))]
2344 [(set_attr "cc" "none_0hit")])
2346 (define_insn "addsf3"
2347 [(set (match_operand:SF 0 "register_operand" "=f,f")
2348 (plus:SF (match_operand:SF 1 "register_operand" "%0,f")
2349 (match_operand:SF 2 "general_operand" "f,?fF")))]
2354 [(set_attr "cc" "none_0hit")])
2356 (define_insn "subsf3"
2357 [(set (match_operand:SF 0 "register_operand" "=f,f")
2358 (minus:SF (match_operand:SF 1 "register_operand" "0,f")
2359 (match_operand:SF 2 "general_operand" "f,?fF")))]
2364 [(set_attr "cc" "none_0hit")])
2366 (define_insn "mulsf3"
2367 [(set (match_operand:SF 0 "register_operand" "=f,f")
2368 (mult:SF (match_operand:SF 1 "register_operand" "%0,f")
2369 (match_operand:SF 2 "general_operand" "f,?fF")))]
2374 [(set_attr "cc" "none_0hit")])
2376 (define_insn "divsf3"
2377 [(set (match_operand:SF 0 "register_operand" "=f,f")
2378 (div:SF (match_operand:SF 1 "register_operand" "0,f")
2379 (match_operand:SF 2 "general_operand" "f,?fF")))]
2384 [(set_attr "cc" "none_0hit")])
2386 (define_insn "fmaddsf4"
2387 [(set (match_operand:SF 0 "register_operand" "=A")
2388 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
2389 (match_operand:SF 2 "register_operand" "f"))
2390 (match_operand:SF 3 "register_operand" "f")))]
2392 "fmadd %1, %2, %3, %0"
2393 [(set_attr "cc" "none_0hit")])
2395 (define_insn "fmsubsf4"
2396 [(set (match_operand:SF 0 "register_operand" "=A")
2397 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
2398 (match_operand:SF 2 "register_operand" "f"))
2399 (match_operand:SF 3 "register_operand" "f")))]
2401 "fmsub %1, %2, %3, %0"
2402 [(set_attr "cc" "none_0hit")])
2404 (define_insn "fnmaddsf4"
2405 [(set (match_operand:SF 0 "register_operand" "=A")
2406 (minus:SF (match_operand:SF 3 "register_operand" "f")
2407 (mult:SF (match_operand:SF 1 "register_operand" "%f")
2408 (match_operand:SF 2 "register_operand" "f"))))]
2410 "fnmadd %1, %2, %3, %0"
2411 [(set_attr "cc" "none_0hit")])
2413 (define_insn "fnmsubsf4"
2414 [(set (match_operand:SF 0 "register_operand" "=A")
2415 (minus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
2416 (match_operand:SF 2 "register_operand" "f")))
2417 (match_operand:SF 3 "register_operand" "f")))]
2419 "fnmsub %1, %2, %3, %0"
2420 [(set_attr "cc" "none_0hit")])
2423 ;; ----------------------------------------------------------------------
2424 ;; PROLOGUE/EPILOGUE
2425 ;; ----------------------------------------------------------------------
2426 (define_expand "prologue"
2429 "expand_prologue (); DONE;")
2431 (define_expand "epilogue"
2440 (define_insn "return_internal"
2445 [(set_attr "cc" "clobber")])
2447 ;; This insn restores the callee saved registers and does a return, it
2448 ;; can also deallocate stack space.
2449 (define_insn "return_internal_regs"
2451 (match_operand:SI 0 "const_int_operand" "i")
2456 fputs (\"\\tret \", asm_out_file);
2457 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
2458 fprintf (asm_out_file, \",%d\\n\", (int) INTVAL (operands[0]));
2461 [(set_attr "cc" "clobber")])
2463 ;; This instruction matches one generated by mn10300_gen_multiple_store()
2464 (define_insn "store_movm"
2465 [(match_parallel 0 "store_multiple_operation"
2466 [(set (reg:SI 9) (plus:SI (reg:SI 9) (match_operand 1 "" "")))])]
2470 fputs (\"\\tmovm \", asm_out_file);
2471 mn10300_print_reg_list (asm_out_file,
2472 store_multiple_operation (operands[0], VOIDmode));
2473 fprintf (asm_out_file, \",(sp)\\n\");
2476 [(set_attr "cc" "clobber")])
2478 (define_insn "return"
2480 "can_use_return_insn ()"
2483 rtx next = next_active_insn (insn);
2486 && GET_CODE (next) == JUMP_INSN
2487 && GET_CODE (PATTERN (next)) == RETURN)
2492 [(set_attr "cc" "clobber")])
2494 ;; Try to combine consecutive updates of the stack pointer (or any
2495 ;; other register for that matter).
2497 [(set (match_operand:SI 0 "register_operand" "=dxay")
2498 (plus:SI (match_dup 0)
2499 (match_operand 1 "const_int_operand" "")))
2501 (plus:SI (match_dup 0)
2502 (match_operand 2 "const_int_operand" "")))]
2506 operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
2507 return \"add %1,%0\";
2509 [(set_attr "cc" "clobber")])
2512 ;; We had patterns to check eq/ne, but the they don't work because
2513 ;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
2515 ;; The Z flag and C flag would be set, and we have no way to
2516 ;; check for the Z flag set and C flag clear.
2518 ;; This will work on the mn10200 because we can check the ZX flag
2519 ;; if the comparison is in HImode.
2521 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2522 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2523 (match_operand 1 "" "")
2525 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2527 [(set_attr "cc" "clobber")])
2530 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2531 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2532 (match_operand 1 "" "")
2534 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2536 [(set_attr "cc" "clobber")])
2539 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2540 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2542 (match_operand 1 "" "")))]
2543 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2545 [(set_attr "cc" "clobber")])
2548 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2549 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2551 (match_operand 1 "" "")))]
2552 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2554 [(set_attr "cc" "clobber")])
2556 (define_expand "int_label"
2557 [(unspec [(match_operand:SI 0 "" "")] UNSPEC_INT_LABEL)]
2560 (define_expand "GOTaddr2picreg"
2564 /* It would be nice to be able to have int_label keep track of the
2565 counter and all, but if we add C code to it, we'll get an insn
2566 back, and we just want the pattern. */
2567 operands[0] = gen_int_label (GEN_INT (mn10300_unspec_int_label_counter++));
2569 emit_insn (gen_am33_loadPC (operands[0]));
2571 emit_insn (gen_mn10300_loadPC (operands[0]));
2572 emit_insn (gen_add_GOT_to_pic_reg (copy_rtx (operands[0])));
2577 (define_insn "am33_loadPC"
2579 [(set (reg:SI PIC_REG) (pc))
2580 (use (match_operand 0 "" ""))])]
2585 (define_insn_and_split "mn10300_loadPC"
2587 [(set (reg:SI PIC_REG) (pc))
2588 (use (match_operand 0 "" ""))])]
2592 [(match_operand 0 "" "")]
2595 rtx sp_reg = gen_rtx_REG (SImode, SP_REG);
2596 int need_stack_space = (get_frame_size () == 0
2597 && crtl->outgoing_args_size == 0);
2599 if (need_stack_space)
2600 emit_move_insn (sp_reg, plus_constant (sp_reg, -4));
2602 emit_insn (gen_call_next_insn (operands[0]));
2604 if (need_stack_space)
2605 emit_insn (gen_pop_pic_reg ());
2607 emit_move_insn (pic_offset_table_rtx, gen_rtx_MEM (SImode, sp_reg));
2612 (define_insn "call_next_insn"
2614 [(set (mem:SI (reg:SI SP_REG)) (pc))
2615 (use (match_operand 0 "" ""))])]
2619 (define_expand "add_GOT_to_pic_reg"
2620 [(set (reg:SI PIC_REG)
2624 (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_GOTSYM_OFF))))]
2627 (define_expand "symGOT2reg"
2628 [(match_operand:SI 0 "" "")
2629 (match_operand:SI 1 "" "")]
2633 rtx insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1]));
2635 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
2637 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
2642 (define_expand "symGOT2reg_i"
2643 [(set (match_operand:SI 0 "" "")
2644 (mem:SI (plus:SI (reg:SI PIC_REG)
2645 (const (unspec [(match_operand:SI 1 "" "")]
2650 (define_expand "symGOTOFF2reg"
2651 [(match_operand:SI 0 "" "") (match_operand:SI 1 "" "")]
2655 rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1]));
2657 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
2662 (define_expand "symGOTOFF2reg_i"
2663 [(set (match_operand:SI 0 "" "")
2664 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOTOFF)))
2665 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI PIC_REG)))]
2669 (define_expand "sym2PIC"
2670 [(unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC)]
2673 (define_expand "sym2PLT"
2674 [(unspec [(match_operand:SI 0 "" "")] UNSPEC_PLT)]