1 ;; GCC machine description for Matsushita MN10300
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 ;; 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Jeff Law (law@cygnus.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
41 (include "predicates.md")
42 (include "constraints.md")
44 ;; Processor type. This attribute must exactly match the processor_type
45 ;; enumeration in mn10300.h.
46 (define_attr "cpu" "mn10300,am33,am33_2,am34"
47 (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu")))
49 ;; Used to control the "enabled" attribute on a per-instruction basis.
50 (define_attr "isa" "base,am33,am33_2,am34"
51 (const_string "base"))
53 (define_attr "enabled" ""
54 (cond [(eq_attr "isa" "base")
57 (and (eq_attr "isa" "am33")
58 (ne (symbol_ref "TARGET_AM33") (const_int 0)))
61 (and (eq_attr "isa" "am33_2")
62 (ne (symbol_ref "TARGET_AM33_2") (const_int 0)))
65 (and (eq_attr "isa" "am34")
66 (ne (symbol_ref "TARGET_AM34") (const_int 0)))
72 ;; Pipeline description.
74 ;; The AM33 only has a single pipeline. It has five stages (fetch,
75 ;; decode, execute, memory access, writeback) each of which normally
76 ;; takes a single CPU clock cycle.
78 ;; The timings attribute consists of two numbers, the first is the
79 ;; throughput, which is the number of cycles the instruction takes
80 ;; to execute and generate a result. The second is the latency
81 ;; which is the effective number of cycles the instruction takes to
82 ;; execute if its result is used by the following instruction. The
83 ;; latency is always greater than or equal to the throughput.
84 ;; These values were taken from the Appendix of the "MN103E Series
85 ;; Instruction Manual" and the timings for the AM34.
87 ;; Note - it would be nice to use strings rather than integers for
88 ;; the possible values of this attribute, so that we can have the
89 ;; gcc build mechanism check for values that are not supported by
90 ;; the reservations below. But this will not work because the code
91 ;; in mn10300_adjust_sched_cost() needs integers not strings.
93 (define_attr "timings" "" (const_int 11))
95 (define_automaton "pipelining")
96 (define_cpu_unit "throughput" "pipelining")
98 (define_insn_reservation "throughput__1_latency__1" 1
99 (eq_attr "timings" "11") "throughput")
100 (define_insn_reservation "throughput__1_latency__2" 2
101 (eq_attr "timings" "12") "throughput,nothing")
102 (define_insn_reservation "throughput__1_latency__3" 3
103 (eq_attr "timings" "13") "throughput,nothing*2")
104 (define_insn_reservation "throughput__1_latency__4" 4
105 (eq_attr "timings" "14") "throughput,nothing*3")
106 (define_insn_reservation "throughput__2_latency__2" 2
107 (eq_attr "timings" "22") "throughput*2")
108 (define_insn_reservation "throughput__2_latency__3" 3
109 (eq_attr "timings" "23") "throughput*2,nothing")
110 (define_insn_reservation "throughput__2_latency__4" 4
111 (eq_attr "timings" "24") "throughput*2,nothing*2")
112 (define_insn_reservation "throughput__2_latency__5" 5
113 (eq_attr "timings" "25") "throughput*2,nothing*3")
114 (define_insn_reservation "throughput__3_latency__3" 3
115 (eq_attr "timings" "33") "throughput*3")
116 (define_insn_reservation "throughput__3_latency__7" 7
117 (eq_attr "timings" "37") "throughput*3,nothing*4")
118 (define_insn_reservation "throughput__4_latency__4" 4
119 (eq_attr "timings" "44") "throughput*4")
120 (define_insn_reservation "throughput__4_latency__7" 7
121 (eq_attr "timings" "47") "throughput*4,nothing*3")
122 (define_insn_reservation "throughput__4_latency__8" 8
123 (eq_attr "timings" "48") "throughput*4,nothing*4")
124 (define_insn_reservation "throughput__5_latency__5" 5
125 (eq_attr "timings" "55") "throughput*5")
126 (define_insn_reservation "throughput__6_latency__6" 6
127 (eq_attr "timings" "66") "throughput*6")
128 (define_insn_reservation "throughput__7_latency__7" 7
129 (eq_attr "timings" "77") "throughput*7")
130 (define_insn_reservation "throughput__7_latency__8" 8
131 (eq_attr "timings" "78") "throughput*7,nothing")
132 (define_insn_reservation "throughput__8_latency__8" 8
133 (eq_attr "timings" "88") "throughput*8")
134 (define_insn_reservation "throughput__9_latency__9" 9
135 (eq_attr "timings" "99") "throughput*9")
136 (define_insn_reservation "throughput__8_latency_14" 14
137 (eq_attr "timings" "814") "throughput*8,nothing*6")
138 (define_insn_reservation "throughput__9_latency_10" 10
139 (eq_attr "timings" "910") "throughput*9,nothing")
140 (define_insn_reservation "throughput_10_latency_10" 10
141 (eq_attr "timings" "1010") "throughput*10")
142 (define_insn_reservation "throughput_12_latency_16" 16
143 (eq_attr "timings" "1216") "throughput*12,nothing*4")
144 (define_insn_reservation "throughput_13_latency_13" 13
145 (eq_attr "timings" "1313") "throughput*13")
146 (define_insn_reservation "throughput_14_latency_14" 14
147 (eq_attr "timings" "1414") "throughput*14")
148 (define_insn_reservation "throughput_13_latency_17" 17
149 (eq_attr "timings" "1317") "throughput*13,nothing*4")
150 (define_insn_reservation "throughput_23_latency_27" 27
151 (eq_attr "timings" "2327") "throughput*23,nothing*4")
152 (define_insn_reservation "throughput_25_latency_31" 31
153 (eq_attr "timings" "2531") "throughput*25,nothing*6")
154 (define_insn_reservation "throughput_38_latency_39" 39
155 (eq_attr "timings" "3839") "throughput*38,nothing")
156 (define_insn_reservation "throughput_39_latency_40" 40
157 (eq_attr "timings" "3940") "throughput*39,nothing")
158 (define_insn_reservation "throughput_40_latency_40" 40
159 (eq_attr "timings" "4040") "throughput*40")
160 (define_insn_reservation "throughput_41_latency_42" 42
161 (eq_attr "timings" "4142") "throughput*41,nothing")
162 (define_insn_reservation "throughput_43_latency_44" 44
163 (eq_attr "timings" "4344") "throughput*43,nothing")
164 (define_insn_reservation "throughput_45_latency_46" 46
165 (eq_attr "timings" "4546") "throughput*45,nothing")
166 (define_insn_reservation "throughput_47_latency_53" 53
167 (eq_attr "timings" "4753") "throughput*47,nothing*6")
169 ;; Note - the conflict between memory load/store instructions
170 ;; and floating point instructions described in section 1-7-4
171 ;; of Chapter 3 of the MN103E Series Instruction Manual is
172 ;; handled by the mn10300_adjust_sched_cost function.
174 ;; ----------------------------------------------------------------------
176 ;; ----------------------------------------------------------------------
180 (define_expand "movqi"
181 [(set (match_operand:QI 0 "nonimmediate_operand")
182 (match_operand:QI 1 "general_operand"))]
186 /* One of the ops has to be in a register. */
187 if (!register_operand (operand0, QImode)
188 && !register_operand (operand1, QImode))
189 operands[1] = copy_to_mode_reg (QImode, operand1);
192 (define_insn "*am33_movqi"
193 [(set (match_operand:QI 0 "nonimmediate_operand"
195 "=d*x*a*f, d*x*a, d*x*a, m, *f, d*x*a")
196 (match_operand:QI 1 "general_operand"
197 "0, d*xai, m, d*xa, d*xa*f, *f"))]
199 && (register_operand (operands[0], QImode)
200 || register_operand (operands[1], QImode))"
203 switch (which_alternative)
208 gcc_assert (! CONST_DOUBLE_P (operands[1]));
210 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
211 && CONST_INT_P (operands[1]))
213 HOST_WIDE_INT val = INTVAL (operands[1]);
215 if (((val & 0x80) && ! (val & 0xffffff00))
216 || ((val & 0x800000) && ! (val & 0xff000000)))
217 return \"movu %1,%0\";
219 return \"mov %1,%0\";
222 return \"movbu %1,%0\";
225 return \"fmov %1,%0\";
230 [(set_attr_alternative "timings"
232 (if_then_else (eq_attr "cpu" "am34")
233 (const_int 11) (const_int 22))
234 (if_then_else (eq_attr "cpu" "am34")
235 (const_int 13) (const_int 24))
236 (if_then_else (eq_attr "cpu" "am34")
237 (const_int 13) (const_int 24))
238 (if_then_else (eq_attr "cpu" "am34")
239 (const_int 47) (const_int 25))
240 (if_then_else (eq_attr "cpu" "am34")
241 (const_int 47) (const_int 25))
246 (define_insn "*mn10300_movqi"
247 [(set (match_operand:QI 0 "nonimmediate_operand" "=d*a,d,d,!*a,d*a,d,m")
248 (match_operand:QI 1 "general_operand" "0, I,i,i, da, m,d"))]
249 "register_operand (operands[0], QImode)
250 || register_operand (operands[1], QImode)"
253 switch (which_alternative)
261 gcc_assert (! CONST_DOUBLE_P (operands[1]));
262 return \"mov %1,%0\";
265 return \"movbu %1,%0\";
270 [(set_attr_alternative "timings"
273 (if_then_else (eq_attr "cpu" "am34")
274 (const_int 11) (const_int 22))
275 (if_then_else (eq_attr "cpu" "am34")
276 (const_int 11) (const_int 22))
277 (if_then_else (eq_attr "cpu" "am34")
278 (const_int 11) (const_int 22))
279 (if_then_else (eq_attr "cpu" "am34")
280 (const_int 13) (const_int 24))
281 (if_then_else (eq_attr "cpu" "am34")
282 (const_int 13) (const_int 24))
289 (define_expand "movhi"
290 [(set (match_operand:HI 0 "nonimmediate_operand")
291 (match_operand:HI 1 "general_operand"))]
295 /* One of the ops has to be in a register. */
296 if (!register_operand (operand1, HImode)
297 && !register_operand (operand0, HImode))
298 operands[1] = copy_to_mode_reg (HImode, operand1);
301 (define_insn "*am33_movhi"
302 [(set (match_operand:HI 0 "nonimmediate_operand"
304 "=d*x*a*f, d*x*a, d*x*a, m, *f, d*x*a")
305 (match_operand:HI 1 "general_operand"
306 "0, d*x*ai, m, d*x*a, d*x*a*f, *f"))]
308 && (register_operand (operands[0], HImode)
309 || register_operand (operands[1], HImode))"
312 switch (which_alternative)
317 gcc_assert (! CONST_DOUBLE_P (operands[1]));
319 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
320 && CONST_INT_P (operands[1]))
322 HOST_WIDE_INT val = INTVAL (operands[1]);
324 if (((val & 0x80) && ! (val & 0xffffff00))
325 || ((val & 0x800000) && ! (val & 0xff000000)))
326 return \"movu %1,%0\";
328 return \"mov %1,%0\";
331 return \"movhu %1,%0\";
334 return \"fmov %1,%0\";
339 [(set_attr_alternative "timings"
341 (if_then_else (eq_attr "cpu" "am34")
342 (const_int 11) (const_int 22))
343 (if_then_else (eq_attr "cpu" "am34")
344 (const_int 13) (const_int 24))
345 (if_then_else (eq_attr "cpu" "am34")
346 (const_int 13) (const_int 24))
347 (if_then_else (eq_attr "cpu" "am34")
348 (const_int 47) (const_int 25))
349 (if_then_else (eq_attr "cpu" "am34")
350 (const_int 47) (const_int 25))
355 (define_insn "*mn10300_movhi"
356 [(set (match_operand:HI 0 "nonimmediate_operand" "=d*a,d,d,!*a,d*a,d,m")
357 (match_operand:HI 1 "general_operand" "0, I,i,i, da, m,d"))]
358 "register_operand (operands[0], HImode)
359 || register_operand (operands[1], HImode)"
362 switch (which_alternative)
370 gcc_assert (! CONST_DOUBLE_P (operands[1]));
371 return \"mov %1,%0\";
374 return \"movhu %1,%0\";
379 [(set_attr_alternative "timings"
382 (if_then_else (eq_attr "cpu" "am34")
383 (const_int 11) (const_int 22))
384 (if_then_else (eq_attr "cpu" "am34")
385 (const_int 11) (const_int 22))
386 (if_then_else (eq_attr "cpu" "am34")
387 (const_int 11) (const_int 22))
388 (if_then_else (eq_attr "cpu" "am34")
389 (const_int 13) (const_int 24))
390 (if_then_else (eq_attr "cpu" "am34")
391 (const_int 13) (const_int 24))
398 ;; We use this to handle addition of two values when one operand is the
399 ;; stack pointer and the other is a memory reference of some kind. Reload
400 ;; does not handle them correctly without this expander.
401 (define_expand "reload_insi"
402 [(set (match_operand:SI 0 "register_operand" "=a")
403 (match_operand:SI 1 "impossible_plus_operand" ""))
404 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
408 gcc_assert (REGNO (operands[0]) != REGNO (operands[2]));
410 if (XEXP (operands[1], 0) == stack_pointer_rtx)
412 if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
413 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
414 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
415 emit_move_insn (operands[2],
417 (GET_MODE (XEXP (operands[1], 1)),
418 SUBREG_REG (XEXP (operands[1], 1))));
420 emit_move_insn (operands[2], XEXP (operands[1], 1));
421 emit_move_insn (operands[0], XEXP (operands[1], 0));
425 if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
426 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
427 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
428 emit_move_insn (operands[2],
430 (GET_MODE (XEXP (operands[1], 0)),
431 SUBREG_REG (XEXP (operands[1], 0))));
433 emit_move_insn (operands[2], XEXP (operands[1], 0));
434 emit_move_insn (operands[0], XEXP (operands[1], 1));
436 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
440 (define_insn "pop_pic_reg"
441 [(set (reg:SI PIC_REG)
442 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
445 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
446 (const_int 44) (const_int 33)))]
449 (define_expand "movsi"
450 [(set (match_operand:SI 0 "nonimmediate_operand")
451 (match_operand:SI 1 "general_operand"))]
455 /* One of the ops has to be in a register. */
456 if (!register_operand (operand1, SImode)
457 && !register_operand (operand0, SImode))
458 operands[1] = copy_to_mode_reg (SImode, operand1);
462 if (SYMBOLIC_CONST_P (operands[1]))
464 if (MEM_P (operands[0]))
465 operands[1] = force_reg (Pmode, operands[1]);
468 temp = (!can_create_pseudo_p ()
470 : gen_reg_rtx (Pmode));
471 operands[1] = mn10300_legitimize_pic_address (operands[1], temp);
474 else if (GET_CODE (operands[1]) == CONST
475 && GET_CODE (XEXP (operands[1], 0)) == PLUS
476 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
478 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
479 temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
481 operands[1] = expand_binop (SImode, add_optab, temp,
482 XEXP (XEXP (operands[1], 0), 1),
483 (!can_create_pseudo_p ()
485 : gen_reg_rtx (Pmode)),
491 (define_insn "*movsi_internal"
492 [(set (match_operand:SI 0 "nonimmediate_operand"
493 "=dax, dax, m, dax, axR, !*y")
494 (match_operand:SI 1 "general_operand"
495 "0, Idax, dax, im, !*y, axR"))
497 "register_operand (operands[0], SImode)
498 || register_operand (operands[1], SImode)"
501 if (which_alternative == 0)
504 gcc_assert (! CONST_DOUBLE_P (operands[1]));
506 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
507 && CONST_INT_P (operands[1]))
509 HOST_WIDE_INT val = INTVAL (operands[1]);
511 if (((val & 0x80) && ! (val & 0xffffff00))
512 || ((val & 0x800000) && ! (val & 0xff000000)))
513 return \"movu %1, %0\";
516 return \"mov %1, %0\";
518 [(set_attr_alternative "timings"
520 (if_then_else (eq_attr "cpu" "am34")
521 (const_int 13) (const_int 24))
522 (if_then_else (eq_attr "cpu" "am34")
523 (const_int 13) (const_int 24))
524 (if_then_else (eq_attr "cpu" "am34")
525 (const_int 13) (const_int 24))
526 (if_then_else (eq_attr "cpu" "am34")
527 (const_int 13) (const_int 24))
528 (if_then_else (eq_attr "cpu" "am34")
529 (const_int 13) (const_int 24))
534 (define_expand "movsf"
535 [(set (match_operand:SF 0 "nonimmediate_operand")
536 (match_operand:SF 1 "general_operand"))]
540 /* One of the ops has to be in a register. */
541 if (!register_operand (operand1, SFmode)
542 && !register_operand (operand0, SFmode))
543 operands[1] = copy_to_mode_reg (SFmode, operand1);
546 (define_insn "*movsf_internal"
547 [(set (match_operand:SF 0 "nonimmediate_operand"
549 "=fdxa, dxa, f, dxaQ, daxm, dax")
550 (match_operand:SF 1 "general_operand"
551 " 0, G, fdxaQF, f, dax, daxFm"))
553 "register_operand (operands[0], SFmode)
554 || register_operand (operands[1], SFmode)"
557 switch (which_alternative)
564 return \"fmov %1, %0\";
568 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
569 && CONST_INT_P (operands[1]))
571 HOST_WIDE_INT val = INTVAL (operands[1]);
573 if (((val & 0x80) && ! (val & 0xffffff00))
574 || ((val & 0x800000) && ! (val & 0xff000000)))
575 return \"movu %1, %0\";
577 return \"mov %1, %0\";
582 [(set_attr_alternative "timings"
584 (if_then_else (eq_attr "cpu" "am34")
585 (const_int 13) (const_int 24))
586 (if_then_else (eq_attr "cpu" "am34")
587 (const_int 47) (const_int 25))
588 (if_then_else (eq_attr "cpu" "am34")
589 (const_int 47) (const_int 25))
590 (if_then_else (eq_attr "cpu" "am34")
591 (const_int 13) (const_int 24))
592 (if_then_else (eq_attr "cpu" "am34")
593 (const_int 13) (const_int 24))
598 (define_expand "movdi"
599 [(set (match_operand:DI 0 "nonimmediate_operand")
600 (match_operand:DI 1 "general_operand"))]
604 /* One of the ops has to be in a register. */
605 if (!register_operand (operand1, DImode)
606 && !register_operand (operand0, DImode))
607 operands[1] = copy_to_mode_reg (DImode, operand1);
611 (define_insn "*movdi_internal" ;; 0 1 2 3 4 5 6 7 8 9
612 [(set (match_operand:DI 0 "nonimmediate_operand" "=dx,ax,dx,a,dxm,dxm,a, a,dx,a")
613 (match_operand:DI 1 "general_operand" "0,0, I, I,dx, a, dx,a,im,im"))]
614 "register_operand (operands[0], DImode)
615 || register_operand (operands[1], DImode)"
621 switch (which_alternative)
628 return \"mov 0, %L0\;mov 0, %H0\";
631 if (rtx_equal_p (operands[0], operands[1]))
632 return \"sub %L1,%L0\;mov %L0,%H0\";
634 return \"mov %1,%L0\;mov %L0,%H0\";
641 if (CONST_INT_P (operands[1]))
644 split_double (operands[1], &low, &high);
645 val[0] = INTVAL (low);
646 val[1] = INTVAL (high);
648 if (CONST_DOUBLE_P (operands[1]))
650 if (GET_MODE (operands[1]) == DFmode)
652 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
653 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
655 else if (GET_MODE (operands[1]) == VOIDmode
656 || GET_MODE (operands[1]) == DImode)
658 val[0] = CONST_DOUBLE_LOW (operands[1]);
659 val[1] = CONST_DOUBLE_HIGH (operands[1]);
663 if (MEM_P (operands[1])
664 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
666 rtx temp = operands[0];
668 while (GET_CODE (temp) == SUBREG)
669 temp = SUBREG_REG (temp);
671 gcc_assert (REG_P (temp));
673 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
674 XEXP (operands[1], 0)))
675 return \"mov %H1,%H0\;mov %L1,%L0\";
677 return \"mov %L1,%L0\;mov %H1,%H0\";
680 else if (MEM_P (operands[1])
681 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
682 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
686 xoperands[0] = operands[0];
687 xoperands[1] = XEXP (operands[1], 0);
689 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
695 if ((CONST_INT_P (operands[1])
696 || CONST_DOUBLE_P (operands[1]))
699 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
700 output_asm_insn (\"mov 0, %L0\", operands);
702 output_asm_insn (\"mov %L1,%L0\", operands);
704 else if ((CONST_INT_P (operands[1])
705 || CONST_DOUBLE_P (operands[1]))
706 && (REGNO_REG_CLASS (true_regnum (operands[0]))
708 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
709 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
710 output_asm_insn (\"movu %L1,%L0\", operands);
712 output_asm_insn (\"mov %L1,%L0\", operands);
714 if ((CONST_INT_P (operands[1])
715 || CONST_DOUBLE_P (operands[1]))
718 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
719 output_asm_insn (\"mov 0, %H0\", operands);
721 output_asm_insn (\"mov %H1,%H0\", operands);
723 else if ((CONST_INT_P (operands[1])
724 || CONST_DOUBLE_P (operands[1]))
726 output_asm_insn (\"mov %L0,%H0\", operands);
727 else if ((CONST_INT_P (operands[1])
728 || CONST_DOUBLE_P (operands[1]))
729 && (REGNO_REG_CLASS (true_regnum (operands[0]))
731 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
732 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
733 output_asm_insn (\"movu %H1,%H0\", operands);
735 output_asm_insn (\"mov %H1,%H0\", operands);
742 ;; The timing of "37" is an approximation of the worst case sceanario.
743 [(set_attr_alternative "timings"
758 (define_expand "movdf"
759 [(set (match_operand:DF 0 "nonimmediate_operand")
760 (match_operand:DF 1 "general_operand"))]
764 /* One of the ops has to be in a register. */
765 if (!register_operand (operand1, DFmode)
766 && !register_operand (operand0, DFmode))
767 operands[1] = copy_to_mode_reg (DFmode, operand1);
770 (define_insn "*am33_2_movdf"
771 [(set (match_operand:DF 0 "nonimmediate_operand"
772 ;; 0 1 2 3 4 5 6 7 8 9 10 11
773 "=fdax,dax,fdxa,f, f,Q,dxm,dxm,a, a,dx,a")
774 (match_operand:DF 1 "general_operand"
775 " 0, G, f, dxaF,Q,f,dx, a, dx,a,Fm,Fm"))]
777 && (register_operand (operands[0], DFmode)
778 || register_operand (operands[1], DFmode))"
784 switch (which_alternative)
790 return \"mov 0, %L0\; mov 0, %H0\";
794 return \"fmov %L1, %L0\; fmov %H1, %H0\";
797 if (MEM_P (operands[1])
798 && CONST_INT_P (XEXP (operands[1], 0))
799 && (INTVAL (XEXP (operands[1], 0)) & 7) == 0)
800 return \"fmov %D1, %D0\";
802 return \"fmov %L1, %L0\; fmov %H1, %H0\";
805 if (MEM_P (operands[0])
806 && CONST_INT_P (XEXP (operands[0], 0))
807 && (INTVAL (XEXP (operands[0], 0)) & 7) == 0)
808 return \"fmov %D1, %D0\";
810 return \"fmov %L1, %L0\; fmov %H1, %H0\";
818 if (CONST_INT_P (operands[1]))
821 split_double (operands[1], &low, &high);
822 val[0] = INTVAL (low);
823 val[1] = INTVAL (high);
825 if (CONST_DOUBLE_P (operands[1]))
827 if (GET_MODE (operands[1]) == DFmode)
829 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
830 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
832 else if (GET_MODE (operands[1]) == VOIDmode
833 || GET_MODE (operands[1]) == DImode)
835 val[0] = CONST_DOUBLE_LOW (operands[1]);
836 val[1] = CONST_DOUBLE_HIGH (operands[1]);
840 if (MEM_P (operands[1])
841 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
843 rtx temp = operands[0];
845 while (GET_CODE (temp) == SUBREG)
846 temp = SUBREG_REG (temp);
848 gcc_assert (REG_P (temp));
850 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
851 XEXP (operands[1], 0)))
852 return \"mov %H1, %H0\; mov %L1, %L0\";
854 return \"mov %L1, %L0\; mov %H1, %H0\";
857 else if (MEM_P (operands[1])
858 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
859 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
863 xoperands[0] = operands[0];
864 xoperands[1] = XEXP (operands[1], 0);
866 output_asm_insn (\"mov %1, %L0\; mov (4, %L0), %H0\; mov (%L0), %L0\",
872 if ((CONST_INT_P (operands[1])
873 || CONST_DOUBLE_P (operands[1]))
876 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
877 output_asm_insn (\"mov 0, %L0\", operands);
879 output_asm_insn (\"mov %L1,%L0\", operands);
881 else if ((CONST_INT_P (operands[1])
882 || CONST_DOUBLE_P (operands[1]))
883 && (REGNO_REG_CLASS (true_regnum (operands[0]))
885 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
886 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
887 output_asm_insn (\"movu %L1, %L0\", operands);
889 output_asm_insn (\"mov %L1, %L0\", operands);
891 if ((CONST_INT_P (operands[1])
892 || CONST_DOUBLE_P (operands[1]))
895 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
896 output_asm_insn (\"mov 0, %H0\", operands);
898 output_asm_insn (\"mov %H1, %H0\", operands);
900 else if ((CONST_INT_P (operands[1])
901 || CONST_DOUBLE_P (operands[1]))
903 output_asm_insn (\"mov %L0,%H0\", operands);
904 else if ((CONST_INT_P (operands[1])
905 || CONST_DOUBLE_P (operands[1]))
906 && (REGNO_REG_CLASS (true_regnum (operands[0]))
908 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
909 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
910 output_asm_insn (\"movu %H1, %H0\", operands);
912 output_asm_insn (\"mov %H1, %H0\", operands);
919 ;; The timing of "37" is an approximation of the worst case sceanario.
920 [(set_attr_alternative "timings"
937 (define_insn "*mn10300_movdf"
938 [(set (match_operand:DF 0 "nonimmediate_operand"
940 "=dxa, dax, dxm, dxm, a, a, dx, a")
941 (match_operand:DF 1 "general_operand"
942 " 0, G, dx, a, dx, a, Fm, Fm"))]
943 "register_operand (operands[0], DFmode)
944 || register_operand (operands[1], DFmode)"
950 switch (which_alternative)
956 return \"mov 0, %L0\; mov 0, %H0\";
964 if (CONST_INT_P (operands[1]))
967 split_double (operands[1], &low, &high);
968 val[0] = INTVAL (low);
969 val[1] = INTVAL (high);
971 if (CONST_DOUBLE_P (operands[1]))
973 if (GET_MODE (operands[1]) == DFmode)
975 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
976 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
978 else if (GET_MODE (operands[1]) == VOIDmode
979 || GET_MODE (operands[1]) == DImode)
981 val[0] = CONST_DOUBLE_LOW (operands[1]);
982 val[1] = CONST_DOUBLE_HIGH (operands[1]);
986 if (MEM_P (operands[1])
987 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
989 rtx temp = operands[0];
991 while (GET_CODE (temp) == SUBREG)
992 temp = SUBREG_REG (temp);
994 gcc_assert (REG_P (temp));
996 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
997 XEXP (operands[1], 0)))
998 return \"mov %H1, %H0\; mov %L1, %L0\";
1000 return \"mov %L1, %L0\; mov %H1, %H0\";
1002 else if (MEM_P (operands[1])
1003 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
1004 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
1008 xoperands[0] = operands[0];
1009 xoperands[1] = XEXP (operands[1], 0);
1011 output_asm_insn (\"mov %1, %L0\; mov (4, %L0), %H0\; mov (%L0), %L0\",
1017 if ((CONST_INT_P (operands[1])
1018 || CONST_DOUBLE_P (operands[1]))
1021 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
1022 output_asm_insn (\"mov 0, %L0\", operands);
1024 output_asm_insn (\"mov %L1, %L0\", operands);
1026 else if ((CONST_INT_P (operands[1])
1027 || CONST_DOUBLE_P (operands[1]))
1028 && (REGNO_REG_CLASS (true_regnum (operands[0]))
1030 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
1031 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
1032 output_asm_insn (\"movu %L1, %L0\", operands);
1034 output_asm_insn (\"mov %L1, %L0\", operands);
1036 if ((CONST_INT_P (operands[1])
1037 || CONST_DOUBLE_P (operands[1]))
1040 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
1041 output_asm_insn (\"mov 0, %H0\", operands);
1043 output_asm_insn (\"mov %H1, %H0\", operands);
1045 else if ((CONST_INT_P (operands[1])
1046 || CONST_DOUBLE_P (operands[1]))
1047 && val[0] == val[1])
1048 output_asm_insn (\"mov %L0, %H0\", operands);
1049 else if ((CONST_INT_P (operands[1])
1050 || CONST_DOUBLE_P (operands[1]))
1051 && (REGNO_REG_CLASS (true_regnum (operands[0]))
1053 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
1054 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
1055 output_asm_insn (\"movu %H1, %H0\", operands);
1057 output_asm_insn (\"mov %H1, %H0\", operands);
1064 ;; Timings of "37" is approximation of the worst case sceanario.
1065 [(set_attr_alternative "timings"
1078 ;; ----------------------------------------------------------------------
1080 ;; ----------------------------------------------------------------------
1082 (define_expand "addsi3"
1083 [(parallel [(set (match_operand:SI 0 "register_operand")
1084 (plus:SI (match_operand:SI 1 "register_operand")
1085 (match_operand:SI 2 "nonmemory_operand")))
1086 (clobber (reg:CC CC_REG))
1092 (define_insn "*am33_addsi3"
1093 [(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,!*y,!dax")
1094 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax")
1095 (match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))
1096 (clobber (reg:CC CC_REG))
1101 switch (which_alternative)
1111 return \"add %2,%0\";
1114 enum reg_class src1_class, src2_class, dst_class;
1116 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
1117 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
1118 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
1120 /* I'm not sure if this can happen or not. Might as well be prepared
1121 and generate the best possible code if it does happen. */
1122 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1123 return \"add %2,%0\";
1124 if (true_regnum (operands[0]) == true_regnum (operands[2]))
1125 return \"add %1,%0\";
1127 /* Catch cases where no extended register was used. These should be
1128 handled just like the mn10300. */
1129 if (src1_class != EXTENDED_REGS
1130 && src2_class != EXTENDED_REGS
1131 && dst_class != EXTENDED_REGS)
1133 /* We have to copy one of the sources into the destination, then
1134 add the other source to the destination.
1136 Carefully select which source to copy to the destination; a
1137 naive implementation will waste a byte when the source classes
1138 are different and the destination is an address register.
1139 Selecting the lowest cost register copy will optimize this
1141 if (REGNO_REG_CLASS (true_regnum (operands[1]))
1142 == REGNO_REG_CLASS (true_regnum (operands[0])))
1143 return \"mov %1,%0\;add %2,%0\";
1144 return \"mov %2,%0\;add %1,%0\";
1147 /* At least one register is an extended register. */
1149 /* The three operand add instruction on the am33 is a win iff the
1150 output register is an extended register, or if both source
1151 registers are extended registers. */
1152 if (dst_class == EXTENDED_REGS
1153 || src1_class == src2_class)
1154 return \"add %2,%1,%0\";
1156 /* It is better to copy one of the sources to the destination, then
1157 perform a 2 address add. The destination in this case must be
1158 an address or data register and one of the sources must be an
1159 extended register and the remaining source must not be an extended
1162 The best code for this case is to copy the extended reg to the
1163 destination, then emit a two address add. */
1164 if (src1_class == EXTENDED_REGS)
1165 return \"mov %1,%0\;add %2,%0\";
1166 return \"mov %2,%0\;add %1,%0\";
1172 [(set_attr "timings" "11,11,11,11,11,11,22")]
1175 (define_insn "*mn10300_addsi3"
1176 [(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,!*y,!dax")
1177 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
1178 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))
1179 (clobber (reg:CC CC_REG))
1184 switch (which_alternative)
1193 return \"add %2,%0\";
1195 /* I'm not sure if this can happen or not. Might as well be prepared
1196 and generate the best possible code if it does happen. */
1197 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1198 return \"add %2,%0\";
1199 if (true_regnum (operands[0]) == true_regnum (operands[2]))
1200 return \"add %1,%0\";
1202 /* We have to copy one of the sources into the destination, then add
1203 the other source to the destination.
1205 Carefully select which source to copy to the destination; a naive
1206 implementation will waste a byte when the source classes are different
1207 and the destination is an address register. Selecting the lowest
1208 cost register copy will optimize this sequence. */
1209 if (REGNO_REG_CLASS (true_regnum (operands[1]))
1210 == REGNO_REG_CLASS (true_regnum (operands[0])))
1211 return \"mov %1,%0\;add %2,%0\";
1212 return \"mov %2,%0\;add %1,%0\";
1217 [(set_attr "timings" "11,11,11,11,11,22")]
1220 ;; ----------------------------------------------------------------------
1221 ;; SUBTRACT INSTRUCTIONS
1222 ;; ----------------------------------------------------------------------
1224 (define_expand "subsi3"
1225 [(parallel [(set (match_operand:SI 0 "register_operand")
1226 (minus:SI (match_operand:SI 1 "register_operand")
1227 (match_operand:SI 2 "nonmemory_operand")))
1228 (clobber (reg:CC CC_REG))
1234 (define_insn "*am33_subsi3"
1235 [(set (match_operand:SI 0 "register_operand" "=dax,!dax")
1236 (minus:SI (match_operand:SI 1 "register_operand" "0,dax")
1237 (match_operand:SI 2 "nonmemory_operand" "daxi,dax")))
1238 (clobber (reg:CC CC_REG))
1243 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1244 return \"sub %2,%0\";
1247 enum reg_class src1_class, src2_class, dst_class;
1249 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
1250 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
1251 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
1253 /* If no extended registers are used, then the best way to handle
1254 this is to copy the first source operand into the destination
1255 and emit a two address subtraction. */
1256 if (src1_class != EXTENDED_REGS
1257 && src2_class != EXTENDED_REGS
1258 && dst_class != EXTENDED_REGS
1259 && true_regnum (operands[0]) != true_regnum (operands[2]))
1260 return \"mov %1,%0\;sub %2,%0\";
1261 return \"sub %2,%1,%0\";
1264 [(set_attr "timings" "11,22")]
1267 (define_insn "*mn10300_subsi3"
1268 [(set (match_operand:SI 0 "register_operand" "=dax")
1269 (minus:SI (match_operand:SI 1 "register_operand" "0")
1270 (match_operand:SI 2 "nonmemory_operand" "daxi")))
1271 (clobber (reg:CC CC_REG))
1275 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1276 (const_int 11) (const_int 22)))]
1279 (define_expand "negsi2"
1280 [(set (match_operand:SI 0 "register_operand")
1281 (neg:SI (match_operand:SI 1 "register_operand")))]
1285 rtx target = gen_reg_rtx (SImode);
1287 emit_move_insn (target, const0_rtx);
1288 emit_insn (gen_subsi3 (target, target, operands[1]));
1289 emit_move_insn (operands[0], target);
1293 ;; ----------------------------------------------------------------------
1294 ;; MULTIPLY INSTRUCTIONS
1295 ;; ----------------------------------------------------------------------
1297 (define_insn "mulsidi3"
1298 [(set (match_operand:DI 0 "register_operand" "=dax")
1299 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
1300 (sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))
1301 (clobber (reg:CC CC_REG))
1305 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1306 (const_int 24) (const_int 23)))]
1309 (define_insn "umulsidi3"
1310 [(set (match_operand:DI 0 "register_operand" "=dax")
1311 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
1312 (zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))
1313 (clobber (reg:CC CC_REG))
1316 "mulu %1,%2,%H0,%L0"
1317 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1318 (const_int 24) (const_int 23)))]
1321 (define_expand "mulsi3"
1322 [(parallel [(set (match_operand:SI 0 "register_operand")
1323 (mult:SI (match_operand:SI 1 "register_operand")
1324 (match_operand:SI 2 "register_operand")))
1325 (clobber (reg:CC CC_REG))
1331 (define_insn "*am33_mulsi3"
1332 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1333 (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
1334 (match_operand:SI 2 "nonmemory_operand" "dx,daxi")))
1335 (clobber (reg:CC CC_REG))
1340 if (TARGET_MULT_BUG)
1341 return \"nop\;nop\;mul %2,%0\";
1343 return \"mul %2,%0\";
1345 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1348 (define_insn "*mn10300_mulsi3"
1349 [(set (match_operand:SI 0 "register_operand" "=dx")
1350 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1351 (match_operand:SI 2 "register_operand" "dx")))
1352 (clobber (reg:CC CC_REG))
1357 if (TARGET_MULT_BUG)
1358 return \"nop\;nop\;mul %2,%0\";
1360 return \"mul %2,%0\";
1362 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1363 (const_int 24) (const_int 23)))]
1366 (define_expand "udivmodsi4"
1367 [(parallel [(set (match_operand:SI 0 "register_operand")
1368 (udiv:SI (match_operand:SI 1 "general_operand")
1369 (match_operand:SI 2 "general_operand")))
1370 (set (match_operand:SI 3 "register_operand")
1371 (umod:SI (match_dup 1) (match_dup 2)))
1372 (clobber (reg:CC CC_REG))
1377 if (!register_operand (operands[1], SImode))
1378 operands[1] = copy_to_mode_reg (SImode, operands[1]);
1379 if (!register_operand (operands[2], SImode))
1380 operands[2] = copy_to_mode_reg (SImode, operands[2]);
1384 (define_insn "*udivmodsi4"
1385 [(set (match_operand:SI 0 "register_operand" "=dx")
1386 (udiv:SI (match_operand:SI 1 "register_operand" "0")
1387 (match_operand:SI 2 "register_operand" "dx")))
1388 (set (match_operand:SI 3 "register_operand" "=&d")
1389 (umod:SI (match_dup 1) (match_dup 2)))
1390 (clobber (reg:CC CC_REG))
1395 output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
1397 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1398 return \"divu %2,%0\";
1400 return \"divu %2,%0\;mov mdr,%3\";
1402 ;; Timings: AM33 AM34
1407 ;; --------------------
1408 ;; total 41/42 45/46 (worst case sceanario)
1409 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1410 (const_int 4546) (const_int 4142)))]
1413 (define_insn "divmodsi4"
1414 [(set (match_operand:SI 0 "register_operand" "=dx")
1415 (div:SI (match_operand:SI 1 "register_operand" "0")
1416 (match_operand:SI 2 "register_operand" "dx")))
1417 (set (match_operand:SI 3 "register_operand" "=d")
1418 (mod:SI (match_dup 1) (match_dup 2)))
1419 (clobber (reg:CC CC_REG))
1424 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1425 return \"ext %0\;div %2,%0\";
1427 return \"ext %0\;div %2,%0\;mov mdr,%3\";
1429 ;; Timings: AM33 AM34
1432 ;; --------------------
1433 ;; total 39/40 43/44 (worst case sceanario)
1434 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1435 (const_int 4344) (const_int 3940)))]
1439 ;; ----------------------------------------------------------------------
1441 ;; ----------------------------------------------------------------------
1443 (define_expand "andsi3"
1444 [(parallel [(set (match_operand:SI 0 "register_operand")
1445 (and:SI (match_operand:SI 1 "register_operand")
1446 (match_operand:SI 2 "nonmemory_operand")))
1447 (clobber (reg:CC CC_REG))
1453 (define_insn "*am33_andsi3"
1454 [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
1455 (and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
1456 (match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))
1457 (clobber (reg:CC CC_REG))
1461 if (CONST_INT_P (operands[2]))
1462 switch (INTVAL (operands[2]))
1464 case 0xff: return "extbu %0";
1465 case 0xffff: return "exthu %0";
1466 case 0x7fffffff: return "add %0, %0; lsr 1, %0";
1467 case 0x3fffffff: return "asl2 %0; lsr 2, %0";
1468 case 0x1fffffff: return "add %0, %0; asl2 %0; lsr 3, %0";
1469 case 0x0fffffff: return "asl2 %0; asl2 %0; lsr 4, %0";
1470 case 0xfffffffe: return "lsr 1, %0; add %0, %0";
1471 case 0xfffffffc: return "lsr 2, %0; asl2 %0";
1472 case 0xfffffff8: return "lsr 3, %0; add %0, %0; asl2 %0";
1473 case 0xfffffff0: return "lsr 4, %0; asl2 %0; asl2 %0";
1476 if (REG_P (operands[2]) && REG_P (operands[1])
1477 && true_regnum (operands[0]) != true_regnum (operands[1])
1478 && true_regnum (operands[0]) != true_regnum (operands[2])
1479 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1480 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1481 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1482 return "mov %1, %0; and %2, %0";
1483 if (REG_P (operands[2]) && REG_P (operands[1])
1484 && true_regnum (operands[0]) != true_regnum (operands[1])
1485 && true_regnum (operands[0]) != true_regnum (operands[2]))
1486 return "and %1, %2, %0";
1487 if (REG_P (operands[2]) && REG_P (operands[0])
1488 && true_regnum (operands[2]) == true_regnum (operands[0]))
1489 return "and %1, %0";
1491 return "and %2, %0";
1493 [(set_attr "timings" "33")]
1496 (define_insn "*mn10300_andsi3"
1497 [(set (match_operand:SI 0 "register_operand" "=dx,dx")
1498 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1499 (match_operand:SI 2 "nonmemory_operand" "N,dxi")))
1500 (clobber (reg:CC CC_REG))
1504 if (CONST_INT_P (operands[2]))
1505 switch (INTVAL (operands[2]))
1507 case 0xff: return "extbu %0";
1508 case 0xffff: return "exthu %0";
1509 case 0x7fffffff: return "add %0, %0; lsr 1, %0";
1510 case 0x3fffffff: return "asl2 %0; lsr 2, %0";
1511 case 0x1fffffff: return "add %0, %0; asl2 %0; lsr 3, %0";
1512 case 0x0fffffff: return "asl2 %0; asl2 %0; lsr 4, %0";
1513 case 0xfffffffe: return "lsr 1, %0; add %0, %0";
1514 case 0xfffffffc: return "lsr 2, %0; asl2 %0";
1515 case 0xfffffff8: return "lsr 3, %0; add %0, %0; asl2 %0";
1516 case 0xfffffff0: return "lsr 4, %0; asl2 %0; asl2 %0";
1519 return "and %2, %0";
1521 [(set_attr "timings" "33")]
1524 ;; ----------------------------------------------------------------------
1526 ;; ----------------------------------------------------------------------
1528 (define_expand "iorsi3"
1529 [(parallel [(set (match_operand:SI 0 "register_operand")
1530 (ior:SI (match_operand:SI 1 "register_operand")
1531 (match_operand:SI 2 "nonmemory_operand")))
1532 (clobber (reg:CC CC_REG))
1538 (define_insn "*am33_iorsi3"
1539 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1540 (ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
1541 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))
1542 (clobber (reg:CC CC_REG))
1547 if (REG_P (operands[2]) && REG_P (operands[1])
1548 && true_regnum (operands[0]) != true_regnum (operands[1])
1549 && true_regnum (operands[0]) != true_regnum (operands[2])
1550 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1551 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1552 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1553 return \"mov %1,%0\;or %2,%0\";
1554 if (REG_P (operands[2]) && REG_P (operands[1])
1555 && true_regnum (operands[0]) != true_regnum (operands[1])
1556 && true_regnum (operands[0]) != true_regnum (operands[2]))
1557 return \"or %1,%2,%0\";
1558 if (REG_P (operands[2]) && REG_P (operands[0])
1559 && true_regnum (operands[2]) == true_regnum (operands[0]))
1560 return \"or %1,%0\";
1561 return \"or %2,%0\";
1563 [(set_attr "timings" "22")]
1566 (define_insn "*mn10300_iorsi3"
1567 [(set (match_operand:SI 0 "register_operand" "=dx")
1568 (ior:SI (match_operand:SI 1 "register_operand" "%0")
1569 (match_operand:SI 2 "nonmemory_operand" "dxi")))
1570 (clobber (reg:CC CC_REG))
1574 [(set_attr "timings" "33")]
1577 ;; ----------------------------------------------------------------------
1579 ;; ----------------------------------------------------------------------
1581 (define_expand "xorsi3"
1582 [(parallel [(set (match_operand:SI 0 "register_operand")
1583 (xor:SI (match_operand:SI 1 "register_operand")
1584 (match_operand:SI 2 "nonmemory_operand")))
1585 (clobber (reg:CC CC_REG))
1591 (define_insn "*am33_xorsi3"
1592 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1593 (xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
1594 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))
1595 (clobber (reg:CC CC_REG))
1600 if (REG_P (operands[2]) && REG_P (operands[1])
1601 && true_regnum (operands[0]) != true_regnum (operands[1])
1602 && true_regnum (operands[0]) != true_regnum (operands[2])
1603 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1604 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1605 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1606 return \"mov %1,%0\;xor %2,%0\";
1607 if (REG_P (operands[2]) && REG_P (operands[1])
1608 && true_regnum (operands[0]) != true_regnum (operands[1])
1609 && true_regnum (operands[0]) != true_regnum (operands[2]))
1610 return \"xor %1,%2,%0\";
1611 if (REG_P (operands[2]) && REG_P (operands[0])
1612 && true_regnum (operands[2]) == true_regnum (operands[0]))
1613 return \"xor %1,%0\";
1614 return \"xor %2,%0\";
1616 [(set_attr "timings" "22")]
1619 (define_insn "*mn10300_xorsi3"
1620 [(set (match_operand:SI 0 "register_operand" "=dx")
1621 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1622 (match_operand:SI 2 "nonmemory_operand" "dxi")))
1623 (clobber (reg:CC CC_REG))
1627 [(set_attr "timings" "11")]
1630 ;; ----------------------------------------------------------------------
1632 ;; ----------------------------------------------------------------------
1634 (define_expand "one_cmplsi2"
1635 [(parallel [(set (match_operand:SI 0 "register_operand")
1636 (not:SI (match_operand:SI 1 "register_operand")))
1637 (clobber (reg:CC CC_REG))
1643 (define_insn "*am33_cmplsi2"
1644 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1645 (not:SI (match_operand:SI 1 "register_operand" "0,0")))
1646 (clobber (reg:CC CC_REG))
1652 (define_insn "*mn10300_cmplsi2"
1653 [(set (match_operand:SI 0 "register_operand" "=dx")
1654 (not:SI (match_operand:SI 1 "register_operand" "0")))
1655 (clobber (reg:CC CC_REG))
1661 ;; -----------------------------------------------------------------
1663 ;; -----------------------------------------------------------------
1666 ;; These set/clear memory in byte sized chunks.
1668 ;; They are no smaller/faster than loading the value into a register
1669 ;; and storing the register, but they don't need a scratch register
1670 ;; which may allow for better code generation.
1671 (define_insn "*byte_clear"
1672 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int 0))
1673 (clobber (reg:CC CC_REG))
1675 "(! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0])
1676 && GET_CODE (XEXP (operands[0], 0)) != PLUS)"
1680 [(set_attr_alternative "timings"
1681 [(if_then_else (eq_attr "cpu" "am34")
1682 (const_int 66) (const_int 77))
1688 (define_insn "*byte_set"
1689 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1))
1690 (clobber (reg:CC CC_REG))
1692 "(! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0])
1693 && GET_CODE (XEXP (operands[0], 0)) != PLUS)"
1697 [(set_attr_alternative "timings"
1698 [(if_then_else (eq_attr "cpu" "am34")
1699 (const_int 66) (const_int 77))
1705 (define_insn "*bit_clear1"
1706 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1708 (and:SI (subreg:SI (match_dup 0) 0)
1709 (match_operand:SI 1 "const_int_operand" "i,i")) 0))
1710 (clobber (reg:CC CC_REG))
1716 [(set_attr_alternative "timings"
1717 [(if_then_else (eq_attr "cpu" "am34")
1718 (const_int 66) (const_int 77))
1724 (define_insn "*bit_clear2"
1725 [(set (match_operand:QI 0 "memory_operand" "=R,T")
1728 (not:QI (match_operand:QI 1 "nonmemory_operand" "i,d"))))
1729 (clobber (reg:CC CC_REG))
1735 [(set_attr_alternative "timings"
1736 [(if_then_else (eq_attr "cpu" "am34")
1737 (const_int 66) (const_int 77))
1743 (define_insn "*bit_set"
1744 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1746 (ior:SI (subreg:SI (match_dup 0) 0)
1747 (match_operand:SI 1 "const_int_operand" "i,i")) 0))
1748 (clobber (reg:CC CC_REG))
1754 [(set_attr_alternative "timings"
1755 [(if_then_else (eq_attr "cpu" "am34")
1756 (const_int 66) (const_int 77))
1762 (define_expand "iorqi3"
1763 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand")
1764 (ior:QI (match_operand:QI 1 "nonimmediate_operand")
1765 (match_operand:QI 2 "nonmemory_operand")))
1766 (clobber (reg:CC CC_REG))
1772 (define_insn "*am33_iorqi3"
1773 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,r")
1774 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
1775 ;; This constraint should really be nonmemory_operand,
1776 ;; but making it general_operand, along with the
1777 ;; condition that not both input operands are MEMs,
1778 ;; helps combine do a better job.
1779 (match_operand:QI 2 "general_operand" "i,d,ir")))
1780 (clobber (reg:CC CC_REG))
1783 ((! MEM_P (operands[2])) || (! MEM_P (operands[1])))"
1788 [(set_attr_alternative "timings"
1789 [(if_then_else (eq_attr "cpu" "am34")
1790 (const_int 66) (const_int 77))
1797 (define_insn "*mn10300_iorqi3"
1798 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d")
1799 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
1800 ;; This constraint should really be nonmemory_operand,
1801 ;; but making it general_operand, along with the
1802 ;; condition that not both input operands are MEMs,
1803 ;; helps combine do a better job.
1804 (match_operand:QI 2 "general_operand" "i,d,id")))
1805 (clobber (reg:CC CC_REG))
1807 "(! MEM_P (operands[2])) || (! MEM_P (operands[1]))"
1812 [(set_attr_alternative "timings"
1813 [(if_then_else (eq_attr "cpu" "am34")
1814 (const_int 66) (const_int 77))
1821 (define_insn "*test_int_bitfield"
1822 [(set (reg:CC CC_REG)
1823 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
1824 (match_operand 1 "const_int_operand" "")
1825 (match_operand 2 "const_int_operand" ""))
1830 int len = INTVAL (operands[1]);
1831 int bit = INTVAL (operands[2]);
1842 xoperands[0] = operands[0];
1843 xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1844 output_asm_insn (\"btst %1,%0\", xoperands);
1849 (define_insn "*test_byte_bitfield"
1850 [(set (reg:CC CC_REG)
1851 (compare (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "R,dx")
1852 (match_operand 1 "const_int_operand" "")
1853 (match_operand 2 "const_int_operand" ""))
1855 "mn10300_mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
1858 int len = INTVAL (operands[1]);
1859 int bit = INTVAL (operands[2]);
1870 /* If the source operand is not a reg (i.e. it is memory), then extract the
1871 bits from mask that we actually want to test. Note that the mask will
1872 never cross a byte boundary. */
1873 if (!REG_P (operands[0]))
1877 else if (mask & 0xff00)
1878 mask = (mask >> 8) & 0xff;
1879 else if (mask & 0xff0000)
1880 mask = (mask >> 16) & 0xff;
1881 else if (mask & 0xff000000)
1882 mask = (mask >> 24) & 0xff;
1885 xoperands[0] = operands[0];
1886 xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1887 if (REG_P (operands[0]))
1888 output_asm_insn (\"btst %1,%0\", xoperands);
1890 output_asm_insn (\"btst %U1,%A0\", xoperands);
1893 [(set_attr_alternative "timings"
1894 [(if_then_else (eq_attr "cpu" "am34")
1895 (const_int 11) (const_int 22))
1896 (if_then_else (eq_attr "cpu" "am34")
1897 (const_int 44) (const_int 55))
1902 (define_insn "*bit_test"
1903 [(set (reg:CC CC_REG)
1904 (compare (and:SI (match_operand:SI 0 "register_operand" "dx")
1905 (match_operand:SI 1 "const_int_operand" ""))
1910 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1911 (const_int 11) (const_int 22)))]
1914 (define_insn "*subreg_bit_test"
1915 [(set (reg:CC CC_REG)
1917 (subreg:SI (match_operand:QI 0 "nonimmediate_operand" "R,dx") 0)
1918 (match_operand:SI 1 "const_8bit_operand" ""))
1924 [(set_attr_alternative "timings"
1925 [(if_then_else (eq_attr "cpu" "am34")
1926 (const_int 44) (const_int 55))
1927 (if_then_else (eq_attr "cpu" "am34")
1928 (const_int 11) (const_int 22))
1934 ;; ----------------------------------------------------------------------
1935 ;; COMPARE AND BRANCH INSTRUCTIONS
1936 ;; ----------------------------------------------------------------------
1938 ;; We expand the comparison into a single insn so that it will not be split
1940 (define_expand "cbranchsi4"
1943 (match_operator 0 "ordered_comparison_operator"
1944 [(match_operand:SI 1 "register_operand")
1945 (match_operand:SI 2 "nonmemory_operand")])
1946 (label_ref (match_operand 3 ""))
1952 (define_insn_and_split "*cbranchsi4_post_reload"
1954 (if_then_else (match_operator 3 "ordered_comparison_operator"
1955 [(match_operand:SI 0 "register_operand" "dax")
1956 (match_operand:SI 1 "nonmemory_operand" "daxi")])
1957 (label_ref (match_operand 2 "" ""))
1965 /* We construct the split by hand as otherwise the JUMP_LABEL
1966 attribute is not set correctly on the jump insn. */
1967 emit_insn (gen_cmpsi (operands[0], operands[1]));
1969 emit_jump_insn (gen_integer_conditional_branch
1970 (gen_rtx_fmt_ee (GET_CODE (operands[3]),
1972 gen_rtx_REG (CCmode, CC_REG),
1978 ;; Ordinarily, the cmp instruction will set the Z bit of cc0 to 1 if
1979 ;; its operands hold equal values, but the operands of a cmp
1980 ;; instruction must be distinct registers. In the case where we'd
1981 ;; like to compare a register to itself, we can achieve this effect
1982 ;; with a btst 0,d0 instead. (This will not alter the contents of d0
1983 ;; but will have the proper effect on cc0. Using d0 is arbitrary; any
1984 ;; data register would work.)
1986 ;; Even though the first alternative would be preferable if it can
1987 ;; possibly match, reload must not be given the opportunity to attempt
1988 ;; to use it. It assumes that such matches can only occur when one of
1989 ;; the operands is used for input and the other for output. Since
1990 ;; this is not the case, it abort()s. Indeed, such a reload cannot be
1991 ;; possibly satisfied, so just mark the alternative with a `!', so
1992 ;; that it is not considered by reload.
1994 (define_insn "cmpsi"
1995 [(set (reg:CC CC_REG)
1996 (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax,dax")
1997 (match_operand:SI 1 "nonmemory_operand" "*0,I,daxi")))]
2000 if (which_alternative == 0)
2001 return \"btst 0,d0\";
2002 if (which_alternative == 1)
2003 return mn10300_output_cmp (operands[0], insn);
2004 return \"cmp %1,%0\";
2006 [(set_attr_alternative "timings"
2008 (if_then_else (eq_attr "cpu" "am34")
2009 (const_int 11) (const_int 22))
2015 (define_insn "integer_conditional_branch"
2017 (if_then_else (match_operator 0 "comparison_operator"
2018 [(reg:CC CC_REG) (const_int 0)])
2019 (label_ref (match_operand 1 "" ""))
2025 (define_expand "cbranchsf4"
2028 (match_operator 0 "ordered_comparison_operator"
2029 [(match_operand:SF 1 "register_operand")
2030 (match_operand:SF 2 "nonmemory_operand")])
2031 (label_ref (match_operand 3 ""))
2037 (define_insn_and_split "*cbranchsf4_post_reload"
2039 (if_then_else (match_operator 3 "ordered_comparison_operator"
2040 [(match_operand:SF 0 "register_operand" "f")
2041 (match_operand:SF 1 "nonmemory_operand" "fF")])
2042 (label_ref (match_operand 2 "" ""))
2047 "&& reload_completed"
2050 /* We construct the split by hand as otherwise the JUMP_LABEL
2051 attribute is not set correctly on the jump insn. */
2052 emit_insn (gen_am33_cmpsf (operands[0], operands[1]));
2054 emit_jump_insn (gen_float_conditional_branch
2055 (gen_rtx_fmt_ee (GET_CODE (operands[3]),
2057 gen_rtx_REG (CC_FLOATmode, CC_REG),
2063 (define_insn "am33_cmpsf"
2064 [(set (reg:CC_FLOAT CC_REG)
2065 (compare:CC_FLOAT (match_operand:SF 0 "register_operand" "f")
2066 (match_operand:SF 1 "nonmemory_operand" "fF")))]
2069 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2070 (const_int 17) (const_int 25)))]
2073 (define_insn "float_conditional_branch"
2075 (if_then_else (match_operator 0 "comparison_operator"
2076 [(reg:CC_FLOAT CC_REG) (const_int 0)])
2077 (label_ref (match_operand 1 "" ""))
2081 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2082 (const_int 44) (const_int 33)))]
2085 ;; Unconditional and other jump instructions.
2089 (label_ref (match_operand 0 "" "")))]
2092 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2093 (const_int 11) (const_int 44)))]
2096 (define_insn "indirect_jump"
2097 [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
2100 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2101 (const_int 11) (const_int 33)))]
2104 (define_expand "builtin_setjmp_receiver"
2105 [(match_operand 0 "" "")]
2110 emit_insn (gen_GOTaddr2picreg ());
2115 (define_expand "casesi"
2116 [(match_operand:SI 0 "register_operand")
2117 (match_operand:SI 1 "immediate_operand")
2118 (match_operand:SI 2 "immediate_operand")
2119 (match_operand 3 "" "") (match_operand 4 "")]
2123 rtx table = gen_reg_rtx (SImode);
2124 rtx index = gen_reg_rtx (SImode);
2125 rtx addr = gen_reg_rtx (Pmode);
2128 emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
2129 emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1]))));
2130 test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]);
2131 emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4]));
2133 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
2134 emit_move_insn (addr, gen_rtx_MEM (SImode,
2135 gen_rtx_PLUS (SImode, table, index)));
2137 emit_insn (gen_addsi3 (addr, addr, table));
2139 emit_jump_insn (gen_tablejump (addr, operands[3]));
2143 (define_insn "tablejump"
2144 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
2145 (use (label_ref (match_operand 1 "" "")))]
2148 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2149 (const_int 11) (const_int 33)))]
2152 ;; Call subroutine with no return value.
2154 (define_expand "call"
2155 [(call (match_operand:QI 0 "general_operand")
2156 (match_operand:SI 1 "general_operand"))]
2159 rtx fn = XEXP (operands[0], 0);
2161 if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
2163 if (MN10300_GLOBAL_P (fn))
2165 /* The PLT code won't run on AM30, but then, there's no
2166 shared library support for AM30 either, so we just assume
2167 the linker is going to adjust all @PLT relocs to the
2169 emit_use (pic_offset_table_rtx);
2170 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
2173 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
2175 if (! call_address_operand (fn, VOIDmode))
2176 fn = force_reg (SImode, fn);
2178 XEXP (operands[0], 0) = fn;
2181 (define_insn "*call_internal"
2182 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S"))
2183 (match_operand:SI 1 "" ""))]
2188 [(set_attr_alternative "timings"
2189 [(if_then_else (eq_attr "cpu" "am34")
2190 (const_int 33) (const_int 44))
2191 (if_then_else (eq_attr "cpu" "am34")
2192 (const_int 55) (const_int 33))
2197 ;; Call subroutine, returning value in operand 0
2198 ;; (which must be a hard register).
2200 (define_expand "call_value"
2201 [(set (match_operand 0 "")
2202 (call (match_operand:QI 1 "general_operand")
2203 (match_operand:SI 2 "general_operand")))]
2206 rtx fn = XEXP (operands[1], 0);
2208 if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
2210 if (MN10300_GLOBAL_P (fn))
2212 /* The PLT code won't run on AM30, but then, there's no
2213 shared library support for AM30 either, so we just assume
2214 the linker is going to adjust all @PLT relocs to the
2216 emit_use (pic_offset_table_rtx);
2217 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
2220 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
2222 if (! call_address_operand (fn, VOIDmode))
2223 fn = force_reg (SImode, fn);
2225 XEXP (operands[1], 0) = fn;
2228 (define_insn "call_value_internal"
2229 [(set (match_operand 0 "" "")
2230 (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S"))
2231 (match_operand:SI 2 "" "")))]
2236 [(set_attr_alternative "timings"
2237 [(if_then_else (eq_attr "cpu" "am34")
2238 (const_int 33) (const_int 44))
2239 (if_then_else (eq_attr "cpu" "am34")
2240 (const_int 55) (const_int 33))
2245 (define_expand "untyped_call"
2246 [(parallel [(call (match_operand 0 "")
2248 (match_operand 1 "")
2249 (match_operand 2 "")])]
2255 emit_call_insn (gen_call (operands[0], const0_rtx));
2257 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2259 rtx set = XVECEXP (operands[2], 0, i);
2260 emit_move_insn (SET_DEST (set), SET_SRC (set));
2271 ;; ----------------------------------------------------------------------
2272 ;; EXTEND INSTRUCTIONS
2273 ;; ----------------------------------------------------------------------
2275 (define_expand "zero_extendqisi2"
2276 [(set (match_operand:SI 0 "register_operand")
2278 (match_operand:QI 1 "nonimmediate_operand")))]
2282 (define_insn "*zero_extendqisi2_am33"
2283 [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx,!dax,!dax,!dax")
2285 (match_operand:QI 1 "nonimmediate_operand" "0,dax,m,0,dax,m")))]
2294 [(set_attr_alternative "timings"
2297 (if_then_else (eq_attr "cpu" "am34")
2298 (const_int 13) (const_int 24))
2301 (if_then_else (eq_attr "cpu" "am34")
2302 (const_int 13) (const_int 24))
2307 (define_insn "*zero_extendqisi2_mn10300"
2308 [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx")
2310 (match_operand:QI 1 "nonimmediate_operand" "0,d,m")))]
2316 [(set_attr_alternative "timings"
2319 (if_then_else (eq_attr "cpu" "am34")
2320 (const_int 13) (const_int 24))
2325 (define_expand "zero_extendhisi2"
2326 [(set (match_operand:SI 0 "register_operand")
2328 (match_operand:HI 1 "nonimmediate_operand")))]
2332 (define_insn "*zero_extendhisi2_am33"
2333 [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx,!dax,!dax,!dax")
2335 (match_operand:HI 1 "nonimmediate_operand" "0,dax,m,0,dax,m")))]
2344 [(set_attr_alternative "timings"
2347 (if_then_else (eq_attr "cpu" "am34")
2348 (const_int 13) (const_int 24))
2351 (if_then_else (eq_attr "cpu" "am34")
2352 (const_int 13) (const_int 24))
2357 (define_insn "*zero_extendhisi2_mn10300"
2358 [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx")
2360 (match_operand:HI 1 "nonimmediate_operand" "0,dx,m")))]
2366 [(set_attr_alternative "timings"
2369 (if_then_else (eq_attr "cpu" "am34")
2370 (const_int 13) (const_int 24))
2375 ;;- sign extension instructions
2377 (define_expand "extendqisi2"
2378 [(set (match_operand:SI 0 "register_operand")
2380 (match_operand:QI 1 "register_operand")))]
2384 (define_insn "*extendqisi2_am33"
2385 [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax,!dax")
2387 (match_operand:QI 1 "register_operand" "0,dx,0,dax")))]
2394 [(set_attr "timings" "11,22,11,22")]
2397 (define_insn "*extendqisi2_mn10300"
2398 [(set (match_operand:SI 0 "register_operand" "=dx,dx")
2400 (match_operand:QI 1 "register_operand" "0,dx")))]
2405 [(set_attr "timings" "11,22")]
2408 (define_expand "extendhisi2"
2409 [(set (match_operand:SI 0 "register_operand")
2411 (match_operand:HI 1 "register_operand")))]
2415 (define_insn "*extendhisi2_am33"
2416 [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax,!dax")
2418 (match_operand:HI 1 "register_operand" "0,dax,0,dax")))]
2425 [(set_attr "timings" "11,22,11,22")]
2428 (define_insn "*extendhisi2_mn10300"
2429 [(set (match_operand:SI 0 "register_operand" "=dx,dx")
2431 (match_operand:HI 1 "register_operand" "0,dx")))]
2436 [(set_attr "timings" "11,22")]
2439 ;; ----------------------------------------------------------------------
2441 ;; ----------------------------------------------------------------------
2443 (define_expand "ashlsi3"
2444 [(parallel [(set (match_operand:SI 0 "register_operand")
2446 (match_operand:SI 1 "register_operand")
2447 (match_operand:QI 2 "nonmemory_operand")))
2448 (clobber (reg:CC CC_REG))
2454 (define_insn "*am33_ashlsi3"
2455 [(set (match_operand:SI 0 "register_operand" "=dax,dx,!dax")
2457 (match_operand:SI 1 "register_operand" "0,0,dax")
2458 (match_operand:QI 2 "nonmemory_operand" "J,dxi,dax")))
2459 (clobber (reg:CC CC_REG))
2464 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
2465 return \"add %0,%0\";
2467 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 2)
2470 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 3
2471 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
2472 return \"asl2 %0\;add %0,%0\";
2474 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 4
2475 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
2476 return \"asl2 %0\;asl2 %0\";
2478 if (true_regnum (operands[1]) == true_regnum (operands[0]))
2479 return \"asl %S2,%0\";
2481 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
2482 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
2483 && true_regnum (operands[0]) != true_regnum (operands[2]))
2484 return \"mov %1,%0\;asl %S2,%0\";
2485 return \"asl %2,%1,%0\";
2487 [(set_attr "timings" "22")]
2490 (define_insn "*mn10300_ashlsi3"
2491 [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
2493 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
2494 (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))
2495 (clobber (reg:CC CC_REG))
2504 [(set_attr "timings" "11,11,22,22,11")]
2507 (define_expand "lshrsi3"
2508 [(parallel [(set (match_operand:SI 0 "register_operand")
2510 (match_operand:SI 1 "register_operand")
2511 (match_operand:QI 2 "nonmemory_operand")))
2512 (clobber (reg:CC CC_REG))
2518 (define_insn "*am33_lshrsi3"
2519 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
2521 (match_operand:SI 1 "register_operand" "0,dax")
2522 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))
2523 (clobber (reg:CC CC_REG))
2528 if (true_regnum (operands[1]) == true_regnum (operands[0]))
2529 return \"lsr %S2,%0\";
2531 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
2532 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
2533 && true_regnum (operands[0]) != true_regnum (operands[2]))
2534 return \"mov %1,%0\;lsr %S2,%0\";
2535 return \"lsr %2,%1,%0\";
2537 [(set_attr "timings" "22")]
2540 (define_insn "*mn10300_lshrsi3"
2541 [(set (match_operand:SI 0 "register_operand" "=dx")
2543 (match_operand:SI 1 "register_operand" "0")
2544 (match_operand:QI 2 "nonmemory_operand" "dxi")))
2545 (clobber (reg:CC CC_REG))
2549 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2550 (const_int 11) (const_int 22)))]
2553 (define_expand "ashrsi3"
2554 [(parallel [(set (match_operand:SI 0 "register_operand")
2556 (match_operand:SI 1 "register_operand")
2557 (match_operand:QI 2 "nonmemory_operand")))
2558 (clobber (reg:CC CC_REG))
2564 (define_insn "*am33_ashrisi3"
2565 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
2567 (match_operand:SI 1 "register_operand" "0,dax")
2568 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))
2569 (clobber (reg:CC CC_REG))
2574 if (true_regnum (operands[1]) == true_regnum (operands[0]))
2575 return \"asr %S2,%0\";
2577 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
2578 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
2579 && true_regnum (operands[0]) != true_regnum (operands[2]))
2580 return \"mov %1,%0\;asr %S2,%0\";
2581 return \"asr %2,%1,%0\";
2583 [(set_attr "timings" "22")]
2586 (define_insn "*mn10300_ashrsi3"
2587 [(set (match_operand:SI 0 "register_operand" "=dx")
2589 (match_operand:SI 1 "register_operand" "0")
2590 (match_operand:QI 2 "nonmemory_operand" "dxi")))
2591 (clobber (reg:CC CC_REG))
2595 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2596 (const_int 11) (const_int 22)))]
2599 ;; ----------------------------------------------------------------------
2601 ;; ----------------------------------------------------------------------
2603 (define_insn "abssf2"
2604 [(set (match_operand:SF 0 "register_operand" "=f,f")
2605 (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
2610 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2611 (const_int 17) (const_int 14)))]
2614 (define_insn "negsf2"
2615 [(set (match_operand:SF 0 "register_operand" "=f,f")
2616 (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
2621 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2622 (const_int 17) (const_int 14)))]
2625 (define_expand "sqrtsf2"
2626 [(set (match_operand:SF 0 "register_operand" "")
2627 (sqrt:SF (match_operand:SF 1 "register_operand" "")))]
2628 "TARGET_AM33_2 && flag_unsafe_math_optimizations"
2630 rtx scratch = gen_reg_rtx (SFmode);
2631 emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
2632 emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
2637 (define_insn "rsqrtsf2"
2638 [(set (match_operand:SF 0 "register_operand" "=f,f")
2639 (div:SF (match_operand:SF 2 "const_1f_operand" "F,F")
2640 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))
2641 (clobber (reg:CC_FLOAT CC_REG))]
2646 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2647 (const_int 4753) (const_int 2327)))]
2650 (define_insn "addsf3"
2651 [(set (match_operand:SF 0 "register_operand" "=f,f")
2652 (plus:SF (match_operand:SF 1 "register_operand" "%0,f")
2653 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
2654 (clobber (reg:CC_FLOAT CC_REG))]
2659 [(set_attr_alternative "timings"
2660 [(if_then_else (eq_attr "cpu" "am34")
2661 (const_int 17) (const_int 14))
2662 (if_then_else (eq_attr "cpu" "am34")
2663 (const_int 17) (const_int 25))
2667 (define_insn "subsf3"
2668 [(set (match_operand:SF 0 "register_operand" "=f,f")
2669 (minus:SF (match_operand:SF 1 "register_operand" "0,f")
2670 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
2671 (clobber (reg:CC_FLOAT CC_REG))]
2676 [(set_attr_alternative "timings"
2677 [(if_then_else (eq_attr "cpu" "am34")
2678 (const_int 17) (const_int 14))
2679 (if_then_else (eq_attr "cpu" "am34")
2680 (const_int 17) (const_int 25))
2684 (define_insn "mulsf3"
2685 [(set (match_operand:SF 0 "register_operand" "=f,f")
2686 (mult:SF (match_operand:SF 1 "register_operand" "%0,f")
2687 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
2688 (clobber (reg:CC_FLOAT CC_REG))
2694 [(set_attr_alternative "timings"
2695 [(if_then_else (eq_attr "cpu" "am34")
2696 (const_int 17) (const_int 14))
2697 (if_then_else (eq_attr "cpu" "am34")
2698 (const_int 17) (const_int 25))
2702 (define_insn "divsf3"
2703 [(set (match_operand:SF 0 "register_operand" "=f,f")
2704 (div:SF (match_operand:SF 1 "register_operand" "0,f")
2705 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
2706 (clobber (reg:CC_FLOAT CC_REG))]
2711 [(set_attr_alternative "timings"
2712 [(if_then_else (eq_attr "cpu" "am34")
2713 (const_int 2531) (const_int 1216))
2714 (if_then_else (eq_attr "cpu" "am34")
2715 (const_int 2531) (const_int 1317))
2719 (define_insn "fmasf4"
2720 [(set (match_operand:SF 0 "register_operand" "=A")
2721 (fma:SF (match_operand:SF 1 "register_operand" "f")
2722 (match_operand:SF 2 "register_operand" "f")
2723 (match_operand:SF 3 "register_operand" "f")))
2724 (clobber (reg:CC_FLOAT CC_REG))
2727 "fmadd %1, %2, %3, %0"
2728 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2729 (const_int 17) (const_int 24)))]
2732 (define_insn "fmssf4"
2733 [(set (match_operand:SF 0 "register_operand" "=A")
2734 (fma:SF (match_operand:SF 1 "register_operand" "f")
2735 (match_operand:SF 2 "register_operand" "f")
2736 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
2737 (clobber (reg:CC_FLOAT CC_REG))
2740 "fmsub %1, %2, %3, %0"
2741 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2742 (const_int 17) (const_int 24)))]
2745 (define_insn "fnmasf4"
2746 [(set (match_operand:SF 0 "register_operand" "=A")
2747 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
2748 (match_operand:SF 2 "register_operand" "f")
2749 (match_operand:SF 3 "register_operand" "f")))
2750 (clobber (reg:CC_FLOAT CC_REG))
2753 "fnmadd %1, %2, %3, %0"
2754 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2755 (const_int 17) (const_int 24)))]
2758 (define_insn "fnmssf4"
2759 [(set (match_operand:SF 0 "register_operand" "=A")
2760 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
2761 (match_operand:SF 2 "register_operand" "f")
2762 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
2763 (clobber (reg:CC_FLOAT CC_REG))
2766 "fnmsub %1, %2, %3, %0"
2767 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2768 (const_int 17) (const_int 24)))]
2771 ;; ----------------------------------------------------------------------
2772 ;; PROLOGUE/EPILOGUE
2773 ;; ----------------------------------------------------------------------
2774 (define_expand "prologue"
2777 "mn10300_expand_prologue (); DONE;")
2779 (define_expand "epilogue"
2784 mn10300_expand_epilogue ();
2788 (define_insn "return_internal"
2793 [(set_attr "timings" "66")]
2796 ;; This insn restores the callee saved registers and does a return, it
2797 ;; can also deallocate stack space.
2798 (define_insn "return_internal_regs"
2800 (match_operand:SI 0 "const_int_operand" "i")
2805 fputs (\"\\tret \", asm_out_file);
2806 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
2807 fprintf (asm_out_file, \",%d\\n\", (int) INTVAL (operands[0]));
2810 ;; Assumes that there will be no more than 8 regs to pop
2811 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2812 (const_int 1414) (const_int 1313)))]
2815 ;; This instruction matches one generated by mn10300_gen_multiple_store()
2816 (define_insn "store_movm"
2817 [(match_parallel 0 "mn10300_store_multiple_operation"
2818 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])]
2822 fputs (\"\\tmovm \", asm_out_file);
2823 mn10300_print_reg_list (asm_out_file,
2824 mn10300_store_multiple_operation (operands[0],
2826 fprintf (asm_out_file, \",(sp)\\n\");
2829 ;; Assume that no more than 8 registers will be pushed.
2830 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2831 (const_int 99) (const_int 88)))]
2834 (define_insn "return"
2836 "mn10300_can_use_return_insn ()"
2839 rtx next = next_active_insn (insn);
2843 && GET_CODE (PATTERN (next)) == RETURN)
2848 [(set_attr "timings" "66")]
2851 ;; Try to combine consecutive updates of the stack pointer (or any
2852 ;; other register for that matter).
2854 [(parallel [(set (match_operand:SI 0 "register_operand" "=dxay")
2855 (plus:SI (match_dup 0)
2856 (match_operand 1 "const_int_operand" "")))
2857 (clobber (reg:CC CC_REG))
2859 (parallel [(set (match_dup 0)
2860 (plus:SI (match_dup 0)
2861 (match_operand 2 "const_int_operand" "")))
2862 (clobber (reg:CC CC_REG))
2868 operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
2869 return \"add %1,%0\";
2873 (define_expand "int_label"
2874 [(unspec [(match_operand:SI 0 "" "")] UNSPEC_INT_LABEL)]
2877 (define_expand "GOTaddr2picreg"
2881 /* It would be nice to be able to have int_label keep track of the
2882 counter and all, but if we add C code to it, we'll get an insn
2883 back, and we just want the pattern. */
2884 operands[0] = gen_int_label (GEN_INT (mn10300_unspec_int_label_counter++));
2886 emit_insn (gen_am33_loadPC (operands[0]));
2888 emit_insn (gen_mn10300_loadPC (operands[0]));
2889 emit_insn (gen_add_GOT_to_pic_reg (copy_rtx (operands[0])));
2894 (define_insn "am33_loadPC"
2896 [(set (reg:SI PIC_REG) (pc))
2897 (use (match_operand 0 "" ""))])]
2902 (define_insn_and_split "mn10300_loadPC"
2904 [(set (reg:SI PIC_REG) (pc))
2905 (use (match_operand 0 "" ""))])]
2908 "&& reload_completed"
2909 [(match_operand 0 "" "")]
2911 rtx sp_reg = gen_rtx_REG (SImode, SP_REG);
2912 int need_stack_space = (get_frame_size () == 0
2913 && crtl->outgoing_args_size == 0);
2915 if (need_stack_space)
2916 emit_insn (gen_addsi3 (sp_reg, sp_reg, GEN_INT (-4)));
2918 emit_insn (gen_call_next_insn (operands[0]));
2920 if (need_stack_space)
2921 emit_insn (gen_pop_pic_reg ());
2923 emit_move_insn (pic_offset_table_rtx, gen_rtx_MEM (SImode, sp_reg));
2928 (define_insn "call_next_insn"
2930 [(set (mem:SI (reg:SI SP_REG)) (pc))
2931 (use (match_operand 0 "" ""))])]
2934 [(set_attr "timings" "44")]
2937 (define_expand "add_GOT_to_pic_reg"
2938 [(parallel [(set (reg:SI PIC_REG)
2942 (unspec:SI [(minus:SI
2945 (const (match_operand:SI 0 "" ""))
2948 (clobber (reg:CC CC_REG))
2952 "operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);"
2955 (define_expand "add_GOT_to_any_reg"
2956 [(parallel [(set (match_operand:SI 0 "" "")
2958 (match_operand:SI 1 "" "")
2963 (const (match_operand:SI 2 "" ""))
2966 (clobber (reg:CC CC_REG))
2970 "operands[3] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);"