gcc/config/nds32/constraints.md

   1 ;; Constraint definitions of Andes NDS32 cpu for GNU compiler
   2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3 ;; Contributed by Andes Technology Corporation.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Check 16.8.7 Defining Machine-Specific Constraints for detail.
  22
  23 ;; NO contrains can be prefixed with: E F V X g i m n o p r s
  24 ;; Machine-dependent integer: I J K L M N O P
  25 ;; Machine-dependent floating: G H
  26
  27
  28 (define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
  29   "LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")
  30
  31 (define_register_constraint "l" "LOW_REGS"
  32   "LOW register class $r0 ~ $r7")
  33
  34 (define_register_constraint "d" "MIDDLE_REGS"
  35   "MIDDLE register class $r0 ~ $r11, $r16 ~ $r19")
  36
  37 (define_register_constraint "h" "HIGH_REGS"
  38   "HIGH register class $r12 ~ $r14, $r20 ~ $r31")
  39
  40
  41 (define_register_constraint "t" "R15_TA_REG"
  42   "Temporary Assist register $ta (i.e. $r15)")
  43
  44 (define_register_constraint "e" "R8_REG"
  45   "Function Entry register $r8)")
  46
  47 (define_register_constraint "k" "STACK_REG"
  48   "Stack register $sp")
  49
  50 (define_register_constraint "v" "R5_REG"
  51   "Register $r5")
  52
  53 (define_register_constraint "x" "FRAME_POINTER_REG"
  54   "Frame pointer register $fp")
  55
  56 (define_constraint "Iv00"
  57   "Constant value 0"
  58   (and (match_code "const_int")
  59        (match_test "ival == 0")))
  60
  61 (define_constraint "Iv01"
  62   "Constant value 1"
  63   (and (match_code "const_int")
  64        (match_test "ival == 1")))
  65
  66 (define_constraint "Iv02"
  67   "Constant value 2"
  68   (and (match_code "const_int")
  69        (match_test "ival == 2")))
  70
  71 (define_constraint "Iv04"
  72   "Constant value 4"
  73   (and (match_code "const_int")
  74        (match_test "ival == 4")))
  75
  76 (define_constraint "Iv08"
  77   "Constant value 8"
  78   (and (match_code "const_int")
  79        (match_test "ival == 8")))
  80
  81 (define_constraint "Iu01"
  82   "Unsigned immediate 1-bit value"
  83   (and (match_code "const_int")
  84        (match_test "ival == 1 || ival == 0")))
  85
  86 (define_constraint "Iu02"
  87   "Unsigned immediate 2-bit value"
  88   (and (match_code "const_int")
  89        (match_test "ival < (1 << 2) && ival >= 0")))
  90
  91 (define_constraint "Iu03"
  92   "Unsigned immediate 3-bit value"
  93   (and (match_code "const_int")
  94        (match_test "ival < (1 << 3) && ival >= 0")))
  95
  96 (define_constraint "In03"
  97   "Negative immediate 3-bit value in the range of -7 to 0"
  98   (and (match_code "const_int")
  99        (match_test "IN_RANGE (ival, -7, 0)")))
 100
 101 (define_constraint "Iu04"
 102   "Unsigned immediate 4-bit value"
 103   (and (match_code "const_int")
 104        (match_test "ival < (1 << 4) && ival >= 0")))
 105
 106 (define_constraint "Is05"
 107   "Signed immediate 5-bit value"
 108   (and (match_code "const_int")
 109        (match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
 110
 111 (define_constraint "Iu05"
 112   "Unsigned immediate 5-bit value"
 113   (and (match_code "const_int")
 114        (match_test "ival < (1 << 5) && ival >= 0")))
 115
 116 (define_constraint "In05"
 117   "Negative immediate 5-bit value in the range of -31 to 0"
 118   (and (match_code "const_int")
 119        (match_test "IN_RANGE (ival, -31, 0)")))
 120
 121 ;; Ip05 is special and dedicated for v3 movpi45 instruction.
 122 ;; movpi45 has imm5u field but the range is 16 ~ 47.
 123 (define_constraint "Ip05"
 124   "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
 125   (and (match_code "const_int")
 126        (match_test "ival < ((1 << 5) + 16)
 127                     && ival >= (0 + 16)
 128                     && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
 129
 130 (define_constraint "Iu06"
 131   "Unsigned immediate 6-bit value constraint for addri36.sp instruction"
 132   (and (match_code "const_int")
 133        (match_test "ival < (1 << 6)
 134                     && ival >= 0
 135                     && (ival % 4 == 0)
 136                     && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
 137
 138 (define_constraint "Iu08"
 139   "Unsigned immediate 8-bit value"
 140   (and (match_code "const_int")
 141        (match_test "ival < (1 << 8) && ival >= 0")))
 142
 143 (define_constraint "Iu09"
 144   "Unsigned immediate 9-bit value"
 145   (and (match_code "const_int")
 146        (match_test "ival < (1 << 9) && ival >= 0")))
 147
 148
 149 (define_constraint "Is08"
 150   "Signed immediate 8-bit value"
 151   (and (match_code "const_int")
 152        (match_test "ival < (1 << 7) && ival >= -(1 << 7)")))
 153
 154 (define_constraint "Is10"
 155   "Signed immediate 10-bit value"
 156   (and (match_code "const_int")
 157        (match_test "ival < (1 << 9) && ival >= -(1 << 9)")))
 158
 159 (define_constraint "Is11"
 160   "Signed immediate 11-bit value"
 161   (and (match_code "const_int")
 162        (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
 163
 164 (define_constraint "Is14"
 165   "Signed immediate 14-bit value"
 166   (and (match_code "const_int")
 167        (match_test "ival < (1 << 13) && ival >= -(1 << 13)")))
 168
 169 (define_constraint "Is15"
 170   "Signed immediate 15-bit value"
 171   (and (match_code "const_int")
 172        (match_test "ival < (1 << 14) && ival >= -(1 << 14)")))
 173
 174 (define_constraint "Iu15"
 175   "Unsigned immediate 15-bit value"
 176   (and (match_code "const_int")
 177        (match_test "ival < (1 << 15) && ival >= 0")))
 178
 179
 180 ;; Ic15 is special and dedicated for performance extension
 181 ;; 'bclr' (single-bit-clear) instruction.
 182 ;; It is used in andsi3 pattern and recognized for the immediate
 183 ;; which is NOT in the range of imm15u but OK for 'bclr' instruction.
 184 ;; (If the immediate value IS in the range of imm15u,
 185 ;;  we can directly use 'andi' instruction.)
 186 (define_constraint "Ic15"
 187   "A constant which is not in the range of imm15u but ok for bclr instruction"
 188   (and (match_code "const_int")
 189        (match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)")))
 190
 191 ;; Ie15 is special and dedicated for performance extension
 192 ;; 'bset' (single-bit-set) instruction.
 193 ;; It is used in iorsi3 pattern and recognized for the immediate
 194 ;; which is NOT in the range of imm15u but OK for 'bset' instruction.
 195 ;; (If the immediate value IS in the range of imm15u,
 196 ;;  we can directly use 'ori' instruction.)
 197 (define_constraint "Ie15"
 198   "A constant which is not in the range of imm15u but ok for bset instruction"
 199   (and (match_code "const_int")
 200        (match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)")))
 201
 202 ;; It15 is special and dedicated for performance extension
 203 ;; 'btgl' (single-bit-toggle) instruction.
 204 ;; It is used in xorsi3 pattern and recognized for the immediate
 205 ;; which is NOT in the range of imm15u but OK for 'btgl' instruction.
 206 ;; (If the immediate value IS in the range of imm15u,
 207 ;;  we can directly use 'xori' instruction.)
 208 (define_constraint "It15"
 209   "A constant which is not in the range of imm15u but ok for btgl instruction"
 210   (and (match_code "const_int")
 211        (match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)")))
 212
 213
 214 ;; Ii15 is special and dedicated for v3 isa
 215 ;; 'bitci' (bit-clear-immediate) instruction.
 216 ;; It is used in andsi3 pattern and recognized for the immediate whose
 217 ;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction.
 218 ;; For example, 'andi $r0,$r0,0xfffffffc' can be presented
 219 ;  with 'bitci $r0,$r0,3'.
 220 (define_constraint "Ii15"
 221   "A constant whose compliment value is in the range of imm15u
 222    and ok for bitci instruction"
 223   (and (match_code "const_int")
 224        (match_test "nds32_can_use_bitci_p (ival)")))
 225
 226
 227 (define_constraint "Is16"
 228   "Signed immediate 16-bit value"
 229   (and (match_code "const_int")
 230        (match_test "ival < (1 << 15) && ival >= -(1 << 15)")))
 231
 232 (define_constraint "Is17"
 233   "Signed immediate 17-bit value"
 234   (and (match_code "const_int")
 235        (match_test "ival < (1 << 16) && ival >= -(1 << 16)")))
 236
 237
 238 (define_constraint "Is19"
 239   "Signed immediate 19-bit value"
 240   (and (match_code "const_int")
 241        (match_test "ival < (1 << 18) && ival >= -(1 << 18)")))
 242
 243
 244 (define_constraint "Is20"
 245   "Signed immediate 20-bit value"
 246   (and (match_code "const_int")
 247        (match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
 248
 249
 250 (define_constraint "Ihig"
 251   "The immediate value that can be simply set high 20-bit"
 252   (and (match_code "const_int")
 253        (match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
 254
 255 (define_constraint "Izeb"
 256   "The immediate value 0xff"
 257   (and (match_code "const_int")
 258        (match_test "(ival == 0xff)")))
 259
 260 (define_constraint "Izeh"
 261   "The immediate value 0xffff"
 262   (and (match_code "const_int")
 263        (match_test "(ival == 0xffff)")))
 264
 265 (define_constraint "Ixls"
 266   "The immediate value 0x01"
 267   (and (match_code "const_int")
 268        (match_test "TARGET_EXT_PERF && (ival == 0x1)")))
 269
 270 (define_constraint "Ix11"
 271   "The immediate value 0x7ff"
 272   (and (match_code "const_int")
 273        (match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
 274
 275 (define_constraint "Ibms"
 276   "The immediate value with power of 2"
 277   (and (match_code "const_int")
 278        (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
 279                     && (IN_RANGE (exact_log2 (ival), 0, 7))")))
 280
 281 (define_constraint "Ifex"
 282   "The immediate value with power of 2 minus 1"
 283   (and (match_code "const_int")
 284        (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
 285                     && (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
 286
 287
 288 (define_memory_constraint "U33"
 289   "Memory constraint for 333 format"
 290   (and (match_code "mem")
 291        (match_test "nds32_mem_format (op) == ADDRESS_POST_INC_LO_REG_IMM3U
 292                     || nds32_mem_format (op) == ADDRESS_POST_MODIFY_LO_REG_IMM3U
 293                     || nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
 294
 295 (define_memory_constraint "U45"
 296   "Memory constraint for 45 format"
 297   (and (match_code "mem")
 298        (match_test "(nds32_mem_format (op) == ADDRESS_REG)
 299                     && (GET_MODE (op) == SImode)")))
 300
 301 (define_memory_constraint "Ufe"
 302   "Memory constraint for fe format"
 303   (and (match_code "mem")
 304        (match_test "nds32_mem_format (op) == ADDRESS_R8_IMM7U
 305                     && (GET_MODE (op) == SImode)")))
 306
 307 (define_memory_constraint "U37"
 308   "Memory constraint for 37 format"
 309   (and (match_code "mem")
 310        (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
 311                     || nds32_mem_format (op) == ADDRESS_FP_IMM7U)
 312                     && (GET_MODE (op) == SImode)")))
 313
 314
 315 (define_memory_constraint "Umw"
 316   "Memory constraint for lwm/smw"
 317   (and (match_code "mem")
 318        (match_test "nds32_valid_smw_lwm_base_p (op)")))
 319
 320 ;; ------------------------------------------------------------------------