1 /* Subroutines used for calculate rtx costs of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2015 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* ------------------------------------------------------------------------ */
25 #include "coretypes.h"
31 #include "optabs.h" /* For GEN_FCN. */
33 #include "tm-constrs.h"
35 /* ------------------------------------------------------------------------ */
38 nds32_rtx_costs_impl (rtx x
,
39 machine_mode mode ATTRIBUTE_UNUSED
,
41 int opno ATTRIBUTE_UNUSED
,
45 int code
= GET_CODE (x
);
47 /* According to 'speed', goto suitable cost model section. */
49 goto performance_cost
;
55 /* This is section for performance cost model. */
57 /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
58 We treat it as 4-cycle cost for each instruction
59 under performance consideration. */
63 /* For 'SET' rtx, we need to return false
64 so that it can recursively calculate costs. */
68 /* Used in combine.c as a marker. */
73 *total
= COSTS_N_INSNS (1);
80 *total
= COSTS_N_INSNS (7);
84 *total
= COSTS_N_INSNS (1);
92 /* This is section for size cost model. */
94 /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
95 We treat it as 4-byte cost for each instruction
96 under code size consideration. */
100 /* For 'SET' rtx, we need to return false
101 so that it can recursively calculate costs. */
105 /* Used in combine.c as a marker. */
110 /* All instructions involving constant operation
111 need to be considered for cost evaluation. */
112 if (outer_code
== SET
)
114 /* (set X imm5s), use movi55, 2-byte cost.
115 (set X imm20s), use movi, 4-byte cost.
116 (set X BIG_INT), use sethi/ori, 8-byte cost. */
117 if (satisfies_constraint_Is05 (x
))
118 *total
= COSTS_N_INSNS (1) - 2;
119 else if (satisfies_constraint_Is20 (x
))
120 *total
= COSTS_N_INSNS (1);
122 *total
= COSTS_N_INSNS (2);
124 else if (outer_code
== PLUS
|| outer_code
== MINUS
)
126 /* Possible addi333/subi333 or subi45/addi45, 2-byte cost.
127 General case, cost 1 instruction with 4-byte. */
128 if (satisfies_constraint_Iu05 (x
))
129 *total
= COSTS_N_INSNS (1) - 2;
131 *total
= COSTS_N_INSNS (1);
133 else if (outer_code
== ASHIFT
)
135 /* Possible slli333, 2-byte cost.
136 General case, cost 1 instruction with 4-byte. */
137 if (satisfies_constraint_Iu03 (x
))
138 *total
= COSTS_N_INSNS (1) - 2;
140 *total
= COSTS_N_INSNS (1);
142 else if (outer_code
== ASHIFTRT
|| outer_code
== LSHIFTRT
)
144 /* Possible srai45 or srli45, 2-byte cost.
145 General case, cost 1 instruction with 4-byte. */
146 if (satisfies_constraint_Iu05 (x
))
147 *total
= COSTS_N_INSNS (1) - 2;
149 *total
= COSTS_N_INSNS (1);
153 /* For other cases, simply set it 4-byte cost. */
154 *total
= COSTS_N_INSNS (1);
159 /* It requires high part and low part processing, set it 8-byte cost. */
160 *total
= COSTS_N_INSNS (2);
164 /* For other cases, generally we set it 4-byte cost
165 and stop resurively traversing. */
166 *total
= COSTS_N_INSNS (1);
174 nds32_address_cost_impl (rtx address
,
175 machine_mode mode ATTRIBUTE_UNUSED
,
176 addr_space_t as ATTRIBUTE_UNUSED
,
182 code
= GET_CODE (address
);
184 /* According to 'speed', goto suitable cost model section. */
186 goto performance_cost
;
191 /* This is section for performance cost model. */
193 /* FALLTHRU, currently we use same cost model as size_cost. */
196 /* This is section for size cost model. */
203 /* We encourage that rtx contains
204 POST_MODIFY/POST_INC/POST_DEC behavior. */
208 /* We can have gp-relative load/store for symbol_ref.
209 Have it 4-byte cost. */
210 return COSTS_N_INSNS (1);
213 /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
214 Have it 4-byte cost. */
215 return COSTS_N_INSNS (1);
218 /* Simply return 4-byte costs. */
219 return COSTS_N_INSNS (1);
222 /* We do not need to check if the address is a legitimate address,
223 because this hook is never called with an invalid address.
224 But we better check the range of
225 const_int value for cost, if it exists. */
226 plus0
= XEXP (address
, 0);
227 plus1
= XEXP (address
, 1);
229 if (REG_P (plus0
) && CONST_INT_P (plus1
))
231 /* If it is possible to be lwi333/swi333 form,
232 make it 2-byte cost. */
233 if (satisfies_constraint_Iu05 (plus1
))
234 return (COSTS_N_INSNS (1) - 2);
236 return COSTS_N_INSNS (1);
239 /* For other 'plus' situation, make it cost 4-byte. */
240 return COSTS_N_INSNS (1);
246 return COSTS_N_INSNS (4);
249 /* ------------------------------------------------------------------------ */