]>
git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/config/nds32/nds32-memory-manipulation.c
1 /* Auxiliary functions for expand movmem, setmem, cmpmem, load_multiple
2 and store_multiple pattern of Andes NDS32 cpu for GNU compiler
3 Copyright (C) 2012-2014 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* ------------------------------------------------------------------------ */
26 #include "coretypes.h"
29 #include "stor-layout.h"
34 #include "hard-reg-set.h"
35 #include "insn-config.h" /* Required by recog.h. */
36 #include "conditions.h"
38 #include "insn-attr.h" /* For DFA state_t. */
39 #include "insn-codes.h" /* For CODE_FOR_xxx. */
40 #include "reload.h" /* For push_reload(). */
50 #include "diagnostic-core.h"
53 #include "tm-constrs.h"
54 #include "optabs.h" /* For GEN_FCN. */
56 #include "target-def.h"
57 #include "langhooks.h" /* For add_builtin_function(). */
61 /* ------------------------------------------------------------------------ */
63 /* Functions to expand load_multiple and store_multiple.
64 They are auxiliary extern functions to help create rtx template.
65 Check nds32-multiple.md file for the patterns. */
67 nds32_expand_load_multiple (int base_regno
, int count
,
68 rtx base_addr
, rtx basemem
)
73 rtx new_addr
, mem
, reg
;
75 /* Create the pattern that is presented in nds32-multiple.md. */
77 result
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
79 for (par_index
= 0; par_index
< count
; par_index
++)
81 offset
= par_index
* 4;
82 /* 4-byte for loading data to each register. */
83 new_addr
= plus_constant (Pmode
, base_addr
, offset
);
84 mem
= adjust_automodify_address_nv (basemem
, SImode
,
86 reg
= gen_rtx_REG (SImode
, base_regno
+ par_index
);
88 XVECEXP (result
, 0, par_index
) = gen_rtx_SET (VOIDmode
, reg
, mem
);
95 nds32_expand_store_multiple (int base_regno
, int count
,
96 rtx base_addr
, rtx basemem
)
101 rtx new_addr
, mem
, reg
;
103 /* Create the pattern that is presented in nds32-multiple.md. */
105 result
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
107 for (par_index
= 0; par_index
< count
; par_index
++)
109 offset
= par_index
* 4;
110 /* 4-byte for storing data to memory. */
111 new_addr
= plus_constant (Pmode
, base_addr
, offset
);
112 mem
= adjust_automodify_address_nv (basemem
, SImode
,
114 reg
= gen_rtx_REG (SImode
, base_regno
+ par_index
);
116 XVECEXP (result
, 0, par_index
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
122 /* Function to move block memory content by
123 using load_multiple and store_multiple.
124 This is auxiliary extern function to help create rtx template.
125 Check nds32-multiple.md file for the patterns. */
127 nds32_expand_movmemqi (rtx dstmem
, rtx srcmem
, rtx total_bytes
, rtx alignment
)
129 HOST_WIDE_INT in_words
, out_words
;
130 rtx dst_base_reg
, src_base_reg
;
133 /* Because reduced-set regsiters has few registers
134 (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31'
135 cannot be used for register allocation),
136 using 8 registers (32 bytes) for moving memory block
137 may easily consume all of them.
138 It makes register allocation/spilling hard to work.
139 So we only allow maximum=4 registers (16 bytes) for
140 moving memory block under reduced-set registers. */
141 if (TARGET_REDUCED_REGS
)
146 /* 1. Total_bytes is integer for sure.
147 2. Alignment is integer for sure.
148 3. Maximum 4 or 8 registers, 4 * 4 = 16 bytes, 8 * 4 = 32 bytes.
149 4. Requires (n * 4) block size.
150 5. Requires 4-byte alignment. */
151 if (GET_CODE (total_bytes
) != CONST_INT
152 || GET_CODE (alignment
) != CONST_INT
153 || INTVAL (total_bytes
) > maximum_bytes
154 || INTVAL (total_bytes
) & 3
155 || INTVAL (alignment
) & 3)
158 dst_base_reg
= copy_to_mode_reg (SImode
, XEXP (dstmem
, 0));
159 src_base_reg
= copy_to_mode_reg (SImode
, XEXP (srcmem
, 0));
161 out_words
= in_words
= INTVAL (total_bytes
) / UNITS_PER_WORD
;
163 emit_insn (nds32_expand_load_multiple (0, in_words
, src_base_reg
, srcmem
));
164 emit_insn (nds32_expand_store_multiple (0, out_words
, dst_base_reg
, dstmem
));
166 /* Successfully create patterns, return 1. */
170 /* ------------------------------------------------------------------------ */