1 /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2022 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* ------------------------------------------------------------------------ */
23 #define IN_TARGET_CODE 1
27 #include "coretypes.h"
32 #include "tree-pass.h"
33 #include "stringpool.h"
38 #include "optabs.h" /* For GEN_FCN. */
42 #include "diagnostic-core.h"
43 #include "stor-layout.h"
49 #include "tm-constrs.h"
54 /* This file should be included last. */
55 #include "target-def.h"
57 /* ------------------------------------------------------------------------ */
59 /* This file is divided into five parts:
61 PART 1: Auxiliary static variable definitions and
62 target hook static variable definitions.
64 PART 2: Auxiliary static function definitions.
66 PART 3: Implement target hook stuff definitions.
68 PART 4: Implemet extern function definitions,
69 the prototype is in nds32-protos.h.
71 PART 5: Initialize target hook structure and definitions. */
73 /* ------------------------------------------------------------------------ */
75 /* PART 1: Auxiliary static variable definitions and
76 target hook static variable definitions. */
78 /* Define intrinsic register names.
79 Please refer to nds32_intrinsic.h file, the index is corresponding to
80 'enum nds32_intrinsic_registers' data type values.
81 NOTE that the base value starting from 1024. */
82 static const char * const nds32_intrinsic_register_names
[] =
240 /* Define instrinsic cctl names. */
241 static const char * const nds32_cctl_names
[] =
269 static const char * const nds32_dpref_names
[] =
279 /* Defining register allocation order for performance.
280 We want to allocate callee-saved registers after others.
281 It may be used by nds32_adjust_reg_alloc_order(). */
282 static const int nds32_reg_alloc_order_for_speed
[] =
284 0, 1, 2, 3, 4, 5, 16, 17,
285 18, 19, 20, 21, 22, 23, 24, 25,
286 26, 27, 6, 7, 8, 9, 10, 11,
290 /* Defining target-specific uses of __attribute__. */
291 static const struct attribute_spec nds32_attribute_table
[] =
293 /* Syntax: { name, min_len, max_len, decl_required, type_required,
294 function_type_required, affects_type_identity, handler,
297 /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */
298 { "interrupt", 1, 64, false, false, false, false, NULL
, NULL
},
299 /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */
300 { "exception", 1, 8, false, false, false, false, NULL
, NULL
},
301 /* Argument is user's interrupt numbers. The vector number is always 0. */
302 { "reset", 1, 1, false, false, false, false, NULL
, NULL
},
304 /* The attributes describing isr nested type. */
305 { "nested", 0, 0, false, false, false, false, NULL
, NULL
},
306 { "not_nested", 0, 0, false, false, false, false, NULL
, NULL
},
307 { "nested_ready", 0, 0, false, false, false, false, NULL
, NULL
},
308 { "critical", 0, 0, false, false, false, false, NULL
, NULL
},
310 /* The attributes describing isr register save scheme. */
311 { "save_all", 0, 0, false, false, false, false, NULL
, NULL
},
312 { "partial_save", 0, 0, false, false, false, false, NULL
, NULL
},
314 /* The attributes used by reset attribute. */
315 { "nmi", 1, 1, false, false, false, false, NULL
, NULL
},
316 { "warm", 1, 1, false, false, false, false, NULL
, NULL
},
318 /* The attributes describing isr security level. */
319 { "secure", 1, 1, false, false, false, false, NULL
, NULL
},
321 /* The attribute telling no prologue/epilogue. */
322 { "naked", 0, 0, false, false, false, false, NULL
, NULL
},
324 /* The attribute is used to tell this function to be ROM patch. */
325 { "indirect_call",0, 0, false, false, false, false, NULL
, NULL
},
327 /* FOR BACKWARD COMPATIBILITY,
328 this attribute also tells no prologue/epilogue. */
329 { "no_prologue", 0, 0, false, false, false, false, NULL
, NULL
},
331 /* The last attribute spec is set to be NULL. */
332 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
336 /* ------------------------------------------------------------------------ */
338 /* PART 2: Auxiliary static function definitions. */
340 /* Function to save and restore machine-specific function data. */
341 static struct machine_function
*
342 nds32_init_machine_status (void)
344 struct machine_function
*machine
;
345 machine
= ggc_cleared_alloc
<machine_function
> ();
347 /* Initially assume this function does not use __builtin_eh_return. */
348 machine
->use_eh_return_p
= 0;
350 /* Initially assume this function needs prologue/epilogue. */
351 machine
->naked_p
= 0;
353 /* Initially assume this function does NOT use fp_as_gp optimization. */
354 machine
->fp_as_gp_p
= 0;
356 /* Initially this function is not under strictly aligned situation. */
357 machine
->strict_aligned_p
= 0;
359 /* Initially this function has no naked and no_prologue attributes. */
360 machine
->attr_naked_p
= 0;
361 machine
->attr_no_prologue_p
= 0;
366 /* Function to compute stack frame size and
367 store into cfun->machine structure. */
369 nds32_compute_stack_frame (void)
375 /* Because nds32_compute_stack_frame() will be called from different place,
376 everytime we enter this function, we have to assume this function
377 needs prologue/epilogue. */
378 cfun
->machine
->naked_p
= 0;
380 /* We need to mark whether this function has naked and no_prologue
381 attribute so that we can distinguish the difference if users applies
382 -mret-in-naked-func option. */
383 cfun
->machine
->attr_naked_p
384 = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
))
386 cfun
->machine
->attr_no_prologue_p
387 = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl
))
390 /* If __builtin_eh_return is used, we better have frame pointer needed
391 so that we can easily locate the stack slot of return address. */
392 if (crtl
->calls_eh_return
)
394 frame_pointer_needed
= 1;
396 /* We need to mark eh data registers that need to be saved
398 cfun
->machine
->eh_return_data_first_regno
= EH_RETURN_DATA_REGNO (0);
399 for (r
= 0; EH_RETURN_DATA_REGNO (r
) != INVALID_REGNUM
; r
++)
400 cfun
->machine
->eh_return_data_last_regno
= r
;
402 cfun
->machine
->eh_return_data_regs_size
403 = 4 * (cfun
->machine
->eh_return_data_last_regno
404 - cfun
->machine
->eh_return_data_first_regno
406 cfun
->machine
->use_eh_return_p
= 1;
410 /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we
411 do not need to handle __builtin_eh_return case in this function. */
412 cfun
->machine
->eh_return_data_first_regno
= SP_REGNUM
;
413 cfun
->machine
->eh_return_data_last_regno
= SP_REGNUM
;
415 cfun
->machine
->eh_return_data_regs_size
= 0;
416 cfun
->machine
->use_eh_return_p
= 0;
419 /* Get variadic arguments size to prepare pretend arguments and
420 we will push them into stack at prologue by ourself. */
421 cfun
->machine
->va_args_size
= crtl
->args
.pretend_args_size
;
422 if (cfun
->machine
->va_args_size
!= 0)
424 cfun
->machine
->va_args_first_regno
425 = NDS32_GPR_ARG_FIRST_REGNUM
426 + NDS32_MAX_GPR_REGS_FOR_ARGS
427 - (crtl
->args
.pretend_args_size
/ UNITS_PER_WORD
);
428 cfun
->machine
->va_args_last_regno
429 = NDS32_GPR_ARG_FIRST_REGNUM
+ NDS32_MAX_GPR_REGS_FOR_ARGS
- 1;
433 cfun
->machine
->va_args_first_regno
= SP_REGNUM
;
434 cfun
->machine
->va_args_last_regno
= SP_REGNUM
;
437 /* Important: We need to make sure that varargs area is 8-byte alignment. */
438 block_size
= cfun
->machine
->va_args_size
;
439 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
441 cfun
->machine
->va_args_area_padding_bytes
442 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
) - block_size
;
445 /* Get local variables, incoming variables, and temporary variables size.
446 Note that we need to make sure it is 8-byte alignment because
447 there may be no padding bytes if we are using LRA. */
448 cfun
->machine
->local_size
= NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ());
450 /* Get outgoing arguments size. */
451 cfun
->machine
->out_args_size
= crtl
->outgoing_args_size
;
453 /* If $fp value is required to be saved on stack, it needs 4 bytes space.
454 Check whether $fp is ever live. */
455 cfun
->machine
->fp_size
= (df_regs_ever_live_p (FP_REGNUM
)) ? 4 : 0;
457 /* If $gp value is required to be saved on stack, it needs 4 bytes space.
458 Check whether we are using PIC code genration. */
459 cfun
->machine
->gp_size
=
460 (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
)) ? 4 : 0;
462 /* If $lp value is required to be saved on stack, it needs 4 bytes space.
463 Check whether $lp is ever live. */
464 cfun
->machine
->lp_size
465 = (flag_always_save_lp
|| df_regs_ever_live_p (LP_REGNUM
)) ? 4 : 0;
467 /* Initially there is no padding bytes. */
468 cfun
->machine
->callee_saved_area_gpr_padding_bytes
= 0;
470 /* Calculate the bytes of saving callee-saved registers on stack. */
471 cfun
->machine
->callee_saved_gpr_regs_size
= 0;
472 cfun
->machine
->callee_saved_first_gpr_regno
= SP_REGNUM
;
473 cfun
->machine
->callee_saved_last_gpr_regno
= SP_REGNUM
;
474 cfun
->machine
->callee_saved_fpr_regs_size
= 0;
475 cfun
->machine
->callee_saved_first_fpr_regno
= SP_REGNUM
;
476 cfun
->machine
->callee_saved_last_fpr_regno
= SP_REGNUM
;
478 /* Currently, there is no need to check $r28~$r31
479 because we will save them in another way. */
480 for (r
= 0; r
< 28; r
++)
482 if (NDS32_REQUIRED_CALLEE_SAVED_P (r
))
484 /* Mark the first required callee-saved register
485 (only need to set it once).
486 If first regno == SP_REGNUM, we can tell that
487 it is the first time to be here. */
488 if (cfun
->machine
->callee_saved_first_gpr_regno
== SP_REGNUM
)
489 cfun
->machine
->callee_saved_first_gpr_regno
= r
;
490 /* Mark the last required callee-saved register. */
491 cfun
->machine
->callee_saved_last_gpr_regno
= r
;
495 /* Recording fpu callee-saved register. */
496 if (TARGET_HARD_FLOAT
)
498 for (r
= NDS32_FIRST_FPR_REGNUM
; r
< NDS32_LAST_FPR_REGNUM
; r
++)
500 if (NDS32_REQUIRED_CALLEE_SAVED_P (r
))
502 /* Mark the first required callee-saved register. */
503 if (cfun
->machine
->callee_saved_first_fpr_regno
== SP_REGNUM
)
505 /* Make first callee-saved number is even,
506 bacause we use doubleword access, and this way
507 promise 8-byte alignemt. */
508 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r
))
509 cfun
->machine
->callee_saved_first_fpr_regno
= r
- 1;
511 cfun
->machine
->callee_saved_first_fpr_regno
= r
;
513 cfun
->machine
->callee_saved_last_fpr_regno
= r
;
517 /* Make last callee-saved register number is odd,
518 we hope callee-saved register is even. */
519 int last_fpr
= cfun
->machine
->callee_saved_last_fpr_regno
;
520 if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr
))
521 cfun
->machine
->callee_saved_last_fpr_regno
++;
524 /* Check if this function can omit prologue/epilogue code fragment.
525 If there is 'no_prologue'/'naked'/'secure' attribute in this function,
526 we can set 'naked_p' flag to indicate that
527 we do not have to generate prologue/epilogue.
528 Or, if all the following conditions succeed,
529 we can set this function 'naked_p' as well:
530 condition 1: first_regno == last_regno == SP_REGNUM,
531 which means we do not have to save
532 any callee-saved registers.
533 condition 2: Both $lp and $fp are NOT live in this function,
534 which means we do not need to save them and there
536 condition 3: There is no local_size, which means
537 we do not need to adjust $sp. */
538 if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl
))
539 || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
))
540 || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl
))
541 || (cfun
->machine
->callee_saved_first_gpr_regno
== SP_REGNUM
542 && cfun
->machine
->callee_saved_last_gpr_regno
== SP_REGNUM
543 && cfun
->machine
->callee_saved_first_fpr_regno
== SP_REGNUM
544 && cfun
->machine
->callee_saved_last_fpr_regno
== SP_REGNUM
545 && !df_regs_ever_live_p (FP_REGNUM
)
546 && !df_regs_ever_live_p (LP_REGNUM
)
547 && cfun
->machine
->local_size
== 0
550 /* Set this function 'naked_p' and other functions can check this flag.
551 Note that in nds32 port, the 'naked_p = 1' JUST means there is no
552 callee-saved, local size, and outgoing size.
553 The varargs space and ret instruction may still present in
554 the prologue/epilogue expanding. */
555 cfun
->machine
->naked_p
= 1;
557 /* No need to save $fp, $gp, and $lp.
558 We should set these value to be zero
559 so that nds32_initial_elimination_offset() can work properly. */
560 cfun
->machine
->fp_size
= 0;
561 cfun
->machine
->gp_size
= 0;
562 cfun
->machine
->lp_size
= 0;
564 /* If stack usage computation is required,
565 we need to provide the static stack size. */
566 if (flag_stack_usage_info
)
567 current_function_static_stack_size
= 0;
569 /* No need to do following adjustment, return immediately. */
573 v3pushpop_p
= NDS32_V3PUSH_AVAILABLE_P
;
575 /* Adjustment for v3push instructions:
576 If we are using v3push (push25/pop25) instructions,
577 we need to make sure Rb is $r6 and Re is
578 located on $r6, $r8, $r10, or $r14.
579 Some results above will be discarded and recomputed.
580 Note that it is only available under V3/V3M ISA and we
581 DO NOT setup following stuff for isr or variadic function. */
585 cfun->machine->fp_size
586 cfun->machine->gp_size
587 cfun->machine->lp_size
588 cfun->machine->callee_saved_first_gpr_regno
589 cfun->machine->callee_saved_last_gpr_regno */
591 /* For v3push instructions, $fp, $gp, and $lp are always saved. */
592 cfun
->machine
->fp_size
= 4;
593 cfun
->machine
->gp_size
= 4;
594 cfun
->machine
->lp_size
= 4;
596 /* Remember to set Rb = $r6. */
597 cfun
->machine
->callee_saved_first_gpr_regno
= 6;
599 if (cfun
->machine
->callee_saved_last_gpr_regno
<= 6)
602 cfun
->machine
->callee_saved_last_gpr_regno
= 6;
604 else if (cfun
->machine
->callee_saved_last_gpr_regno
<= 8)
607 cfun
->machine
->callee_saved_last_gpr_regno
= 8;
609 else if (cfun
->machine
->callee_saved_last_gpr_regno
<= 10)
612 cfun
->machine
->callee_saved_last_gpr_regno
= 10;
614 else if (cfun
->machine
->callee_saved_last_gpr_regno
<= 14)
617 cfun
->machine
->callee_saved_last_gpr_regno
= 14;
619 else if (cfun
->machine
->callee_saved_last_gpr_regno
== SP_REGNUM
)
621 /* If last_regno is SP_REGNUM, which means
622 it is never changed, so set it to Re = $r6. */
623 cfun
->machine
->callee_saved_last_gpr_regno
= 6;
627 /* The program flow should not go here. */
632 int sp_adjust
= cfun
->machine
->local_size
633 + cfun
->machine
->out_args_size
634 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
635 + cfun
->machine
->callee_saved_fpr_regs_size
;
639 && !frame_pointer_needed
)
641 block_size
= cfun
->machine
->fp_size
642 + cfun
->machine
->gp_size
643 + cfun
->machine
->lp_size
;
645 if (cfun
->machine
->callee_saved_last_gpr_regno
!= SP_REGNUM
)
646 block_size
+= (4 * (cfun
->machine
->callee_saved_last_gpr_regno
647 - cfun
->machine
->callee_saved_first_gpr_regno
650 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
652 /* $r14 is last callee save register. */
653 if (cfun
->machine
->callee_saved_last_gpr_regno
654 < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM
)
656 cfun
->machine
->callee_saved_last_gpr_regno
++;
658 else if (cfun
->machine
->callee_saved_first_gpr_regno
== SP_REGNUM
)
660 cfun
->machine
->callee_saved_first_gpr_regno
661 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM
;
662 cfun
->machine
->callee_saved_last_gpr_regno
663 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM
;
668 /* We have correctly set callee_saved_first_gpr_regno
669 and callee_saved_last_gpr_regno.
670 Initially, the callee_saved_gpr_regs_size is supposed to be 0.
671 As long as callee_saved_last_gpr_regno is not SP_REGNUM,
672 we can update callee_saved_gpr_regs_size with new size. */
673 if (cfun
->machine
->callee_saved_last_gpr_regno
!= SP_REGNUM
)
675 /* Compute pushed size of callee-saved registers. */
676 cfun
->machine
->callee_saved_gpr_regs_size
677 = 4 * (cfun
->machine
->callee_saved_last_gpr_regno
678 - cfun
->machine
->callee_saved_first_gpr_regno
682 if (TARGET_HARD_FLOAT
)
684 /* Compute size of callee svaed floating-point registers. */
685 if (cfun
->machine
->callee_saved_last_fpr_regno
!= SP_REGNUM
)
687 cfun
->machine
->callee_saved_fpr_regs_size
688 = 4 * (cfun
->machine
->callee_saved_last_fpr_regno
689 - cfun
->machine
->callee_saved_first_fpr_regno
694 /* Important: We need to make sure that
695 (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size)
697 If it is not, calculate the padding bytes. */
698 block_size
= cfun
->machine
->fp_size
699 + cfun
->machine
->gp_size
700 + cfun
->machine
->lp_size
701 + cfun
->machine
->callee_saved_gpr_regs_size
;
702 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
704 cfun
->machine
->callee_saved_area_gpr_padding_bytes
705 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
) - block_size
;
708 /* If stack usage computation is required,
709 we need to provide the static stack size. */
710 if (flag_stack_usage_info
)
712 current_function_static_stack_size
713 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
)
714 + cfun
->machine
->local_size
715 + cfun
->machine
->out_args_size
;
719 /* Function to create a parallel rtx pattern
720 which presents stack push multiple behavior.
721 The overall concept are:
722 "push registers to memory",
723 "adjust stack pointer". */
725 nds32_emit_stack_push_multiple (unsigned Rb
, unsigned Re
,
726 bool save_fp_p
, bool save_gp_p
, bool save_lp_p
,
742 /* We need to provide a customized rtx which contains
743 necessary information for data analysis,
744 so we create a parallel rtx like this:
745 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
747 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
750 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
752 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
754 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
756 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
758 (set (reg:SI SP_REGNUM)
759 (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
761 /* Calculate the number of registers that will be pushed. */
769 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
770 if (Rb
== SP_REGNUM
&& Re
== SP_REGNUM
)
771 num_use_regs
= extra_count
;
773 num_use_regs
= Re
- Rb
+ 1 + extra_count
;
775 /* In addition to used registers,
776 we need one more space for (set sp sp-x) rtx. */
777 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
778 rtvec_alloc (num_use_regs
+ 1));
781 /* Initialize offset and start to create push behavior. */
782 offset
= -(num_use_regs
* 4);
784 /* Create (set mem regX) from Rb, Rb+1 up to Re. */
785 for (regno
= Rb
; regno
<= Re
; regno
++)
787 /* Rb and Re may be SP_REGNUM.
788 We need to break this loop immediately. */
789 if (regno
== SP_REGNUM
)
792 reg
= gen_rtx_REG (SImode
, regno
);
793 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
796 push_rtx
= gen_rtx_SET (mem
, reg
);
797 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
798 RTX_FRAME_RELATED_P (push_rtx
) = 1;
803 /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */
806 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
807 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
810 push_rtx
= gen_rtx_SET (mem
, reg
);
811 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
812 RTX_FRAME_RELATED_P (push_rtx
) = 1;
818 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
819 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
822 push_rtx
= gen_rtx_SET (mem
, reg
);
823 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
824 RTX_FRAME_RELATED_P (push_rtx
) = 1;
830 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
831 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
834 push_rtx
= gen_rtx_SET (mem
, reg
);
835 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
836 RTX_FRAME_RELATED_P (push_rtx
) = 1;
841 /* Create (set sp sp-x). */
843 /* We need to re-calculate the offset value again for adjustment. */
844 offset
= -(num_use_regs
* 4);
846 = gen_rtx_SET (stack_pointer_rtx
,
847 plus_constant (Pmode
, stack_pointer_rtx
, offset
));
848 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
849 RTX_FRAME_RELATED_P (adjust_sp_rtx
) = 1;
851 parallel_insn
= emit_insn (parallel_insn
);
853 /* The insn rtx 'parallel_insn' will change frame layout.
854 We need to use RTX_FRAME_RELATED_P so that GCC is able to
855 generate CFI (Call Frame Information) stuff. */
856 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
858 /* Don't use GCC's logic for CFI info if we are generate a push for VAARG
859 since we will not restore those register at epilogue. */
862 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
,
863 copy_rtx (adjust_sp_rtx
), NULL_RTX
);
864 REG_NOTES (parallel_insn
) = dwarf
;
868 /* Function to create a parallel rtx pattern
869 which presents stack pop multiple behavior.
870 The overall concept are:
871 "pop registers from memory",
872 "adjust stack pointer". */
874 nds32_emit_stack_pop_multiple (unsigned Rb
, unsigned Re
,
875 bool save_fp_p
, bool save_gp_p
, bool save_lp_p
)
888 rtx dwarf
= NULL_RTX
;
890 /* We need to provide a customized rtx which contains
891 necessary information for data analysis,
892 so we create a parallel rtx like this:
893 (parallel [(set (reg:SI Rb)
894 (mem (reg:SI SP_REGNUM)))
896 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
899 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
900 (set (reg:SI FP_REGNUM)
901 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
902 (set (reg:SI GP_REGNUM)
903 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
904 (set (reg:SI LP_REGNUM)
905 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
906 (set (reg:SI SP_REGNUM)
907 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
909 /* Calculate the number of registers that will be poped. */
917 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
918 if (Rb
== SP_REGNUM
&& Re
== SP_REGNUM
)
919 num_use_regs
= extra_count
;
921 num_use_regs
= Re
- Rb
+ 1 + extra_count
;
923 /* In addition to used registers,
924 we need one more space for (set sp sp+x) rtx. */
925 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
926 rtvec_alloc (num_use_regs
+ 1));
929 /* Initialize offset and start to create pop behavior. */
932 /* Create (set regX mem) from Rb, Rb+1 up to Re. */
933 for (regno
= Rb
; regno
<= Re
; regno
++)
935 /* Rb and Re may be SP_REGNUM.
936 We need to break this loop immediately. */
937 if (regno
== SP_REGNUM
)
940 reg
= gen_rtx_REG (SImode
, regno
);
941 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
944 pop_rtx
= gen_rtx_SET (reg
, mem
);
945 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
946 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
950 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
953 /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */
956 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
957 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
960 pop_rtx
= gen_rtx_SET (reg
, mem
);
961 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
962 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
966 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
970 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
971 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
974 pop_rtx
= gen_rtx_SET (reg
, mem
);
975 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
976 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
980 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
984 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
985 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
988 pop_rtx
= gen_rtx_SET (reg
, mem
);
989 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
990 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
994 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
997 /* Create (set sp sp+x). */
999 /* The offset value is already in place. No need to re-calculate it. */
1001 = gen_rtx_SET (stack_pointer_rtx
,
1002 plus_constant (Pmode
, stack_pointer_rtx
, offset
));
1003 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
1005 /* Tell gcc we adjust SP in this insn. */
1006 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, copy_rtx (adjust_sp_rtx
), dwarf
);
1008 parallel_insn
= emit_insn (parallel_insn
);
1010 /* The insn rtx 'parallel_insn' will change frame layout.
1011 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1012 generate CFI (Call Frame Information) stuff. */
1013 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
1015 /* Add CFI info by manual. */
1016 REG_NOTES (parallel_insn
) = dwarf
;
1019 /* Function to create a parallel rtx pattern
1020 which presents stack v3push behavior.
1021 The overall concept are:
1022 "push registers to memory",
1023 "adjust stack pointer". */
1025 nds32_emit_stack_v3push (unsigned Rb
,
1040 /* We need to provide a customized rtx which contains
1041 necessary information for data analysis,
1042 so we create a parallel rtx like this:
1043 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
1045 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
1048 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
1050 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
1052 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
1054 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
1056 (set (reg:SI SP_REGNUM)
1057 (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
1059 /* Calculate the number of registers that will be pushed.
1060 Since $fp, $gp, and $lp is always pushed with v3push instruction,
1061 we need to count these three registers.
1062 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1063 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1064 num_use_regs
= Re
- Rb
+ 1 + 3;
1066 /* In addition to used registers,
1067 we need one more space for (set sp sp-x-imm8u) rtx. */
1068 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
1069 rtvec_alloc (num_use_regs
+ 1));
1072 /* Initialize offset and start to create push behavior. */
1073 offset
= -(num_use_regs
* 4);
1075 /* Create (set mem regX) from Rb, Rb+1 up to Re.
1076 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1077 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1078 for (regno
= Rb
; regno
<= Re
; regno
++)
1080 reg
= gen_rtx_REG (SImode
, regno
);
1081 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1084 push_rtx
= gen_rtx_SET (mem
, reg
);
1085 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1086 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1087 offset
= offset
+ 4;
1091 /* Create (set mem fp). */
1092 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
1093 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1096 push_rtx
= gen_rtx_SET (mem
, reg
);
1097 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1098 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1099 offset
= offset
+ 4;
1101 /* Create (set mem gp). */
1102 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
1103 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1106 push_rtx
= gen_rtx_SET (mem
, reg
);
1107 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1108 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1109 offset
= offset
+ 4;
1111 /* Create (set mem lp). */
1112 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
1113 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1116 push_rtx
= gen_rtx_SET (mem
, reg
);
1117 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1118 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1119 offset
= offset
+ 4;
1122 /* Create (set sp sp-x-imm8u). */
1124 /* We need to re-calculate the offset value again for adjustment. */
1125 offset
= -(num_use_regs
* 4);
1127 = gen_rtx_SET (stack_pointer_rtx
,
1128 plus_constant (Pmode
,
1131 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
1132 RTX_FRAME_RELATED_P (adjust_sp_rtx
) = 1;
1134 parallel_insn
= emit_insn (parallel_insn
);
1136 /* The insn rtx 'parallel_insn' will change frame layout.
1137 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1138 generate CFI (Call Frame Information) stuff. */
1139 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
1142 /* Function to create a parallel rtx pattern
1143 which presents stack v3pop behavior.
1144 The overall concept are:
1145 "pop registers from memory",
1146 "adjust stack pointer". */
1148 nds32_emit_stack_v3pop (unsigned Rb
,
1162 rtx dwarf
= NULL_RTX
;
1164 /* We need to provide a customized rtx which contains
1165 necessary information for data analysis,
1166 so we create a parallel rtx like this:
1167 (parallel [(set (reg:SI Rb)
1168 (mem (reg:SI SP_REGNUM)))
1170 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
1173 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
1174 (set (reg:SI FP_REGNUM)
1175 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
1176 (set (reg:SI GP_REGNUM)
1177 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
1178 (set (reg:SI LP_REGNUM)
1179 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
1180 (set (reg:SI SP_REGNUM)
1181 (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
1183 /* Calculate the number of registers that will be poped.
1184 Since $fp, $gp, and $lp is always poped with v3pop instruction,
1185 we need to count these three registers.
1186 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1187 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1188 num_use_regs
= Re
- Rb
+ 1 + 3;
1190 /* In addition to used registers,
1191 we need one more space for (set sp sp+x+imm8u) rtx. */
1192 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
1193 rtvec_alloc (num_use_regs
+ 1));
1196 /* Initialize offset and start to create pop behavior. */
1199 /* Create (set regX mem) from Rb, Rb+1 up to Re.
1200 Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1201 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1202 for (regno
= Rb
; regno
<= Re
; regno
++)
1204 reg
= gen_rtx_REG (SImode
, regno
);
1205 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1208 pop_rtx
= gen_rtx_SET (reg
, mem
);
1209 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1210 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1211 offset
= offset
+ 4;
1214 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1217 /* Create (set fp mem). */
1218 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
1219 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1222 pop_rtx
= gen_rtx_SET (reg
, mem
);
1223 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1224 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1225 offset
= offset
+ 4;
1227 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1229 /* Create (set gp mem). */
1230 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
1231 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1234 pop_rtx
= gen_rtx_SET (reg
, mem
);
1235 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1236 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1237 offset
= offset
+ 4;
1239 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1241 /* Create (set lp mem ). */
1242 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
1243 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1246 pop_rtx
= gen_rtx_SET (reg
, mem
);
1247 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1248 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1249 offset
= offset
+ 4;
1251 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1253 /* Create (set sp sp+x+imm8u). */
1255 /* The offset value is already in place. No need to re-calculate it. */
1257 = gen_rtx_SET (stack_pointer_rtx
,
1258 plus_constant (Pmode
,
1261 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
1263 if (frame_pointer_needed
)
1265 /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp)
1267 mean reset frame pointer to $sp and reset to offset 0. */
1268 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
1270 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
1274 /* Tell gcc we adjust SP in this insn. */
1275 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
,
1276 copy_rtx (adjust_sp_rtx
), dwarf
);
1279 parallel_insn
= emit_insn (parallel_insn
);
1281 /* The insn rtx 'parallel_insn' will change frame layout.
1282 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1283 generate CFI (Call Frame Information) stuff. */
1284 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
1286 /* Add CFI info by manual. */
1287 REG_NOTES (parallel_insn
) = dwarf
;
1291 nds32_emit_load_gp (void)
1293 rtx got_symbol
, pat
;
1295 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
1296 emit_insn (gen_blockage ());
1298 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1299 /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */
1300 pat
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, got_symbol
), UNSPEC_GOTINIT
);
1301 pat
= gen_rtx_CONST (SImode
, gen_rtx_PLUS (Pmode
, pat
, GEN_INT (-8)));
1302 emit_insn (gen_sethi (pic_offset_table_rtx
,pat
));
1304 /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */
1305 pat
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, got_symbol
), UNSPEC_GOTINIT
);
1306 pat
= gen_rtx_CONST (SImode
, gen_rtx_PLUS (Pmode
, pat
, GEN_INT (-4)));
1307 emit_insn (gen_lo_sum (pic_offset_table_rtx
, pic_offset_table_rtx
, pat
));
1310 emit_insn (gen_add_pc (pic_offset_table_rtx
, pic_offset_table_rtx
));
1312 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
1313 emit_insn (gen_blockage ());
1316 /* Function that may creates more instructions
1317 for large value on adjusting stack pointer.
1319 In nds32 target, 'addi' can be used for stack pointer
1320 adjustment in prologue/epilogue stage.
1321 However, sometimes there are too many local variables so that
1322 the adjustment value is not able to be fit in the 'addi' instruction.
1323 One solution is to move value into a register
1324 and then use 'add' instruction.
1325 In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */
1327 nds32_emit_adjust_frame (rtx to_reg
, rtx from_reg
, int adjust_value
)
1330 rtx frame_adjust_insn
;
1331 rtx adjust_value_rtx
= GEN_INT (adjust_value
);
1333 if (adjust_value
== 0)
1336 if (!satisfies_constraint_Is15 (adjust_value_rtx
))
1338 /* The value is not able to fit in single addi instruction.
1339 Create more instructions of moving value into a register
1340 and then add stack pointer with it. */
1342 /* $r15 is going to be temporary register to hold the value. */
1343 tmp_reg
= gen_rtx_REG (SImode
, TA_REGNUM
);
1345 /* Create one more instruction to move value
1346 into the temporary register. */
1347 emit_move_insn (tmp_reg
, adjust_value_rtx
);
1349 /* Create new 'add' rtx. */
1350 frame_adjust_insn
= gen_addsi3 (to_reg
,
1353 /* Emit rtx into insn list and receive its transformed insn rtx. */
1354 frame_adjust_insn
= emit_insn (frame_adjust_insn
);
1356 /* Because (tmp_reg <- full_value) may be split into two
1357 rtl patterns, we cannot set its RTX_FRAME_RELATED_P.
1358 We need to construct another (sp <- sp + full_value)
1359 and then insert it into sp_adjust_insn's reg note to
1360 represent a frame related expression.
1361 GCC knows how to refer it and output debug information. */
1366 plus_rtx
= plus_constant (Pmode
, from_reg
, adjust_value
);
1367 set_rtx
= gen_rtx_SET (to_reg
, plus_rtx
);
1368 add_reg_note (frame_adjust_insn
, REG_FRAME_RELATED_EXPR
, set_rtx
);
1372 /* Generate sp adjustment instruction if and only if sp_adjust != 0. */
1373 frame_adjust_insn
= gen_addsi3 (to_reg
,
1376 /* Emit rtx into instructions list and receive INSN rtx form. */
1377 frame_adjust_insn
= emit_insn (frame_adjust_insn
);
1380 /* The insn rtx 'sp_adjust_insn' will change frame layout.
1381 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1382 generate CFI (Call Frame Information) stuff. */
1383 RTX_FRAME_RELATED_P (frame_adjust_insn
) = 1;
1386 /* Return true if MODE/TYPE need double word alignment. */
1388 nds32_needs_double_word_align (machine_mode mode
, const_tree type
)
1392 /* Pick up the alignment according to the mode or type. */
1393 align
= NDS32_MODE_TYPE_ALIGN (mode
, type
);
1395 return (align
> PARM_BOUNDARY
);
1398 /* Return true if FUNC is a naked function. */
1400 nds32_naked_function_p (tree func
)
1402 /* FOR BACKWARD COMPATIBILITY,
1403 we need to support 'no_prologue' attribute as well. */
1407 if (TREE_CODE (func
) != FUNCTION_DECL
)
1410 /* We have to use lookup_attribute() to check attributes.
1411 Because attr_naked_p and attr_no_prologue_p are set in
1412 nds32_compute_stack_frame() and the function has not been
1414 t_naked
= lookup_attribute ("naked", DECL_ATTRIBUTES (func
));
1415 t_no_prologue
= lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func
));
1417 return ((t_naked
!= NULL_TREE
) || (t_no_prologue
!= NULL_TREE
));
1420 /* Function that determine whether a load postincrement is a good thing to use
1421 for a given mode. */
1423 nds32_use_load_post_increment (machine_mode mode
)
1425 return (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE(E_DImode
));
1428 /* Function that check if 'X' is a valid address register.
1429 The variable 'STRICT' is very important to
1430 make decision for register number.
1433 => We are in reload pass or after reload pass.
1434 The register number should be strictly limited in general registers.
1437 => Before reload pass, we are free to use any register number. */
1439 nds32_address_register_rtx_p (rtx x
, bool strict
)
1443 if (GET_CODE (x
) != REG
)
1449 return REGNO_OK_FOR_BASE_P (regno
);
1454 /* Function that check if 'INDEX' is valid to be a index rtx for address.
1456 OUTER_MODE : Machine mode of outer address rtx.
1457 INDEX : Check if this rtx is valid to be a index for address.
1458 STRICT : If it is true, we are in reload pass or after reload pass. */
1460 nds32_legitimate_index_p (machine_mode outer_mode
,
1468 switch (GET_CODE (index
))
1471 regno
= REGNO (index
);
1472 /* If we are in reload pass or after reload pass,
1473 we need to limit it to general register. */
1475 return REGNO_OK_FOR_INDEX_P (regno
);
1480 /* The alignment of the integer value is determined by 'outer_mode'. */
1481 switch (GET_MODE_SIZE (outer_mode
))
1484 /* Further check if the value is legal for the 'outer_mode'. */
1485 if (satisfies_constraint_Is15 (index
))
1490 /* Further check if the value is legal for the 'outer_mode'. */
1491 if (satisfies_constraint_Is16 (index
))
1493 /* If it is not under strictly aligned situation,
1494 we can return true without checking alignment. */
1495 if (!cfun
->machine
->strict_aligned_p
)
1497 /* Make sure address is half word alignment. */
1498 else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index
)))
1504 /* Further check if the value is legal for the 'outer_mode'. */
1505 if (satisfies_constraint_Is17 (index
))
1507 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
))
1509 if (!satisfies_constraint_Is14 (index
))
1513 /* If it is not under strictly aligned situation,
1514 we can return true without checking alignment. */
1515 if (!cfun
->machine
->strict_aligned_p
)
1517 /* Make sure address is word alignment. */
1518 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index
)))
1524 if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index
) + 4,
1527 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
))
1529 if (!satisfies_constraint_Is14 (index
))
1533 /* If it is not under strictly aligned situation,
1534 we can return true without checking alignment. */
1535 if (!cfun
->machine
->strict_aligned_p
)
1537 /* Make sure address is word alignment.
1538 Currently we do not have 64-bit load/store yet,
1539 so we will use two 32-bit load/store instructions to do
1540 memory access and they are single word alignment. */
1541 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index
)))
1553 op0
= XEXP (index
, 0);
1554 op1
= XEXP (index
, 1);
1556 if (REG_P (op0
) && CONST_INT_P (op1
))
1559 multiplier
= INTVAL (op1
);
1561 /* We only allow (mult reg const_int_1), (mult reg const_int_2),
1562 (mult reg const_int_4) or (mult reg const_int_8). */
1563 if (multiplier
!= 1 && multiplier
!= 2
1564 && multiplier
!= 4 && multiplier
!= 8)
1567 regno
= REGNO (op0
);
1568 /* Limit it in general registers if we are
1569 in reload pass or after reload pass. */
1571 return REGNO_OK_FOR_INDEX_P (regno
);
1579 op0
= XEXP (index
, 0);
1580 op1
= XEXP (index
, 1);
1582 if (REG_P (op0
) && CONST_INT_P (op1
))
1585 /* op1 is already the sv value for use to do left shift. */
1588 /* We only allow (ashift reg const_int_0)
1589 or (ashift reg const_int_1) or (ashift reg const_int_2) or
1590 (ashift reg const_int_3). */
1591 if (sv
!= 0 && sv
!= 1 && sv
!=2 && sv
!= 3)
1594 regno
= REGNO (op0
);
1595 /* Limit it in general registers if we are
1596 in reload pass or after reload pass. */
1598 return REGNO_OK_FOR_INDEX_P (regno
);
1611 nds32_register_pass (
1612 rtl_opt_pass
*(*make_pass_func
) (gcc::context
*),
1613 enum pass_positioning_ops pass_pos
,
1614 const char *ref_pass_name
)
1616 opt_pass
*new_opt_pass
= make_pass_func (g
);
1618 struct register_pass_info insert_pass
=
1620 new_opt_pass
, /* pass */
1621 ref_pass_name
, /* reference_pass_name */
1622 1, /* ref_pass_instance_number */
1623 pass_pos
/* po_op */
1626 register_pass (&insert_pass
);
1629 /* This function is called from nds32_option_override ().
1630 All new passes should be registered here. */
1632 nds32_register_passes (void)
1634 nds32_register_pass (
1635 make_pass_nds32_fp_as_gp
,
1636 PASS_POS_INSERT_BEFORE
,
1639 nds32_register_pass (
1640 make_pass_nds32_relax_opt
,
1641 PASS_POS_INSERT_AFTER
,
1645 /* ------------------------------------------------------------------------ */
1647 /* PART 3: Implement target hook stuff definitions. */
1650 /* Computing the Length of an Insn.
1651 Modifies the length assigned to instruction INSN.
1652 LEN is the initially computed length of the insn. */
1654 nds32_adjust_insn_length (rtx_insn
*insn
, int length
)
1656 int adjust_value
= 0;
1657 switch (recog_memoized (insn
))
1659 case CODE_FOR_call_internal
:
1660 case CODE_FOR_call_value_internal
:
1662 if (NDS32_ALIGN_P ())
1664 rtx_insn
*next_insn
= next_active_insn (insn
);
1665 if (next_insn
&& get_attr_length (next_insn
) != 2)
1668 /* We need insert a nop after a noretun function call
1669 to prevent software breakpoint corrupt the next function. */
1670 if (find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
1678 return length
+ adjust_value
;
1685 /* Storage Layout. */
1687 /* This function will be called just before expansion into rtl. */
1689 nds32_expand_to_rtl_hook (void)
1691 /* We need to set strictly aligned situation.
1692 After that, the memory address checking in nds32_legitimate_address_p()
1693 will take alignment offset into consideration so that it will not create
1694 unaligned [base + offset] access during the rtl optimization. */
1695 cfun
->machine
->strict_aligned_p
= 1;
1699 /* Register Usage. */
1702 nds32_conditional_register_usage (void)
1706 if (TARGET_LINUX_ABI
)
1707 fixed_regs
[TP_REGNUM
] = 1;
1709 if (TARGET_HARD_FLOAT
)
1711 for (regno
= NDS32_FIRST_FPR_REGNUM
;
1712 regno
<= NDS32_LAST_FPR_REGNUM
; regno
++)
1714 fixed_regs
[regno
] = 0;
1715 if (regno
< NDS32_FIRST_FPR_REGNUM
+ NDS32_MAX_FPR_REGS_FOR_ARGS
)
1716 call_used_regs
[regno
] = 1;
1717 else if (regno
>= NDS32_FIRST_FPR_REGNUM
+ 22
1718 && regno
< NDS32_FIRST_FPR_REGNUM
+ 48)
1719 call_used_regs
[regno
] = 1;
1721 call_used_regs
[regno
] = 0;
1724 else if (TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
1726 for (regno
= NDS32_FIRST_FPR_REGNUM
;
1727 regno
<= NDS32_LAST_FPR_REGNUM
;
1729 fixed_regs
[regno
] = 0;
1734 /* Register Classes. */
1736 static unsigned char
1737 nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED
,
1740 /* Return the maximum number of consecutive registers
1741 needed to represent "mode" in a register of "rclass". */
1742 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1746 nds32_register_priority (int hard_regno
)
1748 /* Encourage to use r0-r7 for LRA when optimize for size. */
1753 else if (hard_regno
< 16)
1755 else if (hard_regno
< 28)
1762 if (hard_regno
> 27)
1770 nds32_can_change_mode_class (machine_mode from
,
1774 /* Don't spill double-precision register to two singal-precision
1776 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
1777 && GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
1779 return !reg_classes_intersect_p (rclass
, FP_REGS
);
1786 /* Stack Layout and Calling Conventions. */
1788 /* There are three kinds of pointer concepts using in GCC compiler:
1790 frame pointer: A pointer to the first location of local variables.
1791 stack pointer: A pointer to the top of a stack frame.
1792 argument pointer: A pointer to the incoming arguments.
1794 In nds32 target calling convention, we are using 8-byte alignment.
1795 Besides, we would like to have each stack frame of a function includes:
1798 1. previous hard frame pointer
1800 3. callee-saved registers
1801 4. <padding bytes> (we will calculte in nds32_compute_stack_frame()
1803 cfun->machine->callee_saved_area_padding_bytes)
1807 2. spilling location
1808 3. <padding bytes> (it will be calculated by GCC itself)
1809 4. incoming arguments
1810 5. <padding bytes> (it will be calculated by GCC itself)
1813 1. <padding bytes> (it will be calculated by GCC itself)
1814 2. outgoing arguments
1816 We 'wrap' these blocks together with
1817 hard frame pointer ($r28) and stack pointer ($r31).
1818 By applying the basic frame/stack/argument pointers concept,
1819 the layout of a stack frame shoule be like this:
1822 old stack pointer -> ----
1824 | | saved arguments for
1825 | | vararg functions
1827 hard frame pointer -> --
1828 & argument pointer | | \
1829 | | previous hardware frame pointer
1831 | | callee-saved registers
1836 | | and incoming arguments
1843 stack pointer -> ----
1845 $SFP and $AP are used to represent frame pointer and arguments pointer,
1846 which will be both eliminated as hard frame pointer. */
1848 /* -- Eliminating Frame Pointer and Arg Pointer. */
1851 nds32_can_eliminate (const int from_reg
, const int to_reg
)
1853 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
1856 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== HARD_FRAME_POINTER_REGNUM
)
1859 if (from_reg
== FRAME_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
1862 if (from_reg
== FRAME_POINTER_REGNUM
&& to_reg
== HARD_FRAME_POINTER_REGNUM
)
1868 /* -- Passing Arguments in Registers. */
1871 nds32_function_arg (cumulative_args_t ca
, const function_arg_info
&arg
)
1874 CUMULATIVE_ARGS
*cum
= get_cumulative_args (ca
);
1875 tree type
= arg
.type
;
1876 machine_mode mode
= arg
.mode
;
1878 /* The last time this hook is called,
1879 it is called with an end marker. */
1880 if (arg
.end_marker_p ())
1883 /* For nameless arguments, we need to take care it individually. */
1886 /* If we are under hard float abi, we have arguments passed on the
1887 stack and all situation can be handled by GCC itself. */
1888 if (TARGET_HARD_FLOAT
)
1891 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum
->gpr_offset
, mode
, type
))
1893 /* If we still have enough registers to pass argument, pick up
1894 next available register number. */
1896 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
);
1897 return gen_rtx_REG (mode
, regno
);
1900 /* No register available, return NULL_RTX.
1901 The compiler will use stack to pass argument instead. */
1905 /* The following is to handle named argument.
1906 Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT
1908 if (TARGET_HARD_FLOAT
)
1910 /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR
1911 to pass argument. We have to further check TYPE and MODE so
1912 that we can determine which kind of register we shall use. */
1914 /* Note that we need to pass argument entirely in registers under
1916 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1917 && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum
->fpr_offset
, mode
, type
))
1919 /* Pick up the next available FPR register number. */
1921 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum
->fpr_offset
, mode
, type
);
1922 return gen_rtx_REG (mode
, regno
);
1924 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
1925 && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum
->gpr_offset
, mode
, type
))
1927 /* Pick up the next available GPR register number. */
1929 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
);
1930 return gen_rtx_REG (mode
, regno
);
1935 /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass
1936 argument. Since we allow to pass argument partially in registers,
1937 we can just return it if there are still registers available. */
1938 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum
->gpr_offset
, mode
, type
))
1940 /* Pick up the next available register number. */
1942 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
);
1943 return gen_rtx_REG (mode
, regno
);
1948 /* No register available, return NULL_RTX.
1949 The compiler will use stack to pass argument instead. */
1954 nds32_must_pass_in_stack (const function_arg_info
&arg
)
1956 /* Return true if a type must be passed in memory.
1957 If it is NOT using hard float abi, small aggregates can be
1958 passed in a register even we are calling a variadic function.
1959 So there is no need to take padding into consideration. */
1960 if (TARGET_HARD_FLOAT
)
1961 return must_pass_in_stack_var_size_or_pad (arg
);
1963 return must_pass_in_stack_var_size (arg
);
1967 nds32_arg_partial_bytes (cumulative_args_t ca
, const function_arg_info
&arg
)
1969 /* Returns the number of bytes at the beginning of an argument that
1970 must be put in registers. The value must be zero for arguments that are
1971 passed entirely in registers or that are entirely pushed on the stack.
1972 Besides, TARGET_FUNCTION_ARG for these arguments should return the
1973 first register to be used by the caller for this argument. */
1974 unsigned int needed_reg_count
;
1975 unsigned int remaining_reg_count
;
1976 CUMULATIVE_ARGS
*cum
;
1978 cum
= get_cumulative_args (ca
);
1980 /* Under hard float abi, we better have argument entirely passed in
1981 registers or pushed on the stack so that we can reduce the complexity
1982 of dealing with cum->gpr_offset and cum->fpr_offset. */
1983 if (TARGET_HARD_FLOAT
)
1986 /* If we have already runned out of argument registers, return zero
1987 so that the argument will be entirely pushed on the stack. */
1988 if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, arg
.mode
, arg
.type
)
1989 >= NDS32_GPR_ARG_FIRST_REGNUM
+ NDS32_MAX_GPR_REGS_FOR_ARGS
)
1992 /* Calculate how many registers do we need for this argument. */
1993 needed_reg_count
= NDS32_NEED_N_REGS_FOR_ARG (arg
.mode
, arg
.type
);
1995 /* Calculate how many argument registers have left for passing argument.
1996 Note that we should count it from next available register number. */
1998 = NDS32_MAX_GPR_REGS_FOR_ARGS
1999 - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
,
2001 - NDS32_GPR_ARG_FIRST_REGNUM
);
2003 /* Note that we have to return the nubmer of bytes, not registers count. */
2004 if (needed_reg_count
> remaining_reg_count
)
2005 return remaining_reg_count
* UNITS_PER_WORD
;
2011 nds32_function_arg_advance (cumulative_args_t ca
,
2012 const function_arg_info
&arg
)
2014 CUMULATIVE_ARGS
*cum
= get_cumulative_args (ca
);
2015 tree type
= arg
.type
;
2016 machine_mode mode
= arg
.mode
;
2020 /* We need to further check TYPE and MODE so that we can determine
2021 which kind of register we shall advance. */
2023 /* Under hard float abi, we may advance FPR registers. */
2024 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2027 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum
->fpr_offset
, mode
, type
)
2028 - NDS32_FPR_ARG_FIRST_REGNUM
2029 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
2034 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
2035 - NDS32_GPR_ARG_FIRST_REGNUM
2036 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
2041 /* If this nameless argument is NOT under TARGET_HARD_FLOAT,
2042 we can advance next register as well so that caller is
2043 able to pass arguments in registers and callee must be
2044 in charge of pushing all of them into stack. */
2045 if (!TARGET_HARD_FLOAT
)
2048 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
2049 - NDS32_GPR_ARG_FIRST_REGNUM
2050 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
2056 nds32_function_arg_boundary (machine_mode mode
, const_tree type
)
2058 return (nds32_needs_double_word_align (mode
, type
)
2059 ? NDS32_DOUBLE_WORD_ALIGNMENT
2064 nds32_vector_mode_supported_p (machine_mode mode
)
2066 if (mode
== V4QImode
2067 || mode
== V2HImode
)
2068 return NDS32_EXT_DSP_P ();
2073 /* -- How Scalar Function Values Are Returned. */
2076 nds32_function_value (const_tree ret_type
,
2077 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
2078 bool outgoing ATTRIBUTE_UNUSED
)
2083 mode
= TYPE_MODE (ret_type
);
2084 unsignedp
= TYPE_UNSIGNED (ret_type
);
2086 if (INTEGRAL_TYPE_P (ret_type
))
2087 mode
= promote_mode (ret_type
, mode
, &unsignedp
);
2089 if (TARGET_HARD_FLOAT
&& (mode
== SFmode
|| mode
== DFmode
))
2090 return gen_rtx_REG (mode
, NDS32_FPR_RET_FIRST_REGNUM
);
2092 return gen_rtx_REG (mode
, NDS32_GPR_RET_FIRST_REGNUM
);
2096 nds32_libcall_value (machine_mode mode
,
2097 const_rtx fun ATTRIBUTE_UNUSED
)
2099 if (TARGET_HARD_FLOAT
&& (mode
== SFmode
|| mode
== DFmode
))
2100 return gen_rtx_REG (mode
, NDS32_FPR_RET_FIRST_REGNUM
);
2102 return gen_rtx_REG (mode
, NDS32_GPR_RET_FIRST_REGNUM
);
2106 nds32_function_value_regno_p (const unsigned int regno
)
2108 if (regno
== NDS32_GPR_RET_FIRST_REGNUM
2109 || (TARGET_HARD_FLOAT
2110 && regno
== NDS32_FPR_RET_FIRST_REGNUM
))
2116 /* -- How Large Values Are Returned. */
2119 nds32_return_in_memory (const_tree type
,
2120 const_tree fntype ATTRIBUTE_UNUSED
)
2122 /* Note that int_size_in_bytes can return -1 if the size can vary
2123 or is larger than an integer. */
2124 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2126 /* For COMPLEX_TYPE, if the total size cannot be hold within two registers,
2127 the return value is supposed to be in memory. We need to be aware of
2128 that the size may be -1. */
2129 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2130 if (size
< 0 || size
> 2 * UNITS_PER_WORD
)
2133 /* If it is BLKmode and the total size cannot be hold within two registers,
2134 the return value is supposed to be in memory. We need to be aware of
2135 that the size may be -1. */
2136 if (TYPE_MODE (type
) == BLKmode
)
2137 if (size
< 0 || size
> 2 * UNITS_PER_WORD
)
2140 /* For other cases, having result in memory is unnecessary. */
2144 /* -- Function Entry and Exit. */
2146 /* The content produced from this function
2147 will be placed before prologue body. */
2149 nds32_asm_function_prologue (FILE *file
)
2152 const char *func_name
;
2156 /* All stack frame information is supposed to be
2157 already computed when expanding prologue.
2158 The result is in cfun->machine.
2159 DO NOT call nds32_compute_stack_frame() here
2160 because it may corrupt the essential information. */
2162 fprintf (file
, "\t! BEGIN PROLOGUE\n");
2163 fprintf (file
, "\t! fp needed: %d\n", frame_pointer_needed
);
2164 fprintf (file
, "\t! pretend_args: %d\n", cfun
->machine
->va_args_size
);
2165 fprintf (file
, "\t! local_size: %d\n", cfun
->machine
->local_size
);
2166 fprintf (file
, "\t! out_args_size: %d\n", cfun
->machine
->out_args_size
);
2168 /* Use df_regs_ever_live_p() to detect if the register
2169 is ever used in the current function. */
2170 fprintf (file
, "\t! registers ever_live: ");
2171 for (r
= 0; r
< 65; r
++)
2173 if (df_regs_ever_live_p (r
))
2174 fprintf (file
, "%s, ", reg_names
[r
]);
2178 /* Display the attributes of this function. */
2179 fprintf (file
, "\t! function attributes: ");
2180 /* Get the attributes tree list.
2181 Note that GCC builds attributes list with reverse order. */
2182 attrs
= DECL_ATTRIBUTES (current_function_decl
);
2184 /* If there is no any attribute, print out "None". */
2186 fprintf (file
, "None");
2188 /* If there are some attributes, try if we need to
2189 construct isr vector information. */
2190 func_name
= IDENTIFIER_POINTER (DECL_NAME (current_function_decl
));
2191 nds32_construct_isr_vectors_information (attrs
, func_name
);
2193 /* Display all attributes of this function. */
2196 name
= TREE_PURPOSE (attrs
);
2197 fprintf (file
, "%s ", IDENTIFIER_POINTER (name
));
2199 /* Pick up the next attribute. */
2200 attrs
= TREE_CHAIN (attrs
);
2205 /* After rtl prologue has been expanded, this function is used. */
2207 nds32_asm_function_end_prologue (FILE *file
)
2209 fprintf (file
, "\t! END PROLOGUE\n");
2212 /* Before rtl epilogue has been expanded, this function is used. */
2214 nds32_asm_function_begin_epilogue (FILE *file
)
2216 fprintf (file
, "\t! BEGIN EPILOGUE\n");
2219 /* The content produced from this function
2220 will be placed after epilogue body. */
2222 nds32_asm_function_epilogue (FILE *file
)
2224 fprintf (file
, "\t! END EPILOGUE\n");
2228 nds32_asm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
2229 HOST_WIDE_INT delta
,
2230 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2233 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk
));
2236 assemble_start_function (thunk
, fnname
);
2237 /* Make sure unwind info is emitted for the thunk if needed. */
2238 final_start_function (emit_barrier (), file
, 1);
2240 this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
2246 fprintf (file
, "\tsmw.adm\t$r31, [$r31], $r31, 4\n");
2247 fprintf (file
, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n",
2248 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
2249 fprintf (file
, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n",
2250 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
2251 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
2254 fprintf (file
, "\tadd5.pc\t$gp\n");
2257 fprintf (file
, "\tmfusr\t$ta, $pc\n");
2258 fprintf (file
, "\tadd\t%s, $ta, %s\n",
2259 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
2260 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
2266 if (satisfies_constraint_Is15 (GEN_INT (delta
)))
2268 fprintf (file
, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC
"\n",
2269 this_regno
, this_regno
, delta
);
2271 else if (satisfies_constraint_Is20 (GEN_INT (delta
)))
2273 fprintf (file
, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC
"\n", delta
);
2274 fprintf (file
, "\tadd\t$r%d, $r%d, $ta\n", this_regno
, this_regno
);
2279 "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC
")\n",
2282 "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC
")\n",
2284 fprintf (file
, "\tadd\t$r%d, $r%d, $ta\n", this_regno
, this_regno
);
2290 fprintf (file
, "\tla\t$ta, ");
2291 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2292 fprintf (file
, "@PLT\n");
2293 fprintf (file
, "\t! epilogue\n");
2294 fprintf (file
, "\tlwi.bi\t%s, [%s], 4\n",
2295 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
2296 reg_names
[STACK_POINTER_REGNUM
]);
2297 fprintf (file
, "\tbr\t$ta\n");
2301 fprintf (file
, "\tb\t");
2302 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2303 fprintf (file
, "\n");
2306 final_end_function ();
2307 assemble_end_function (thunk
, fnname
);
2310 /* -- Permitting tail calls. */
2312 /* Return true if it is ok to do sibling call optimization. */
2314 nds32_function_ok_for_sibcall (tree decl
,
2315 tree exp ATTRIBUTE_UNUSED
)
2317 /* The DECL is NULL if it is an indirect call. */
2319 /* 1. Do not apply sibling call if -mv3push is enabled,
2320 because pop25 instruction also represents return behavior.
2321 2. If this function is a isr function, do not apply sibling call
2322 because it may perform the behavior that user does not expect.
2323 3. If this function is a variadic function, do not apply sibling call
2324 because the stack layout may be a mess.
2325 4. We don't want to apply sibling call optimization for indirect
2326 sibcall because the pop behavior in epilogue may pollute the
2327 content of caller-saved regsiter when the register is used for
2329 5. In pic mode, it may use some registers for PLT call. */
2330 return (!TARGET_V3PUSH
2331 && !nds32_isr_function_p (current_function_decl
)
2332 && (cfun
->machine
->va_args_size
== 0)
2337 /* Determine whether we need to enable warning for function return check. */
2339 nds32_warn_func_return (tree decl
)
2341 /* Naked functions are implemented entirely in assembly, including the
2342 return sequence, so suppress warnings about this. */
2343 return !nds32_naked_function_p (decl
);
2347 /* Implementing the Varargs Macros. */
2350 nds32_setup_incoming_varargs (cumulative_args_t ca
,
2351 const function_arg_info
&arg
,
2352 int *pretend_args_size
,
2353 int second_time ATTRIBUTE_UNUSED
)
2355 unsigned int total_args_regs
;
2356 unsigned int num_of_used_regs
;
2357 unsigned int remaining_reg_count
;
2358 CUMULATIVE_ARGS
*cum
;
2360 /* If we are under hard float abi, we do not need to set *pretend_args_size.
2361 So that all nameless arguments are pushed by caller and all situation
2362 can be handled by GCC itself. */
2363 if (TARGET_HARD_FLOAT
)
2366 /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers,
2367 counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments.
2368 However, for nameless(anonymous) arguments, we should push them on the
2369 stack so that all the nameless arguments appear to have been passed
2370 consecutively in the memory for accessing. Hence, we need to check and
2371 exclude the registers that are used for named arguments. */
2373 cum
= get_cumulative_args (ca
);
2375 /* ARG describes the last argument.
2376 We need those information to determine the remaining registers
2379 = NDS32_MAX_GPR_REGS_FOR_ARGS
+ NDS32_GPR_ARG_FIRST_REGNUM
;
2381 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, arg
.mode
, arg
.type
)
2382 + NDS32_NEED_N_REGS_FOR_ARG (arg
.mode
, arg
.type
);
2384 remaining_reg_count
= total_args_regs
- num_of_used_regs
;
2385 *pretend_args_size
= remaining_reg_count
* UNITS_PER_WORD
;
2391 nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
2393 /* If this hook returns true, the named argument of FUNCTION_ARG is always
2394 true for named arguments, and false for unnamed arguments. */
2399 /* Trampolines for Nested Functions. */
2402 nds32_asm_trampoline_template (FILE *f
)
2404 if (TARGET_REDUCED_REGS
)
2406 /* Trampoline is not supported on reduced-set registers yet. */
2407 sorry ("a nested function is not supported for reduced registers");
2411 asm_fprintf (f
, "\t! Trampoline code template\n");
2412 asm_fprintf (f
, "\t! This code fragment will be copied "
2413 "into stack on demand\n");
2415 asm_fprintf (f
, "\tmfusr\t$r16,$pc\n");
2416 asm_fprintf (f
, "\tlwi\t$r15,[$r16 + 20] "
2417 "! load nested function address\n");
2418 asm_fprintf (f
, "\tlwi\t$r16,[$r16 + 16] "
2419 "! load chain_value\n");
2420 asm_fprintf (f
, "\tjr\t$r15\n");
2423 /* Preserve space ($pc + 16) for saving chain_value,
2424 nds32_trampoline_init will fill the value in this slot. */
2425 asm_fprintf (f
, "\t! space for saving chain_value\n");
2426 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2428 /* Preserve space ($pc + 20) for saving nested function address,
2429 nds32_trampoline_init will fill the value in this slot. */
2430 asm_fprintf (f
, "\t! space for saving nested function address\n");
2431 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2434 /* Emit RTL insns to initialize the variable parts of a trampoline. */
2436 nds32_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2440 /* Nested function address. */
2442 /* The memory rtx that is going to
2443 be filled with chain_value. */
2444 rtx chain_value_mem
;
2445 /* The memory rtx that is going to
2446 be filled with nested function address. */
2447 rtx nested_func_mem
;
2449 /* Start address of trampoline code in stack, for doing cache sync. */
2450 rtx sync_cache_addr
;
2451 /* Temporary register for sync instruction. */
2453 /* Instruction-cache sync instruction,
2454 requesting an argument as starting address. */
2456 /* For convenience reason of doing comparison. */
2457 int tramp_align_in_bytes
;
2459 /* Trampoline is not supported on reduced-set registers yet. */
2460 if (TARGET_REDUCED_REGS
)
2461 sorry ("a nested function is not supported for reduced registers");
2463 /* STEP 1: Copy trampoline code template into stack,
2464 fill up essential data into stack. */
2466 /* Extract nested function address rtx. */
2467 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2469 /* m_tramp is memory rtx that is going to be filled with trampoline code.
2470 We have nds32_asm_trampoline_template() to emit template pattern. */
2471 emit_block_move (m_tramp
, assemble_trampoline_template (),
2472 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2474 /* After copying trampoline code into stack,
2475 fill chain_value into stack. */
2476 chain_value_mem
= adjust_address (m_tramp
, SImode
, 16);
2477 emit_move_insn (chain_value_mem
, chain_value
);
2478 /* After copying trampoline code int stack,
2479 fill nested function address into stack. */
2480 nested_func_mem
= adjust_address (m_tramp
, SImode
, 20);
2481 emit_move_insn (nested_func_mem
, fnaddr
);
2483 /* STEP 2: Sync instruction-cache. */
2485 /* We have successfully filled trampoline code into stack.
2486 However, in order to execute code in stack correctly,
2487 we must sync instruction cache. */
2488 sync_cache_addr
= XEXP (m_tramp
, 0);
2489 tmp_reg
= gen_reg_rtx (SImode
);
2490 isync_insn
= gen_unspec_volatile_isync (tmp_reg
);
2492 /* Because nds32_cache_block_size is in bytes,
2493 we get trampoline alignment in bytes for convenient comparison. */
2494 tramp_align_in_bytes
= TRAMPOLINE_ALIGNMENT
/ BITS_PER_UNIT
;
2496 if (tramp_align_in_bytes
>= nds32_cache_block_size
2497 && (tramp_align_in_bytes
% nds32_cache_block_size
) == 0)
2499 /* Under this condition, the starting address of trampoline
2500 must be aligned to the starting address of each cache block
2501 and we do not have to worry about cross-boundary issue. */
2503 i
< (TRAMPOLINE_SIZE
+ nds32_cache_block_size
- 1)
2504 / nds32_cache_block_size
;
2507 emit_move_insn (tmp_reg
,
2508 plus_constant (Pmode
, sync_cache_addr
,
2509 nds32_cache_block_size
* i
));
2510 emit_insn (isync_insn
);
2513 else if (TRAMPOLINE_SIZE
> nds32_cache_block_size
)
2515 /* The starting address of trampoline code
2516 may not be aligned to the cache block,
2517 so the trampoline code may be across two cache block.
2518 We need to sync the last element, which is 4-byte size,
2519 of trampoline template. */
2521 i
< (TRAMPOLINE_SIZE
+ nds32_cache_block_size
- 1)
2522 / nds32_cache_block_size
;
2525 emit_move_insn (tmp_reg
,
2526 plus_constant (Pmode
, sync_cache_addr
,
2527 nds32_cache_block_size
* i
));
2528 emit_insn (isync_insn
);
2531 /* The last element of trampoline template is 4-byte size. */
2532 emit_move_insn (tmp_reg
,
2533 plus_constant (Pmode
, sync_cache_addr
,
2534 TRAMPOLINE_SIZE
- 4));
2535 emit_insn (isync_insn
);
2539 /* This is the simplest case.
2540 Because TRAMPOLINE_SIZE is less than or
2541 equal to nds32_cache_block_size,
2542 we can just sync start address and
2543 the last element of trampoline code. */
2545 /* Sync starting address of tampoline code. */
2546 emit_move_insn (tmp_reg
, sync_cache_addr
);
2547 emit_insn (isync_insn
);
2548 /* Sync the last element, which is 4-byte size,
2549 of trampoline template. */
2550 emit_move_insn (tmp_reg
,
2551 plus_constant (Pmode
, sync_cache_addr
,
2552 TRAMPOLINE_SIZE
- 4));
2553 emit_insn (isync_insn
);
2556 /* Set instruction serialization barrier
2557 to guarantee the correct operations. */
2558 emit_insn (gen_unspec_volatile_isb ());
2562 /* Addressing Modes. */
2565 nds32_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
2567 if (TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
2569 /* When using floating-point instructions,
2570 we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */
2571 if ((mode
== DFmode
|| mode
== SFmode
)
2572 && (GET_CODE (x
) == SYMBOL_REF
2573 || GET_CODE(x
) == CONST
))
2576 /* Allow [post_modify] addressing mode, when using FPU instructions. */
2577 if (GET_CODE (x
) == POST_MODIFY
2580 if (GET_CODE (XEXP (x
, 0)) == REG
2581 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2583 rtx plus_op
= XEXP (x
, 1);
2584 rtx op0
= XEXP (plus_op
, 0);
2585 rtx op1
= XEXP (plus_op
, 1);
2587 if (nds32_address_register_rtx_p (op0
, strict
)
2588 && CONST_INT_P (op1
))
2590 if (satisfies_constraint_Is14 (op1
))
2592 /* If it is not under strictly aligned situation,
2593 we can return true without checking alignment. */
2594 if (!cfun
->machine
->strict_aligned_p
)
2596 /* Make sure address is word alignment.
2597 Currently we do not have 64-bit load/store yet,
2598 so we will use two 32-bit load/store instructions to do
2599 memory access and they are single word alignment. */
2600 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1
)))
2608 /* For (mem:DI addr) or (mem:DF addr) case,
2609 we only allow 'addr' to be [reg], [symbol_ref],
2610 [const], or [reg + const_int] pattern. */
2611 if (mode
== DImode
|| mode
== DFmode
)
2613 /* Allow [Reg + const_int] addressing mode. */
2614 if (GET_CODE (x
) == PLUS
)
2616 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
)
2617 && nds32_legitimate_index_p (mode
, XEXP (x
, 1), strict
)
2618 && CONST_INT_P (XEXP (x
, 1)))
2620 else if (nds32_address_register_rtx_p (XEXP (x
, 1), strict
)
2621 && nds32_legitimate_index_p (mode
, XEXP (x
, 0), strict
)
2622 && CONST_INT_P (XEXP (x
, 0)))
2626 /* Allow [post_inc] and [post_dec] addressing mode. */
2627 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == POST_DEC
)
2629 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
))
2633 /* Now check [reg], [symbol_ref], and [const]. */
2634 if (GET_CODE (x
) != REG
2635 && GET_CODE (x
) != SYMBOL_REF
2636 && GET_CODE (x
) != CONST
)
2640 /* Check if 'x' is a valid address. */
2641 switch (GET_CODE (x
))
2644 /* (mem (reg A)) => [Ra] */
2645 return nds32_address_register_rtx_p (x
, strict
);
2648 /* (mem (symbol_ref A)) => [symbol_ref] */
2650 if (flag_pic
|| SYMBOL_REF_TLS_MODEL (x
))
2653 if (TARGET_ICT_MODEL_LARGE
&& nds32_indirect_call_referenced_p (x
))
2656 /* If -mcmodel=large, the 'symbol_ref' is not a valid address
2657 during or after LRA/reload phase. */
2658 if (TARGET_CMODEL_LARGE
2659 && (reload_completed
2660 || reload_in_progress
2661 || lra_in_progress
))
2663 /* If -mcmodel=medium and the symbol references to rodata section,
2664 the 'symbol_ref' is not a valid address during or after
2665 LRA/reload phase. */
2666 if (TARGET_CMODEL_MEDIUM
2667 && (NDS32_SYMBOL_REF_RODATA_P (x
)
2668 || CONSTANT_POOL_ADDRESS_P (x
))
2669 && (reload_completed
2670 || reload_in_progress
2671 || lra_in_progress
))
2677 /* (mem (const (...)))
2678 => [ + const_addr ], where const_addr = symbol_ref + const_int */
2679 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2681 rtx plus_op
= XEXP (x
, 0);
2683 rtx op0
= XEXP (plus_op
, 0);
2684 rtx op1
= XEXP (plus_op
, 1);
2686 if (GET_CODE (op0
) == SYMBOL_REF
&& CONST_INT_P (op1
))
2688 /* Now we see the [ + const_addr ] pattern, but we need
2689 some further checking. */
2691 if (flag_pic
|| SYMBOL_REF_TLS_MODEL (op0
))
2694 /* If -mcmodel=large, the 'const_addr' is not a valid address
2695 during or after LRA/reload phase. */
2696 if (TARGET_CMODEL_LARGE
2697 && (reload_completed
2698 || reload_in_progress
2699 || lra_in_progress
))
2701 /* If -mcmodel=medium and the symbol references to rodata section,
2702 the 'const_addr' is not a valid address during or after
2703 LRA/reload phase. */
2704 if (TARGET_CMODEL_MEDIUM
2705 && NDS32_SYMBOL_REF_RODATA_P (op0
)
2706 && (reload_completed
2707 || reload_in_progress
2708 || lra_in_progress
))
2711 /* At this point we can make sure 'const_addr' is a
2720 /* (mem (post_modify (reg) (plus (reg) (reg))))
2722 /* (mem (post_modify (reg) (plus (reg) (const_int))))
2723 => [Ra], const_int */
2724 if (GET_CODE (XEXP (x
, 0)) == REG
2725 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2727 rtx plus_op
= XEXP (x
, 1);
2729 rtx op0
= XEXP (plus_op
, 0);
2730 rtx op1
= XEXP (plus_op
, 1);
2732 if (nds32_address_register_rtx_p (op0
, strict
)
2733 && nds32_legitimate_index_p (mode
, op1
, strict
))
2743 /* (mem (post_inc reg)) => [Ra], 1/2/4 */
2744 /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */
2745 /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
2746 We only need to deal with register Ra. */
2747 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
))
2753 /* (mem (plus reg const_int))
2755 /* (mem (plus reg reg))
2757 /* (mem (plus (mult reg const_int) reg))
2758 => [Ra + Rb << sv] */
2759 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
)
2760 && nds32_legitimate_index_p (mode
, XEXP (x
, 1), strict
))
2762 else if (nds32_address_register_rtx_p (XEXP (x
, 1), strict
)
2763 && nds32_legitimate_index_p (mode
, XEXP (x
, 0), strict
))
2769 /* (mem (lo_sum (reg) (symbol_ref))) */
2770 /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */
2771 /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */
2772 /* The LO_SUM is a valid address if and only if we would like to
2773 generate 32-bit full address memory access with any of following
2776 2. -mcmodel=medium and the symbol_ref references to rodata. */
2783 if (!REG_P (XEXP (x
, 0)))
2786 if (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
2788 else if (GET_CODE (XEXP (x
, 1)) == CONST
)
2790 rtx plus
= XEXP(XEXP (x
, 1), 0);
2791 if (GET_CODE (plus
) == PLUS
)
2792 sym
= XEXP (plus
, 0);
2793 else if (GET_CODE (plus
) == UNSPEC
)
2794 sym
= XVECEXP (plus
, 0, 0);
2799 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
);
2801 if (TARGET_ICT_MODEL_LARGE
2802 && nds32_indirect_call_referenced_p (sym
))
2805 if (TARGET_CMODEL_LARGE
)
2807 else if (TARGET_CMODEL_MEDIUM
2808 && NDS32_SYMBOL_REF_RODATA_P (sym
))
2820 nds32_legitimize_address (rtx x
,
2821 rtx oldx ATTRIBUTE_UNUSED
,
2822 machine_mode mode ATTRIBUTE_UNUSED
)
2824 if (nds32_tls_referenced_p (x
))
2825 x
= nds32_legitimize_tls_address (x
);
2826 else if (flag_pic
&& SYMBOLIC_CONST_P (x
))
2827 x
= nds32_legitimize_pic_address (x
);
2828 else if (TARGET_ICT_MODEL_LARGE
&& nds32_indirect_call_referenced_p (x
))
2829 x
= nds32_legitimize_ict_address (x
);
2835 nds32_legitimate_constant_p (machine_mode mode
, rtx x
)
2837 switch (GET_CODE (x
))
2840 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
2841 && (mode
== DFmode
|| mode
== SFmode
))
2847 if (GET_CODE (x
) == PLUS
)
2849 if (!CONST_INT_P (XEXP (x
, 1)))
2854 if (GET_CODE (x
) == UNSPEC
)
2856 switch (XINT (x
, 1))
2873 /* TLS symbols need a call to resolve in
2874 precompute_register_parameters. */
2875 if (SYMBOL_REF_TLS_MODEL (x
))
2885 /* Reorgnize the UNSPEC CONST and return its direct symbol. */
2887 nds32_delegitimize_address (rtx x
)
2889 x
= delegitimize_mem_from_attrs (x
);
2891 if (GET_CODE(x
) == CONST
)
2893 rtx inner
= XEXP (x
, 0);
2895 /* Handle for GOTOFF. */
2896 if (GET_CODE (inner
) == PLUS
)
2897 inner
= XEXP (inner
, 0);
2899 if (GET_CODE (inner
) == UNSPEC
)
2901 switch (XINT (inner
, 1))
2903 case UNSPEC_GOTINIT
:
2912 x
= XVECEXP (inner
, 0, 0);
2923 nds32_vectorize_preferred_simd_mode (scalar_mode mode
)
2925 if (!NDS32_EXT_DSP_P ())
2940 nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2942 switch (GET_CODE (x
))
2945 return !nds32_legitimate_constant_p (mode
, x
);
2947 /* All symbols have to be accessed through gp-relative in PIC mode. */
2948 /* We don't want to force symbol as constant pool in .text section,
2949 because we use the gp-relatived instruction to load in small
2952 || SYMBOL_REF_TLS_MODEL (x
)
2953 || TARGET_CMODEL_SMALL
2954 || TARGET_CMODEL_MEDIUM
)
2959 if (flag_pic
&& (lra_in_progress
|| reload_completed
))
2969 /* Condition Code Status. */
2971 /* -- Representation of condition codes using registers. */
2974 nds32_canonicalize_comparison (int *code
,
2975 rtx
*op0 ATTRIBUTE_UNUSED
,
2977 bool op0_preserve_value ATTRIBUTE_UNUSED
)
2979 /* When the instruction combination pass tries to combine a comparison insn
2980 with its previous insns, it also transforms the operator in order to
2981 minimize its constant field. For example, it tries to transform a
2982 comparison insn from
2985 (const_int 10 [0xa])))
2989 (const_int 9 [0x9])))
2991 However, the nds32 target only provides instructions supporting the LTU
2992 operation directly, and the implementation of the pattern "cbranchsi4"
2993 only expands the LTU form. In order to handle the non-LTU operations
2994 generated from passes other than the RTL expansion pass, we have to
2995 implement this hook to revert those changes. Since we only expand the LTU
2996 operator in the RTL expansion pass, we might only need to handle the LEU
2997 case, unless we find other optimization passes perform more aggressive
3000 if (*code
== LEU
&& CONST_INT_P (*op1
))
3002 *op1
= gen_int_mode (INTVAL (*op1
) + 1, SImode
);
3008 /* Describing Relative Costs of Operations. */
3011 nds32_register_move_cost (machine_mode mode
,
3015 /* In garywolf cpu, FPR to GPR is chaper than other cpu. */
3016 if (TARGET_PIPELINE_GRAYWOLF
)
3018 if (GET_MODE_SIZE (mode
) == 8)
3021 if (from
== FP_REGS
&& to
!= FP_REGS
)
3024 if (from
!= FP_REGS
&& to
== FP_REGS
)
3029 if ((from
== FP_REGS
&& to
!= FP_REGS
)
3030 || (from
!= FP_REGS
&& to
== FP_REGS
))
3035 if ((from
== FP_REGS
&& to
!= FP_REGS
)
3036 || (from
!= FP_REGS
&& to
== FP_REGS
))
3038 else if (from
== HIGH_REGS
|| to
== HIGH_REGS
)
3039 return optimize_size
? 6 : 2;
3045 nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3046 reg_class_t rclass ATTRIBUTE_UNUSED
,
3047 bool in ATTRIBUTE_UNUSED
)
3052 /* This target hook describes the relative costs of RTL expressions.
3053 Return 'true' when all subexpressions of x have been processed.
3054 Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
3055 Refer to gcc/rtlanal.c for more information. */
3057 nds32_rtx_costs (rtx x
,
3064 return nds32_rtx_costs_impl (x
, mode
, outer_code
, opno
, total
, speed
);
3068 nds32_address_cost (rtx address
,
3073 return nds32_address_cost_impl (address
, mode
, as
, speed
);
3077 /* Dividing the Output into Sections (Texts, Data, . . . ). */
3079 /* If references to a symbol or a constant must be treated differently
3080 depending on something about the variable or function named by the symbol
3081 (such as what section it is in), we use this hook to store flags
3082 in symbol_ref rtx. */
3084 nds32_encode_section_info (tree decl
, rtx rtl
, int new_decl_p
)
3086 default_encode_section_info (decl
, rtl
, new_decl_p
);
3088 /* For the memory rtx, if it references to rodata section, we can store
3089 NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the
3090 nds32_legitimate_address_p() can determine how to treat such symbol_ref
3091 based on -mcmodel=X and this information. */
3092 if (MEM_P (rtl
) && MEM_READONLY_P (rtl
))
3094 rtx addr
= XEXP (rtl
, 0);
3096 if (GET_CODE (addr
) == SYMBOL_REF
)
3098 /* For (mem (symbol_ref X)) case. */
3099 SYMBOL_REF_FLAGS (addr
) |= NDS32_SYMBOL_FLAG_RODATA
;
3101 else if (GET_CODE (addr
) == CONST
3102 && GET_CODE (XEXP (addr
, 0)) == PLUS
)
3104 /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */
3105 rtx plus_op
= XEXP (addr
, 0);
3106 rtx op0
= XEXP (plus_op
, 0);
3107 rtx op1
= XEXP (plus_op
, 1);
3109 if (GET_CODE (op0
) == SYMBOL_REF
&& CONST_INT_P (op1
))
3110 SYMBOL_REF_FLAGS (op0
) |= NDS32_SYMBOL_FLAG_RODATA
;
3116 /* Defining the Output Assembler Language. */
3118 /* -- The Overall Framework of an Assembler File. */
3121 nds32_asm_file_start (void)
3123 default_file_start ();
3126 fprintf (asm_out_file
, "\t.pic\n");
3128 /* Tell assembler which ABI we are using. */
3129 fprintf (asm_out_file
, "\t! ABI version\n");
3130 if (TARGET_HARD_FLOAT
)
3131 fprintf (asm_out_file
, "\t.abi_2fp_plus\n");
3133 fprintf (asm_out_file
, "\t.abi_2\n");
3135 /* Tell assembler that this asm code is generated by compiler. */
3136 fprintf (asm_out_file
, "\t! This asm file is generated by compiler\n");
3137 fprintf (asm_out_file
, "\t.flag\tverbatim\n");
3139 /* Insert directive for linker to distinguish object's ict flag. */
3140 if (!TARGET_LINUX_ABI
)
3142 if (TARGET_ICT_MODEL_LARGE
)
3143 fprintf (asm_out_file
, "\t.ict_model\tlarge\n");
3145 fprintf (asm_out_file
, "\t.ict_model\tsmall\n");
3148 /* We need to provide the size of each vector for interrupt handler
3149 under elf toolchain. */
3150 if (!TARGET_LINUX_ABI
)
3152 fprintf (asm_out_file
, "\t! This vector size directive is required "
3153 "for checking inconsistency on interrupt handler\n");
3154 fprintf (asm_out_file
, "\t.vec_size\t%d\n", nds32_isr_vector_size
);
3157 /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os,
3158 the compiler may produce 'la $fp,_FP_BASE_' instruction
3159 at prologue for fp-as-gp optimization.
3160 We should emit weak reference of _FP_BASE_ to avoid undefined reference
3161 in case user does not pass '--relax' option to linker. */
3162 if (!TARGET_LINUX_ABI
&& (TARGET_FORCE_FP_AS_GP
|| optimize_size
))
3164 fprintf (asm_out_file
, "\t! This weak reference is required to do "
3165 "fp-as-gp link time optimization\n");
3166 fprintf (asm_out_file
, "\t.weak\t_FP_BASE_\n");
3169 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3172 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V2");
3174 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V3");
3176 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V3M");
3178 switch (nds32_cpu_option
)
3181 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N6");
3185 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N7");
3189 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N8");
3193 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "E8");
3197 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N9");
3201 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N10");
3205 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "Graywolf");
3210 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N13");
3214 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "SIMPLE");
3221 if (TARGET_CMODEL_SMALL
)
3222 fprintf (asm_out_file
, "\t! Code model\t\t: %s\n", "SMALL");
3223 if (TARGET_CMODEL_MEDIUM
)
3224 fprintf (asm_out_file
, "\t! Code model\t\t: %s\n", "MEDIUM");
3225 if (TARGET_CMODEL_LARGE
)
3226 fprintf (asm_out_file
, "\t! Code model\t\t: %s\n", "LARGE");
3228 fprintf (asm_out_file
, "\t! Endian setting\t: %s\n",
3229 ((TARGET_BIG_ENDIAN
) ? "big-endian"
3230 : "little-endian"));
3231 fprintf (asm_out_file
, "\t! Use SP floating-point instruction\t: %s\n",
3232 ((TARGET_FPU_SINGLE
) ? "Yes"
3234 fprintf (asm_out_file
, "\t! Use DP floating-point instruction\t: %s\n",
3235 ((TARGET_FPU_DOUBLE
) ? "Yes"
3237 fprintf (asm_out_file
, "\t! ABI version\t\t: %s\n",
3238 ((TARGET_HARD_FLOAT
) ? "ABI2FP+"
3241 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3243 fprintf (asm_out_file
, "\t! Use conditional move\t\t: %s\n",
3244 ((TARGET_CMOV
) ? "Yes"
3246 fprintf (asm_out_file
, "\t! Use performance extension\t: %s\n",
3247 ((TARGET_EXT_PERF
) ? "Yes"
3249 fprintf (asm_out_file
, "\t! Use performance extension 2\t: %s\n",
3250 ((TARGET_EXT_PERF2
) ? "Yes"
3252 fprintf (asm_out_file
, "\t! Use string extension\t\t: %s\n",
3253 ((TARGET_EXT_STRING
) ? "Yes"
3256 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3258 fprintf (asm_out_file
, "\t! V3PUSH instructions\t: %s\n",
3259 ((TARGET_V3PUSH
) ? "Yes"
3261 fprintf (asm_out_file
, "\t! 16-bit instructions\t: %s\n",
3262 ((TARGET_16_BIT
) ? "Yes"
3264 fprintf (asm_out_file
, "\t! Reduced registers set\t: %s\n",
3265 ((TARGET_REDUCED_REGS
) ? "Yes"
3268 fprintf (asm_out_file
, "\t! Support unaligned access\t\t: %s\n",
3269 (flag_unaligned_access
? "Yes"
3272 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3275 fprintf (asm_out_file
, "\t! Optimization level\t: -Os\n");
3276 else if (optimize_fast
)
3277 fprintf (asm_out_file
, "\t! Optimization level\t: -Ofast\n");
3278 else if (optimize_debug
)
3279 fprintf (asm_out_file
, "\t! Optimization level\t: -Og\n");
3281 fprintf (asm_out_file
, "\t! Optimization level\t: -O%d\n", optimize
);
3283 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3285 fprintf (asm_out_file
, "\t! Cache block size\t: %d\n",
3286 nds32_cache_block_size
);
3288 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3290 nds32_asm_file_start_for_isr ();
3294 nds32_asm_file_end (void)
3296 nds32_asm_file_end_for_isr ();
3298 /* The NDS32 Linux stack is mapped non-executable by default, so add a
3299 .note.GNU-stack section. */
3300 if (TARGET_LINUX_ABI
)
3301 file_end_indicate_exec_stack ();
3303 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3307 nds32_asm_output_addr_const_extra (FILE *file
, rtx x
)
3309 if (GET_CODE (x
) == UNSPEC
)
3311 switch (XINT (x
, 1))
3313 case UNSPEC_GOTINIT
:
3314 output_addr_const (file
, XVECEXP (x
, 0, 0));
3317 output_addr_const (file
, XVECEXP (x
, 0, 0));
3318 fputs ("@GOTOFF", file
);
3321 output_addr_const (file
, XVECEXP (x
, 0, 0));
3322 fputs ("@GOT", file
);
3325 output_addr_const (file
, XVECEXP (x
, 0, 0));
3326 fputs ("@PLT", file
);
3329 output_addr_const (file
, XVECEXP (x
, 0, 0));
3330 fputs ("@TLSDESC", file
);
3333 output_addr_const (file
, XVECEXP (x
, 0, 0));
3334 fputs ("@TLSDESC", file
);
3337 output_addr_const (file
, XVECEXP (x
, 0, 0));
3338 fputs ("@GOTTPOFF", file
);
3341 output_addr_const (file
, XVECEXP (x
, 0, 0));
3342 fputs ("@TPOFF", file
);
3345 output_addr_const (file
, XVECEXP (x
, 0, 0));
3346 fputs ("@ICT", file
);
3357 /* -- Output and Generation of Labels. */
3360 nds32_asm_globalize_label (FILE *stream
, const char *name
)
3362 fputs ("\t.global\t", stream
);
3363 assemble_name (stream
, name
);
3364 fputs ("\n", stream
);
3367 /* -- Output of Assembler Instructions. */
3370 nds32_print_operand (FILE *stream
, rtx x
, int code
)
3372 HOST_WIDE_INT op_value
= 0;
3373 HOST_WIDE_INT one_position
;
3374 HOST_WIDE_INT zero_position
;
3375 bool pick_lsb_p
= false;
3376 bool pick_msb_p
= false;
3379 if (CONST_INT_P (x
))
3380 op_value
= INTVAL (x
);
3385 /* Do nothing special. */
3389 /* Use exact_log2() to search the 0-bit position. */
3390 gcc_assert (CONST_INT_P (x
));
3391 zero_position
= exact_log2 (~UINTVAL (x
) & GET_MODE_MASK (SImode
));
3392 gcc_assert (zero_position
!= -1);
3393 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, zero_position
);
3395 /* No need to handle following process, so return immediately. */
3399 gcc_assert (MEM_P (x
)
3400 && GET_CODE (XEXP (x
, 0)) == PLUS
3401 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
3402 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (XEXP (XEXP (x
, 0), 1)));
3404 /* No need to handle following process, so return immediately. */
3408 gcc_assert (CONST_INT_P (x
)
3412 || INTVAL (x
) == 24));
3413 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) / 8);
3415 /* No need to handle following process, so return immediately. */
3419 /* Use exact_log2() to search the 1-bit position. */
3420 gcc_assert (CONST_INT_P (x
));
3421 one_position
= exact_log2 (UINTVAL (x
) & GET_MODE_MASK (SImode
));
3422 gcc_assert (one_position
!= -1);
3423 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, one_position
);
3425 /* No need to handle following process, so return immediately. */
3429 /* X is supposed to be REG rtx. */
3430 gcc_assert (REG_P (x
));
3431 /* Claim that we are going to pick LSB part of X. */
3436 /* X is supposed to be REG rtx. */
3437 gcc_assert (REG_P (x
));
3438 /* Claim that we are going to pick MSB part of X. */
3443 /* 'x' is supposed to be CONST_INT, get the value. */
3444 gcc_assert (CONST_INT_P (x
));
3446 /* According to the Andes architecture,
3447 the system/user register index range is 0 ~ 1023.
3448 In order to avoid conflict between user-specified-integer value
3449 and enum-specified-register value,
3450 the 'enum nds32_intrinsic_registers' value
3451 in nds32_intrinsic.h starts from 1024. */
3452 if (op_value
< 1024 && op_value
>= 0)
3454 /* If user gives integer value directly (0~1023),
3455 we just print out the value. */
3456 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, op_value
);
3458 else if (op_value
< 0
3459 || op_value
>= ((int) ARRAY_SIZE (nds32_intrinsic_register_names
)
3462 /* The enum index value for array size is out of range. */
3463 error ("intrinsic register index is out of range");
3467 /* If user applies normal way with __NDS32_REG_XXX__ enum data,
3468 we can print out register name. Remember to substract 1024. */
3469 fprintf (stream
, "%s",
3470 nds32_intrinsic_register_names
[op_value
- 1024]);
3473 /* No need to handle following process, so return immediately. */
3476 case 'R': /* cctl valck */
3477 /* Note the cctl divide to 5 group and share the same name table. */
3478 if (op_value
< 0 || op_value
> 4)
3479 error ("CCTL intrinsic function subtype out of range!");
3480 fprintf (stream
, "%s", nds32_cctl_names
[op_value
]);
3483 case 'T': /* cctl idxwbinv */
3484 /* Note the cctl divide to 5 group and share the same name table. */
3485 if (op_value
< 0 || op_value
> 4)
3486 error ("CCTL intrinsic function subtype out of range!");
3487 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 4]);
3490 case 'U': /* cctl vawbinv */
3491 /* Note the cctl divide to 5 group and share the same name table. */
3492 if (op_value
< 0 || op_value
> 4)
3493 error ("CCTL intrinsic function subtype out of range!");
3494 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 8]);
3497 case 'X': /* cctl idxread */
3498 /* Note the cctl divide to 5 group and share the same name table. */
3499 if (op_value
< 0 || op_value
> 4)
3500 error ("CCTL intrinsic function subtype out of range!");
3501 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 12]);
3504 case 'W': /* cctl idxwitre */
3505 /* Note the cctl divide to 5 group and share the same name table. */
3506 if (op_value
< 0 || op_value
> 4)
3507 error ("CCTL intrinsic function subtype out of range!");
3508 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 16]);
3511 case 'Z': /* dpref */
3512 fprintf (stream
, "%s", nds32_dpref_names
[op_value
]);
3517 output_operand_lossage ("invalid operand output code");
3521 switch (GET_CODE (x
))
3524 output_addr_const (stream
, x
);
3528 output_addr_const (stream
, x
);
3530 if (!TARGET_LINUX_ABI
&& nds32_indirect_call_referenced_p (x
))
3531 fprintf (stream
, "@ICT");
3536 /* Print a Double-precision register name. */
3537 if ((GET_MODE (x
) == DImode
|| GET_MODE (x
) == DFmode
)
3538 && NDS32_IS_FPR_REGNUM (REGNO (x
)))
3541 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno
))
3543 output_operand_lossage ("invalid operand for code '%c'", code
);
3546 fprintf (stream
, "$fd%d", (regno
- NDS32_FIRST_FPR_REGNUM
) >> 1);
3550 /* Print LSB or MSB part of register pair if the
3551 constraint modifier 'L' or 'H' is specified. */
3552 if ((GET_MODE (x
) == DImode
|| GET_MODE (x
) == DFmode
)
3553 && NDS32_IS_GPR_REGNUM (REGNO (x
)))
3555 if ((pick_lsb_p
&& WORDS_BIG_ENDIAN
)
3556 || (pick_msb_p
&& !WORDS_BIG_ENDIAN
))
3558 /* If we would like to print out LSB register under big-endian,
3559 or print out MSB register under little-endian, we need to
3560 increase register number. */
3563 fputs (reg_names
[regno
], stream
);
3568 /* Forbid using static chain register ($r16)
3569 on reduced-set registers configuration. */
3570 if (TARGET_REDUCED_REGS
3571 && REGNO (x
) == STATIC_CHAIN_REGNUM
)
3572 sorry ("a nested function is not supported for reduced registers");
3574 /* Normal cases, print out register name. */
3575 fputs (reg_names
[REGNO (x
)], stream
);
3579 output_address (GET_MODE (x
), XEXP (x
, 0));
3583 if (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
)
3585 const REAL_VALUE_TYPE
*rv
;
3587 gcc_assert (GET_MODE (x
) == SFmode
);
3589 rv
= CONST_DOUBLE_REAL_VALUE (XEXP (x
, 0));
3590 REAL_VALUE_TO_TARGET_SINGLE (*rv
, val
);
3592 fprintf (stream
, "hi20(0x%lx)", val
);
3599 const REAL_VALUE_TYPE
*rv
;
3601 gcc_assert (GET_MODE (x
) == SFmode
);
3603 rv
= CONST_DOUBLE_REAL_VALUE (x
);
3604 REAL_VALUE_TO_TARGET_SINGLE (*rv
, val
);
3606 fprintf (stream
, "0x%lx", val
);
3612 output_addr_const (stream
, x
);
3616 fprintf (stream
, HOST_WIDE_INT_PRINT_HEX
, const_vector_to_hwint (x
));
3620 /* This is a special case for inline assembly using memory address 'p'.
3621 The inline assembly code is expected to use pesudo instruction
3622 for the operand. EX: la */
3623 output_addr_const (stream
, XEXP(x
, 1));
3627 /* Generally, output_addr_const () is able to handle most cases.
3628 We want to see what CODE could appear,
3629 so we use gcc_unreachable() to stop it. */
3637 nds32_print_operand_address (FILE *stream
,
3638 machine_mode mode ATTRIBUTE_UNUSED
,
3643 switch (GET_CODE (x
))
3647 /* [ + symbol_ref] */
3648 /* [ + const_addr], where const_addr = symbol_ref + const_int */
3649 fputs ("[ + ", stream
);
3650 output_addr_const (stream
, x
);
3651 fputs ("]", stream
);
3655 /* This is a special case for inline assembly using memory operand 'm'.
3656 The inline assembly code is expected to use pesudo instruction
3657 for the operand. EX: [ls].[bhw] */
3658 fputs ("[ + ", stream
);
3660 output_addr_const (stream
, op1
);
3661 fputs ("]", stream
);
3665 /* Forbid using static chain register ($r16)
3666 on reduced-set registers configuration. */
3667 if (TARGET_REDUCED_REGS
3668 && REGNO (x
) == STATIC_CHAIN_REGNUM
)
3669 sorry ("a nested function is not supported for reduced registers");
3672 fprintf (stream
, "[%s]", reg_names
[REGNO (x
)]);
3679 /* Checking op0, forbid using static chain register ($r16)
3680 on reduced-set registers configuration. */
3681 if (TARGET_REDUCED_REGS
3683 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
3684 sorry ("a nested function is not supported for reduced registers");
3685 /* Checking op1, forbid using static chain register ($r16)
3686 on reduced-set registers configuration. */
3687 if (TARGET_REDUCED_REGS
3689 && REGNO (op1
) == STATIC_CHAIN_REGNUM
)
3690 sorry ("a nested function is not supported for reduced registers");
3692 if (REG_P (op0
) && CONST_INT_P (op1
))
3695 fprintf (stream
, "[%s + (" HOST_WIDE_INT_PRINT_DEC
")]",
3696 reg_names
[REGNO (op0
)], INTVAL (op1
));
3698 else if (REG_P (op0
) && REG_P (op1
))
3701 fprintf (stream
, "[%s + %s]",
3702 reg_names
[REGNO (op0
)], reg_names
[REGNO (op1
)]);
3704 else if (GET_CODE (op0
) == MULT
&& REG_P (op1
))
3707 From observation, the pattern looks like:
3708 (plus:SI (mult:SI (reg:SI 58)
3709 (const_int 4 [0x4]))
3713 /* We need to set sv to output shift value. */
3714 if (INTVAL (XEXP (op0
, 1)) == 1)
3716 else if (INTVAL (XEXP (op0
, 1)) == 2)
3718 else if (INTVAL (XEXP (op0
, 1)) == 4)
3720 else if (INTVAL (XEXP (op0
, 1)) == 8)
3725 fprintf (stream
, "[%s + %s << %d]",
3726 reg_names
[REGNO (op1
)],
3727 reg_names
[REGNO (XEXP (op0
, 0))],
3730 else if (GET_CODE (op0
) == ASHIFT
&& REG_P (op1
))
3733 In normal, ASHIFT can be converted to MULT like above case.
3734 But when the address rtx does not go through canonicalize_address
3735 defined in fwprop, we'll need this case. */
3736 int sv
= INTVAL (XEXP (op0
, 1));
3737 gcc_assert (sv
<= 3 && sv
>=0);
3739 fprintf (stream
, "[%s + %s << %d]",
3740 reg_names
[REGNO (op1
)],
3741 reg_names
[REGNO (XEXP (op0
, 0))],
3746 /* The control flow is not supposed to be here. */
3754 /* (post_modify (regA) (plus (regA) (regB)))
3755 (post_modify (regA) (plus (regA) (const_int)))
3756 We would like to extract
3757 regA and regB (or const_int) from plus rtx. */
3758 op0
= XEXP (XEXP (x
, 1), 0);
3759 op1
= XEXP (XEXP (x
, 1), 1);
3761 /* Checking op0, forbid using static chain register ($r16)
3762 on reduced-set registers configuration. */
3763 if (TARGET_REDUCED_REGS
3765 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
3766 sorry ("a nested function is not supported for reduced registers");
3767 /* Checking op1, forbid using static chain register ($r16)
3768 on reduced-set registers configuration. */
3769 if (TARGET_REDUCED_REGS
3771 && REGNO (op1
) == STATIC_CHAIN_REGNUM
)
3772 sorry ("a nested function is not supported for reduced registers");
3774 if (REG_P (op0
) && REG_P (op1
))
3777 fprintf (stream
, "[%s], %s",
3778 reg_names
[REGNO (op0
)], reg_names
[REGNO (op1
)]);
3780 else if (REG_P (op0
) && CONST_INT_P (op1
))
3783 fprintf (stream
, "[%s], " HOST_WIDE_INT_PRINT_DEC
,
3784 reg_names
[REGNO (op0
)], INTVAL (op1
));
3788 /* The control flow is not supposed to be here. */
3799 /* Checking op0, forbid using static chain register ($r16)
3800 on reduced-set registers configuration. */
3801 if (TARGET_REDUCED_REGS
3803 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
3804 sorry ("a nested function is not supported for reduced registers");
3808 /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4"
3809 The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
3810 We only need to deal with register Ra. */
3811 fprintf (stream
, "[%s]", reg_names
[REGNO (op0
)]);
3815 /* The control flow is not supposed to be here. */
3823 /* Generally, output_addr_const () is able to handle most cases.
3824 We want to see what CODE could appear,
3825 so we use gcc_unreachable() to stop it. */
3832 /* -- Assembler Commands for Exception Regions. */
3835 nds32_dwarf_register_span (rtx reg
)
3837 rtx dwarf_high
, dwarf_low
;
3842 mode
= GET_MODE (reg
);
3843 regno
= REGNO (reg
);
3845 /* We need to adjust dwarf register information for floating-point registers
3846 rather than using default register number mapping. */
3847 if (regno
>= NDS32_FIRST_FPR_REGNUM
3848 && regno
<= NDS32_LAST_FPR_REGNUM
)
3850 if (mode
== DFmode
|| mode
== SCmode
)
3852 /* By default, GCC maps increasing register numbers to increasing
3853 memory locations, but paired FPRs in NDS32 target are always
3859 We must return parallel rtx to represent such layout. */
3860 dwarf_high
= gen_rtx_REG (word_mode
, regno
);
3861 dwarf_low
= gen_rtx_REG (word_mode
, regno
+ 1);
3862 return gen_rtx_PARALLEL (VOIDmode
,
3863 gen_rtvec (2, dwarf_low
, dwarf_high
));
3865 else if (mode
== DCmode
)
3867 rtx dwarf_high_re
= gen_rtx_REG (word_mode
, regno
);
3868 rtx dwarf_low_re
= gen_rtx_REG (word_mode
, regno
+ 1);
3869 rtx dwarf_high_im
= gen_rtx_REG (word_mode
, regno
);
3870 rtx dwarf_low_im
= gen_rtx_REG (word_mode
, regno
+ 1);
3871 return gen_rtx_PARALLEL (VOIDmode
,
3872 gen_rtvec (4, dwarf_low_re
, dwarf_high_re
,
3873 dwarf_high_im
, dwarf_low_im
));
3875 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3881 /* We should not be here. */
3889 /* Map internal gcc register numbers to DWARF2 register numbers. */
3892 nds32_dbx_register_number (unsigned int regno
)
3894 /* The nds32 port in GDB maintains a mapping between dwarf register
3895 number and displayed register name. For backward compatibility to
3896 previous toolchain, currently our gdb still has four registers
3897 (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler
3898 does not count those four registers in its register number table.
3899 So we have to add 4 on its register number and then create new
3900 dwarf information. Hopefully we can discard such workaround
3902 if (NDS32_IS_FPR_REGNUM (regno
))
3909 /* Defining target-specific uses of __attribute__. */
3911 /* Add some checking after merging attributes. */
3913 nds32_merge_decl_attributes (tree olddecl
, tree newdecl
)
3915 tree combined_attrs
;
3917 /* Create combined attributes. */
3918 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
3919 DECL_ATTRIBUTES (newdecl
));
3921 /* Since newdecl is acutally a duplicate of olddecl,
3922 we can take olddecl for some operations. */
3923 if (TREE_CODE (olddecl
) == FUNCTION_DECL
)
3925 /* Check isr-specific attributes conflict. */
3926 nds32_check_isr_attrs_conflict (olddecl
, combined_attrs
);
3929 return combined_attrs
;
3932 /* Add some checking when inserting attributes. */
3934 nds32_insert_attributes (tree decl
, tree
*attributes
)
3936 /* A "indirect_call" function attribute implies "noinline" and "noclone"
3937 for elf toolchain to support ROM patch mechanism. */
3938 if (TREE_CODE (decl
) == FUNCTION_DECL
3939 && lookup_attribute ("indirect_call", *attributes
) != NULL
)
3941 tree new_attrs
= *attributes
;
3943 if (TARGET_LINUX_ABI
)
3944 error("cannot use indirect_call attribute under linux toolchain");
3946 if (lookup_attribute ("noinline", new_attrs
) == NULL
)
3947 new_attrs
= tree_cons (get_identifier ("noinline"), NULL
, new_attrs
);
3948 if (lookup_attribute ("noclone", new_attrs
) == NULL
)
3949 new_attrs
= tree_cons (get_identifier ("noclone"), NULL
, new_attrs
);
3951 if (!TREE_PUBLIC (decl
))
3952 error ("indirect_call attribute can%'t apply for static function");
3954 *attributes
= new_attrs
;
3957 /* For function declaration, we need to check isr-specific attributes:
3958 1. Call nds32_check_isr_attrs_conflict() to check any conflict.
3959 2. Check valid integer value for interrupt/exception.
3960 3. Check valid integer value for reset.
3961 4. Check valid function for nmi/warm. */
3962 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3965 tree intr
, excp
, reset
;
3967 /* Pick up function attributes. */
3968 func_attrs
= *attributes
;
3970 /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */
3971 nds32_check_isr_attrs_conflict (decl
, func_attrs
);
3973 /* Now we are starting to check valid id value
3974 for interrupt/exception/reset.
3975 Note that we ONLY check its validity here.
3976 To construct isr vector information, it is still performed
3977 by nds32_construct_isr_vectors_information(). */
3978 intr
= lookup_attribute ("interrupt", func_attrs
);
3979 excp
= lookup_attribute ("exception", func_attrs
);
3980 reset
= lookup_attribute ("reset", func_attrs
);
3982 /* The following code may use attribute arguments. If there is no
3983 argument from source code, it will cause segmentation fault.
3984 Therefore, return dircetly and report error message later. */
3985 if ((intr
&& TREE_VALUE (intr
) == NULL
)
3986 || (excp
&& TREE_VALUE (excp
) == NULL
)
3987 || (reset
&& TREE_VALUE (reset
) == NULL
))
3990 /* ------------------------------------------------------------- */
3992 FOR BACKWARD COMPATIBILITY, we need to support following patterns:
3994 __attribute__((interrupt("XXX;YYY;id=ZZZ")))
3995 __attribute__((exception("XXX;YYY;id=ZZZ")))
3996 __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
3998 If interrupt/exception/reset appears and its argument is a
3999 STRING_CST, we will use other functions to parse string in the
4000 nds32_construct_isr_vectors_information() and then set necessary
4001 isr information in the nds32_isr_vectors[] array. Here we can
4002 just return immediately to avoid new-syntax checking. */
4003 if (intr
!= NULL_TREE
4004 && TREE_CODE (TREE_VALUE (TREE_VALUE (intr
))) == STRING_CST
)
4006 if (excp
!= NULL_TREE
4007 && TREE_CODE (TREE_VALUE (TREE_VALUE (excp
))) == STRING_CST
)
4009 if (reset
!= NULL_TREE
4010 && TREE_CODE (TREE_VALUE (TREE_VALUE (reset
))) == STRING_CST
)
4012 /* ------------------------------------------------------------- */
4016 /* Deal with interrupt/exception. */
4018 unsigned int lower_bound
, upper_bound
;
4020 /* The way to handle interrupt or exception is the same,
4021 we just need to take care of actual vector number.
4022 For interrupt(0..63), the actual vector number is (9..72).
4023 For exception(1..8), the actual vector number is (1..8). */
4024 lower_bound
= (intr
) ? (0) : (1);
4025 upper_bound
= (intr
) ? (63) : (8);
4027 /* Prepare id list so that we can traverse id value. */
4028 id_list
= (intr
) ? (TREE_VALUE (intr
)) : (TREE_VALUE (excp
));
4030 /* 2. Check valid integer value for interrupt/exception. */
4035 /* Pick up each vector id value. */
4036 id
= TREE_VALUE (id_list
);
4037 /* Issue error if it is not a valid integer value. */
4038 if (TREE_CODE (id
) != INTEGER_CST
4039 || wi::ltu_p (wi::to_wide (id
), lower_bound
)
4040 || wi::gtu_p (wi::to_wide (id
), upper_bound
))
4041 error ("invalid id value for interrupt/exception attribute");
4043 /* Advance to next id. */
4044 id_list
= TREE_CHAIN (id_list
);
4049 /* Deal with reset. */
4053 unsigned int lower_bound
;
4054 unsigned int upper_bound
;
4056 /* Prepare id_list and identify id value so that
4057 we can check if total number of vectors is valid. */
4058 id_list
= TREE_VALUE (reset
);
4059 id
= TREE_VALUE (id_list
);
4061 /* The maximum numbers for user's interrupt is 64. */
4065 /* 3. Check valid integer value for reset. */
4066 if (TREE_CODE (id
) != INTEGER_CST
4067 || wi::ltu_p (wi::to_wide (id
), lower_bound
)
4068 || wi::gtu_p (wi::to_wide (id
), upper_bound
))
4069 error ("invalid id value for reset attribute");
4071 /* 4. Check valid function for nmi/warm. */
4072 nmi
= lookup_attribute ("nmi", func_attrs
);
4073 warm
= lookup_attribute ("warm", func_attrs
);
4075 if (nmi
!= NULL_TREE
)
4080 nmi_func_list
= TREE_VALUE (nmi
);
4081 nmi_func
= TREE_VALUE (nmi_func_list
);
4083 /* Issue error if it is not a valid nmi function. */
4084 if (TREE_CODE (nmi_func
) != IDENTIFIER_NODE
)
4085 error ("invalid nmi function for reset attribute");
4088 if (warm
!= NULL_TREE
)
4090 tree warm_func_list
;
4093 warm_func_list
= TREE_VALUE (warm
);
4094 warm_func
= TREE_VALUE (warm_func_list
);
4096 /* Issue error if it is not a valid warm function. */
4097 if (TREE_CODE (warm_func
) != IDENTIFIER_NODE
)
4098 error ("invalid warm function for reset attribute");
4103 /* No interrupt, exception, or reset attribute is set. */
4110 nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED
,
4111 tree pop_target ATTRIBUTE_UNUSED
)
4113 /* Currently, we do not parse any pragma target by ourself,
4114 so just simply return false. */
4119 nds32_option_override (void)
4121 /* After all the command options have been parsed,
4122 we shall deal with some flags for changing compiler settings. */
4124 /* At first, we check if we have to strictly
4125 set some flags based on ISA family. */
4128 /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */
4129 target_flags
&= ~MASK_V3PUSH
;
4133 /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */
4134 if (nds32_arch_option
== ARCH_V3J
)
4135 target_flags
|= MASK_REDUCED_REGS
;
4139 /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
4140 target_flags
|= MASK_REDUCED_REGS
;
4141 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */
4142 target_flags
&= ~MASK_EXT_PERF
;
4143 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */
4144 target_flags
&= ~MASK_EXT_PERF2
;
4145 /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */
4146 target_flags
&= ~MASK_EXT_STRING
;
4149 error ("not support %<-fpic%> option for v3m toolchain");
4152 /* See if we are using reduced-set registers:
4153 $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31
4154 If so, we must forbid using $r11~$r14, $r16~$r27. */
4155 if (TARGET_REDUCED_REGS
)
4159 /* Prevent register allocator from
4160 choosing it as doing register allocation. */
4161 for (r
= 11; r
<= 14; r
++)
4162 fixed_regs
[r
] = call_used_regs
[r
] = 1;
4163 for (r
= 16; r
<= 27; r
++)
4164 fixed_regs
[r
] = call_used_regs
[r
] = 1;
4167 /* See if user explicitly would like to use fp-as-gp optimization.
4168 If so, we must prevent $fp from being allocated
4169 during register allocation. */
4170 if (TARGET_FORCE_FP_AS_GP
)
4171 fixed_regs
[FP_REGNUM
] = call_used_regs
[FP_REGNUM
] = 1;
4175 /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */
4176 target_flags
&= ~MASK_V3PUSH
;
4179 if (TARGET_HARD_FLOAT
&& !(TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
))
4181 if (nds32_arch_option
== ARCH_V3S
|| nds32_arch_option
== ARCH_V3F
)
4182 error ("Disable FPU ISA, "
4183 "the ABI option must be enable %<-mfloat-abi=soft%>");
4185 error ("%<-mabi=2fp+%> option only support when FPU available, "
4186 "must be enable %<-mext-fpu-sp%> or %<-mext-fpu-dp%>");
4189 nds32_init_rtx_costs ();
4191 nds32_register_passes ();
4195 /* Miscellaneous Parameters. */
4198 nds32_md_asm_adjust (vec
<rtx
> &outputs ATTRIBUTE_UNUSED
,
4199 vec
<rtx
> &inputs ATTRIBUTE_UNUSED
,
4200 vec
<machine_mode
> &input_modes ATTRIBUTE_UNUSED
,
4201 vec
<const char *> &constraints ATTRIBUTE_UNUSED
,
4202 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
,
4205 if (!flag_inline_asm_r15
)
4207 clobbers
.safe_push (gen_rtx_REG (SImode
, TA_REGNUM
));
4208 SET_HARD_REG_BIT (clobbered_regs
, TA_REGNUM
);
4214 nds32_init_builtins (void)
4216 nds32_init_builtins_impl ();
4220 nds32_builtin_decl (unsigned code
, bool initialize_p
)
4222 /* Implement in nds32-intrinsic.c. */
4223 return nds32_builtin_decl_impl (code
, initialize_p
);
4227 nds32_expand_builtin (tree exp
,
4233 return nds32_expand_builtin_impl (exp
, target
, subtarget
, mode
, ignore
);
4236 /* Implement TARGET_INIT_LIBFUNCS. */
4238 nds32_init_libfuncs (void)
4240 if (TARGET_LINUX_ABI
)
4241 init_sync_libfuncs (UNITS_PER_WORD
);
4244 /* ------------------------------------------------------------------------ */
4246 /* PART 4: Implemet extern function definitions,
4247 the prototype is in nds32-protos.h. */
4249 /* Run-time Target Specification. */
4252 nds32_cpu_cpp_builtins(struct cpp_reader
*pfile
)
4254 #define builtin_define(TXT) cpp_define (pfile, TXT)
4255 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
4256 builtin_define ("__nds32__");
4257 builtin_define ("__NDS32__");
4259 /* We need to provide builtin macro to describe the size of
4260 each vector for interrupt handler under elf toolchain. */
4261 if (!TARGET_LINUX_ABI
)
4263 if (TARGET_ISR_VECTOR_SIZE_4_BYTE
)
4264 builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__");
4266 builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__");
4269 if (TARGET_HARD_FLOAT
)
4270 builtin_define ("__NDS32_ABI_2FP_PLUS__");
4272 builtin_define ("__NDS32_ABI_2__");
4275 builtin_define ("__NDS32_ISA_V2__");
4277 builtin_define ("__NDS32_ISA_V3__");
4279 builtin_define ("__NDS32_ISA_V3M__");
4281 if (TARGET_FPU_SINGLE
)
4282 builtin_define ("__NDS32_EXT_FPU_SP__");
4283 if (TARGET_FPU_DOUBLE
)
4284 builtin_define ("__NDS32_EXT_FPU_DP__");
4286 if (TARGET_EXT_FPU_FMA
)
4287 builtin_define ("__NDS32_EXT_FPU_FMA__");
4288 if (NDS32_EXT_FPU_DOT_E
)
4289 builtin_define ("__NDS32_EXT_FPU_DOT_E__");
4290 if (TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
4292 switch (nds32_fp_regnum
)
4296 builtin_define ("__NDS32_EXT_FPU_CONFIG_0__");
4300 builtin_define ("__NDS32_EXT_FPU_CONFIG_1__");
4304 builtin_define ("__NDS32_EXT_FPU_CONFIG_2__");
4308 builtin_define ("__NDS32_EXT_FPU_CONFIG_3__");
4315 if (TARGET_BIG_ENDIAN
)
4316 builtin_define ("__NDS32_EB__");
4318 builtin_define ("__NDS32_EL__");
4320 if (TARGET_REDUCED_REGS
)
4321 builtin_define ("__NDS32_REDUCED_REGS__");
4323 builtin_define ("__NDS32_CMOV__");
4324 if (TARGET_EXT_PERF
)
4325 builtin_define ("__NDS32_EXT_PERF__");
4326 if (TARGET_EXT_PERF2
)
4327 builtin_define ("__NDS32_EXT_PERF2__");
4328 if (TARGET_EXT_STRING
)
4329 builtin_define ("__NDS32_EXT_STRING__");
4331 builtin_define ("__NDS32_16_BIT__");
4332 if (TARGET_GP_DIRECT
)
4333 builtin_define ("__NDS32_GP_DIRECT__");
4335 builtin_define ("__NDS32_VH__");
4336 if (NDS32_EXT_DSP_P ())
4337 builtin_define ("__NDS32_EXT_DSP__");
4339 if (TARGET_BIG_ENDIAN
)
4340 builtin_define ("__big_endian__");
4342 builtin_assert ("cpu=nds32");
4343 builtin_assert ("machine=nds32");
4345 if (TARGET_HARD_FLOAT
)
4346 builtin_define ("__NDS32_ABI_2FP_PLUS");
4348 builtin_define ("__NDS32_ABI_2");
4350 #undef builtin_define
4351 #undef builtin_assert
4355 /* Defining Data Structures for Per-function Information. */
4358 nds32_init_expanders (void)
4360 /* Arrange to initialize and mark the machine per-function status. */
4361 init_machine_status
= nds32_init_machine_status
;
4365 /* Register Usage. */
4367 /* -- Order of Allocation of Registers. */
4370 nds32_adjust_reg_alloc_order (void)
4372 const int nds32_reg_alloc_order
[] = REG_ALLOC_ORDER
;
4374 /* Copy the default register allocation order, which is designed
4375 to optimize for code size. */
4376 memcpy(reg_alloc_order
, nds32_reg_alloc_order
, sizeof (reg_alloc_order
));
4378 /* Adjust few register allocation order when optimizing for speed. */
4381 memcpy (reg_alloc_order
, nds32_reg_alloc_order_for_speed
,
4382 sizeof (nds32_reg_alloc_order_for_speed
));
4386 /* -- How Values Fit in Registers. */
4389 nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED
,
4392 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
4395 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4398 nds32_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4400 if (regno
>= FIRST_PSEUDO_REGISTER
)
4403 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
) && NDS32_IS_FPR_REGNUM (regno
))
4405 if (NDS32_IS_EXT_FPR_REGNUM(regno
))
4406 return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno
) && (mode
== DFmode
));
4407 else if (mode
== SFmode
|| mode
== SImode
)
4408 return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno
);
4409 else if (mode
== DFmode
)
4410 return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno
);
4415 /* Restrict double-word quantities to even register pairs. */
4416 if (regno
<= NDS32_LAST_GPR_REGNUM
)
4417 return (targetm
.hard_regno_nregs (regno
, mode
) == 1
4423 /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to
4424 tie QI/HI/SI modes together. */
4427 nds32_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4429 if ((GET_MODE_CLASS (mode1
) == MODE_INT
4430 && GET_MODE_CLASS (mode2
) == MODE_INT
)
4431 && GET_MODE_SIZE (mode1
) <= UNITS_PER_WORD
4432 && GET_MODE_SIZE (mode2
) <= UNITS_PER_WORD
)
4435 if (GET_MODE_SIZE (mode1
) == GET_MODE_SIZE (mode2
))
4437 if ((TARGET_FPU_SINGLE
&& !TARGET_FPU_DOUBLE
)
4438 && (mode1
== DFmode
|| mode2
== DFmode
))
4447 /* Register Classes. */
4450 nds32_regno_reg_class (int regno
)
4452 /* Refer to nds32.h for more register class details. */
4454 if (regno
>= 0 && regno
<= 7)
4456 else if (regno
>= 8 && regno
<= 11)
4458 else if (regno
>= 12 && regno
<= 14)
4460 else if (regno
== 15)
4462 else if (regno
>= 16 && regno
<= 19)
4464 else if (regno
>= 20 && regno
<= 31)
4466 else if (regno
== 32 || regno
== 33)
4468 /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't
4469 know how to allocate register for $SFP and $AP, just tell IRA they
4470 are GENERAL_REGS, and ARM do this hack too. */
4471 return GENERAL_REGS
;
4473 else if (regno
>= 34 && regno
<= 97)
4480 /* Stack Layout and Calling Conventions. */
4482 /* -- Basic Stack Layout. */
4485 nds32_dynamic_chain_address (rtx frameaddr
)
4489 /* If -mv3push is specified, we push $fp, $gp, and $lp into stack.
4490 We can access dynamic chain address from stack by [$fp - 12]. */
4491 return plus_constant (Pmode
, frameaddr
, -12);
4495 /* For general case we push $fp and $lp into stack at prologue.
4496 We can access dynamic chain address from stack by [$fp - 8]. */
4497 return plus_constant (Pmode
, frameaddr
, -8);
4502 nds32_return_addr_rtx (int count
,
4510 /* In nds32 ABI design, we can expect that $lp is always available
4511 from stack by [$fp - 4] location. */
4513 addr
= plus_constant (Pmode
, frameaddr
, offset
);
4514 addr
= memory_address (Pmode
, addr
);
4516 return gen_rtx_MEM (Pmode
, addr
);
4519 /* If count == 0, it means we are at current frame,
4520 the return address is $r30 ($lp). */
4521 return get_hard_reg_initial_val (Pmode
, LP_REGNUM
);
4524 /* -- Eliminating Frame Pointer and Arg Pointer. */
4527 nds32_initial_elimination_offset (unsigned int from_reg
, unsigned int to_reg
)
4529 HOST_WIDE_INT offset
;
4531 /* Compute and setup stack frame size.
4532 The result will be in cfun->machine. */
4533 nds32_compute_stack_frame ();
4535 /* Remember to consider
4536 cfun->machine->callee_saved_area_gpr_padding_bytes and
4537 cfun->machine->eh_return_data_regs_size
4538 when calculating offset. */
4539 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
4541 offset
= (cfun
->machine
->fp_size
4542 + cfun
->machine
->gp_size
4543 + cfun
->machine
->lp_size
4544 + cfun
->machine
->callee_saved_gpr_regs_size
4545 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4546 + cfun
->machine
->callee_saved_fpr_regs_size
4547 + cfun
->machine
->eh_return_data_regs_size
4548 + cfun
->machine
->local_size
4549 + cfun
->machine
->out_args_size
);
4551 else if (from_reg
== ARG_POINTER_REGNUM
4552 && to_reg
== HARD_FRAME_POINTER_REGNUM
)
4556 else if (from_reg
== FRAME_POINTER_REGNUM
4557 && to_reg
== STACK_POINTER_REGNUM
)
4559 offset
= (cfun
->machine
->local_size
+ cfun
->machine
->out_args_size
);
4561 else if (from_reg
== FRAME_POINTER_REGNUM
4562 && to_reg
== HARD_FRAME_POINTER_REGNUM
)
4564 offset
= (-1) * (cfun
->machine
->fp_size
4565 + cfun
->machine
->gp_size
4566 + cfun
->machine
->lp_size
4567 + cfun
->machine
->callee_saved_gpr_regs_size
4568 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4569 + cfun
->machine
->callee_saved_fpr_regs_size
4570 + cfun
->machine
->eh_return_data_regs_size
);
4580 /* -- Passing Arguments in Registers. */
4583 nds32_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
4584 tree fntype ATTRIBUTE_UNUSED
,
4585 rtx libname ATTRIBUTE_UNUSED
,
4586 tree fndecl ATTRIBUTE_UNUSED
,
4587 int n_named_args ATTRIBUTE_UNUSED
)
4589 /* Initial available registers. The values are offset against
4590 NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM
4591 for passing arguments. */
4592 cum
->gpr_offset
= 0;
4593 cum
->fpr_offset
= 0;
4596 /* -- Function Entry and Exit. */
4598 /* Function for normal multiple push prologue. */
4600 nds32_expand_prologue (void)
4606 /* Compute and setup stack frame size.
4607 The result will be in cfun->machine. */
4608 nds32_compute_stack_frame ();
4610 /* Check frame_pointer_needed again to prevent fp is need after reload. */
4611 if (frame_pointer_needed
)
4612 cfun
->machine
->fp_as_gp_p
= false;
4614 /* If this is a variadic function, first we need to push argument
4615 registers that hold the unnamed argument value. */
4616 if (cfun
->machine
->va_args_size
!= 0)
4618 Rb
= cfun
->machine
->va_args_first_regno
;
4619 Re
= cfun
->machine
->va_args_last_regno
;
4620 /* No need to push $fp, $gp, or $lp. */
4621 nds32_emit_stack_push_multiple (Rb
, Re
, false, false, false, true);
4623 /* We may also need to adjust stack pointer for padding bytes
4624 because varargs may cause $sp not 8-byte aligned. */
4625 if (cfun
->machine
->va_args_area_padding_bytes
)
4627 /* Generate sp adjustment instruction. */
4628 sp_adjust
= cfun
->machine
->va_args_area_padding_bytes
;
4630 nds32_emit_adjust_frame (stack_pointer_rtx
,
4636 /* If the function is 'naked',
4637 we do not have to generate prologue code fragment. */
4638 if (cfun
->machine
->naked_p
&& !flag_pic
)
4641 /* Get callee_first_regno and callee_last_regno. */
4642 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
4643 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
4645 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
4646 to be saved, we don't have to create multiple push instruction.
4647 Otherwise, a multiple push instruction is needed. */
4648 if (!(Rb
== SP_REGNUM
&& Re
== SP_REGNUM
4649 && cfun
->machine
->fp_size
== 0
4650 && cfun
->machine
->gp_size
== 0
4651 && cfun
->machine
->lp_size
== 0))
4653 /* Create multiple push instruction rtx. */
4654 nds32_emit_stack_push_multiple (
4656 cfun
->machine
->fp_size
, cfun
->machine
->gp_size
, cfun
->machine
->lp_size
,
4660 /* Save eh data registers. */
4661 if (cfun
->machine
->use_eh_return_p
)
4663 Rb
= cfun
->machine
->eh_return_data_first_regno
;
4664 Re
= cfun
->machine
->eh_return_data_last_regno
;
4666 /* No need to push $fp, $gp, or $lp.
4667 Also, this is not variadic arguments push. */
4668 nds32_emit_stack_push_multiple (Rb
, Re
, false, false, false, false);
4671 /* Check frame_pointer_needed to see
4672 if we shall emit fp adjustment instruction. */
4673 if (frame_pointer_needed
)
4675 /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size)
4676 + (4 * callee-saved-registers)
4677 + (4 * exception-handling-data-registers)
4678 Note: No need to adjust
4679 cfun->machine->callee_saved_area_gpr_padding_bytes,
4680 because, at this point, stack pointer is just
4681 at the position after push instruction. */
4682 fp_adjust
= cfun
->machine
->fp_size
4683 + cfun
->machine
->gp_size
4684 + cfun
->machine
->lp_size
4685 + cfun
->machine
->callee_saved_gpr_regs_size
4686 + cfun
->machine
->eh_return_data_regs_size
;
4688 nds32_emit_adjust_frame (hard_frame_pointer_rtx
,
4693 /* Save fpu registers. */
4694 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
4696 /* When $sp moved to bottom of stack, we need to check whether
4697 the range of offset in the FPU instruction. */
4698 int fpr_offset
= cfun
->machine
->local_size
4699 + cfun
->machine
->out_args_size
4700 + cfun
->machine
->callee_saved_fpr_regs_size
;
4702 /* Check FPU instruction offset imm14s. */
4703 if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset
)))
4705 int fpr_space
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
4706 + cfun
->machine
->callee_saved_fpr_regs_size
;
4708 /* Save fpu registers, need to allocate stack space
4709 for fpu callee registers. And now $sp position
4710 on callee saved fpr registers. */
4711 nds32_emit_adjust_frame (stack_pointer_rtx
,
4715 /* Emit fpu store instruction, using [$sp + offset] store
4717 nds32_emit_push_fpr_callee_saved (0);
4719 /* Adjust $sp = $sp - local_size - out_args_size. */
4720 sp_adjust
= cfun
->machine
->local_size
4721 + cfun
->machine
->out_args_size
;
4723 /* Allocate stack space for local size and out args size. */
4724 nds32_emit_adjust_frame (stack_pointer_rtx
,
4730 /* Offset range in Is14, so $sp moved to bottom of stack. */
4732 /* Adjust $sp = $sp - local_size - out_args_size
4733 - callee_saved_area_gpr_padding_bytes
4734 - callee_saved_fpr_regs_size. */
4735 sp_adjust
= cfun
->machine
->local_size
4736 + cfun
->machine
->out_args_size
4737 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4738 + cfun
->machine
->callee_saved_fpr_regs_size
;
4740 nds32_emit_adjust_frame (stack_pointer_rtx
,
4744 /* Emit fpu store instruction, using [$sp + offset] store
4746 int fpr_position
= cfun
->machine
->out_args_size
4747 + cfun
->machine
->local_size
;
4748 nds32_emit_push_fpr_callee_saved (fpr_position
);
4753 /* Adjust $sp = $sp - local_size - out_args_size
4754 - callee_saved_area_gpr_padding_bytes. */
4755 sp_adjust
= cfun
->machine
->local_size
4756 + cfun
->machine
->out_args_size
4757 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4759 /* sp_adjust value may be out of range of the addi instruction,
4760 create alternative add behavior with TA_REGNUM if necessary,
4761 using NEGATIVE value to tell that we are decreasing address. */
4762 nds32_emit_adjust_frame (stack_pointer_rtx
,
4767 /* Emit gp setup instructions for -fpic. */
4768 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
4769 nds32_emit_load_gp ();
4771 /* If user applies -mno-sched-prolog-epilog option,
4772 we need to prevent instructions of function body from being
4773 scheduled with stack adjustment in prologue. */
4774 if (!flag_sched_prolog_epilog
)
4775 emit_insn (gen_blockage ());
4778 /* Function for normal multiple pop epilogue. */
4780 nds32_expand_epilogue (bool sibcall_p
)
4785 /* Compute and setup stack frame size.
4786 The result will be in cfun->machine. */
4787 nds32_compute_stack_frame ();
4789 /* If user applies -mno-sched-prolog-epilog option,
4790 we need to prevent instructions of function body from being
4791 scheduled with stack adjustment in epilogue. */
4792 if (!flag_sched_prolog_epilog
)
4793 emit_insn (gen_blockage ());
4795 /* If the function is 'naked', we do not have to generate
4796 epilogue code fragment BUT 'ret' instruction.
4797 However, if this function is also a variadic function,
4798 we need to create adjust stack pointer before 'ret' instruction. */
4799 if (cfun
->machine
->naked_p
)
4801 /* If this is a variadic function, we do not have to restore argument
4802 registers but need to adjust stack pointer back to previous stack
4803 frame location before return. */
4804 if (cfun
->machine
->va_args_size
!= 0)
4806 /* Generate sp adjustment instruction.
4807 We need to consider padding bytes here. */
4808 sp_adjust
= cfun
->machine
->va_args_size
4809 + cfun
->machine
->va_args_area_padding_bytes
;
4811 nds32_emit_adjust_frame (stack_pointer_rtx
,
4816 /* Generate return instruction by using 'return_internal' pattern.
4817 Make sure this instruction is after gen_blockage(). */
4820 /* We need to further check attributes to determine whether
4821 there should be return instruction at epilogue.
4822 If the attribute naked exists but -mno-ret-in-naked-func
4823 is issued, there is NO need to generate return instruction. */
4824 if (cfun
->machine
->attr_naked_p
&& !flag_ret_in_naked_func
)
4827 emit_jump_insn (gen_return_internal ());
4832 if (frame_pointer_needed
)
4834 /* Restore fpu registers. */
4835 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
4837 int gpr_padding
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4839 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4840 - (4 * callee-saved-registers)
4841 - (4 * exception-handling-data-registers)
4842 - (4 * callee-saved-gpr-registers padding byte)
4843 - (4 * callee-saved-fpr-registers)
4844 Note: we want to adjust stack pointer
4845 to the position for callee-saved fpr register,
4846 And restore fpu register use .bi instruction to adjust $sp
4847 from callee-saved fpr register to pop instruction. */
4848 sp_adjust
= cfun
->machine
->fp_size
4849 + cfun
->machine
->gp_size
4850 + cfun
->machine
->lp_size
4851 + cfun
->machine
->callee_saved_gpr_regs_size
4852 + cfun
->machine
->eh_return_data_regs_size
4853 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4854 + cfun
->machine
->callee_saved_fpr_regs_size
;
4856 nds32_emit_adjust_frame (stack_pointer_rtx
,
4857 hard_frame_pointer_rtx
,
4860 /* Emit fpu load instruction, using .bi instruction
4861 load fpu registers. */
4862 nds32_emit_pop_fpr_callee_saved (gpr_padding
);
4866 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4867 - (4 * callee-saved-registers)
4868 - (4 * exception-handling-data-registers)
4869 Note: No need to adjust
4870 cfun->machine->callee_saved_area_gpr_padding_bytes,
4871 because we want to adjust stack pointer
4872 to the position for pop instruction. */
4873 sp_adjust
= cfun
->machine
->fp_size
4874 + cfun
->machine
->gp_size
4875 + cfun
->machine
->lp_size
4876 + cfun
->machine
->callee_saved_gpr_regs_size
4877 + cfun
->machine
->eh_return_data_regs_size
;
4879 nds32_emit_adjust_frame (stack_pointer_rtx
,
4880 hard_frame_pointer_rtx
,
4886 /* Restore fpu registers. */
4887 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
4889 int gpr_padding
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4891 /* Adjust $sp = $sp + local_size + out_args_size. */
4892 sp_adjust
= cfun
->machine
->local_size
4893 + cfun
->machine
->out_args_size
;
4895 nds32_emit_adjust_frame (stack_pointer_rtx
,
4899 /* Emit fpu load instruction, using .bi instruction
4900 load fpu registers, and adjust $sp from callee-saved fpr register
4901 to callee-saved gpr register. */
4902 nds32_emit_pop_fpr_callee_saved (gpr_padding
);
4906 /* If frame pointer is NOT needed,
4907 we cannot calculate the sp adjustment from frame pointer.
4908 Instead, we calculate the adjustment by local_size,
4909 out_args_size, and callee_saved_area_gpr_padding_bytes.
4910 Notice that such sp adjustment value may be out of range,
4911 so we have to deal with it as well. */
4913 /* Adjust $sp = $sp + local_size + out_args_size
4914 + callee_saved_area_gpr_padding_bytes. */
4915 sp_adjust
= cfun
->machine
->local_size
4916 + cfun
->machine
->out_args_size
4917 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4919 nds32_emit_adjust_frame (stack_pointer_rtx
,
4925 /* Restore eh data registers. */
4926 if (cfun
->machine
->use_eh_return_p
)
4928 Rb
= cfun
->machine
->eh_return_data_first_regno
;
4929 Re
= cfun
->machine
->eh_return_data_last_regno
;
4931 /* No need to pop $fp, $gp, or $lp. */
4932 nds32_emit_stack_pop_multiple (Rb
, Re
, false, false, false);
4935 /* Get callee_first_regno and callee_last_regno. */
4936 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
4937 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
4939 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
4940 to be saved, we don't have to create multiple pop instruction.
4941 Otherwise, a multiple pop instruction is needed. */
4942 if (!(Rb
== SP_REGNUM
&& Re
== SP_REGNUM
4943 && cfun
->machine
->fp_size
== 0
4944 && cfun
->machine
->gp_size
== 0
4945 && cfun
->machine
->lp_size
== 0))
4947 /* Create multiple pop instruction rtx. */
4948 nds32_emit_stack_pop_multiple (
4950 cfun
->machine
->fp_size
, cfun
->machine
->gp_size
, cfun
->machine
->lp_size
);
4953 /* If this is a variadic function, we do not have to restore argument
4954 registers but need to adjust stack pointer back to previous stack
4955 frame location before return. */
4956 if (cfun
->machine
->va_args_size
!= 0)
4958 /* Generate sp adjustment instruction.
4959 We need to consider padding bytes here. */
4960 sp_adjust
= cfun
->machine
->va_args_size
4961 + cfun
->machine
->va_args_area_padding_bytes
;
4963 nds32_emit_adjust_frame (stack_pointer_rtx
,
4968 /* If this function uses __builtin_eh_return, make stack adjustment
4969 for exception handler. */
4970 if (cfun
->machine
->use_eh_return_p
)
4972 /* We need to unwind the stack by the offset computed by
4973 EH_RETURN_STACKADJ_RTX. However, at this point the CFA is
4974 based on SP. Ideally we would update the SP and define the
4975 CFA along the lines of:
4977 SP = SP + EH_RETURN_STACKADJ_RTX
4978 (regnote CFA = SP - EH_RETURN_STACKADJ_RTX)
4980 However the dwarf emitter only understands a constant
4983 The solution chosen here is to use the otherwise $ta ($r15)
4984 as a temporary register to hold the current SP value. The
4985 CFA is described using $ta then SP is modified. */
4990 ta_reg
= gen_rtx_REG (SImode
, TA_REGNUM
);
4992 insn
= emit_move_insn (ta_reg
, stack_pointer_rtx
);
4993 add_reg_note (insn
, REG_CFA_DEF_CFA
, ta_reg
);
4994 RTX_FRAME_RELATED_P (insn
) = 1;
4996 emit_insn (gen_addsi3 (stack_pointer_rtx
,
4998 EH_RETURN_STACKADJ_RTX
));
5000 /* Ensure the assignment to $ta does not get optimized away. */
5004 /* Generate return instruction. */
5006 emit_jump_insn (gen_return_internal ());
5009 /* Function for v3push prologue. */
5011 nds32_expand_prologue_v3push (void)
5018 /* Compute and setup stack frame size.
5019 The result will be in cfun->machine. */
5020 nds32_compute_stack_frame ();
5022 if (cfun
->machine
->callee_saved_gpr_regs_size
> 0)
5023 df_set_regs_ever_live (FP_REGNUM
, 1);
5025 /* Check frame_pointer_needed again to prevent fp is need after reload. */
5026 if (frame_pointer_needed
)
5027 cfun
->machine
->fp_as_gp_p
= false;
5029 /* If the function is 'naked',
5030 we do not have to generate prologue code fragment. */
5031 if (cfun
->machine
->naked_p
&& !flag_pic
)
5034 /* Get callee_first_regno and callee_last_regno. */
5035 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
5036 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
5038 /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
5039 where imm8u has to be 8-byte alignment. */
5040 sp_adjust
= cfun
->machine
->local_size
5041 + cfun
->machine
->out_args_size
5042 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5043 + cfun
->machine
->callee_saved_fpr_regs_size
;
5045 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
5046 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
))
5048 /* We can use 'push25 Re,imm8u'. */
5050 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
5051 the pattern 'stack_v3push' is implemented in nds32.md. */
5052 nds32_emit_stack_v3push (Rb
, Re
, sp_adjust
);
5054 /* Save fpu registers. */
5055 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5057 /* Calculate fpr position. */
5058 int fpr_position
= cfun
->machine
->local_size
5059 + cfun
->machine
->out_args_size
;
5060 /* Emit fpu store instruction, using [$sp + offset] store
5062 nds32_emit_push_fpr_callee_saved (fpr_position
);
5065 /* Check frame_pointer_needed to see
5066 if we shall emit fp adjustment instruction. */
5067 if (frame_pointer_needed
)
5069 /* adjust $fp = $sp + 4 ($fp size)
5072 + (4 * n) (callee-saved registers)
5073 + sp_adjust ('push25 Re,imm8u')
5074 Note: Since we use 'push25 Re,imm8u',
5075 the position of stack pointer is further
5076 changed after push instruction.
5077 Hence, we need to take sp_adjust value
5078 into consideration. */
5079 fp_adjust
= cfun
->machine
->fp_size
5080 + cfun
->machine
->gp_size
5081 + cfun
->machine
->lp_size
5082 + cfun
->machine
->callee_saved_gpr_regs_size
5085 nds32_emit_adjust_frame (hard_frame_pointer_rtx
,
5092 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5094 /* Calculate fpr space. */
5095 fpr_space
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
5096 + cfun
->machine
->callee_saved_fpr_regs_size
;
5098 /* We have to use 'push25 Re, fpr_space', to pre-allocate
5099 callee saved fpr registers space. */
5100 nds32_emit_stack_v3push (Rb
, Re
, fpr_space
);
5101 nds32_emit_push_fpr_callee_saved (0);
5105 /* We have to use 'push25 Re,0' and
5106 expand one more instruction to adjust $sp later. */
5108 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
5109 the pattern 'stack_v3push' is implemented in nds32.md. */
5110 nds32_emit_stack_v3push (Rb
, Re
, 0);
5113 /* Check frame_pointer_needed to see
5114 if we shall emit fp adjustment instruction. */
5115 if (frame_pointer_needed
)
5117 /* adjust $fp = $sp + 4 ($fp size)
5120 + (4 * n) (callee-saved registers)
5121 Note: Since we use 'push25 Re,0',
5122 the stack pointer is just at the position
5123 after push instruction.
5124 No need to take sp_adjust into consideration. */
5125 fp_adjust
= cfun
->machine
->fp_size
5126 + cfun
->machine
->gp_size
5127 + cfun
->machine
->lp_size
5128 + cfun
->machine
->callee_saved_gpr_regs_size
;
5130 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5132 /* We use 'push25 Re, fpr_space', the $sp is
5133 on callee saved fpr position, so need to consider
5135 fp_adjust
= fp_adjust
+ fpr_space
;
5138 nds32_emit_adjust_frame (hard_frame_pointer_rtx
,
5143 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5145 /* We use 'push25 Re, fpr_space',
5146 the $sp is on callee saved fpr position,
5147 no need to consider fpr space. */
5148 sp_adjust
= sp_adjust
- fpr_space
;
5151 /* Because we use 'push25 Re,0',
5152 we need to expand one more instruction to adjust $sp.
5153 using NEGATIVE value to tell that we are decreasing address. */
5154 nds32_emit_adjust_frame (stack_pointer_rtx
,
5159 /* Emit gp setup instructions for -fpic. */
5160 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
5161 nds32_emit_load_gp ();
5163 /* Prevent the instruction scheduler from
5164 moving instructions across the boundary. */
5165 emit_insn (gen_blockage ());
5168 /* Function for v3pop epilogue. */
5170 nds32_expand_epilogue_v3pop (bool sibcall_p
)
5175 /* Compute and setup stack frame size.
5176 The result will be in cfun->machine. */
5177 nds32_compute_stack_frame ();
5179 /* Prevent the instruction scheduler from
5180 moving instructions across the boundary. */
5181 emit_insn (gen_blockage ());
5183 /* If the function is 'naked', we do not have to generate
5184 epilogue code fragment BUT 'ret' instruction. */
5185 if (cfun
->machine
->naked_p
)
5187 /* Generate return instruction by using 'return_internal' pattern.
5188 Make sure this instruction is after gen_blockage().
5189 First we need to check this is a function without sibling call. */
5192 /* We need to further check attributes to determine whether
5193 there should be return instruction at epilogue.
5194 If the attribute naked exists but -mno-ret-in-naked-func
5195 is issued, there is NO need to generate return instruction. */
5196 if (cfun
->machine
->attr_naked_p
&& !flag_ret_in_naked_func
)
5199 emit_jump_insn (gen_return_internal ());
5204 /* Get callee_first_regno and callee_last_regno. */
5205 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
5206 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
5208 /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
5209 where imm8u has to be 8-byte alignment. */
5210 sp_adjust
= cfun
->machine
->local_size
5211 + cfun
->machine
->out_args_size
5212 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5213 + cfun
->machine
->callee_saved_fpr_regs_size
;
5215 /* We have to consider alloca issue as well.
5216 If the function does call alloca(), the stack pointer is not fixed.
5217 In that case, we cannot use 'pop25 Re,imm8u' directly.
5218 We have to caculate stack pointer from frame pointer
5219 and then use 'pop25 Re,0'.
5220 Of course, the frame_pointer_needed should be nonzero
5221 if the function calls alloca(). */
5222 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
5223 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
)
5224 && !cfun
->calls_alloca
)
5226 /* Restore fpu registers. */
5227 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5229 int fpr_position
= cfun
->machine
->local_size
5230 + cfun
->machine
->out_args_size
;
5231 /* Emit fpu load instruction, using [$sp + offset] restore
5233 nds32_emit_v3pop_fpr_callee_saved (fpr_position
);
5236 /* We can use 'pop25 Re,imm8u'. */
5238 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
5239 the pattern 'stack_v3pop' is implementad in nds32.md. */
5240 nds32_emit_stack_v3pop (Rb
, Re
, sp_adjust
);
5244 /* We have to use 'pop25 Re,0', and prior to it,
5245 we must expand one more instruction to adjust $sp. */
5247 if (frame_pointer_needed
)
5249 /* adjust $sp = $fp - 4 ($fp size)
5252 - (4 * n) (callee-saved registers)
5253 Note: No need to adjust
5254 cfun->machine->callee_saved_area_gpr_padding_bytes,
5255 because we want to adjust stack pointer
5256 to the position for pop instruction. */
5257 sp_adjust
= cfun
->machine
->fp_size
5258 + cfun
->machine
->gp_size
5259 + cfun
->machine
->lp_size
5260 + cfun
->machine
->callee_saved_gpr_regs_size
;
5262 /* Restore fpu registers. */
5263 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5265 /* Set $sp to callee saved fpr position, we need to restore
5267 sp_adjust
= sp_adjust
5268 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5269 + cfun
->machine
->callee_saved_fpr_regs_size
;
5271 nds32_emit_adjust_frame (stack_pointer_rtx
,
5272 hard_frame_pointer_rtx
,
5275 /* Emit fpu load instruction, using [$sp + offset] restore
5277 nds32_emit_v3pop_fpr_callee_saved (0);
5281 nds32_emit_adjust_frame (stack_pointer_rtx
,
5282 hard_frame_pointer_rtx
,
5288 /* If frame pointer is NOT needed,
5289 we cannot calculate the sp adjustment from frame pointer.
5290 Instead, we calculate the adjustment by local_size,
5291 out_args_size, and callee_saved_area_padding_bytes.
5292 Notice that such sp adjustment value may be out of range,
5293 so we have to deal with it as well. */
5295 /* Adjust $sp = $sp + local_size + out_args_size
5296 + callee_saved_area_gpr_padding_bytes
5297 + callee_saved_fpr_regs_size. */
5298 sp_adjust
= cfun
->machine
->local_size
5299 + cfun
->machine
->out_args_size
5300 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5301 + cfun
->machine
->callee_saved_fpr_regs_size
;
5303 /* Restore fpu registers. */
5304 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5306 /* Set $sp to callee saved fpr position, we need to restore
5308 sp_adjust
= sp_adjust
5309 - cfun
->machine
->callee_saved_area_gpr_padding_bytes
5310 - cfun
->machine
->callee_saved_fpr_regs_size
;
5312 nds32_emit_adjust_frame (stack_pointer_rtx
,
5316 /* Emit fpu load instruction, using [$sp + offset] restore
5318 nds32_emit_v3pop_fpr_callee_saved (0);
5322 /* sp_adjust value may be out of range of the addi instruction,
5323 create alternative add behavior with TA_REGNUM if necessary,
5324 using POSITIVE value to tell that we are increasing
5326 nds32_emit_adjust_frame (stack_pointer_rtx
,
5332 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5334 /* We have fpr need to restore, so $sp is set on callee saved fpr
5335 position. And we use 'pop25 Re, fpr_space' to adjust $sp. */
5336 int fpr_space
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
5337 + cfun
->machine
->callee_saved_fpr_regs_size
;
5338 nds32_emit_stack_v3pop (Rb
, Re
, fpr_space
);
5342 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
5343 the pattern 'stack_v3pop' is implementad in nds32.md. */
5344 nds32_emit_stack_v3pop (Rb
, Re
, 0);
5347 /* Generate return instruction. */
5348 emit_jump_insn (gen_pop25return ());
5351 /* Return nonzero if this function is known to have a null epilogue.
5352 This allows the optimizer to omit jumps to jumps if no stack
5355 nds32_can_use_return_insn (void)
5359 /* Prior to reloading, we can't tell how many registers must be saved.
5360 Thus we cannot determine whether this function has null epilogue. */
5361 if (!reload_completed
)
5364 /* If attribute 'naked' appears but -mno-ret-in-naked-func is used,
5365 we cannot use return instruction. */
5366 if (cfun
->machine
->attr_naked_p
&& !flag_ret_in_naked_func
)
5369 sp_adjust
= cfun
->machine
->local_size
5370 + cfun
->machine
->out_args_size
5371 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5372 + cfun
->machine
->callee_saved_fpr_regs_size
;
5373 if (!cfun
->machine
->fp_as_gp_p
5374 && satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
5375 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
)
5376 && !cfun
->calls_alloca
5377 && NDS32_V3PUSH_AVAILABLE_P
5378 && !(TARGET_HARD_FLOAT
5379 && (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)))
5382 /* If no stack was created, two conditions must be satisfied:
5383 1. This is a naked function.
5384 So there is no callee-saved, local size, or outgoing size.
5385 2. This is NOT a variadic function.
5386 So there is no pushing arguement registers into the stack. */
5387 return (cfun
->machine
->naked_p
&& (cfun
->machine
->va_args_size
== 0));
5391 nds32_case_vector_shorten_mode (int min_offset
, int max_offset
,
5392 rtx body ATTRIBUTE_UNUSED
)
5394 if (min_offset
< 0 || max_offset
>= 0x2000)
5398 /* The jump table maybe need to 2 byte alignment,
5399 so reserved 1 byte for check max_offset. */
5400 if (max_offset
>= 0xff)
5407 /* ------------------------------------------------------------------------ */
5409 /* Return alignment for the label. */
5411 nds32_target_alignment (rtx_insn
*label
)
5415 if (!NDS32_ALIGN_P ())
5418 insn
= next_active_insn (label
);
5420 /* Always align to 4 byte when first instruction after label is jump
5421 instruction since length for that might changed, so let's always align
5422 it for make sure we don't lose any perfomance here. */
5424 || (get_attr_length (insn
) == 2
5425 && !JUMP_P (insn
) && !CALL_P (insn
)))
5431 /* Return alignment for data. */
5433 nds32_data_alignment (tree data
,
5434 unsigned int basic_align
)
5436 if ((basic_align
< BITS_PER_WORD
)
5437 && (TREE_CODE (data
) == ARRAY_TYPE
5438 || TREE_CODE (data
) == UNION_TYPE
5439 || TREE_CODE (data
) == RECORD_TYPE
))
5440 return BITS_PER_WORD
;
5445 /* Return alignment for constant value. */
5446 static HOST_WIDE_INT
5447 nds32_constant_alignment (const_tree constant
,
5448 HOST_WIDE_INT basic_align
)
5450 /* Make string literal and constant for constructor to word align. */
5451 if (((TREE_CODE (constant
) == STRING_CST
5452 || TREE_CODE (constant
) == CONSTRUCTOR
5453 || TREE_CODE (constant
) == UNION_TYPE
5454 || TREE_CODE (constant
) == RECORD_TYPE
5455 || TREE_CODE (constant
) == ARRAY_TYPE
)
5456 && basic_align
< BITS_PER_WORD
))
5457 return BITS_PER_WORD
;
5462 /* Return alignment for local variable. */
5464 nds32_local_alignment (tree local ATTRIBUTE_UNUSED
,
5465 unsigned int basic_align
)
5467 bool at_least_align_to_word
= false;
5468 /* Make local array, struct and union at least align to word for make
5469 sure it can unroll memcpy when initialize by constant. */
5470 switch (TREE_CODE (local
))
5475 at_least_align_to_word
= true;
5478 at_least_align_to_word
= false;
5481 if (at_least_align_to_word
5482 && (basic_align
< BITS_PER_WORD
))
5483 return BITS_PER_WORD
;
5489 nds32_split_double_word_load_store_p(rtx
*operands
, bool load_p
)
5491 rtx mem
= load_p
? operands
[1] : operands
[0];
5492 /* Do split at split2 if -O0 or schedule 2 not enable. */
5493 if (optimize
== 0 || !flag_schedule_insns_after_reload
)
5494 return !satisfies_constraint_Da (mem
) || MEM_VOLATILE_P (mem
);
5496 /* Split double word load store after copy propgation. */
5497 if (current_pass
== NULL
)
5500 const char *pass_name
= current_pass
->name
;
5501 if (pass_name
&& ((strcmp (pass_name
, "split3") == 0)
5502 || (strcmp (pass_name
, "split5") == 0)))
5503 return !satisfies_constraint_Da (mem
) || MEM_VOLATILE_P (mem
);
5509 nds32_use_blocks_for_constant_p (machine_mode mode
,
5510 const_rtx x ATTRIBUTE_UNUSED
)
5512 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
5513 && (mode
== DFmode
|| mode
== SFmode
))
5519 /* ------------------------------------------------------------------------ */
5521 /* PART 5: Initialize target hook structure and definitions. */
5523 /* Controlling the Compilation Driver. */
5526 /* Run-time Target Specification. */
5529 /* Defining Data Structures for Per-function Information. */
5532 /* Storage Layout. */
5534 #undef TARGET_PROMOTE_FUNCTION_MODE
5535 #define TARGET_PROMOTE_FUNCTION_MODE \
5536 default_promote_function_mode_always_promote
5538 #undef TARGET_EXPAND_TO_RTL_HOOK
5539 #define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook
5541 #undef TARGET_CONSTANT_ALIGNMENT
5542 #define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment
5545 /* Layout of Source Language Data Types. */
5548 /* Register Usage. */
5550 /* -- Basic Characteristics of Registers. */
5552 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5553 #define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage
5555 /* -- Order of Allocation of Registers. */
5557 /* -- How Values Fit in Registers. */
5559 #undef TARGET_HARD_REGNO_NREGS
5560 #define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs
5562 #undef TARGET_HARD_REGNO_MODE_OK
5563 #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok
5565 #undef TARGET_MODES_TIEABLE_P
5566 #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p
5568 /* -- Handling Leaf Functions. */
5570 /* -- Registers That Form a Stack. */
5573 /* Register Classes. */
5575 #undef TARGET_CLASS_MAX_NREGS
5576 #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs
5578 #undef TARGET_REGISTER_PRIORITY
5579 #define TARGET_REGISTER_PRIORITY nds32_register_priority
5581 #undef TARGET_CAN_CHANGE_MODE_CLASS
5582 #define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class
5585 /* Obsolete Macros for Defining Constraints. */
5588 /* Stack Layout and Calling Conventions. */
5590 /* -- Basic Stack Layout. */
5592 /* -- Exception Handling Support. */
5594 /* -- Specifying How Stack Checking is Done. */
5596 /* -- Registers That Address the Stack Frame. */
5598 /* -- Eliminating Frame Pointer and Arg Pointer. */
5600 #undef TARGET_CAN_ELIMINATE
5601 #define TARGET_CAN_ELIMINATE nds32_can_eliminate
5603 /* -- Passing Function Arguments on the Stack. */
5605 /* -- Passing Arguments in Registers. */
5607 #undef TARGET_FUNCTION_ARG
5608 #define TARGET_FUNCTION_ARG nds32_function_arg
5610 #undef TARGET_MUST_PASS_IN_STACK
5611 #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack
5613 #undef TARGET_ARG_PARTIAL_BYTES
5614 #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes
5616 #undef TARGET_FUNCTION_ARG_ADVANCE
5617 #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance
5619 #undef TARGET_FUNCTION_ARG_BOUNDARY
5620 #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary
5622 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5623 #define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p
5625 /* -- How Scalar Function Values Are Returned. */
5627 #undef TARGET_FUNCTION_VALUE
5628 #define TARGET_FUNCTION_VALUE nds32_function_value
5630 #undef TARGET_LIBCALL_VALUE
5631 #define TARGET_LIBCALL_VALUE nds32_libcall_value
5633 #undef TARGET_FUNCTION_VALUE_REGNO_P
5634 #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p
5636 /* -- How Large Values Are Returned. */
5638 #undef TARGET_RETURN_IN_MEMORY
5639 #define TARGET_RETURN_IN_MEMORY nds32_return_in_memory
5641 /* -- Caller-Saves Register Allocation. */
5643 /* -- Function Entry and Exit. */
5645 #undef TARGET_ASM_FUNCTION_PROLOGUE
5646 #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue
5648 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
5649 #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue
5651 #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
5652 #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue
5654 #undef TARGET_ASM_FUNCTION_EPILOGUE
5655 #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue
5657 #undef TARGET_ASM_OUTPUT_MI_THUNK
5658 #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk
5660 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5661 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
5663 /* -- Generating Code for Profiling. */
5665 /* -- Permitting tail calls. */
5667 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5668 #define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall
5670 #undef TARGET_WARN_FUNC_RETURN
5671 #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return
5673 /* Stack smashing protection. */
5676 /* Implementing the Varargs Macros. */
5678 #undef TARGET_SETUP_INCOMING_VARARGS
5679 #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs
5681 #undef TARGET_STRICT_ARGUMENT_NAMING
5682 #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming
5685 /* Trampolines for Nested Functions. */
5687 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
5688 #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template
5690 #undef TARGET_TRAMPOLINE_INIT
5691 #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init
5694 /* Implicit Calls to Library Routines. */
5697 /* Addressing Modes. */
5699 #undef TARGET_LEGITIMATE_ADDRESS_P
5700 #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p
5702 #undef TARGET_LEGITIMIZE_ADDRESS
5703 #define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address
5705 #undef TARGET_LEGITIMATE_CONSTANT_P
5706 #define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p
5708 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
5709 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode
5711 #undef TARGET_CANNOT_FORCE_CONST_MEM
5712 #define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem
5714 #undef TARGET_DELEGITIMIZE_ADDRESS
5715 #define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address
5718 /* Anchored Addresses. */
5721 /* Condition Code Status. */
5723 /* -- Representation of condition codes using (cc0). */
5725 /* -- Representation of condition codes using registers. */
5727 #undef TARGET_CANONICALIZE_COMPARISON
5728 #define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison
5730 /* -- Macros to control conditional execution. */
5733 /* Describing Relative Costs of Operations. */
5735 #undef TARGET_REGISTER_MOVE_COST
5736 #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost
5738 #undef TARGET_MEMORY_MOVE_COST
5739 #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost
5741 #undef TARGET_RTX_COSTS
5742 #define TARGET_RTX_COSTS nds32_rtx_costs
5744 #undef TARGET_ADDRESS_COST
5745 #define TARGET_ADDRESS_COST nds32_address_cost
5748 /* Adjusting the Instruction Scheduler. */
5751 /* Dividing the Output into Sections (Texts, Data, . . . ). */
5753 #undef TARGET_ENCODE_SECTION_INFO
5754 #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info
5757 /* Position Independent Code. */
5760 /* Defining the Output Assembler Language. */
5762 /* -- The Overall Framework of an Assembler File. */
5764 #undef TARGET_ASM_FILE_START
5765 #define TARGET_ASM_FILE_START nds32_asm_file_start
5766 #undef TARGET_ASM_FILE_END
5767 #define TARGET_ASM_FILE_END nds32_asm_file_end
5769 /* -- Output of Data. */
5771 #undef TARGET_ASM_ALIGNED_HI_OP
5772 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
5774 #undef TARGET_ASM_ALIGNED_SI_OP
5775 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
5777 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
5778 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra
5780 /* -- Output of Uninitialized Variables. */
5782 /* -- Output and Generation of Labels. */
5784 #undef TARGET_ASM_GLOBALIZE_LABEL
5785 #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label
5787 /* -- How Initialization Functions Are Handled. */
5789 /* -- Macros Controlling Initialization Routines. */
5791 /* -- Output of Assembler Instructions. */
5793 #undef TARGET_PRINT_OPERAND
5794 #define TARGET_PRINT_OPERAND nds32_print_operand
5795 #undef TARGET_PRINT_OPERAND_ADDRESS
5796 #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address
5798 /* -- Output of Dispatch Tables. */
5800 /* -- Assembler Commands for Exception Regions. */
5802 #undef TARGET_DWARF_REGISTER_SPAN
5803 #define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span
5805 /* -- Assembler Commands for Alignment. */
5808 /* Controlling Debugging Information Format. */
5810 /* -- Macros Affecting All Debugging Formats. */
5812 /* -- Specific Options for DBX Output. */
5814 /* -- Open-Ended Hooks for DBX Format. */
5816 /* -- File Names in DBX Format. */
5818 /* -- Macros for DWARF Output. */
5820 /* -- Macros for VMS Debug Format. */
5823 /* Cross Compilation and Floating Point. */
5826 /* Mode Switching Instructions. */
5829 /* Defining target-specific uses of __attribute__. */
5831 #undef TARGET_ATTRIBUTE_TABLE
5832 #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table
5834 #undef TARGET_MERGE_DECL_ATTRIBUTES
5835 #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes
5837 #undef TARGET_INSERT_ATTRIBUTES
5838 #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes
5840 #undef TARGET_OPTION_PRAGMA_PARSE
5841 #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse
5843 #undef TARGET_OPTION_OVERRIDE
5844 #define TARGET_OPTION_OVERRIDE nds32_option_override
5847 /* Emulating TLS. */
5849 #undef TARGET_HAVE_TLS
5850 #define TARGET_HAVE_TLS TARGET_LINUX_ABI
5853 /* Defining coprocessor specifics for MIPS targets. */
5856 /* Parameters for Precompiled Header Validity Checking. */
5859 /* C++ ABI parameters. */
5862 /* Adding support for named address spaces. */
5865 /* Miscellaneous Parameters. */
5867 #undef TARGET_MD_ASM_ADJUST
5868 #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust
5870 #undef TARGET_INIT_BUILTINS
5871 #define TARGET_INIT_BUILTINS nds32_init_builtins
5873 #undef TARGET_BUILTIN_DECL
5874 #define TARGET_BUILTIN_DECL nds32_builtin_decl
5876 #undef TARGET_EXPAND_BUILTIN
5877 #define TARGET_EXPAND_BUILTIN nds32_expand_builtin
5879 #undef TARGET_INIT_LIBFUNCS
5880 #define TARGET_INIT_LIBFUNCS nds32_init_libfuncs
5882 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5883 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p
5885 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
5886 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
5889 /* ------------------------------------------------------------------------ */
5891 /* Initialize the GCC target structure. */
5893 struct gcc_target targetm
= TARGET_INITIALIZER
;
5895 /* ------------------------------------------------------------------------ */