1 /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2014 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* ------------------------------------------------------------------------ */
25 #include "coretypes.h"
28 #include "stor-layout.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h" /* Required by recog.h. */
35 #include "conditions.h"
37 #include "insn-attr.h" /* For DFA state_t. */
38 #include "insn-codes.h" /* For CODE_FOR_xxx. */
39 #include "reload.h" /* For push_reload(). */
44 #include "diagnostic-core.h"
47 #include "tm-constrs.h"
48 #include "optabs.h" /* For GEN_FCN. */
50 #include "target-def.h"
51 #include "langhooks.h" /* For add_builtin_function(). */
55 /* ------------------------------------------------------------------------ */
57 /* This file is divided into five parts:
59 PART 1: Auxiliary static variable definitions and
60 target hook static variable definitions.
62 PART 2: Auxiliary static function definitions.
64 PART 3: Implement target hook stuff definitions.
66 PART 4: Implemet extern function definitions,
67 the prototype is in nds32-protos.h.
69 PART 5: Initialize target hook structure and definitions. */
71 /* ------------------------------------------------------------------------ */
73 /* PART 1: Auxiliary static variable definitions and
74 target hook static variable definitions. */
76 /* Define intrinsic register names.
77 Please refer to nds32_intrinsic.h file, the index is corresponding to
78 'enum nds32_intrinsic_registers' data type values.
79 NOTE that the base value starting from 1024. */
80 static const char * const nds32_intrinsic_register_names
[] =
82 "$PSW", "$IPSW", "$ITYPE", "$IPC"
85 /* Defining target-specific uses of __attribute__. */
86 static const struct attribute_spec nds32_attribute_table
[] =
88 /* Syntax: { name, min_len, max_len, decl_required, type_required,
89 function_type_required, handler, affects_type_identity } */
91 /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */
92 { "interrupt", 1, 64, false, false, false, NULL
, false },
93 /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */
94 { "exception", 1, 8, false, false, false, NULL
, false },
95 /* Argument is user's interrupt numbers. The vector number is always 0. */
96 { "reset", 1, 1, false, false, false, NULL
, false },
98 /* The attributes describing isr nested type. */
99 { "nested", 0, 0, false, false, false, NULL
, false },
100 { "not_nested", 0, 0, false, false, false, NULL
, false },
101 { "nested_ready", 0, 0, false, false, false, NULL
, false },
103 /* The attributes describing isr register save scheme. */
104 { "save_all", 0, 0, false, false, false, NULL
, false },
105 { "partial_save", 0, 0, false, false, false, NULL
, false },
107 /* The attributes used by reset attribute. */
108 { "nmi", 1, 1, false, false, false, NULL
, false },
109 { "warm", 1, 1, false, false, false, NULL
, false },
111 /* The attribute telling no prologue/epilogue. */
112 { "naked", 0, 0, false, false, false, NULL
, false },
114 /* The last attribute spec is set to be NULL. */
115 { NULL
, 0, 0, false, false, false, NULL
, false }
119 /* ------------------------------------------------------------------------ */
121 /* PART 2: Auxiliary static function definitions. */
123 /* Function to save and restore machine-specific function data. */
124 static struct machine_function
*
125 nds32_init_machine_status (void)
127 struct machine_function
*machine
;
128 machine
= ggc_cleared_alloc
<machine_function
> ();
130 /* Initially assume this function needs prologue/epilogue. */
131 machine
->naked_p
= 0;
133 /* Initially assume this function does NOT use fp_as_gp optimization. */
134 machine
->fp_as_gp_p
= 0;
139 /* Function to compute stack frame size and
140 store into cfun->machine structure. */
142 nds32_compute_stack_frame (void)
147 /* Because nds32_compute_stack_frame() will be called from different place,
148 everytime we enter this function, we have to assume this function
149 needs prologue/epilogue. */
150 cfun
->machine
->naked_p
= 0;
152 /* Get variadic arguments size to prepare pretend arguments and
153 we will push them into stack at prologue by ourself. */
154 cfun
->machine
->va_args_size
= crtl
->args
.pretend_args_size
;
155 if (cfun
->machine
->va_args_size
!= 0)
157 cfun
->machine
->va_args_first_regno
158 = NDS32_GPR_ARG_FIRST_REGNUM
159 + NDS32_MAX_GPR_REGS_FOR_ARGS
160 - (crtl
->args
.pretend_args_size
/ UNITS_PER_WORD
);
161 cfun
->machine
->va_args_last_regno
162 = NDS32_GPR_ARG_FIRST_REGNUM
+ NDS32_MAX_GPR_REGS_FOR_ARGS
- 1;
166 cfun
->machine
->va_args_first_regno
= SP_REGNUM
;
167 cfun
->machine
->va_args_last_regno
= SP_REGNUM
;
170 /* Important: We need to make sure that varargs area is 8-byte alignment. */
171 block_size
= cfun
->machine
->va_args_size
;
172 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
174 cfun
->machine
->va_args_area_padding_bytes
175 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
) - block_size
;
178 /* Get local variables, incoming variables, and temporary variables size.
179 Note that we need to make sure it is 8-byte alignment because
180 there may be no padding bytes if we are using LRA. */
181 cfun
->machine
->local_size
= NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ());
183 /* Get outgoing arguments size. */
184 cfun
->machine
->out_args_size
= crtl
->outgoing_args_size
;
186 /* If $fp value is required to be saved on stack, it needs 4 bytes space.
187 Check whether $fp is ever live. */
188 cfun
->machine
->fp_size
= (df_regs_ever_live_p (FP_REGNUM
)) ? 4 : 0;
190 /* If $gp value is required to be saved on stack, it needs 4 bytes space.
191 Check whether we are using PIC code genration. */
192 cfun
->machine
->gp_size
= (flag_pic
) ? 4 : 0;
194 /* If $lp value is required to be saved on stack, it needs 4 bytes space.
195 Check whether $lp is ever live. */
196 cfun
->machine
->lp_size
= (df_regs_ever_live_p (LP_REGNUM
)) ? 4 : 0;
198 /* Initially there is no padding bytes. */
199 cfun
->machine
->callee_saved_area_padding_bytes
= 0;
201 /* Calculate the bytes of saving callee-saved registers on stack. */
202 cfun
->machine
->callee_saved_regs_size
= 0;
203 cfun
->machine
->callee_saved_regs_first_regno
= SP_REGNUM
;
204 cfun
->machine
->callee_saved_regs_last_regno
= SP_REGNUM
;
205 /* Currently, there is no need to check $r28~$r31
206 because we will save them in another way. */
207 for (r
= 0; r
< 28; r
++)
209 if (NDS32_REQUIRED_CALLEE_SAVED_P (r
))
211 /* Mark the first required callee-saved register
212 (only need to set it once).
213 If first regno == SP_REGNUM, we can tell that
214 it is the first time to be here. */
215 if (cfun
->machine
->callee_saved_regs_first_regno
== SP_REGNUM
)
216 cfun
->machine
->callee_saved_regs_first_regno
= r
;
217 /* Mark the last required callee-saved register. */
218 cfun
->machine
->callee_saved_regs_last_regno
= r
;
222 /* Check if this function can omit prologue/epilogue code fragment.
223 If there is 'naked' attribute in this function,
224 we can set 'naked_p' flag to indicate that
225 we do not have to generate prologue/epilogue.
226 Or, if all the following conditions succeed,
227 we can set this function 'naked_p' as well:
228 condition 1: first_regno == last_regno == SP_REGNUM,
229 which means we do not have to save
230 any callee-saved registers.
231 condition 2: Both $lp and $fp are NOT live in this function,
232 which means we do not need to save them and there
234 condition 3: There is no local_size, which means
235 we do not need to adjust $sp. */
236 if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
))
237 || (cfun
->machine
->callee_saved_regs_first_regno
== SP_REGNUM
238 && cfun
->machine
->callee_saved_regs_last_regno
== SP_REGNUM
239 && !df_regs_ever_live_p (FP_REGNUM
)
240 && !df_regs_ever_live_p (LP_REGNUM
)
241 && cfun
->machine
->local_size
== 0))
243 /* Set this function 'naked_p' and other functions can check this flag.
244 Note that in nds32 port, the 'naked_p = 1' JUST means there is no
245 callee-saved, local size, and outgoing size.
246 The varargs space and ret instruction may still present in
247 the prologue/epilogue expanding. */
248 cfun
->machine
->naked_p
= 1;
250 /* No need to save $fp, $gp, and $lp.
251 We should set these value to be zero
252 so that nds32_initial_elimination_offset() can work properly. */
253 cfun
->machine
->fp_size
= 0;
254 cfun
->machine
->gp_size
= 0;
255 cfun
->machine
->lp_size
= 0;
257 /* If stack usage computation is required,
258 we need to provide the static stack size. */
259 if (flag_stack_usage_info
)
260 current_function_static_stack_size
= 0;
262 /* No need to do following adjustment, return immediately. */
266 /* Adjustment for v3push instructions:
267 If we are using v3push (push25/pop25) instructions,
268 we need to make sure Rb is $r6 and Re is
269 located on $r6, $r8, $r10, or $r14.
270 Some results above will be discarded and recomputed.
271 Note that it is only available under V3/V3M ISA and we
272 DO NOT setup following stuff for isr or variadic function. */
274 && !nds32_isr_function_p (current_function_decl
)
275 && (cfun
->machine
->va_args_size
== 0))
278 cfun->machine->fp_size
279 cfun->machine->gp_size
280 cfun->machine->lp_size
281 cfun->machine->callee_saved_regs_first_regno
282 cfun->machine->callee_saved_regs_last_regno */
284 /* For v3push instructions, $fp, $gp, and $lp are always saved. */
285 cfun
->machine
->fp_size
= 4;
286 cfun
->machine
->gp_size
= 4;
287 cfun
->machine
->lp_size
= 4;
289 /* Remember to set Rb = $r6. */
290 cfun
->machine
->callee_saved_regs_first_regno
= 6;
292 if (cfun
->machine
->callee_saved_regs_last_regno
<= 6)
295 cfun
->machine
->callee_saved_regs_last_regno
= 6;
297 else if (cfun
->machine
->callee_saved_regs_last_regno
<= 8)
300 cfun
->machine
->callee_saved_regs_last_regno
= 8;
302 else if (cfun
->machine
->callee_saved_regs_last_regno
<= 10)
305 cfun
->machine
->callee_saved_regs_last_regno
= 10;
307 else if (cfun
->machine
->callee_saved_regs_last_regno
<= 14)
310 cfun
->machine
->callee_saved_regs_last_regno
= 14;
312 else if (cfun
->machine
->callee_saved_regs_last_regno
== SP_REGNUM
)
314 /* If last_regno is SP_REGNUM, which means
315 it is never changed, so set it to Re = $r6. */
316 cfun
->machine
->callee_saved_regs_last_regno
= 6;
320 /* The program flow should not go here. */
325 /* We have correctly set callee_saved_regs_first_regno
326 and callee_saved_regs_last_regno.
327 Initially, the callee_saved_regs_size is supposed to be 0.
328 As long as callee_saved_regs_last_regno is not SP_REGNUM,
329 we can update callee_saved_regs_size with new size. */
330 if (cfun
->machine
->callee_saved_regs_last_regno
!= SP_REGNUM
)
332 /* Compute pushed size of callee-saved registers. */
333 cfun
->machine
->callee_saved_regs_size
334 = 4 * (cfun
->machine
->callee_saved_regs_last_regno
335 - cfun
->machine
->callee_saved_regs_first_regno
339 /* Important: We need to make sure that
340 (fp_size + gp_size + lp_size + callee_saved_regs_size)
342 If it is not, calculate the padding bytes. */
343 block_size
= cfun
->machine
->fp_size
344 + cfun
->machine
->gp_size
345 + cfun
->machine
->lp_size
346 + cfun
->machine
->callee_saved_regs_size
;
347 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
349 cfun
->machine
->callee_saved_area_padding_bytes
350 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
) - block_size
;
353 /* If stack usage computation is required,
354 we need to provide the static stack size. */
355 if (flag_stack_usage_info
)
357 current_function_static_stack_size
358 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
)
359 + cfun
->machine
->local_size
360 + cfun
->machine
->out_args_size
;
364 /* Function to create a parallel rtx pattern
365 which presents stack push multiple behavior.
366 The overall concept are:
367 "push registers to memory",
368 "adjust stack pointer". */
370 nds32_emit_stack_push_multiple (rtx Rb
, rtx Re
, rtx En4
)
377 int save_fp
, save_gp
, save_lp
;
385 /* We need to provide a customized rtx which contains
386 necessary information for data analysis,
387 so we create a parallel rtx like this:
388 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
390 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
393 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
395 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
397 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
399 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
401 (set (reg:SI SP_REGNUM)
402 (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
404 /* Determine whether we need to save $fp, $gp, or $lp. */
405 save_fp
= INTVAL (En4
) & 0x8;
406 save_gp
= INTVAL (En4
) & 0x4;
407 save_lp
= INTVAL (En4
) & 0x2;
409 /* Calculate the number of registers that will be pushed. */
417 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
418 if (REGNO (Rb
) == SP_REGNUM
&& REGNO (Re
) == SP_REGNUM
)
419 num_use_regs
= extra_count
;
421 num_use_regs
= REGNO (Re
) - REGNO (Rb
) + 1 + extra_count
;
423 /* In addition to used registers,
424 we need one more space for (set sp sp-x) rtx. */
425 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
426 rtvec_alloc (num_use_regs
+ 1));
429 /* Initialize offset and start to create push behavior. */
430 offset
= -(num_use_regs
* 4);
432 /* Create (set mem regX) from Rb, Rb+1 up to Re. */
433 for (regno
= REGNO (Rb
); regno
<= (int) REGNO (Re
); regno
++)
435 /* Rb and Re may be SP_REGNUM.
436 We need to break this loop immediately. */
437 if (regno
== SP_REGNUM
)
440 reg
= gen_rtx_REG (SImode
, regno
);
441 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
444 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
445 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
446 RTX_FRAME_RELATED_P (push_rtx
) = 1;
451 /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */
454 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
455 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
458 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
459 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
460 RTX_FRAME_RELATED_P (push_rtx
) = 1;
466 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
467 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
470 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
471 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
472 RTX_FRAME_RELATED_P (push_rtx
) = 1;
478 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
479 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
482 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
483 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
484 RTX_FRAME_RELATED_P (push_rtx
) = 1;
489 /* Create (set sp sp-x). */
491 /* We need to re-calculate the offset value again for adjustment. */
492 offset
= -(num_use_regs
* 4);
494 = gen_rtx_SET (VOIDmode
,
496 plus_constant (Pmode
, stack_pointer_rtx
, offset
));
497 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
498 RTX_FRAME_RELATED_P (adjust_sp_rtx
) = 1;
500 parallel_insn
= emit_insn (parallel_insn
);
502 /* The insn rtx 'parallel_insn' will change frame layout.
503 We need to use RTX_FRAME_RELATED_P so that GCC is able to
504 generate CFI (Call Frame Information) stuff. */
505 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
508 /* Function to create a parallel rtx pattern
509 which presents stack pop multiple behavior.
510 The overall concept are:
511 "pop registers from memory",
512 "adjust stack pointer". */
514 nds32_emit_stack_pop_multiple (rtx Rb
, rtx Re
, rtx En4
)
521 int save_fp
, save_gp
, save_lp
;
528 rtx dwarf
= NULL_RTX
;
530 /* We need to provide a customized rtx which contains
531 necessary information for data analysis,
532 so we create a parallel rtx like this:
533 (parallel [(set (reg:SI Rb)
534 (mem (reg:SI SP_REGNUM)))
536 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
539 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
540 (set (reg:SI FP_REGNUM)
541 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
542 (set (reg:SI GP_REGNUM)
543 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
544 (set (reg:SI LP_REGNUM)
545 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
546 (set (reg:SI SP_REGNUM)
547 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
549 /* Determine whether we need to restore $fp, $gp, or $lp. */
550 save_fp
= INTVAL (En4
) & 0x8;
551 save_gp
= INTVAL (En4
) & 0x4;
552 save_lp
= INTVAL (En4
) & 0x2;
554 /* Calculate the number of registers that will be poped. */
562 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
563 if (REGNO (Rb
) == SP_REGNUM
&& REGNO (Re
) == SP_REGNUM
)
564 num_use_regs
= extra_count
;
566 num_use_regs
= REGNO (Re
) - REGNO (Rb
) + 1 + extra_count
;
568 /* In addition to used registers,
569 we need one more space for (set sp sp+x) rtx. */
570 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
571 rtvec_alloc (num_use_regs
+ 1));
574 /* Initialize offset and start to create pop behavior. */
577 /* Create (set regX mem) from Rb, Rb+1 up to Re. */
578 for (regno
= REGNO (Rb
); regno
<= (int) REGNO (Re
); regno
++)
580 /* Rb and Re may be SP_REGNUM.
581 We need to break this loop immediately. */
582 if (regno
== SP_REGNUM
)
585 reg
= gen_rtx_REG (SImode
, regno
);
586 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
589 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
590 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
591 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
595 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
598 /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */
601 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
602 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
605 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
606 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
607 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
611 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
615 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
616 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
619 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
620 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
621 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
625 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
629 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
630 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
633 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
634 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
635 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
639 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
642 /* Create (set sp sp+x). */
644 /* The offset value is already in place. No need to re-calculate it. */
646 = gen_rtx_SET (VOIDmode
,
648 plus_constant (Pmode
, stack_pointer_rtx
, offset
));
649 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
651 /* Tell gcc we adjust SP in this insn. */
652 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, copy_rtx (adjust_sp_rtx
), dwarf
);
654 parallel_insn
= emit_insn (parallel_insn
);
656 /* The insn rtx 'parallel_insn' will change frame layout.
657 We need to use RTX_FRAME_RELATED_P so that GCC is able to
658 generate CFI (Call Frame Information) stuff. */
659 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
661 /* Add CFI info by manual. */
662 REG_NOTES (parallel_insn
) = dwarf
;
665 /* Function to create a parallel rtx pattern
666 which presents stack v3push behavior.
667 The overall concept are:
668 "push registers to memory",
669 "adjust stack pointer". */
671 nds32_emit_stack_v3push (rtx Rb
,
673 rtx En4 ATTRIBUTE_UNUSED
,
687 /* We need to provide a customized rtx which contains
688 necessary information for data analysis,
689 so we create a parallel rtx like this:
690 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
692 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
695 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
697 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
699 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
701 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
703 (set (reg:SI SP_REGNUM)
704 (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
706 /* Calculate the number of registers that will be pushed.
707 Since $fp, $gp, and $lp is always pushed with v3push instruction,
708 we need to count these three registers.
709 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
710 So there is no need to worry about Rb=Re=SP_REGNUM case. */
711 num_use_regs
= REGNO (Re
) - REGNO (Rb
) + 1 + 3;
713 /* In addition to used registers,
714 we need one more space for (set sp sp-x-imm8u) rtx. */
715 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
716 rtvec_alloc (num_use_regs
+ 1));
719 /* Initialize offset and start to create push behavior. */
720 offset
= -(num_use_regs
* 4);
722 /* Create (set mem regX) from Rb, Rb+1 up to Re.
723 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
724 So there is no need to worry about Rb=Re=SP_REGNUM case. */
725 for (regno
= REGNO (Rb
); regno
<= (int) REGNO (Re
); regno
++)
727 reg
= gen_rtx_REG (SImode
, regno
);
728 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
731 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
732 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
733 RTX_FRAME_RELATED_P (push_rtx
) = 1;
738 /* Create (set mem fp). */
739 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
740 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
743 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
744 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
745 RTX_FRAME_RELATED_P (push_rtx
) = 1;
748 /* Create (set mem gp). */
749 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
750 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
753 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
754 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
755 RTX_FRAME_RELATED_P (push_rtx
) = 1;
758 /* Create (set mem lp). */
759 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
760 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
763 push_rtx
= gen_rtx_SET (VOIDmode
, mem
, reg
);
764 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
765 RTX_FRAME_RELATED_P (push_rtx
) = 1;
769 /* Create (set sp sp-x-imm8u). */
771 /* We need to re-calculate the offset value again for adjustment. */
772 offset
= -(num_use_regs
* 4);
774 = gen_rtx_SET (VOIDmode
,
776 plus_constant (Pmode
,
778 offset
- INTVAL (imm8u
)));
779 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
780 RTX_FRAME_RELATED_P (adjust_sp_rtx
) = 1;
782 parallel_insn
= emit_insn (parallel_insn
);
784 /* The insn rtx 'parallel_insn' will change frame layout.
785 We need to use RTX_FRAME_RELATED_P so that GCC is able to
786 generate CFI (Call Frame Information) stuff. */
787 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
790 /* Function to create a parallel rtx pattern
791 which presents stack v3pop behavior.
792 The overall concept are:
793 "pop registers from memory",
794 "adjust stack pointer". */
796 nds32_emit_stack_v3pop (rtx Rb
,
798 rtx En4 ATTRIBUTE_UNUSED
,
811 rtx dwarf
= NULL_RTX
;
813 /* We need to provide a customized rtx which contains
814 necessary information for data analysis,
815 so we create a parallel rtx like this:
816 (parallel [(set (reg:SI Rb)
817 (mem (reg:SI SP_REGNUM)))
819 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
822 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
823 (set (reg:SI FP_REGNUM)
824 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
825 (set (reg:SI GP_REGNUM)
826 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
827 (set (reg:SI LP_REGNUM)
828 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
829 (set (reg:SI SP_REGNUM)
830 (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
832 /* Calculate the number of registers that will be poped.
833 Since $fp, $gp, and $lp is always poped with v3pop instruction,
834 we need to count these three registers.
835 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
836 So there is no need to worry about Rb=Re=SP_REGNUM case. */
837 num_use_regs
= REGNO (Re
) - REGNO (Rb
) + 1 + 3;
839 /* In addition to used registers,
840 we need one more space for (set sp sp+x+imm8u) rtx. */
841 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
842 rtvec_alloc (num_use_regs
+ 1));
845 /* Initialize offset and start to create pop behavior. */
848 /* Create (set regX mem) from Rb, Rb+1 up to Re.
849 Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
850 So there is no need to worry about Rb=Re=SP_REGNUM case. */
851 for (regno
= REGNO (Rb
); regno
<= (int) REGNO (Re
); regno
++)
853 reg
= gen_rtx_REG (SImode
, regno
);
854 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
857 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
858 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
859 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
863 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
866 /* Create (set fp mem). */
867 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
868 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
871 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
872 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
873 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
876 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
878 /* Create (set gp mem). */
879 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
880 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
883 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
884 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
885 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
888 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
890 /* Create (set lp mem ). */
891 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
892 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
895 pop_rtx
= gen_rtx_SET (VOIDmode
, reg
, mem
);
896 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
897 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
900 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
902 /* Create (set sp sp+x+imm8u). */
904 /* The offset value is already in place. No need to re-calculate it. */
906 = gen_rtx_SET (VOIDmode
,
908 plus_constant (Pmode
,
910 offset
+ INTVAL (imm8u
)));
911 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
913 /* Tell gcc we adjust SP in this insn. */
914 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, copy_rtx (adjust_sp_rtx
), dwarf
);
916 parallel_insn
= emit_insn (parallel_insn
);
918 /* The insn rtx 'parallel_insn' will change frame layout.
919 We need to use RTX_FRAME_RELATED_P so that GCC is able to
920 generate CFI (Call Frame Information) stuff. */
921 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
923 /* Add CFI info by manual. */
924 REG_NOTES (parallel_insn
) = dwarf
;
927 /* Function that may creates more instructions
928 for large value on adjusting stack pointer.
930 In nds32 target, 'addi' can be used for stack pointer
931 adjustment in prologue/epilogue stage.
932 However, sometimes there are too many local variables so that
933 the adjustment value is not able to be fit in the 'addi' instruction.
934 One solution is to move value into a register
935 and then use 'add' instruction.
936 In practice, we use TA_REGNUM ($r15) to accomplish this purpose.
937 Also, we need to return zero for sp adjustment so that
938 proglogue/epilogue knows there is no need to create 'addi' instruction. */
940 nds32_force_addi_stack_int (int full_value
)
947 if (!satisfies_constraint_Is15 (GEN_INT (full_value
)))
949 /* The value is not able to fit in single addi instruction.
950 Create more instructions of moving value into a register
951 and then add stack pointer with it. */
953 /* $r15 is going to be temporary register to hold the value. */
954 tmp_reg
= gen_rtx_REG (SImode
, TA_REGNUM
);
956 /* Create one more instruction to move value
957 into the temporary register. */
958 emit_move_insn (tmp_reg
, GEN_INT (full_value
));
960 /* Create new 'add' rtx. */
961 sp_adjust_insn
= gen_addsi3 (stack_pointer_rtx
,
964 /* Emit rtx into insn list and receive its transformed insn rtx. */
965 sp_adjust_insn
= emit_insn (sp_adjust_insn
);
967 /* At prologue, we need to tell GCC that this is frame related insn,
968 so that we can consider this instruction to output debug information.
969 If full_value is NEGATIVE, it means this function
970 is invoked by expand_prologue. */
973 /* Because (tmp_reg <- full_value) may be split into two
974 rtl patterns, we can not set its RTX_FRAME_RELATED_P.
975 We need to construct another (sp <- sp + full_value)
976 and then insert it into sp_adjust_insn's reg note to
977 represent a frame related expression.
978 GCC knows how to refer it and output debug information. */
983 plus_rtx
= plus_constant (Pmode
, stack_pointer_rtx
, full_value
);
984 set_rtx
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, plus_rtx
);
985 add_reg_note (sp_adjust_insn
, REG_FRAME_RELATED_EXPR
, set_rtx
);
987 RTX_FRAME_RELATED_P (sp_adjust_insn
) = 1;
990 /* We have used alternative way to adjust stack pointer value.
991 Return zero so that prologue/epilogue
992 will not generate other instructions. */
997 /* The value is able to fit in addi instruction.
998 However, remember to make it to be positive value
999 because we want to return 'adjustment' result. */
1000 adjust_value
= (full_value
< 0) ? (-full_value
) : (full_value
);
1002 return adjust_value
;
1006 /* Return true if MODE/TYPE need double word alignment. */
1008 nds32_needs_double_word_align (enum machine_mode mode
, const_tree type
)
1012 /* Pick up the alignment according to the mode or type. */
1013 align
= NDS32_MODE_TYPE_ALIGN (mode
, type
);
1015 return (align
> PARM_BOUNDARY
);
1018 /* Return true if FUNC is a naked function. */
1020 nds32_naked_function_p (tree func
)
1024 if (TREE_CODE (func
) != FUNCTION_DECL
)
1027 t
= lookup_attribute ("naked", DECL_ATTRIBUTES (func
));
1029 return (t
!= NULL_TREE
);
1032 /* Function that check if 'X' is a valid address register.
1033 The variable 'STRICT' is very important to
1034 make decision for register number.
1037 => We are in reload pass or after reload pass.
1038 The register number should be strictly limited in general registers.
1041 => Before reload pass, we are free to use any register number. */
1043 nds32_address_register_rtx_p (rtx x
, bool strict
)
1047 if (GET_CODE (x
) != REG
)
1053 return REGNO_OK_FOR_BASE_P (regno
);
1058 /* Function that check if 'INDEX' is valid to be a index rtx for address.
1060 OUTER_MODE : Machine mode of outer address rtx.
1061 INDEX : Check if this rtx is valid to be a index for address.
1062 STRICT : If it is true, we are in reload pass or after reload pass. */
1064 nds32_legitimate_index_p (enum machine_mode outer_mode
,
1072 switch (GET_CODE (index
))
1075 regno
= REGNO (index
);
1076 /* If we are in reload pass or after reload pass,
1077 we need to limit it to general register. */
1079 return REGNO_OK_FOR_INDEX_P (regno
);
1084 /* The alignment of the integer value is determined by 'outer_mode'. */
1085 if (GET_MODE_SIZE (outer_mode
) == 1)
1087 /* Further check if the value is legal for the 'outer_mode'. */
1088 if (!satisfies_constraint_Is15 (index
))
1091 /* Pass all test, the value is valid, return true. */
1094 if (GET_MODE_SIZE (outer_mode
) == 2
1095 && NDS32_HALF_WORD_ALIGN_P (INTVAL (index
)))
1097 /* Further check if the value is legal for the 'outer_mode'. */
1098 if (!satisfies_constraint_Is16 (index
))
1101 /* Pass all test, the value is valid, return true. */
1104 if (GET_MODE_SIZE (outer_mode
) == 4
1105 && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index
)))
1107 /* Further check if the value is legal for the 'outer_mode'. */
1108 if (!satisfies_constraint_Is17 (index
))
1111 /* Pass all test, the value is valid, return true. */
1114 if (GET_MODE_SIZE (outer_mode
) == 8
1115 && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index
)))
1117 /* Further check if the value is legal for the 'outer_mode'. */
1118 if (!satisfies_constraint_Is17 (gen_int_mode (INTVAL (index
) + 4,
1122 /* Pass all test, the value is valid, return true. */
1129 op0
= XEXP (index
, 0);
1130 op1
= XEXP (index
, 1);
1132 if (REG_P (op0
) && CONST_INT_P (op1
))
1135 multiplier
= INTVAL (op1
);
1137 /* We only allow (mult reg const_int_1)
1138 or (mult reg const_int_2) or (mult reg const_int_4). */
1139 if (multiplier
!= 1 && multiplier
!= 2 && multiplier
!= 4)
1142 regno
= REGNO (op0
);
1143 /* Limit it in general registers if we are
1144 in reload pass or after reload pass. */
1146 return REGNO_OK_FOR_INDEX_P (regno
);
1154 op0
= XEXP (index
, 0);
1155 op1
= XEXP (index
, 1);
1157 if (REG_P (op0
) && CONST_INT_P (op1
))
1160 /* op1 is already the sv value for use to do left shift. */
1163 /* We only allow (ashift reg const_int_0)
1164 or (ashift reg const_int_1) or (ashift reg const_int_2). */
1165 if (sv
!= 0 && sv
!= 1 && sv
!=2)
1168 regno
= REGNO (op0
);
1169 /* Limit it in general registers if we are
1170 in reload pass or after reload pass. */
1172 return REGNO_OK_FOR_INDEX_P (regno
);
1184 /* ------------------------------------------------------------------------ */
1186 /* PART 3: Implement target hook stuff definitions. */
1188 /* Register Classes. */
1190 static unsigned char
1191 nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED
,
1192 enum machine_mode mode
)
1194 /* Return the maximum number of consecutive registers
1195 needed to represent "mode" in a register of "rclass". */
1196 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1200 nds32_register_priority (int hard_regno
)
1202 /* Encourage to use r0-r7 for LRA when optimize for size. */
1203 if (optimize_size
&& hard_regno
< 8)
1209 /* Stack Layout and Calling Conventions. */
1211 /* There are three kinds of pointer concepts using in GCC compiler:
1213 frame pointer: A pointer to the first location of local variables.
1214 stack pointer: A pointer to the top of a stack frame.
1215 argument pointer: A pointer to the incoming arguments.
1217 In nds32 target calling convention, we are using 8-byte alignment.
1218 Besides, we would like to have each stack frame of a function includes:
1221 1. previous hard frame pointer
1223 3. callee-saved registers
1224 4. <padding bytes> (we will calculte in nds32_compute_stack_frame()
1226 cfun->machine->callee_saved_area_padding_bytes)
1230 2. spilling location
1231 3. <padding bytes> (it will be calculated by GCC itself)
1232 4. incoming arguments
1233 5. <padding bytes> (it will be calculated by GCC itself)
1236 1. <padding bytes> (it will be calculated by GCC itself)
1237 2. outgoing arguments
1239 We 'wrap' these blocks together with
1240 hard frame pointer ($r28) and stack pointer ($r31).
1241 By applying the basic frame/stack/argument pointers concept,
1242 the layout of a stack frame shoule be like this:
1245 old stack pointer -> ----
1247 | | saved arguments for
1248 | | vararg functions
1250 hard frame pointer -> --
1251 & argument pointer | | \
1252 | | previous hardware frame pointer
1254 | | callee-saved registers
1259 | | and incoming arguments
1266 stack pointer -> ----
1268 $SFP and $AP are used to represent frame pointer and arguments pointer,
1269 which will be both eliminated as hard frame pointer. */
1271 /* -- Eliminating Frame Pointer and Arg Pointer. */
1274 nds32_can_eliminate (const int from_reg
, const int to_reg
)
1276 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
1279 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== HARD_FRAME_POINTER_REGNUM
)
1282 if (from_reg
== FRAME_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
1285 if (from_reg
== FRAME_POINTER_REGNUM
&& to_reg
== HARD_FRAME_POINTER_REGNUM
)
1291 /* -- Passing Arguments in Registers. */
1294 nds32_function_arg (cumulative_args_t ca
, enum machine_mode mode
,
1295 const_tree type
, bool named
)
1297 CUMULATIVE_ARGS
*cum
= get_cumulative_args (ca
);
1299 /* The last time this hook is called,
1300 it is called with MODE == VOIDmode. */
1301 if (mode
== VOIDmode
)
1304 /* For nameless arguments, they are passed on the stack. */
1308 /* If there are still registers available, return it. */
1309 if (NDS32_ARG_PASS_IN_REG_P (cum
->gpr_offset
, mode
, type
))
1311 /* Pick up the next available register number. */
1314 regno
= NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
);
1315 return gen_rtx_REG (mode
, regno
);
1319 /* No register available, return NULL_RTX.
1320 The compiler will use stack to pass argument instead. */
1326 nds32_function_arg_advance (cumulative_args_t ca
, enum machine_mode mode
,
1327 const_tree type
, bool named
)
1329 CUMULATIVE_ARGS
*cum
= get_cumulative_args (ca
);
1331 /* Advance next register for use.
1332 Only named argument could be advanced. */
1336 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
1337 - NDS32_GPR_ARG_FIRST_REGNUM
1338 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
1343 nds32_function_arg_boundary (enum machine_mode mode
, const_tree type
)
1345 return (nds32_needs_double_word_align (mode
, type
)
1346 ? NDS32_DOUBLE_WORD_ALIGNMENT
1350 /* -- How Scalar Function Values Are Returned. */
1353 nds32_function_value (const_tree ret_type
,
1354 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1355 bool outgoing ATTRIBUTE_UNUSED
)
1357 enum machine_mode mode
;
1360 mode
= TYPE_MODE (ret_type
);
1361 unsignedp
= TYPE_UNSIGNED (ret_type
);
1363 mode
= promote_mode (ret_type
, mode
, &unsignedp
);
1365 return gen_rtx_REG (mode
, NDS32_GPR_RET_FIRST_REGNUM
);
1369 nds32_libcall_value (enum machine_mode mode
,
1370 const_rtx fun ATTRIBUTE_UNUSED
)
1372 return gen_rtx_REG (mode
, NDS32_GPR_RET_FIRST_REGNUM
);
1376 nds32_function_value_regno_p (const unsigned int regno
)
1378 return (regno
== NDS32_GPR_RET_FIRST_REGNUM
);
1381 /* -- Function Entry and Exit. */
1383 /* The content produced from this function
1384 will be placed before prologue body. */
1386 nds32_asm_function_prologue (FILE *file
,
1387 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1390 const char *func_name
;
1394 /* All stack frame information is supposed to be
1395 already computed when expanding prologue.
1396 The result is in cfun->machine.
1397 DO NOT call nds32_compute_stack_frame() here
1398 because it may corrupt the essential information. */
1400 fprintf (file
, "\t! BEGIN PROLOGUE\n");
1401 fprintf (file
, "\t! fp needed: %d\n", frame_pointer_needed
);
1402 fprintf (file
, "\t! pretend_args: %d\n", cfun
->machine
->va_args_size
);
1403 fprintf (file
, "\t! local_size: %d\n", cfun
->machine
->local_size
);
1404 fprintf (file
, "\t! out_args_size: %d\n", cfun
->machine
->out_args_size
);
1406 /* Use df_regs_ever_live_p() to detect if the register
1407 is ever used in the current function. */
1408 fprintf (file
, "\t! registers ever_live: ");
1409 for (r
= 0; r
< 32; r
++)
1411 if (df_regs_ever_live_p (r
))
1412 fprintf (file
, "%s, ", reg_names
[r
]);
1416 /* Display the attributes of this function. */
1417 fprintf (file
, "\t! function attributes: ");
1418 /* Get the attributes tree list.
1419 Note that GCC builds attributes list with reverse order. */
1420 attrs
= DECL_ATTRIBUTES (current_function_decl
);
1422 /* If there is no any attribute, print out "None". */
1424 fprintf (file
, "None");
1426 /* If there are some attributes, try if we need to
1427 construct isr vector information. */
1428 func_name
= IDENTIFIER_POINTER (DECL_NAME (current_function_decl
));
1429 nds32_construct_isr_vectors_information (attrs
, func_name
);
1431 /* Display all attributes of this function. */
1434 name
= TREE_PURPOSE (attrs
);
1435 fprintf (file
, "%s ", IDENTIFIER_POINTER (name
));
1437 /* Pick up the next attribute. */
1438 attrs
= TREE_CHAIN (attrs
);
1443 /* After rtl prologue has been expanded, this function is used. */
1445 nds32_asm_function_end_prologue (FILE *file
)
1447 fprintf (file
, "\t! END PROLOGUE\n");
1449 /* If frame pointer is NOT needed and -mfp-as-gp is issued,
1450 we can generate special directive: ".omit_fp_begin"
1451 to guide linker doing fp-as-gp optimization.
1452 However, for a naked function, which means
1453 it should not have prologue/epilogue,
1454 using fp-as-gp still requires saving $fp by push/pop behavior and
1455 there is no benefit to use fp-as-gp on such small function.
1456 So we need to make sure this function is NOT naked as well. */
1457 if (!frame_pointer_needed
1458 && !cfun
->machine
->naked_p
1459 && cfun
->machine
->fp_as_gp_p
)
1461 fprintf (file
, "\t! ----------------------------------------\n");
1462 fprintf (file
, "\t! Guide linker to do "
1463 "link time optimization: fp-as-gp\n");
1464 fprintf (file
, "\t! We add one more instruction to "
1465 "initialize $fp near to $gp location.\n");
1466 fprintf (file
, "\t! If linker fails to use fp-as-gp transformation,\n");
1467 fprintf (file
, "\t! this extra instruction should be "
1468 "eliminated at link stage.\n");
1469 fprintf (file
, "\t.omit_fp_begin\n");
1470 fprintf (file
, "\tla\t$fp,_FP_BASE_\n");
1471 fprintf (file
, "\t! ----------------------------------------\n");
1475 /* Before rtl epilogue has been expanded, this function is used. */
1477 nds32_asm_function_begin_epilogue (FILE *file
)
1479 /* If frame pointer is NOT needed and -mfp-as-gp is issued,
1480 we can generate special directive: ".omit_fp_end"
1481 to claim fp-as-gp optimization range.
1482 However, for a naked function,
1483 which means it should not have prologue/epilogue,
1484 using fp-as-gp still requires saving $fp by push/pop behavior and
1485 there is no benefit to use fp-as-gp on such small function.
1486 So we need to make sure this function is NOT naked as well. */
1487 if (!frame_pointer_needed
1488 && !cfun
->machine
->naked_p
1489 && cfun
->machine
->fp_as_gp_p
)
1491 fprintf (file
, "\t! ----------------------------------------\n");
1492 fprintf (file
, "\t! Claim the range of fp-as-gp "
1493 "link time optimization\n");
1494 fprintf (file
, "\t.omit_fp_end\n");
1495 fprintf (file
, "\t! ----------------------------------------\n");
1498 fprintf (file
, "\t! BEGIN EPILOGUE\n");
1501 /* The content produced from this function
1502 will be placed after epilogue body. */
1504 nds32_asm_function_epilogue (FILE *file
,
1505 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1507 fprintf (file
, "\t! END EPILOGUE\n");
1511 nds32_asm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
1512 HOST_WIDE_INT delta
,
1513 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1518 /* Make sure unwind info is emitted for the thunk if needed. */
1519 final_start_function (emit_barrier (), file
, 1);
1521 this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
1527 if (satisfies_constraint_Is15 (GEN_INT (delta
)))
1529 fprintf (file
, "\taddi\t$r%d, $r%d, %ld\n",
1530 this_regno
, this_regno
, delta
);
1532 else if (satisfies_constraint_Is20 (GEN_INT (delta
)))
1534 fprintf (file
, "\tmovi\t$ta, %ld\n", delta
);
1535 fprintf (file
, "\tadd\t$r%d, $r%d, $ta\n", this_regno
, this_regno
);
1539 fprintf (file
, "\tsethi\t$ta, hi20(%ld)\n", delta
);
1540 fprintf (file
, "\tori\t$ta, $ta, lo12(%ld)\n", delta
);
1541 fprintf (file
, "\tadd\t$r%d, $r%d, $ta\n", this_regno
, this_regno
);
1545 fprintf (file
, "\tb\t");
1546 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
1547 fprintf (file
, "\n");
1549 final_end_function ();
1552 /* -- Permitting tail calls. */
1554 /* Determine whether we need to enable warning for function return check. */
1556 nds32_warn_func_return (tree decl
)
1558 /* Naked functions are implemented entirely in assembly, including the
1559 return sequence, so suppress warnings about this. */
1560 return !nds32_naked_function_p (decl
);
1564 /* Implementing the Varargs Macros. */
1567 nds32_setup_incoming_varargs (cumulative_args_t ca
,
1568 enum machine_mode mode
,
1570 int *pretend_args_size
,
1571 int second_time ATTRIBUTE_UNUSED
)
1573 unsigned int total_args_regs
;
1574 unsigned int num_of_used_regs
;
1575 unsigned int remaining_reg_count
;
1576 CUMULATIVE_ARGS
*cum
;
1578 /* If we are under hard float abi, we do not need to set *pretend_args_size.
1579 So that all nameless arguments are pushed by caller and all situation
1580 can be handled by GCC itself. */
1581 if (TARGET_HARD_FLOAT
)
1584 /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers,
1585 counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments.
1586 However, for nameless(anonymous) arguments, we should push them on the
1587 stack so that all the nameless arguments appear to have been passed
1588 consecutively in the memory for accessing. Hence, we need to check and
1589 exclude the registers that are used for named arguments. */
1591 cum
= get_cumulative_args (ca
);
1593 /* The MODE and TYPE describe the last argument.
1594 We need those information to determine the remaining registers
1597 = NDS32_MAX_GPR_REGS_FOR_ARGS
+ NDS32_GPR_ARG_FIRST_REGNUM
;
1599 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
1600 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
1602 remaining_reg_count
= total_args_regs
- num_of_used_regs
;
1603 *pretend_args_size
= remaining_reg_count
* UNITS_PER_WORD
;
1609 nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
1611 /* If this hook returns true, the named argument of FUNCTION_ARG is always
1612 true for named arguments, and false for unnamed arguments. */
1617 /* Trampolines for Nested Functions. */
1620 nds32_asm_trampoline_template (FILE *f
)
1622 if (TARGET_REDUCED_REGS
)
1624 /* Trampoline is not supported on reduced-set registers yet. */
1625 sorry ("a nested function is not supported for reduced registers");
1629 asm_fprintf (f
, "\t! Trampoline code template\n");
1630 asm_fprintf (f
, "\t! This code fragment will be copied "
1631 "into stack on demand\n");
1633 asm_fprintf (f
, "\tmfusr\t$r16,$pc\n");
1634 asm_fprintf (f
, "\tlwi\t$r15,[$r16 + 20] "
1635 "! load nested function address\n");
1636 asm_fprintf (f
, "\tlwi\t$r16,[$r16 + 16] "
1637 "! load chain_value\n");
1638 asm_fprintf (f
, "\tjr\t$r15\n");
1641 /* Preserve space ($pc + 16) for saving chain_value,
1642 nds32_trampoline_init will fill the value in this slot. */
1643 asm_fprintf (f
, "\t! space for saving chain_value\n");
1644 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
1646 /* Preserve space ($pc + 20) for saving nested function address,
1647 nds32_trampoline_init will fill the value in this slot. */
1648 asm_fprintf (f
, "\t! space for saving nested function address\n");
1649 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
1652 /* Emit RTL insns to initialize the variable parts of a trampoline. */
1654 nds32_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
1658 /* Nested function address. */
1660 /* The memory rtx that is going to
1661 be filled with chain_value. */
1662 rtx chain_value_mem
;
1663 /* The memory rtx that is going to
1664 be filled with nested function address. */
1665 rtx nested_func_mem
;
1667 /* Start address of trampoline code in stack, for doing cache sync. */
1668 rtx sync_cache_addr
;
1669 /* Temporary register for sync instruction. */
1671 /* Instruction-cache sync instruction,
1672 requesting an argument as starting address. */
1674 /* For convenience reason of doing comparison. */
1675 int tramp_align_in_bytes
;
1677 /* Trampoline is not supported on reduced-set registers yet. */
1678 if (TARGET_REDUCED_REGS
)
1679 sorry ("a nested function is not supported for reduced registers");
1681 /* STEP 1: Copy trampoline code template into stack,
1682 fill up essential data into stack. */
1684 /* Extract nested function address rtx. */
1685 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
1687 /* m_tramp is memory rtx that is going to be filled with trampoline code.
1688 We have nds32_asm_trampoline_template() to emit template pattern. */
1689 emit_block_move (m_tramp
, assemble_trampoline_template (),
1690 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
1692 /* After copying trampoline code into stack,
1693 fill chain_value into stack. */
1694 chain_value_mem
= adjust_address (m_tramp
, SImode
, 16);
1695 emit_move_insn (chain_value_mem
, chain_value
);
1696 /* After copying trampoline code int stack,
1697 fill nested function address into stack. */
1698 nested_func_mem
= adjust_address (m_tramp
, SImode
, 20);
1699 emit_move_insn (nested_func_mem
, fnaddr
);
1701 /* STEP 2: Sync instruction-cache. */
1703 /* We have successfully filled trampoline code into stack.
1704 However, in order to execute code in stack correctly,
1705 we must sync instruction cache. */
1706 sync_cache_addr
= XEXP (m_tramp
, 0);
1707 tmp_reg
= gen_reg_rtx (SImode
);
1708 isync_insn
= gen_unspec_volatile_isync (tmp_reg
);
1710 /* Because nds32_cache_block_size is in bytes,
1711 we get trampoline alignment in bytes for convenient comparison. */
1712 tramp_align_in_bytes
= TRAMPOLINE_ALIGNMENT
/ BITS_PER_UNIT
;
1714 if (tramp_align_in_bytes
>= nds32_cache_block_size
1715 && (tramp_align_in_bytes
% nds32_cache_block_size
) == 0)
1717 /* Under this condition, the starting address of trampoline
1718 must be aligned to the starting address of each cache block
1719 and we do not have to worry about cross-boundary issue. */
1721 i
< (TRAMPOLINE_SIZE
+ nds32_cache_block_size
- 1)
1722 / nds32_cache_block_size
;
1725 emit_move_insn (tmp_reg
,
1726 plus_constant (Pmode
, sync_cache_addr
,
1727 nds32_cache_block_size
* i
));
1728 emit_insn (isync_insn
);
1731 else if (TRAMPOLINE_SIZE
> nds32_cache_block_size
)
1733 /* The starting address of trampoline code
1734 may not be aligned to the cache block,
1735 so the trampoline code may be across two cache block.
1736 We need to sync the last element, which is 4-byte size,
1737 of trampoline template. */
1739 i
< (TRAMPOLINE_SIZE
+ nds32_cache_block_size
- 1)
1740 / nds32_cache_block_size
;
1743 emit_move_insn (tmp_reg
,
1744 plus_constant (Pmode
, sync_cache_addr
,
1745 nds32_cache_block_size
* i
));
1746 emit_insn (isync_insn
);
1749 /* The last element of trampoline template is 4-byte size. */
1750 emit_move_insn (tmp_reg
,
1751 plus_constant (Pmode
, sync_cache_addr
,
1752 TRAMPOLINE_SIZE
- 4));
1753 emit_insn (isync_insn
);
1757 /* This is the simplest case.
1758 Because TRAMPOLINE_SIZE is less than or
1759 equal to nds32_cache_block_size,
1760 we can just sync start address and
1761 the last element of trampoline code. */
1763 /* Sync starting address of tampoline code. */
1764 emit_move_insn (tmp_reg
, sync_cache_addr
);
1765 emit_insn (isync_insn
);
1766 /* Sync the last element, which is 4-byte size,
1767 of trampoline template. */
1768 emit_move_insn (tmp_reg
,
1769 plus_constant (Pmode
, sync_cache_addr
,
1770 TRAMPOLINE_SIZE
- 4));
1771 emit_insn (isync_insn
);
1774 /* Set instruction serialization barrier
1775 to guarantee the correct operations. */
1776 emit_insn (gen_unspec_volatile_isb ());
1780 /* Addressing Modes. */
1783 nds32_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1785 /* For (mem:DI addr) or (mem:DF addr) case,
1786 we only allow 'addr' to be [reg], [symbol_ref],
1787 [const], or [reg + const_int] pattern. */
1788 if (mode
== DImode
|| mode
== DFmode
)
1790 /* Allow [Reg + const_int] addressing mode. */
1791 if (GET_CODE (x
) == PLUS
)
1793 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
)
1794 && nds32_legitimate_index_p (mode
, XEXP (x
, 1), strict
)
1795 && CONST_INT_P (XEXP (x
, 1)))
1798 else if (nds32_address_register_rtx_p (XEXP (x
, 1), strict
)
1799 && nds32_legitimate_index_p (mode
, XEXP (x
, 0), strict
)
1800 && CONST_INT_P (XEXP (x
, 0)))
1804 /* Now check [reg], [symbol_ref], and [const]. */
1805 if (GET_CODE (x
) != REG
1806 && GET_CODE (x
) != SYMBOL_REF
1807 && GET_CODE (x
) != CONST
)
1811 /* Check if 'x' is a valid address. */
1812 switch (GET_CODE (x
))
1815 /* (mem (reg A)) => [Ra] */
1816 return nds32_address_register_rtx_p (x
, strict
);
1820 if (!TARGET_GP_DIRECT
1821 && (reload_completed
1822 || reload_in_progress
1823 || lra_in_progress
))
1826 /* (mem (symbol_ref A)) => [symbol_ref] */
1827 return !currently_expanding_to_rtl
;
1831 if (!TARGET_GP_DIRECT
1832 && (reload_completed
1833 || reload_in_progress
1834 || lra_in_progress
))
1837 /* (mem (const (...)))
1838 => [ + const_addr ], where const_addr = symbol_ref + const_int */
1839 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
1841 rtx plus_op
= XEXP (x
, 0);
1843 rtx op0
= XEXP (plus_op
, 0);
1844 rtx op1
= XEXP (plus_op
, 1);
1846 if (GET_CODE (op0
) == SYMBOL_REF
&& CONST_INT_P (op1
))
1855 /* (mem (post_modify (reg) (plus (reg) (reg))))
1857 /* (mem (post_modify (reg) (plus (reg) (const_int))))
1858 => [Ra], const_int */
1859 if (GET_CODE (XEXP (x
, 0)) == REG
1860 && GET_CODE (XEXP (x
, 1)) == PLUS
)
1862 rtx plus_op
= XEXP (x
, 1);
1864 rtx op0
= XEXP (plus_op
, 0);
1865 rtx op1
= XEXP (plus_op
, 1);
1867 if (nds32_address_register_rtx_p (op0
, strict
)
1868 && nds32_legitimate_index_p (mode
, op1
, strict
))
1878 /* (mem (post_inc reg)) => [Ra], 1/2/4 */
1879 /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */
1880 /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
1881 We only need to deal with register Ra. */
1882 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
))
1888 /* (mem (plus reg const_int))
1890 /* (mem (plus reg reg))
1892 /* (mem (plus (mult reg const_int) reg))
1893 => [Ra + Rb << sv] */
1894 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
)
1895 && nds32_legitimate_index_p (mode
, XEXP (x
, 1), strict
))
1897 else if (nds32_address_register_rtx_p (XEXP (x
, 1), strict
)
1898 && nds32_legitimate_index_p (mode
, XEXP (x
, 0), strict
))
1904 if (!TARGET_GP_DIRECT
)
1913 /* Describing Relative Costs of Operations. */
1916 nds32_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1920 if (from
== HIGH_REGS
|| to
== HIGH_REGS
)
1927 nds32_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1928 reg_class_t rclass ATTRIBUTE_UNUSED
,
1929 bool in ATTRIBUTE_UNUSED
)
1934 /* This target hook describes the relative costs of RTL expressions.
1935 Return 'true' when all subexpressions of x have been processed.
1936 Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
1937 Refer to gcc/rtlanal.c for more information. */
1939 nds32_rtx_costs (rtx x
,
1946 return nds32_rtx_costs_impl (x
, code
, outer_code
, opno
, total
, speed
);
1950 nds32_address_cost (rtx address
,
1951 enum machine_mode mode
,
1955 return nds32_address_cost_impl (address
, mode
, as
, speed
);
1959 /* Defining the Output Assembler Language. */
1961 /* -- The Overall Framework of an Assembler File. */
1964 nds32_asm_file_start (void)
1966 default_file_start ();
1968 /* Tell assembler which ABI we are using. */
1969 fprintf (asm_out_file
, "\t! ABI version\n");
1970 fprintf (asm_out_file
, "\t.abi_2\n");
1972 /* Tell assembler that this asm code is generated by compiler. */
1973 fprintf (asm_out_file
, "\t! This asm file is generated by compiler\n");
1974 fprintf (asm_out_file
, "\t.flag\tverbatim\n");
1975 /* Give assembler the size of each vector for interrupt handler. */
1976 fprintf (asm_out_file
, "\t! This vector size directive is required "
1977 "for checking inconsistency on interrupt handler\n");
1978 fprintf (asm_out_file
, "\t.vec_size\t%d\n", nds32_isr_vector_size
);
1980 /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os,
1981 the compiler may produce 'la $fp,_FP_BASE_' instruction
1982 at prologue for fp-as-gp optimization.
1983 We should emit weak reference of _FP_BASE_ to avoid undefined reference
1984 in case user does not pass '--relax' option to linker. */
1985 if (TARGET_FORCE_FP_AS_GP
|| optimize_size
)
1987 fprintf (asm_out_file
, "\t! This weak reference is required to do "
1988 "fp-as-gp link time optimization\n");
1989 fprintf (asm_out_file
, "\t.weak\t_FP_BASE_\n");
1991 /* If user enables '-mex9', we should emit relaxation directive
1992 to tell linker that this file is allowed to do ex9 optimization. */
1995 fprintf (asm_out_file
, "\t! This relaxation directive is required "
1996 "to do ex9 link time optimization\n");
1997 fprintf (asm_out_file
, "\t.relax\tex9\n");
2000 fprintf (asm_out_file
, "\t! ------------------------------------\n");
2003 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V2");
2005 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V3");
2007 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V3M");
2009 fprintf (asm_out_file
, "\t! Endian setting\t: %s\n",
2010 ((TARGET_BIG_ENDIAN
) ? "big-endian"
2011 : "little-endian"));
2013 fprintf (asm_out_file
, "\t! ------------------------------------\n");
2015 fprintf (asm_out_file
, "\t! Use conditional move\t\t: %s\n",
2016 ((TARGET_CMOV
) ? "Yes"
2018 fprintf (asm_out_file
, "\t! Use performance extension\t: %s\n",
2019 ((TARGET_PERF_EXT
) ? "Yes"
2022 fprintf (asm_out_file
, "\t! ------------------------------------\n");
2024 fprintf (asm_out_file
, "\t! V3PUSH instructions\t: %s\n",
2025 ((TARGET_V3PUSH
) ? "Yes"
2027 fprintf (asm_out_file
, "\t! 16-bit instructions\t: %s\n",
2028 ((TARGET_16_BIT
) ? "Yes"
2030 fprintf (asm_out_file
, "\t! GP base access\t: %s\n",
2031 ((TARGET_GP_DIRECT
) ? "Yes"
2033 fprintf (asm_out_file
, "\t! Reduced registers set\t: %s\n",
2034 ((TARGET_REDUCED_REGS
) ? "Yes"
2037 fprintf (asm_out_file
, "\t! ------------------------------------\n");
2040 fprintf (asm_out_file
, "\t! Optimization level\t: -Os\n");
2042 fprintf (asm_out_file
, "\t! Optimization level\t: -O%d\n", optimize
);
2044 fprintf (asm_out_file
, "\t! ------------------------------------\n");
2046 fprintf (asm_out_file
, "\t! Cache block size\t: %d\n",
2047 nds32_cache_block_size
);
2049 fprintf (asm_out_file
, "\t! ------------------------------------\n");
2051 nds32_asm_file_start_for_isr ();
2055 nds32_asm_file_end (void)
2057 nds32_asm_file_end_for_isr ();
2059 fprintf (asm_out_file
, "\t! ------------------------------------\n");
2062 /* -- Output and Generation of Labels. */
2065 nds32_asm_globalize_label (FILE *stream
, const char *name
)
2067 fputs ("\t.global\t", stream
);
2068 assemble_name (stream
, name
);
2069 fputs ("\n", stream
);
2072 /* -- Output of Assembler Instructions. */
2075 nds32_print_operand (FILE *stream
, rtx x
, int code
)
2082 /* Do nothing special. */
2086 /* 'x' is supposed to be CONST_INT, get the value. */
2087 gcc_assert (CONST_INT_P (x
));
2088 op_value
= INTVAL (x
);
2090 /* According to the Andes architecture,
2091 the system/user register index range is 0 ~ 1023.
2092 In order to avoid conflict between user-specified-integer value
2093 and enum-specified-register value,
2094 the 'enum nds32_intrinsic_registers' value
2095 in nds32_intrinsic.h starts from 1024. */
2096 if (op_value
< 1024 && op_value
>= 0)
2098 /* If user gives integer value directly (0~1023),
2099 we just print out the value. */
2100 fprintf (stream
, "%d", op_value
);
2102 else if (op_value
< 0
2103 || op_value
>= ((int) ARRAY_SIZE (nds32_intrinsic_register_names
)
2106 /* The enum index value for array size is out of range. */
2107 error ("intrinsic register index is out of range");
2111 /* If user applies normal way with __NDS32_REG_XXX__ enum data,
2112 we can print out register name. Remember to substract 1024. */
2113 fprintf (stream
, "%s",
2114 nds32_intrinsic_register_names
[op_value
- 1024]);
2117 /* No need to handle following process, so return immediately. */
2122 output_operand_lossage ("invalid operand output code");
2126 switch (GET_CODE (x
))
2130 output_addr_const (stream
, x
);
2134 /* Forbid using static chain register ($r16)
2135 on reduced-set registers configuration. */
2136 if (TARGET_REDUCED_REGS
2137 && REGNO (x
) == STATIC_CHAIN_REGNUM
)
2138 sorry ("a nested function is not supported for reduced registers");
2140 /* Normal cases, print out register name. */
2141 fputs (reg_names
[REGNO (x
)], stream
);
2145 output_address (XEXP (x
, 0));
2151 output_addr_const (stream
, x
);
2155 /* Generally, output_addr_const () is able to handle most cases.
2156 We want to see what CODE could appear,
2157 so we use gcc_unreachable() to stop it. */
2165 nds32_print_operand_address (FILE *stream
, rtx x
)
2169 switch (GET_CODE (x
))
2173 /* [ + symbol_ref] */
2174 /* [ + const_addr], where const_addr = symbol_ref + const_int */
2175 fputs ("[ + ", stream
);
2176 output_addr_const (stream
, x
);
2177 fputs ("]", stream
);
2181 /* Forbid using static chain register ($r16)
2182 on reduced-set registers configuration. */
2183 if (TARGET_REDUCED_REGS
2184 && REGNO (x
) == STATIC_CHAIN_REGNUM
)
2185 sorry ("a nested function is not supported for reduced registers");
2188 fprintf (stream
, "[%s]", reg_names
[REGNO (x
)]);
2195 /* Checking op0, forbid using static chain register ($r16)
2196 on reduced-set registers configuration. */
2197 if (TARGET_REDUCED_REGS
2199 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
2200 sorry ("a nested function is not supported for reduced registers");
2201 /* Checking op1, forbid using static chain register ($r16)
2202 on reduced-set registers configuration. */
2203 if (TARGET_REDUCED_REGS
2205 && REGNO (op1
) == STATIC_CHAIN_REGNUM
)
2206 sorry ("a nested function is not supported for reduced registers");
2208 if (REG_P (op0
) && CONST_INT_P (op1
))
2211 fprintf (stream
, "[%s + (%d)]",
2212 reg_names
[REGNO (op0
)], (int)INTVAL (op1
));
2214 else if (REG_P (op0
) && REG_P (op1
))
2217 fprintf (stream
, "[%s + %s]",
2218 reg_names
[REGNO (op0
)], reg_names
[REGNO (op1
)]);
2220 else if (GET_CODE (op0
) == MULT
&& REG_P (op1
))
2223 From observation, the pattern looks like:
2224 (plus:SI (mult:SI (reg:SI 58)
2225 (const_int 4 [0x4]))
2229 /* We need to set sv to output shift value. */
2230 if (INTVAL (XEXP (op0
, 1)) == 1)
2232 else if (INTVAL (XEXP (op0
, 1)) == 2)
2234 else if (INTVAL (XEXP (op0
, 1)) == 4)
2239 fprintf (stream
, "[%s + %s << %d]",
2240 reg_names
[REGNO (op1
)],
2241 reg_names
[REGNO (XEXP (op0
, 0))],
2246 /* The control flow is not supposed to be here. */
2254 /* (post_modify (regA) (plus (regA) (regB)))
2255 (post_modify (regA) (plus (regA) (const_int)))
2256 We would like to extract
2257 regA and regB (or const_int) from plus rtx. */
2258 op0
= XEXP (XEXP (x
, 1), 0);
2259 op1
= XEXP (XEXP (x
, 1), 1);
2261 /* Checking op0, forbid using static chain register ($r16)
2262 on reduced-set registers configuration. */
2263 if (TARGET_REDUCED_REGS
2265 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
2266 sorry ("a nested function is not supported for reduced registers");
2267 /* Checking op1, forbid using static chain register ($r16)
2268 on reduced-set registers configuration. */
2269 if (TARGET_REDUCED_REGS
2271 && REGNO (op1
) == STATIC_CHAIN_REGNUM
)
2272 sorry ("a nested function is not supported for reduced registers");
2274 if (REG_P (op0
) && REG_P (op1
))
2277 fprintf (stream
, "[%s], %s",
2278 reg_names
[REGNO (op0
)], reg_names
[REGNO (op1
)]);
2280 else if (REG_P (op0
) && CONST_INT_P (op1
))
2283 fprintf (stream
, "[%s], %d",
2284 reg_names
[REGNO (op0
)], (int)INTVAL (op1
));
2288 /* The control flow is not supposed to be here. */
2299 /* Checking op0, forbid using static chain register ($r16)
2300 on reduced-set registers configuration. */
2301 if (TARGET_REDUCED_REGS
2303 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
2304 sorry ("a nested function is not supported for reduced registers");
2308 /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4"
2309 The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
2310 We only need to deal with register Ra. */
2311 fprintf (stream
, "[%s]", reg_names
[REGNO (op0
)]);
2315 /* The control flow is not supposed to be here. */
2323 /* Generally, output_addr_const () is able to handle most cases.
2324 We want to see what CODE could appear,
2325 so we use gcc_unreachable() to stop it. */
2333 /* Defining target-specific uses of __attribute__. */
2335 /* Add some checking after merging attributes. */
2337 nds32_merge_decl_attributes (tree olddecl
, tree newdecl
)
2339 tree combined_attrs
;
2341 /* Create combined attributes. */
2342 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
2343 DECL_ATTRIBUTES (newdecl
));
2345 /* Since newdecl is acutally a duplicate of olddecl,
2346 we can take olddecl for some operations. */
2347 if (TREE_CODE (olddecl
) == FUNCTION_DECL
)
2349 /* Check isr-specific attributes conflict. */
2350 nds32_check_isr_attrs_conflict (olddecl
, combined_attrs
);
2353 return combined_attrs
;
2356 /* Add some checking when inserting attributes. */
2358 nds32_insert_attributes (tree decl
, tree
*attributes
)
2360 /* For function declaration, we need to check isr-specific attributes:
2361 1. Call nds32_check_isr_attrs_conflict() to check any conflict.
2362 2. Check valid integer value for interrupt/exception.
2363 3. Check valid integer value for reset.
2364 4. Check valid function for nmi/warm. */
2365 if (TREE_CODE (decl
) == FUNCTION_DECL
)
2368 tree intr
, excp
, reset
;
2370 /* Pick up function attributes. */
2371 func_attrs
= *attributes
;
2373 /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */
2374 nds32_check_isr_attrs_conflict (decl
, func_attrs
);
2376 /* Now we are starting to check valid id value
2377 for interrupt/exception/reset.
2378 Note that we ONLY check its validity here.
2379 To construct isr vector information, it is still performed
2380 by nds32_construct_isr_vectors_information(). */
2381 intr
= lookup_attribute ("interrupt", func_attrs
);
2382 excp
= lookup_attribute ("exception", func_attrs
);
2383 reset
= lookup_attribute ("reset", func_attrs
);
2387 /* Deal with interrupt/exception. */
2389 unsigned int lower_bound
, upper_bound
;
2391 /* The way to handle interrupt or exception is the same,
2392 we just need to take care of actual vector number.
2393 For interrupt(0..63), the actual vector number is (9..72).
2394 For exception(1..8), the actual vector number is (1..8). */
2395 lower_bound
= (intr
) ? (0) : (1);
2396 upper_bound
= (intr
) ? (63) : (8);
2398 /* Prepare id list so that we can traverse id value. */
2399 id_list
= (intr
) ? (TREE_VALUE (intr
)) : (TREE_VALUE (excp
));
2401 /* 2. Check valid integer value for interrupt/exception. */
2406 /* Pick up each vector id value. */
2407 id
= TREE_VALUE (id_list
);
2408 /* Issue error if it is not a valid integer value. */
2409 if (TREE_CODE (id
) != INTEGER_CST
2410 || wi::ltu_p (id
, lower_bound
)
2411 || wi::gtu_p (id
, upper_bound
))
2412 error ("invalid id value for interrupt/exception attribute");
2414 /* Advance to next id. */
2415 id_list
= TREE_CHAIN (id_list
);
2420 /* Deal with reset. */
2424 unsigned int lower_bound
;
2425 unsigned int upper_bound
;
2427 /* Prepare id_list and identify id value so that
2428 we can check if total number of vectors is valid. */
2429 id_list
= TREE_VALUE (reset
);
2430 id
= TREE_VALUE (id_list
);
2432 /* The maximum numbers for user's interrupt is 64. */
2436 /* 3. Check valid integer value for reset. */
2437 if (TREE_CODE (id
) != INTEGER_CST
2438 || wi::ltu_p (id
, lower_bound
)
2439 || wi::gtu_p (id
, upper_bound
))
2440 error ("invalid id value for reset attribute");
2442 /* 4. Check valid function for nmi/warm. */
2443 nmi
= lookup_attribute ("nmi", func_attrs
);
2444 warm
= lookup_attribute ("warm", func_attrs
);
2446 if (nmi
!= NULL_TREE
)
2451 nmi_func_list
= TREE_VALUE (nmi
);
2452 nmi_func
= TREE_VALUE (nmi_func_list
);
2454 /* Issue error if it is not a valid nmi function. */
2455 if (TREE_CODE (nmi_func
) != IDENTIFIER_NODE
)
2456 error ("invalid nmi function for reset attribute");
2459 if (warm
!= NULL_TREE
)
2461 tree warm_func_list
;
2464 warm_func_list
= TREE_VALUE (warm
);
2465 warm_func
= TREE_VALUE (warm_func_list
);
2467 /* Issue error if it is not a valid warm function. */
2468 if (TREE_CODE (warm_func
) != IDENTIFIER_NODE
)
2469 error ("invalid warm function for reset attribute");
2474 /* No interrupt, exception, or reset attribute is set. */
2481 nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED
,
2482 tree pop_target ATTRIBUTE_UNUSED
)
2484 /* Currently, we do not parse any pragma target by ourself,
2485 so just simply return false. */
2490 nds32_option_override (void)
2492 /* After all the command options have been parsed,
2493 we shall deal with some flags for changing compiler settings. */
2495 /* At first, we check if we have to strictly
2496 set some flags based on ISA family. */
2499 /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */
2500 target_flags
&= ~MASK_V3PUSH
;
2504 /* Under V3 ISA, currently nothing should be strictly set. */
2508 /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
2509 target_flags
|= MASK_REDUCED_REGS
;
2510 /* Under V3M ISA, we need to strictly disable TARGET_PERF_EXT. */
2511 target_flags
&= ~MASK_PERF_EXT
;
2514 /* See if we are using reduced-set registers:
2515 $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31
2516 If so, we must forbid using $r11~$r14, $r16~$r27. */
2517 if (TARGET_REDUCED_REGS
)
2521 /* Prevent register allocator from
2522 choosing it as doing register allocation. */
2523 for (r
= 11; r
<= 14; r
++)
2524 fixed_regs
[r
] = call_used_regs
[r
] = 1;
2525 for (r
= 16; r
<= 27; r
++)
2526 fixed_regs
[r
] = call_used_regs
[r
] = 1;
2529 /* See if user explicitly would like to use fp-as-gp optimization.
2530 If so, we must prevent $fp from being allocated
2531 during register allocation. */
2532 if (TARGET_FORCE_FP_AS_GP
)
2533 fixed_regs
[FP_REGNUM
] = call_used_regs
[FP_REGNUM
] = 1;
2537 /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */
2538 target_flags
&= ~MASK_V3PUSH
;
2541 /* Currently, we don't support PIC code generation yet. */
2543 sorry ("not support -fpic");
2547 /* Miscellaneous Parameters. */
2550 nds32_init_builtins (void)
2552 nds32_init_builtins_impl ();
2556 nds32_expand_builtin (tree exp
,
2559 enum machine_mode mode
,
2562 return nds32_expand_builtin_impl (exp
, target
, subtarget
, mode
, ignore
);
2566 /* ------------------------------------------------------------------------ */
2568 /* PART 4: Implemet extern function definitions,
2569 the prototype is in nds32-protos.h. */
2571 /* Defining Data Structures for Per-function Information. */
2574 nds32_init_expanders (void)
2576 /* Arrange to initialize and mark the machine per-function status. */
2577 init_machine_status
= nds32_init_machine_status
;
2581 /* Register Usage. */
2583 /* -- How Values Fit in Registers. */
2586 nds32_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
,
2587 enum machine_mode mode
)
2589 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
2593 nds32_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
2595 /* Restrict double-word quantities to even register pairs. */
2596 if (HARD_REGNO_NREGS (regno
, mode
) == 1
2604 /* Register Classes. */
2607 nds32_regno_reg_class (int regno
)
2609 /* Refer to nds32.h for more register class details. */
2611 if (regno
>= 0 && regno
<= 7)
2613 else if (regno
>= 8 && regno
<= 11)
2615 else if (regno
>= 12 && regno
<= 14)
2617 else if (regno
== 15)
2619 else if (regno
>= 16 && regno
<= 19)
2621 else if (regno
>= 20 && regno
<= 31)
2623 else if (regno
== 32 || regno
== 33)
2630 /* Stack Layout and Calling Conventions. */
2632 /* -- Basic Stack Layout. */
2635 nds32_return_addr_rtx (int count
,
2636 rtx frameaddr ATTRIBUTE_UNUSED
)
2638 /* There is no way to determine the return address
2639 if frameaddr is the frame that has 'count' steps
2640 up from current frame. */
2644 /* If count == 0, it means we are at current frame,
2645 the return address is $r30 ($lp). */
2646 return get_hard_reg_initial_val (Pmode
, LP_REGNUM
);
2649 /* -- Eliminating Frame Pointer and Arg Pointer. */
2652 nds32_initial_elimination_offset (unsigned int from_reg
, unsigned int to_reg
)
2654 HOST_WIDE_INT offset
;
2656 /* Compute and setup stack frame size.
2657 The result will be in cfun->machine. */
2658 nds32_compute_stack_frame ();
2660 /* Remember to consider
2661 cfun->machine->callee_saved_area_padding_bytes
2662 when calculating offset. */
2663 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
2665 offset
= (cfun
->machine
->fp_size
2666 + cfun
->machine
->gp_size
2667 + cfun
->machine
->lp_size
2668 + cfun
->machine
->callee_saved_regs_size
2669 + cfun
->machine
->callee_saved_area_padding_bytes
2670 + cfun
->machine
->local_size
2671 + cfun
->machine
->out_args_size
);
2673 else if (from_reg
== ARG_POINTER_REGNUM
2674 && to_reg
== HARD_FRAME_POINTER_REGNUM
)
2678 else if (from_reg
== FRAME_POINTER_REGNUM
2679 && to_reg
== STACK_POINTER_REGNUM
)
2681 offset
= (cfun
->machine
->local_size
+ cfun
->machine
->out_args_size
);
2683 else if (from_reg
== FRAME_POINTER_REGNUM
2684 && to_reg
== HARD_FRAME_POINTER_REGNUM
)
2686 offset
= (-1) * (cfun
->machine
->fp_size
2687 + cfun
->machine
->gp_size
2688 + cfun
->machine
->lp_size
2689 + cfun
->machine
->callee_saved_regs_size
2690 + cfun
->machine
->callee_saved_area_padding_bytes
);
2700 /* -- Passing Arguments in Registers. */
2703 nds32_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
2704 tree fntype ATTRIBUTE_UNUSED
,
2705 rtx libname ATTRIBUTE_UNUSED
,
2706 tree fndecl ATTRIBUTE_UNUSED
,
2707 int n_named_args ATTRIBUTE_UNUSED
)
2709 /* Initial available registers
2710 (in offset, corresponding to NDS32_GPR_ARG_FIRST_REGNUM)
2711 for passing arguments. */
2712 cum
->gpr_offset
= 0;
2715 /* -- Function Entry and Exit. */
2717 /* Function for normal multiple push prologue. */
2719 nds32_expand_prologue (void)
2726 rtx fp_adjust_insn
, sp_adjust_insn
;
2728 /* Before computing everything for stack frame size,
2729 we check if it is still worth to use fp_as_gp optimization.
2730 If it is, the 'df_regs_ever_live_p (FP_REGNUM)' will be set
2731 so that $fp will be saved on stack. */
2732 cfun
->machine
->fp_as_gp_p
= nds32_fp_as_gp_check_available ();
2734 /* Compute and setup stack frame size.
2735 The result will be in cfun->machine. */
2736 nds32_compute_stack_frame ();
2738 /* If the function is 'naked',
2739 we do not have to generate prologue code fragment. */
2740 if (cfun
->machine
->naked_p
)
2743 /* Get callee_first_regno and callee_last_regno. */
2744 Rb
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_first_regno
);
2745 Re
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_last_regno
);
2747 /* nds32_emit_stack_push_multiple(first_regno, last_regno),
2748 the pattern 'stack_push_multiple' is implemented in nds32.md.
2749 For En4 field, we have to calculate its constant value.
2750 Refer to Andes ISA for more information. */
2752 if (cfun
->machine
->fp_size
)
2754 if (cfun
->machine
->gp_size
)
2756 if (cfun
->machine
->lp_size
)
2759 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
2760 to be saved, we don't have to create multiple push instruction.
2761 Otherwise, a multiple push instruction is needed. */
2762 if (!(REGNO (Rb
) == SP_REGNUM
&& REGNO (Re
) == SP_REGNUM
&& en4_const
== 0))
2764 /* Create multiple push instruction rtx. */
2765 nds32_emit_stack_push_multiple (Rb
, Re
, GEN_INT (en4_const
));
2768 /* Check frame_pointer_needed to see
2769 if we shall emit fp adjustment instruction. */
2770 if (frame_pointer_needed
)
2772 /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size)
2773 + (4 * callee-saved-registers)
2774 Note: No need to adjust
2775 cfun->machine->callee_saved_area_padding_bytes,
2776 because, at this point, stack pointer is just
2777 at the position after push instruction. */
2778 fp_adjust
= cfun
->machine
->fp_size
2779 + cfun
->machine
->gp_size
2780 + cfun
->machine
->lp_size
2781 + cfun
->machine
->callee_saved_regs_size
;
2782 fp_adjust_insn
= gen_addsi3 (hard_frame_pointer_rtx
,
2784 GEN_INT (fp_adjust
));
2785 /* Emit rtx into instructions list and receive INSN rtx form. */
2786 fp_adjust_insn
= emit_insn (fp_adjust_insn
);
2789 /* Adjust $sp = $sp - local_size - out_args_size
2790 - callee_saved_area_padding_bytes. */
2791 sp_adjust
= cfun
->machine
->local_size
2792 + cfun
->machine
->out_args_size
2793 + cfun
->machine
->callee_saved_area_padding_bytes
;
2794 /* sp_adjust value may be out of range of the addi instruction,
2795 create alternative add behavior with TA_REGNUM if necessary,
2796 using NEGATIVE value to tell that we are decreasing address. */
2797 sp_adjust
= nds32_force_addi_stack_int ( (-1) * sp_adjust
);
2800 /* Generate sp adjustment instruction if and only if sp_adjust != 0. */
2801 sp_adjust_insn
= gen_addsi3 (stack_pointer_rtx
,
2803 GEN_INT (-1 * sp_adjust
));
2804 /* Emit rtx into instructions list and receive INSN rtx form. */
2805 sp_adjust_insn
= emit_insn (sp_adjust_insn
);
2807 /* The insn rtx 'sp_adjust_insn' will change frame layout.
2808 We need to use RTX_FRAME_RELATED_P so that GCC is able to
2809 generate CFI (Call Frame Information) stuff. */
2810 RTX_FRAME_RELATED_P (sp_adjust_insn
) = 1;
2813 /* Prevent the instruction scheduler from
2814 moving instructions across the boundary. */
2815 emit_insn (gen_blockage ());
2818 /* Function for normal multiple pop epilogue. */
2820 nds32_expand_epilogue (void)
2828 /* Compute and setup stack frame size.
2829 The result will be in cfun->machine. */
2830 nds32_compute_stack_frame ();
2832 /* Prevent the instruction scheduler from
2833 moving instructions across the boundary. */
2834 emit_insn (gen_blockage ());
2836 /* If the function is 'naked', we do not have to generate
2837 epilogue code fragment BUT 'ret' instruction. */
2838 if (cfun
->machine
->naked_p
)
2840 /* Generate return instruction by using
2841 unspec_volatile_func_return pattern.
2842 Make sure this instruction is after gen_blockage().
2843 NOTE that $lp will become 'live'
2844 after this instruction has been emitted. */
2845 emit_insn (gen_unspec_volatile_func_return ());
2849 if (frame_pointer_needed
)
2851 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
2852 - (4 * callee-saved-registers)
2853 Note: No need to adjust
2854 cfun->machine->callee_saved_area_padding_bytes,
2855 because we want to adjust stack pointer
2856 to the position for pop instruction. */
2857 sp_adjust
= cfun
->machine
->fp_size
2858 + cfun
->machine
->gp_size
2859 + cfun
->machine
->lp_size
2860 + cfun
->machine
->callee_saved_regs_size
;
2861 sp_adjust_insn
= gen_addsi3 (stack_pointer_rtx
,
2862 hard_frame_pointer_rtx
,
2863 GEN_INT (-1 * sp_adjust
));
2864 /* Emit rtx into instructions list and receive INSN rtx form. */
2865 sp_adjust_insn
= emit_insn (sp_adjust_insn
);
2869 /* If frame pointer is NOT needed,
2870 we cannot calculate the sp adjustment from frame pointer.
2871 Instead, we calculate the adjustment by local_size,
2872 out_args_size, and callee_saved_area_padding_bytes.
2873 Notice that such sp adjustment value may be out of range,
2874 so we have to deal with it as well. */
2876 /* Adjust $sp = $sp + local_size + out_args_size
2877 + callee_saved_area_padding_bytes. */
2878 sp_adjust
= cfun
->machine
->local_size
2879 + cfun
->machine
->out_args_size
2880 + cfun
->machine
->callee_saved_area_padding_bytes
;
2881 /* sp_adjust value may be out of range of the addi instruction,
2882 create alternative add behavior with TA_REGNUM if necessary,
2883 using POSITIVE value to tell that we are increasing address. */
2884 sp_adjust
= nds32_force_addi_stack_int (sp_adjust
);
2887 /* Generate sp adjustment instruction
2888 if and only if sp_adjust != 0. */
2889 sp_adjust_insn
= gen_addsi3 (stack_pointer_rtx
,
2891 GEN_INT (sp_adjust
));
2892 /* Emit rtx into instructions list and receive INSN rtx form. */
2893 sp_adjust_insn
= emit_insn (sp_adjust_insn
);
2897 /* Get callee_first_regno and callee_last_regno. */
2898 Rb
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_first_regno
);
2899 Re
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_last_regno
);
2901 /* nds32_emit_stack_pop_multiple(first_regno, last_regno),
2902 the pattern 'stack_pop_multiple' is implementad in nds32.md.
2903 For En4 field, we have to calculate its constant value.
2904 Refer to Andes ISA for more information. */
2906 if (cfun
->machine
->fp_size
)
2908 if (cfun
->machine
->gp_size
)
2910 if (cfun
->machine
->lp_size
)
2913 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
2914 to be saved, we don't have to create multiple pop instruction.
2915 Otherwise, a multiple pop instruction is needed. */
2916 if (!(REGNO (Rb
) == SP_REGNUM
&& REGNO (Re
) == SP_REGNUM
&& en4_const
== 0))
2918 /* Create multiple pop instruction rtx. */
2919 nds32_emit_stack_pop_multiple (Rb
, Re
, GEN_INT (en4_const
));
2922 /* Generate return instruction by using
2923 unspec_volatile_func_return pattern. */
2924 emit_insn (gen_unspec_volatile_func_return ());
2927 /* Function for v3push prologue. */
2929 nds32_expand_prologue_v3push (void)
2935 rtx fp_adjust_insn
, sp_adjust_insn
;
2937 /* Before computing everything for stack frame size,
2938 we check if it is still worth to use fp_as_gp optimization.
2939 If it is, the 'df_regs_ever_live_p (FP_REGNUM)' will be set
2940 so that $fp will be saved on stack. */
2941 cfun
->machine
->fp_as_gp_p
= nds32_fp_as_gp_check_available ();
2943 /* Compute and setup stack frame size.
2944 The result will be in cfun->machine. */
2945 nds32_compute_stack_frame ();
2947 /* If the function is 'naked',
2948 we do not have to generate prologue code fragment. */
2949 if (cfun
->machine
->naked_p
)
2952 /* Get callee_first_regno and callee_last_regno. */
2953 Rb
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_first_regno
);
2954 Re
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_last_regno
);
2956 /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
2957 where imm8u has to be 8-byte alignment. */
2958 sp_adjust
= cfun
->machine
->local_size
2959 + cfun
->machine
->out_args_size
2960 + cfun
->machine
->callee_saved_area_padding_bytes
;
2962 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
2963 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
))
2965 /* We can use 'push25 Re,imm8u'. */
2967 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
2968 the pattern 'stack_v3push' is implemented in nds32.md.
2969 The (const_int 14) means v3push always push { $fp $gp $lp }. */
2970 nds32_emit_stack_v3push (Rb
, Re
,
2971 GEN_INT (14), GEN_INT (sp_adjust
));
2973 /* Check frame_pointer_needed to see
2974 if we shall emit fp adjustment instruction. */
2975 if (frame_pointer_needed
)
2977 /* adjust $fp = $sp + 4 ($fp size)
2980 + (4 * n) (callee-saved registers)
2981 + sp_adjust ('push25 Re,imm8u')
2982 Note: Since we use 'push25 Re,imm8u',
2983 the position of stack pointer is further
2984 changed after push instruction.
2985 Hence, we need to take sp_adjust value
2986 into consideration. */
2987 fp_adjust
= cfun
->machine
->fp_size
2988 + cfun
->machine
->gp_size
2989 + cfun
->machine
->lp_size
2990 + cfun
->machine
->callee_saved_regs_size
2992 fp_adjust_insn
= gen_addsi3 (hard_frame_pointer_rtx
,
2994 GEN_INT (fp_adjust
));
2995 /* Emit rtx into instructions list and receive INSN rtx form. */
2996 fp_adjust_insn
= emit_insn (fp_adjust_insn
);
3001 /* We have to use 'push25 Re,0' and
3002 expand one more instruction to adjust $sp later. */
3004 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
3005 the pattern 'stack_v3push' is implemented in nds32.md.
3006 The (const_int 14) means v3push always push { $fp $gp $lp }. */
3007 nds32_emit_stack_v3push (Rb
, Re
,
3008 GEN_INT (14), GEN_INT (0));
3010 /* Check frame_pointer_needed to see
3011 if we shall emit fp adjustment instruction. */
3012 if (frame_pointer_needed
)
3014 /* adjust $fp = $sp + 4 ($fp size)
3017 + (4 * n) (callee-saved registers)
3018 Note: Since we use 'push25 Re,0',
3019 the stack pointer is just at the position
3020 after push instruction.
3021 No need to take sp_adjust into consideration. */
3022 fp_adjust
= cfun
->machine
->fp_size
3023 + cfun
->machine
->gp_size
3024 + cfun
->machine
->lp_size
3025 + cfun
->machine
->callee_saved_regs_size
;
3026 fp_adjust_insn
= gen_addsi3 (hard_frame_pointer_rtx
,
3028 GEN_INT (fp_adjust
));
3029 /* Emit rtx into instructions list and receive INSN rtx form. */
3030 fp_adjust_insn
= emit_insn (fp_adjust_insn
);
3033 /* Because we use 'push25 Re,0',
3034 we need to expand one more instruction to adjust $sp.
3035 However, sp_adjust value may be out of range of the addi instruction,
3036 create alternative add behavior with TA_REGNUM if necessary,
3037 using NEGATIVE value to tell that we are decreasing address. */
3038 sp_adjust
= nds32_force_addi_stack_int ( (-1) * sp_adjust
);
3041 /* Generate sp adjustment instruction
3042 if and only if sp_adjust != 0. */
3043 sp_adjust_insn
= gen_addsi3 (stack_pointer_rtx
,
3045 GEN_INT (-1 * sp_adjust
));
3046 /* Emit rtx into instructions list and receive INSN rtx form. */
3047 sp_adjust_insn
= emit_insn (sp_adjust_insn
);
3049 /* The insn rtx 'sp_adjust_insn' will change frame layout.
3050 We need to use RTX_FRAME_RELATED_P so that GCC is able to
3051 generate CFI (Call Frame Information) stuff. */
3052 RTX_FRAME_RELATED_P (sp_adjust_insn
) = 1;
3056 /* Prevent the instruction scheduler from
3057 moving instructions across the boundary. */
3058 emit_insn (gen_blockage ());
3061 /* Function for v3pop epilogue. */
3063 nds32_expand_epilogue_v3pop (void)
3070 /* Compute and setup stack frame size.
3071 The result will be in cfun->machine. */
3072 nds32_compute_stack_frame ();
3074 /* Prevent the instruction scheduler from
3075 moving instructions across the boundary. */
3076 emit_insn (gen_blockage ());
3078 /* If the function is 'naked', we do not have to generate
3079 epilogue code fragment BUT 'ret' instruction. */
3080 if (cfun
->machine
->naked_p
)
3082 /* Generate return instruction by using
3083 unspec_volatile_func_return pattern.
3084 Make sure this instruction is after gen_blockage().
3085 NOTE that $lp will become 'live'
3086 after this instruction has been emitted. */
3087 emit_insn (gen_unspec_volatile_func_return ());
3091 /* Get callee_first_regno and callee_last_regno. */
3092 Rb
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_first_regno
);
3093 Re
= gen_rtx_REG (SImode
, cfun
->machine
->callee_saved_regs_last_regno
);
3095 /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
3096 where imm8u has to be 8-byte alignment. */
3097 sp_adjust
= cfun
->machine
->local_size
3098 + cfun
->machine
->out_args_size
3099 + cfun
->machine
->callee_saved_area_padding_bytes
;
3101 /* We have to consider alloca issue as well.
3102 If the function does call alloca(), the stack pointer is not fixed.
3103 In that case, we cannot use 'pop25 Re,imm8u' directly.
3104 We have to caculate stack pointer from frame pointer
3105 and then use 'pop25 Re,0'.
3106 Of course, the frame_pointer_needed should be nonzero
3107 if the function calls alloca(). */
3108 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
3109 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
)
3110 && !cfun
->calls_alloca
)
3112 /* We can use 'pop25 Re,imm8u'. */
3114 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
3115 the pattern 'stack_v3pop' is implementad in nds32.md.
3116 The (const_int 14) means v3pop always pop { $fp $gp $lp }. */
3117 nds32_emit_stack_v3pop (Rb
, Re
,
3118 GEN_INT (14), GEN_INT (sp_adjust
));
3122 /* We have to use 'pop25 Re,0', and prior to it,
3123 we must expand one more instruction to adjust $sp. */
3125 if (frame_pointer_needed
)
3127 /* adjust $sp = $fp - 4 ($fp size)
3130 - (4 * n) (callee-saved registers)
3131 Note: No need to adjust
3132 cfun->machine->callee_saved_area_padding_bytes,
3133 because we want to adjust stack pointer
3134 to the position for pop instruction. */
3135 sp_adjust
= cfun
->machine
->fp_size
3136 + cfun
->machine
->gp_size
3137 + cfun
->machine
->lp_size
3138 + cfun
->machine
->callee_saved_regs_size
;
3139 sp_adjust_insn
= gen_addsi3 (stack_pointer_rtx
,
3140 hard_frame_pointer_rtx
,
3141 GEN_INT (-1 * sp_adjust
));
3142 /* Emit rtx into instructions list and receive INSN rtx form. */
3143 sp_adjust_insn
= emit_insn (sp_adjust_insn
);
3147 /* If frame pointer is NOT needed,
3148 we cannot calculate the sp adjustment from frame pointer.
3149 Instead, we calculate the adjustment by local_size,
3150 out_args_size, and callee_saved_area_padding_bytes.
3151 Notice that such sp adjustment value may be out of range,
3152 so we have to deal with it as well. */
3154 /* Adjust $sp = $sp + local_size + out_args_size
3155 + callee_saved_area_padding_bytes. */
3156 sp_adjust
= cfun
->machine
->local_size
3157 + cfun
->machine
->out_args_size
3158 + cfun
->machine
->callee_saved_area_padding_bytes
;
3159 /* sp_adjust value may be out of range of the addi instruction,
3160 create alternative add behavior with TA_REGNUM if necessary,
3161 using POSITIVE value to tell that we are increasing address. */
3162 sp_adjust
= nds32_force_addi_stack_int (sp_adjust
);
3165 /* Generate sp adjustment instruction
3166 if and only if sp_adjust != 0. */
3167 sp_adjust_insn
= gen_addsi3 (stack_pointer_rtx
,
3169 GEN_INT (sp_adjust
));
3170 /* Emit rtx into instructions list and receive INSN rtx form. */
3171 sp_adjust_insn
= emit_insn (sp_adjust_insn
);
3175 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
3176 the pattern 'stack_v3pop' is implementad in nds32.md. */
3177 /* The (const_int 14) means v3pop always pop { $fp $gp $lp }. */
3178 nds32_emit_stack_v3pop (Rb
, Re
,
3179 GEN_INT (14), GEN_INT (0));
3183 /* ------------------------------------------------------------------------ */
3185 /* Function to test 333-form for load/store instructions.
3186 This is auxiliary extern function for auxiliary macro in nds32.h.
3187 Because it is a little complicated, we use function instead of macro. */
3189 nds32_ls_333_p (rtx rt
, rtx ra
, rtx imm
, enum machine_mode mode
)
3191 if (REGNO_REG_CLASS (REGNO (rt
)) == LOW_REGS
3192 && REGNO_REG_CLASS (REGNO (ra
)) == LOW_REGS
)
3194 if (GET_MODE_SIZE (mode
) == 4)
3195 return satisfies_constraint_Iu05 (imm
);
3197 if (GET_MODE_SIZE (mode
) == 2)
3198 return satisfies_constraint_Iu04 (imm
);
3200 if (GET_MODE_SIZE (mode
) == 1)
3201 return satisfies_constraint_Iu03 (imm
);
3208 /* Computing the Length of an Insn.
3209 Modifies the length assigned to instruction INSN.
3210 LEN is the initially computed length of the insn. */
3212 nds32_adjust_insn_length (rtx_insn
*insn
, int length
)
3216 switch (recog_memoized (insn
))
3218 case CODE_FOR_move_df
:
3219 case CODE_FOR_move_di
:
3220 /* Adjust length of movd44 to 2. */
3221 src
= XEXP (PATTERN (insn
), 1);
3222 dst
= XEXP (PATTERN (insn
), 0);
3226 && (REGNO (src
) % 2) == 0
3227 && (REGNO (dst
) % 2) == 0)
3239 /* Return align 2 (log base 2) if the next instruction of LABEL is 4 byte. */
3241 nds32_target_alignment (rtx label
)
3248 insn
= next_active_insn (label
);
3252 else if ((get_attr_length (insn
) % 4) == 0)
3258 /* ------------------------------------------------------------------------ */
3260 /* PART 5: Initialize target hook structure and definitions. */
3262 /* Controlling the Compilation Driver. */
3265 /* Run-time Target Specification. */
3268 /* Defining Data Structures for Per-function Information. */
3271 /* Storage Layout. */
3273 #undef TARGET_PROMOTE_FUNCTION_MODE
3274 #define TARGET_PROMOTE_FUNCTION_MODE \
3275 default_promote_function_mode_always_promote
3278 /* Layout of Source Language Data Types. */
3281 /* Register Usage. */
3283 /* -- Basic Characteristics of Registers. */
3285 /* -- Order of Allocation of Registers. */
3287 /* -- How Values Fit in Registers. */
3289 /* -- Handling Leaf Functions. */
3291 /* -- Registers That Form a Stack. */
3294 /* Register Classes. */
3296 #undef TARGET_CLASS_MAX_NREGS
3297 #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs
3300 #define TARGET_LRA_P hook_bool_void_true
3302 #undef TARGET_REGISTER_PRIORITY
3303 #define TARGET_REGISTER_PRIORITY nds32_register_priority
3306 /* Obsolete Macros for Defining Constraints. */
3309 /* Stack Layout and Calling Conventions. */
3311 /* -- Basic Stack Layout. */
3313 /* -- Exception Handling Support. */
3315 /* -- Specifying How Stack Checking is Done. */
3317 /* -- Registers That Address the Stack Frame. */
3319 /* -- Eliminating Frame Pointer and Arg Pointer. */
3321 #undef TARGET_CAN_ELIMINATE
3322 #define TARGET_CAN_ELIMINATE nds32_can_eliminate
3324 /* -- Passing Function Arguments on the Stack. */
3326 /* -- Passing Arguments in Registers. */
3328 #undef TARGET_FUNCTION_ARG
3329 #define TARGET_FUNCTION_ARG nds32_function_arg
3331 #undef TARGET_FUNCTION_ARG_ADVANCE
3332 #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance
3334 #undef TARGET_FUNCTION_ARG_BOUNDARY
3335 #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary
3337 /* -- How Scalar Function Values Are Returned. */
3339 #undef TARGET_FUNCTION_VALUE
3340 #define TARGET_FUNCTION_VALUE nds32_function_value
3342 #undef TARGET_LIBCALL_VALUE
3343 #define TARGET_LIBCALL_VALUE nds32_libcall_value
3345 #undef TARGET_FUNCTION_VALUE_REGNO_P
3346 #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p
3348 /* -- How Large Values Are Returned. */
3350 /* -- Caller-Saves Register Allocation. */
3352 /* -- Function Entry and Exit. */
3354 #undef TARGET_ASM_FUNCTION_PROLOGUE
3355 #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue
3357 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
3358 #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue
3360 #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
3361 #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue
3363 #undef TARGET_ASM_FUNCTION_EPILOGUE
3364 #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue
3366 #undef TARGET_ASM_OUTPUT_MI_THUNK
3367 #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk
3369 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3370 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
3372 /* -- Generating Code for Profiling. */
3374 /* -- Permitting tail calls. */
3376 #undef TARGET_WARN_FUNC_RETURN
3377 #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return
3379 /* Stack smashing protection. */
3382 /* Implementing the Varargs Macros. */
3384 #undef TARGET_SETUP_INCOMING_VARARGS
3385 #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs
3387 #undef TARGET_STRICT_ARGUMENT_NAMING
3388 #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming
3391 /* Trampolines for Nested Functions. */
3393 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
3394 #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template
3396 #undef TARGET_TRAMPOLINE_INIT
3397 #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init
3400 /* Implicit Calls to Library Routines. */
3403 /* Addressing Modes. */
3405 #undef TARGET_LEGITIMATE_ADDRESS_P
3406 #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p
3409 /* Anchored Addresses. */
3412 /* Condition Code Status. */
3414 /* -- Representation of condition codes using (cc0). */
3416 /* -- Representation of condition codes using registers. */
3418 /* -- Macros to control conditional execution. */
3421 /* Describing Relative Costs of Operations. */
3423 #undef TARGET_REGISTER_MOVE_COST
3424 #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost
3426 #undef TARGET_MEMORY_MOVE_COST
3427 #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost
3429 #undef TARGET_RTX_COSTS
3430 #define TARGET_RTX_COSTS nds32_rtx_costs
3432 #undef TARGET_ADDRESS_COST
3433 #define TARGET_ADDRESS_COST nds32_address_cost
3436 /* Adjusting the Instruction Scheduler. */
3439 /* Dividing the Output into Sections (Texts, Data, . . . ). */
3442 /* Position Independent Code. */
3445 /* Defining the Output Assembler Language. */
3447 /* -- The Overall Framework of an Assembler File. */
3449 #undef TARGET_ASM_FILE_START
3450 #define TARGET_ASM_FILE_START nds32_asm_file_start
3451 #undef TARGET_ASM_FILE_END
3452 #define TARGET_ASM_FILE_END nds32_asm_file_end
3454 /* -- Output of Data. */
3456 #undef TARGET_ASM_ALIGNED_HI_OP
3457 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
3459 #undef TARGET_ASM_ALIGNED_SI_OP
3460 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
3462 /* -- Output of Uninitialized Variables. */
3464 /* -- Output and Generation of Labels. */
3466 #undef TARGET_ASM_GLOBALIZE_LABEL
3467 #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label
3469 /* -- How Initialization Functions Are Handled. */
3471 /* -- Macros Controlling Initialization Routines. */
3473 /* -- Output of Assembler Instructions. */
3475 #undef TARGET_PRINT_OPERAND
3476 #define TARGET_PRINT_OPERAND nds32_print_operand
3477 #undef TARGET_PRINT_OPERAND_ADDRESS
3478 #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address
3480 /* -- Output of Dispatch Tables. */
3482 /* -- Assembler Commands for Exception Regions. */
3484 /* -- Assembler Commands for Alignment. */
3487 /* Controlling Debugging Information Format. */
3489 /* -- Macros Affecting All Debugging Formats. */
3491 /* -- Specific Options for DBX Output. */
3493 /* -- Open-Ended Hooks for DBX Format. */
3495 /* -- File Names in DBX Format. */
3497 /* -- Macros for SDB and DWARF Output. */
3499 /* -- Macros for VMS Debug Format. */
3502 /* Cross Compilation and Floating Point. */
3505 /* Mode Switching Instructions. */
3508 /* Defining target-specific uses of __attribute__. */
3510 #undef TARGET_ATTRIBUTE_TABLE
3511 #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table
3513 #undef TARGET_MERGE_DECL_ATTRIBUTES
3514 #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes
3516 #undef TARGET_INSERT_ATTRIBUTES
3517 #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes
3519 #undef TARGET_OPTION_PRAGMA_PARSE
3520 #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse
3522 #undef TARGET_OPTION_OVERRIDE
3523 #define TARGET_OPTION_OVERRIDE nds32_option_override
3526 /* Emulating TLS. */
3529 /* Defining coprocessor specifics for MIPS targets. */
3532 /* Parameters for Precompiled Header Validity Checking. */
3535 /* C++ ABI parameters. */
3538 /* Adding support for named address spaces. */
3541 /* Miscellaneous Parameters. */
3543 #undef TARGET_INIT_BUILTINS
3544 #define TARGET_INIT_BUILTINS nds32_init_builtins
3546 #undef TARGET_EXPAND_BUILTIN
3547 #define TARGET_EXPAND_BUILTIN nds32_expand_builtin
3550 /* ------------------------------------------------------------------------ */
3552 /* Initialize the GCC target structure. */
3554 struct gcc_target targetm
= TARGET_INITIALIZER
;
3556 /* ------------------------------------------------------------------------ */