gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  28   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  29
  30 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  31    It is used in nds32_encode_section_info() to store flag in symbol_ref
  32    in case the symbol should be placed in .rodata section.
  33    So that we can check it in nds32_legitimate_address_p().  */
  34 #define NDS32_SYMBOL_FLAG_RODATA \
  35   (SYMBOL_FLAG_MACH_DEP << 0)
  36 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  37   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  38
  39 /* Classifies expand result for expand helper function.  */
  40 enum nds32_expand_result_type
  41 {
  42   EXPAND_DONE,
  43   EXPAND_FAIL,
  44   EXPAND_CREATE_TEMPLATE
  45 };
  46
  47 /* Classifies address type to distinguish 16-bit/32-bit format.  */
  48 enum nds32_16bit_address_type
  49 {
  50   /* [reg]: 45 format address.  */
  51   ADDRESS_REG,
  52   /* [lo_reg + imm3u]: 333 format address.  */
  53   ADDRESS_LO_REG_IMM3U,
  54   /* post_inc [lo_reg + imm3u]: 333 format address.  */
  55   ADDRESS_POST_INC_LO_REG_IMM3U,
  56   /* post_modify [lo_reg + imm3u]: 333 format address.  */
  57   ADDRESS_POST_MODIFY_LO_REG_IMM3U,
  58   /* [$r8 + imm7u]: r8 imply address.  */
  59   ADDRESS_R8_IMM7U,
  60   /* [$fp + imm7u]: fp imply address.  */
  61   ADDRESS_FP_IMM7U,
  62   /* [$sp + imm7u]: sp imply address.  */
  63   ADDRESS_SP_IMM7U,
  64   /* Other address format.  */
  65   ADDRESS_NOT_16BIT_FORMAT
  66 };
  67
  68
  69 /* ------------------------------------------------------------------------ */
  70
  71 /* Define maximum numbers of registers for passing arguments.  */
  72 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
  73 #define NDS32_MAX_FPR_REGS_FOR_ARGS 6
  74
  75 /* Define the register number for first argument.  */
  76 #define NDS32_GPR_ARG_FIRST_REGNUM 0
  77 #define NDS32_FPR_ARG_FIRST_REGNUM 34
  78
  79 /* Define the register number for return value.  */
  80 #define NDS32_GPR_RET_FIRST_REGNUM 0
  81 #define NDS32_FPR_RET_FIRST_REGNUM 34
  82
  83 /* Define the first integer register number.  */
  84 #define NDS32_FIRST_GPR_REGNUM 0
  85 /* Define the last integer register number.  */
  86 #define NDS32_LAST_GPR_REGNUM 31
  87
  88 #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
  89 #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
  90   (TARGET_REDUCED_REGS ? 10 : 14)
  91
  92 /* Define the floating-point number of registers.  */
  93 #define NDS32_FLOAT_REGISTER_NUMBER                           \
  94  (((nds32_fp_regnum == NDS32_CONFIG_FPU_0)              \
  95    || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8      \
  96   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1)            \
  97     || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16    \
  98   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2)            \
  99     || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32    \
 100   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3)            \
 101     || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64    \
 102   : 32)
 103
 104 #define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
 105
 106 /* Define the first floating-point register number.  */
 107 #define NDS32_FIRST_FPR_REGNUM 34
 108 /* Define the last floating-point register number.  */
 109 #define NDS32_LAST_FPR_REGNUM \
 110   (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
 111
 112
 113 #define NDS32_IS_EXT_FPR_REGNUM(regno) \
 114   (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
 115    && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
 116
 117 #define NDS32_IS_FPR_REGNUM(regno) \
 118   (((regno) >= NDS32_FIRST_FPR_REGNUM) \
 119    && ((regno) <= NDS32_LAST_FPR_REGNUM))
 120
 121 #define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
 122   ((regno) <= NDS32_LAST_FPR_REGNUM)
 123
 124 #define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
 125   ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
 126
 127 #define NDS32_IS_GPR_REGNUM(regno) \
 128   (((regno) <= NDS32_LAST_GPR_REGNUM))
 129
 130 /* Define double word alignment bits.  */
 131 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 132
 133 /* Define alignment checking macros for convenience.  */
 134 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 135 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 136 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 137
 138 /* Determine whether we would like to have code generation strictly aligned.
 139    We set it strictly aligned when -malways-align is enabled.
 140    Check gcc/common/config/nds32/nds32-common.c for the optimizations that
 141    apply -malways-align.  */
 142 #define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
 143 /* Get alignment according to mode or type information.
 144    When 'type' is nonnull, there is no need to look at 'mode'.  */
 145 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 146   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 147
 148 /* Round X up to the nearest double word.  */
 149 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 150
 151
 152 /* This macro is used to calculate the numbers of registers for
 153    containing 'size' bytes of the argument.
 154    The size of a register is a word in nds32 target.
 155    So we use UNITS_PER_WORD to do the calculation.  */
 156 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 157   ((mode == BLKmode)                                                     \
 158    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 159    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 160
 161 /* This macro is used to return the register number for passing argument.
 162    We need to obey the following rules:
 163      1. If it is required MORE THAN one register,
 164         we need to further check if it really needs to be
 165         aligned on double words.
 166           a) If double word alignment is necessary,
 167              the register number must be even value.
 168           b) Otherwise, the register number can be odd or even value.
 169      2. If it is required ONLY one register,
 170         the register number can be odd or even value.  */
 171 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 172   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 173    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 174       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 175       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 176    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 177
 178 #define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
 179   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 180    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 181       ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 182       : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))               \
 183    : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
 184
 185 /* These two macros are to check if there are still available registers
 186    for passing argument, which must be entirely in registers.  */
 187 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 188   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 189     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 190    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 191        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 192
 193 #define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type)   \
 194   ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 195     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 196    <= (NDS32_FPR_ARG_FIRST_REGNUM                               \
 197        + NDS32_MAX_FPR_REGS_FOR_ARGS))
 198
 199 /* These two macros are to check if there are still available registers
 200    for passing argument, either entirely in registers or partially
 201    in registers.  */
 202 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 203   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 204    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 205
 206 #define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
 207   (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 208    < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
 209
 210 /* This macro is to check if the register is required to be saved on stack.
 211    If call_used_regs[regno] == 0, regno is the callee-saved register.
 212    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 213    As long as the register satisfies both criteria above,
 214    it is required to be saved.  */
 215 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 216   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 217
 218 /* This macro is to check if the push25/pop25 are available to be used
 219    for code generation.  Because pop25 also performs return behavior,
 220    the instructions may not be available for some cases.
 221    If we want to use push25/pop25, all the following conditions must
 222    be satisfied:
 223      1. TARGET_V3PUSH is set.
 224      2. Current function is not an ISR function.
 225      3. Current function is not a variadic function.*/
 226 #define NDS32_V3PUSH_AVAILABLE_P  \
 227   (TARGET_V3PUSH \
 228    && !nds32_isr_function_p (current_function_decl) \
 229    && (cfun->machine->va_args_size == 0))
 230
 231 /* ------------------------------------------------------------------------ */
 232
 233 /* A C structure for machine-specific, per-function data.
 234    This is added to the cfun structure.  */
 235 struct GTY(()) machine_function
 236 {
 237   /* Number of bytes allocated on the stack for variadic args
 238      if we want to push them into stack as pretend arguments by ourself.  */
 239   int va_args_size;
 240   /* Number of bytes reserved on the stack for
 241      local and temporary variables.  */
 242   int local_size;
 243   /* Number of bytes allocated on the stack for outgoing arguments.  */
 244   int out_args_size;
 245
 246   /* Number of bytes on the stack for saving $fp.  */
 247   int fp_size;
 248   /* Number of bytes on the stack for saving $gp.  */
 249   int gp_size;
 250   /* Number of bytes on the stack for saving $lp.  */
 251   int lp_size;
 252
 253   /* Number of bytes on the stack for saving general purpose
 254      callee-saved registers.  */
 255   int callee_saved_gpr_regs_size;
 256
 257   /* Number of bytes on the stack for saving floating-point
 258      callee-saved registers.  */
 259   int callee_saved_fpr_regs_size;
 260
 261   /* The padding bytes in callee-saved area may be required.  */
 262   int callee_saved_area_gpr_padding_bytes;
 263
 264   /* The first required general purpose callee-saved register.  */
 265   int callee_saved_first_gpr_regno;
 266   /* The last required general purpose callee-saved register.  */
 267   int callee_saved_last_gpr_regno;
 268
 269   /* The first required floating-point callee-saved register.  */
 270   int callee_saved_first_fpr_regno;
 271   /* The last required floating-point callee-saved register.  */
 272   int callee_saved_last_fpr_regno;
 273
 274   /* The padding bytes in varargs area may be required.  */
 275   int va_args_area_padding_bytes;
 276
 277   /* The first required register that should be saved on stack for va_args.  */
 278   int va_args_first_regno;
 279   /* The last required register that should be saved on stack for va_args.  */
 280   int va_args_last_regno;
 281
 282   /* Number of bytes on the stack for saving exception handling registers.  */
 283   int eh_return_data_regs_size;
 284   /* The first register of passing exception handling information.  */
 285   int eh_return_data_first_regno;
 286   /* The last register of passing exception handling information.  */
 287   int eh_return_data_last_regno;
 288
 289   /* Indicate that whether this function
 290      calls __builtin_eh_return.  */
 291   int use_eh_return_p;
 292
 293   /* Indicate that whether this function needs
 294      prologue/epilogue code generation.  */
 295   int naked_p;
 296   /* Indicate that whether this function
 297      uses fp_as_gp optimization.  */
 298   int fp_as_gp_p;
 299 };
 300
 301 /* A C structure that contains the arguments information.  */
 302 typedef struct
 303 {
 304   unsigned int gpr_offset;
 305   unsigned int fpr_offset;
 306 } nds32_cumulative_args;
 307
 308 /* ------------------------------------------------------------------------ */
 309
 310 /* The following we define C-ISR related stuff.
 311    In nds32 architecture, we have 73 vectors for interrupt/exception.
 312    For each vector (except for vector 0, which is used for reset behavior),
 313    we allow users to set its register saving scheme and interrupt level.  */
 314
 315 /* There are 73 vectors in nds32 architecture.
 316    0 for reset handler,
 317    1-8 for exception handler,
 318    and 9-72 for interrupt handler.
 319    We use an array, which is defined in nds32.c, to record
 320    essential information for each vector.  */
 321 #define NDS32_N_ISR_VECTORS 73
 322
 323 /* Define possible isr category.  */
 324 enum nds32_isr_category
 325 {
 326   NDS32_ISR_NONE,
 327   NDS32_ISR_INTERRUPT,
 328   NDS32_ISR_EXCEPTION,
 329   NDS32_ISR_RESET
 330 };
 331
 332 /* Define isr register saving scheme.  */
 333 enum nds32_isr_save_reg
 334 {
 335   NDS32_SAVE_ALL,
 336   NDS32_PARTIAL_SAVE
 337 };
 338
 339 /* Define isr nested type.  */
 340 enum nds32_isr_nested_type
 341 {
 342   NDS32_NESTED,
 343   NDS32_NOT_NESTED,
 344   NDS32_NESTED_READY
 345 };
 346
 347 /* Define structure to record isr information.
 348    The isr vector array 'isr_vectors[]' with this structure
 349    is defined in nds32.c.  */
 350 struct nds32_isr_info
 351 {
 352   /* The field to identify isr category.
 353      It should be set to NDS32_ISR_NONE by default.
 354      If user specifies a function as isr by using attribute,
 355      this field will be set accordingly.  */
 356   enum nds32_isr_category category;
 357
 358   /* A string for the applied function name.
 359      It should be set to empty string by default.  */
 360   char func_name[100];
 361
 362   /* The register saving scheme.
 363      It should be set to NDS32_PARTIAL_SAVE by default
 364      unless user specifies attribute to change it.  */
 365   enum nds32_isr_save_reg save_reg;
 366
 367   /* The nested type.
 368      It should be set to NDS32_NOT_NESTED by default
 369      unless user specifies attribute to change it.  */
 370   enum nds32_isr_nested_type nested_type;
 371
 372   /* Total vectors.
 373      The total vectors = interrupt + exception numbers + reset.
 374      It should be set to 0 by default.
 375      This field is ONLY used in NDS32_ISR_RESET category.  */
 376   unsigned int total_n_vectors;
 377
 378   /* A string for nmi handler name.
 379      It should be set to empty string by default.
 380      This field is ONLY used in NDS32_ISR_RESET category.  */
 381   char nmi_name[100];
 382
 383   /* A string for warm handler name.
 384      It should be set to empty string by default.
 385      This field is ONLY used in NDS32_ISR_RESET category.  */
 386   char warm_name[100];
 387 };
 388
 389 /* ------------------------------------------------------------------------ */
 390
 391 /* Define code for all nds32 builtins.  */
 392 enum nds32_builtins
 393 {
 394   NDS32_BUILTIN_ISYNC,
 395   NDS32_BUILTIN_ISB,
 396   NDS32_BUILTIN_DSB,
 397   NDS32_BUILTIN_MSYNC_ALL,
 398   NDS32_BUILTIN_MSYNC_STORE,
 399   NDS32_BUILTIN_MFSR,
 400   NDS32_BUILTIN_MFUSR,
 401   NDS32_BUILTIN_MTSR,
 402   NDS32_BUILTIN_MTSR_ISB,
 403   NDS32_BUILTIN_MTSR_DSB,
 404   NDS32_BUILTIN_MTUSR,
 405   NDS32_BUILTIN_SETGIE_EN,
 406   NDS32_BUILTIN_SETGIE_DIS,
 407   NDS32_BUILTIN_FMFCFG,
 408   NDS32_BUILTIN_FMFCSR,
 409   NDS32_BUILTIN_FMTCSR,
 410   NDS32_BUILTIN_FCPYNSS,
 411   NDS32_BUILTIN_FCPYSS,
 412   NDS32_BUILTIN_FCPYNSD,
 413   NDS32_BUILTIN_FCPYSD,
 414   NDS32_BUILTIN_ABS,
 415   NDS32_BUILTIN_AVE,
 416   NDS32_BUILTIN_BCLR,
 417   NDS32_BUILTIN_BSET,
 418   NDS32_BUILTIN_BTGL,
 419   NDS32_BUILTIN_BTST,
 420   NDS32_BUILTIN_CLIP,
 421   NDS32_BUILTIN_CLIPS,
 422   NDS32_BUILTIN_CLZ,
 423   NDS32_BUILTIN_CLO,
 424   NDS32_BUILTIN_MAX,
 425   NDS32_BUILTIN_MIN,
 426   NDS32_BUILTIN_PBSAD,
 427   NDS32_BUILTIN_PBSADA,
 428   NDS32_BUILTIN_BSE,
 429   NDS32_BUILTIN_BSP,
 430   NDS32_BUILTIN_FFB,
 431   NDS32_BUILTIN_FFMISM,
 432   NDS32_BUILTIN_FLMISM,
 433
 434   NDS32_BUILTIN_ROTR,
 435   NDS32_BUILTIN_SVA,
 436   NDS32_BUILTIN_SVS,
 437   NDS32_BUILTIN_WSBH,
 438   NDS32_BUILTIN_JR_ITOFF,
 439   NDS32_BUILTIN_JR_TOFF,
 440   NDS32_BUILTIN_JRAL_ITON,
 441   NDS32_BUILTIN_JRAL_TON,
 442   NDS32_BUILTIN_RET_ITOFF,
 443   NDS32_BUILTIN_RET_TOFF,
 444   NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
 445   NDS32_BUILTIN_STANDBY_WAKE_GRANT,
 446   NDS32_BUILTIN_STANDBY_WAKE_DONE,
 447   NDS32_BUILTIN_TEQZ,
 448   NDS32_BUILTIN_TNEZ,
 449   NDS32_BUILTIN_TRAP,
 450   NDS32_BUILTIN_SETEND_BIG,
 451   NDS32_BUILTIN_SETEND_LITTLE,
 452   NDS32_BUILTIN_SYSCALL,
 453   NDS32_BUILTIN_BREAK,
 454   NDS32_BUILTIN_NOP,
 455   NDS32_BUILTIN_SCHE_BARRIER,
 456   NDS32_BUILTIN_GET_CURRENT_SP,
 457   NDS32_BUILTIN_SET_CURRENT_SP,
 458   NDS32_BUILTIN_RETURN_ADDRESS,
 459   NDS32_BUILTIN_LLW,
 460   NDS32_BUILTIN_LWUP,
 461   NDS32_BUILTIN_LBUP,
 462   NDS32_BUILTIN_SCW,
 463   NDS32_BUILTIN_SWUP,
 464   NDS32_BUILTIN_SBUP,
 465   NDS32_BUILTIN_CCTL_VA_LCK,
 466   NDS32_BUILTIN_CCTL_IDX_WBINVAL,
 467   NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
 468   NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
 469   NDS32_BUILTIN_CCTL_IDX_READ,
 470   NDS32_BUILTIN_CCTL_IDX_WRITE,
 471   NDS32_BUILTIN_CCTL_L1D_INVALALL,
 472   NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
 473   NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
 474   NDS32_BUILTIN_DPREF_QW,
 475   NDS32_BUILTIN_DPREF_HW,
 476   NDS32_BUILTIN_DPREF_W,
 477   NDS32_BUILTIN_DPREF_DW,
 478   NDS32_BUILTIN_TLBOP_TRD,
 479   NDS32_BUILTIN_TLBOP_TWR,
 480   NDS32_BUILTIN_TLBOP_RWR,
 481   NDS32_BUILTIN_TLBOP_RWLK,
 482   NDS32_BUILTIN_TLBOP_UNLK,
 483   NDS32_BUILTIN_TLBOP_PB,
 484   NDS32_BUILTIN_TLBOP_INV,
 485   NDS32_BUILTIN_TLBOP_FLUA,
 486   NDS32_BUILTIN_UALOAD_HW,
 487   NDS32_BUILTIN_UALOAD_W,
 488   NDS32_BUILTIN_UALOAD_DW,
 489   NDS32_BUILTIN_UASTORE_HW,
 490   NDS32_BUILTIN_UASTORE_W,
 491   NDS32_BUILTIN_UASTORE_DW,
 492   NDS32_BUILTIN_COUNT
 493 };
 494
 495 /* ------------------------------------------------------------------------ */
 496
 497 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 498
 499 #define TARGET_ISA_V3 \
 500   (nds32_arch_option == ARCH_V3 \
 501    || nds32_arch_option == ARCH_V3F \
 502    || nds32_arch_option == ARCH_V3S)
 503 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 504
 505 #define TARGET_CMODEL_SMALL \
 506    (nds32_cmodel_option == CMODEL_SMALL)
 507 #define TARGET_CMODEL_MEDIUM \
 508    (nds32_cmodel_option == CMODEL_MEDIUM)
 509 #define TARGET_CMODEL_LARGE \
 510    (nds32_cmodel_option == CMODEL_LARGE)
 511
 512 /* When -mcmodel=small or -mcmodel=medium,
 513    compiler may generate gp-base instruction directly.  */
 514 #define TARGET_GP_DIRECT \
 515    (nds32_cmodel_option == CMODEL_SMALL\
 516     || nds32_cmodel_option == CMODEL_MEDIUM)
 517
 518
 519 /* Run-time Target Specification.  */
 520 #define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
 521 /* Use hardware floating point calling convention.  */
 522 #define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
 523
 524 /* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
 525    1 means  hard ABI and using full floating-point instruction,
 526    2 means hard ABI and only using single-precision floating-point
 527    instruction  */
 528 #if TARGET_ARCH_DEFAULT == 1
 529 #  define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 530 #  define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
 531 #  define TARGET_DEFAULT_FPU_FMA 0
 532 #else
 533 #  if TARGET_ARCH_DEFAULT == 2
 534 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 535 #    define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
 536 #    define TARGET_DEFAULT_FPU_FMA 0
 537 #  else
 538 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2
 539 #    define TARGET_DEFAULT_FPU_ISA 0
 540 #    define TARGET_DEFAULT_FPU_FMA 0
 541 #  endif
 542 #endif
 543
 544 #define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
 545 /* ------------------------------------------------------------------------ */
 546 \f
 547 /* Controlling the Compilation Driver.  */
 548
 549 #define OPTION_DEFAULT_SPECS \
 550   {"arch", " %{!march=*:-march=%(VALUE)}" \
 551            " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 552            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
 553            " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
 554            " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 555            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
 556   {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
 557
 558 #define CC1_SPEC \
 559   ""
 560
 561 #define ASM_SPEC \
 562   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 563   " %{march=*:-march=%*}" \
 564   " %{mabi=*:-mabi=v%*}" \
 565   " %{mconfig-fpu=*:-mfpu-freg=%*}" \
 566   " %{mext-fpu-mac:-mmac}" \
 567   " %{mno-ext-fpu-mac:-mno-mac}" \
 568   " %{mext-fpu-sp:-mfpu-sp-ext}" \
 569   " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
 570   " %{mext-fpu-dp:-mfpu-dp-ext}" \
 571   " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}"
 572
 573 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 574 #define LINK_SPEC \
 575   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 576   " %{mrelax:--relax}"
 577
 578 #define LIB_SPEC \
 579   " -lc -lgloss"
 580
 581 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 582    by applying different crt stuff.  In the convention, crt0.o is the
 583    startup file without constructor/destructor;
 584    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 585    startup files with constructor/destructor.
 586    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 587    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 588    currently provided by GCC for nds32 target.
 589
 590    For nds32 target so far:
 591    If -mno-ctor-dtor, we are going to link
 592    "crt0.o [user objects]".
 593    If general cases, we are going to link
 594    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 595 #define STARTFILE_SPEC \
 596   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 597   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 598 #define ENDFILE_SPEC \
 599   " %{!mno-ctor-dtor:crtend1.o%s}"
 600
 601 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 602    configure gcc with --target=nds32be-* setting.
 603    Check gcc/config.gcc for more information.  */
 604 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 605 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 606 #else
 607 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 608 #endif
 609
 610 /* Currently we only have elf toolchain,
 611    where -mcmodel=medium is always the default.  */
 612 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 613
 614 #define MULTILIB_DEFAULTS \
 615   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 616
 617 \f
 618 /* Run-time Target Specification.  */
 619
 620 #define TARGET_CPU_CPP_BUILTINS() \
 621   nds32_cpu_cpp_builtins (pfile)
 622
 623 \f
 624 /* Defining Data Structures for Per-function Information.  */
 625
 626 /* This macro is called once per function,
 627    before generation of any RTL has begun.  */
 628 #define INIT_EXPANDERS  nds32_init_expanders ()
 629
 630 \f
 631 /* Storage Layout.  */
 632
 633 #define BITS_BIG_ENDIAN 0
 634
 635 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 636
 637 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 638
 639 #define UNITS_PER_WORD 4
 640
 641 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 642   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 643     {                                                                       \
 644       (m) = SImode;                                                         \
 645     }
 646
 647 #define PARM_BOUNDARY 32
 648
 649 #define STACK_BOUNDARY 64
 650
 651 #define FUNCTION_BOUNDARY \
 652   ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16)
 653
 654 #define BIGGEST_ALIGNMENT 64
 655
 656 #define EMPTY_FIELD_BOUNDARY 32
 657
 658 #define STRUCTURE_SIZE_BOUNDARY 8
 659
 660 #define STRICT_ALIGNMENT 1
 661
 662 #define PCC_BITFIELD_TYPE_MATTERS 1
 663
 664 \f
 665 /* Layout of Source Language Data Types.  */
 666
 667 #define INT_TYPE_SIZE           32
 668 #define SHORT_TYPE_SIZE         16
 669 #define LONG_TYPE_SIZE          32
 670 #define LONG_LONG_TYPE_SIZE     64
 671
 672 #define FLOAT_TYPE_SIZE         32
 673 #define DOUBLE_TYPE_SIZE        64
 674 #define LONG_DOUBLE_TYPE_SIZE   64
 675
 676 #define DEFAULT_SIGNED_CHAR 1
 677
 678 #define SIZE_TYPE "long unsigned int"
 679 #define PTRDIFF_TYPE "long int"
 680 #define WCHAR_TYPE "unsigned int"
 681 #define WCHAR_TYPE_SIZE 32
 682
 683 \f
 684 /* Register Usage.  */
 685
 686 /* Number of actual hardware registers.
 687    The hardware registers are assigned numbers for the compiler
 688    from 0 to just below FIRST_PSEUDO_REGISTER.
 689    All registers that the compiler knows about must be given numbers,
 690    even those that are not normally considered general registers.  */
 691 #define FIRST_PSEUDO_REGISTER 101
 692
 693 /* An initializer that says which registers are used for fixed
 694    purposes all throughout the compiled code and are therefore
 695    not available for general allocation.
 696
 697    $r28 : $fp
 698    $r29 : $gp
 699    $r30 : $lp
 700    $r31 : $sp
 701
 702    caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
 703    callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
 704
 705    reserved for assembler : $r15
 706    reserved for other use : $r24, $r25, $r26, $r27 */
 707 #define FIXED_REGISTERS \
 708 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 709       0,   0,   0,   0,   0,   0,   0,   0,     \
 710   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 711       0,   0,   0,   0,   0,   0,   0,   1,     \
 712   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 713       0,   0,   0,   0,   0,   0,   0,   0,     \
 714   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 715       1,   1,   1,   1,   0,   1,   0,   1,     \
 716   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
 717       1,   1,   1,   1,   1,   1,   1,   1,     \
 718   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
 719       1,   1,   1,   1,   1,   1,   1,   1,     \
 720   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
 721       1,   1,   1,   1,   1,   1,   1,   1,     \
 722   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
 723       1,   1,   1,   1,   1,   1,   1,   1,     \
 724   /* fs30 fs31 fd16      fd17      fd18      */ \
 725       1,   1,   1,   1,   1,   1,   1,   1,     \
 726   /* fd19      fd20      fd21      fd22      */ \
 727       1,   1,   1,   1,   1,   1,   1,   1,     \
 728   /* fd23      fd24      fd25      fd26      */ \
 729       1,   1,   1,   1,   1,   1,   1,   1,     \
 730   /* fd27      fd28      fd29      fd30      */ \
 731       1,   1,   1,   1,   1,   1,   1,   1,     \
 732   /* fd31      Reserved..................... */ \
 733       1,   1,   1,   1,   1                     \
 734 }
 735
 736 /* Identifies the registers that are not available for
 737    general allocation of values that must live across
 738    function calls -- so they are caller-save registers.
 739
 740    0 : callee-save registers
 741    1 : caller-save registers */
 742 #define CALL_USED_REGISTERS \
 743 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 744       1,   1,   1,   1,   1,   1,   0,   0,     \
 745   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 746       0,   0,   0,   0,   0,   0,   0,   1,     \
 747   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 748       1,   1,   1,   1,   1,   1,   1,   1,     \
 749   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 750       1,   1,   1,   1,   0,   1,   0,   1,     \
 751   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
 752       1,   1,   1,   1,   1,   1,   1,   1,     \
 753   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
 754       1,   1,   1,   1,   1,   1,   1,   1,     \
 755   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
 756       1,   1,   1,   1,   1,   1,   1,   1,     \
 757   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
 758       1,   1,   1,   1,   1,   1,   1,   1,     \
 759   /* fs30 fs31 fd16      fd17      fd18      */ \
 760       1,   1,   1,   1,   1,   1,   1,   1,     \
 761   /* fd19      fd20      fd21      fd22      */ \
 762       1,   1,   1,   1,   1,   1,   1,   1,     \
 763   /* fd23      fd24      fd25      fd26      */ \
 764       1,   1,   1,   1,   1,   1,   1,   1,     \
 765   /* fd27      fd28      fd29      fd30      */ \
 766       1,   1,   1,   1,   1,   1,   1,   1,     \
 767   /* fd31      Reserved..................... */ \
 768       1,   1,   1,   1,   1                     \
 769 }
 770
 771 /* In nds32 target, we have three levels of registers:
 772      LOW_COST_REGS    : $r0 ~ $r7
 773      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 774      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 775 #define REG_ALLOC_ORDER \
 776 {   0,   1,   2,   3,   4,   5,   6,   7, \
 777    16,  17,  18,  19,   9,  10,  11,  12, \
 778    13,  14,  8,   15,  20,  21,  22,  23, \
 779    24,  25,  26,  27,  28,  29,  30,  31, \
 780    32,  33,  34,  35,  36,  37,  38,  39, \
 781    40,  41,  42,  43,  44,  45,  46,  47, \
 782    48,  49,  50,  51,  52,  53,  54,  55, \
 783    56,  57,  58,  59,  60,  61,  62,  63, \
 784    64,  65,  66,  67,  68,  69,  70,  71, \
 785    72,  73,  74,  75,  76,  77,  78,  79, \
 786    80,  81,  82,  83,  84,  85,  86,  87, \
 787    88,  89,  90,  91,  92,  93,  94,  95, \
 788    96,  97,  98,  99, 100,                \
 789 }
 790
 791 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
 792    to be rearranged based on optimizing for speed or size.  */
 793 #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
 794
 795 /* Tell IRA to use the order we define rather than messing it up with its
 796    own cost calculations.  */
 797 #define HONOR_REG_ALLOC_ORDER optimize_size
 798
 799 \f
 800 /* Register Classes.  */
 801
 802 /* In nds32 target, we have three levels of registers:
 803      Low cost regsiters    : $r0 ~ $r7
 804      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 805      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 806
 807    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 808    so that it provides more chance to use low cost registers.  */
 809 enum reg_class
 810 {
 811   NO_REGS,
 812   R5_REG,
 813   R8_REG,
 814   R15_TA_REG,
 815   STACK_REG,
 816   FRAME_POINTER_REG,
 817   LOW_REGS,
 818   MIDDLE_REGS,
 819   HIGH_REGS,
 820   GENERAL_REGS,
 821   FRAME_REGS,
 822   FP_REGS,
 823   ALL_REGS,
 824   LIM_REG_CLASSES
 825 };
 826
 827 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 828
 829 #define REG_CLASS_NAMES \
 830 {                       \
 831   "NO_REGS",            \
 832   "R5_REG",             \
 833   "R8_REG",             \
 834   "R15_TA_REG",         \
 835   "STACK_REG",          \
 836   "FRAME_POINTER_REG",  \
 837   "LOW_REGS",           \
 838   "MIDDLE_REGS",        \
 839   "HIGH_REGS",          \
 840   "GENERAL_REGS",       \
 841   "FRAME_REGS",         \
 842   "FP_REGS",            \
 843   "ALL_REGS"            \
 844 }
 845
 846 #define REG_CLASS_CONTENTS \
 847 { /* NO_REGS                                    */  \
 848   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
 849   /* R5_REG              : 5                    */  \
 850   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
 851   /* R8_REG              : 8                    */  \
 852   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
 853   /* R15_TA_REG          : 15                   */  \
 854   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
 855   /* STACK_REG           : 31                   */  \
 856   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
 857   /* FRAME_POINTER_REG   : 28                   */  \
 858   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
 859   /* LOW_REGS            : 0-7                  */  \
 860   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
 861   /* MIDDLE_REGS         : 0-11, 16-19          */  \
 862   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
 863   /* HIGH_REGS           : 12-14, 20-31         */  \
 864   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
 865   /* GENERAL_REGS        : 0-31                 */  \
 866   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
 867   /* FRAME_REGS          : 32, 33               */  \
 868   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
 869   /* FP_REGS             : 34-98                */  \
 870   {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
 871   /* ALL_REGS            : 0-100                */  \
 872   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
 873 }
 874
 875 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 876
 877 #define BASE_REG_CLASS GENERAL_REGS
 878 #define INDEX_REG_CLASS GENERAL_REGS
 879
 880 #define TEST_REGNO(R, TEST, VALUE) \
 881   ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
 882
 883 /* Return nonzero if it is suitable for use as a
 884    base register in operand addresses.
 885    So far, we return nonzero only if "num" is a hard reg
 886    of the suitable class or a pseudo register which is
 887    allocated to a suitable hard reg.  */
 888 #define REGNO_OK_FOR_BASE_P(num) \
 889   (TEST_REGNO (num, <, 32) \
 890    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
 891    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
 892
 893 /* Return nonzero if it is suitable for use as a
 894    index register in operand addresses.
 895    So far, we return nonzero only if "num" is a hard reg
 896    of the suitable class or a pseudo register which is
 897    allocated to a suitable hard reg.
 898    The difference between an index register and a base register is that
 899    the index register may be scaled.  */
 900 #define REGNO_OK_FOR_INDEX_P(num) \
 901   (TEST_REGNO (num, <, 32) \
 902    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
 903    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
 904
 905 \f
 906 /* Obsolete Macros for Defining Constraints.  */
 907
 908 \f
 909 /* Stack Layout and Calling Conventions.  */
 910
 911 #define STACK_GROWS_DOWNWARD 1
 912
 913 #define FRAME_GROWS_DOWNWARD 1
 914
 915 #define STACK_POINTER_OFFSET 0
 916
 917 #define FIRST_PARM_OFFSET(fundecl) \
 918   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 919
 920 /* A C expression whose value is RTL representing the address in a stack frame
 921    where the pointer to the caller's frame is stored.  */
 922 #define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
 923   nds32_dynamic_chain_address (frameaddr)
 924
 925 #define RETURN_ADDR_RTX(count, frameaddr) \
 926   nds32_return_addr_rtx (count, frameaddr)
 927
 928 /* A C expression whose value is RTL representing the location
 929    of the incoming return address at the beginning of any function
 930    before the prologue.
 931    If this RTL is REG, you should also define
 932    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 933 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 934 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 935
 936 /* Use $r0 $r1 to pass exception handling information.  */
 937 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
 938 /* The register $r2 that represents a location in which to store a stack
 939    adjustment to be applied before function return.
 940    This is used to unwind the stack to an exception handler's call frame.  */
 941 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
 942
 943 #define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
 944
 945 #define STACK_POINTER_REGNUM SP_REGNUM
 946
 947 #define FRAME_POINTER_REGNUM 33
 948
 949 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 950
 951 #define ARG_POINTER_REGNUM 32
 952
 953 #define STATIC_CHAIN_REGNUM 16
 954
 955 #define ELIMINABLE_REGS                                \
 956 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 957   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 958   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 959   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 960
 961 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 962   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 963
 964 #define ACCUMULATE_OUTGOING_ARGS 1
 965
 966 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 967
 968 #define CUMULATIVE_ARGS nds32_cumulative_args
 969
 970 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 971   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 972
 973 #define FUNCTION_ARG_REGNO_P(regno)                                           \
 974  (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
 975   || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)                                \
 976       && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM,                       \
 977                    NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
 978
 979 #define DEFAULT_PCC_STRUCT_RETURN 0
 980
 981 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 982    from a function, the stack pointer does not matter.
 983    The value is tested only in functions that have frame pointers.
 984    In nds32 target, the function epilogue recovers the
 985    stack pointer from the frame.  */
 986 #define EXIT_IGNORE_STACK 1
 987
 988 #define FUNCTION_PROFILER(file, labelno) \
 989   fprintf (file, "/* profiler %d */\n", (labelno))
 990
 991 #define PROFILE_HOOK(LABEL)                                             \
 992   {                                                                     \
 993     rtx fun, lp;                                                        \
 994     lp = get_hard_reg_initial_val (Pmode, LP_REGNUM);                   \
 995     fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount");                        \
 996     emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode);           \
 997   }
 998
 999 \f
1000 /* Implementing the Varargs Macros.  */
1001
1002 \f
1003 /* Trampolines for Nested Functions.  */
1004
1005 /* Giving A-function and B-function,
1006    if B-function wants to call A-function's nested function,
1007    we need to fill trampoline code into A-function's stack
1008    so that B-function can execute the code in stack to indirectly
1009    jump to (like 'trampoline' action) desired nested function.
1010
1011    The trampoline code for nds32 target must contains following parts:
1012
1013      1. instructions (4 * 4 = 16 bytes):
1014           get $pc first
1015           load chain_value to static chain register via $pc
1016           load nested function address to $r15 via $pc
1017           jump to desired nested function via $r15
1018      2. data (4 * 2 = 8 bytes):
1019           chain_value
1020           nested function address
1021
1022    Please check nds32.c implementation for more information.  */
1023 #define TRAMPOLINE_SIZE 24
1024
1025 /* Because all instructions/data in trampoline template are 4-byte size,
1026    we set trampoline alignment 8*4=32 bits.  */
1027 #define TRAMPOLINE_ALIGNMENT 32
1028
1029 \f
1030 /* Implicit Calls to Library Routines.  */
1031
1032 \f
1033 /* Addressing Modes.  */
1034
1035 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
1036 #define HAVE_POST_INCREMENT 1
1037 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
1038 #define HAVE_POST_DECREMENT 1
1039
1040 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
1041 #define HAVE_POST_MODIFY_DISP 1
1042 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
1043 #define HAVE_POST_MODIFY_REG  1
1044
1045 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1046
1047 #define MAX_REGS_PER_ADDRESS 3
1048
1049 \f
1050 /* Anchored Addresses.  */
1051
1052 \f
1053 /* Condition Code Status.  */
1054
1055 \f
1056 /* Describing Relative Costs of Operations.  */
1057
1058 /* A C expression for the cost of a branch instruction.
1059    A value of 1 is the default;
1060    other values are interpreted relative to that.  */
1061 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
1062
1063 /* Override BRANCH_COST heuristic which empirically produces worse
1064    performance for removing short circuiting from the logical ops.  */
1065 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1066
1067 #define SLOW_BYTE_ACCESS 1
1068
1069 #define NO_FUNCTION_CSE 1
1070
1071 \f
1072 /* Adjusting the Instruction Scheduler.  */
1073
1074 \f
1075 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
1076
1077 #define TEXT_SECTION_ASM_OP     "\t.text"
1078 #define DATA_SECTION_ASM_OP     "\t.data"
1079
1080 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1081    So we use '.section .bss' alternatively.  */
1082 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
1083
1084 /* Define this macro to be an expression with a nonzero value if jump tables
1085    (for tablejump insns) should be output in the text section,
1086    along with the assembler instructions.
1087    Otherwise, the readonly data section is used.  */
1088 #define JUMP_TABLES_IN_TEXT_SECTION 1
1089
1090 \f
1091 /* Position Independent Code.  */
1092
1093 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1094
1095 \f
1096 /* Defining the Output Assembler Language.  */
1097
1098 #define ASM_COMMENT_START "!"
1099
1100 #define ASM_APP_ON "! #APP"
1101
1102 #define ASM_APP_OFF "! #NO_APP\n"
1103
1104 #define ASM_OUTPUT_LABELREF(stream, name) \
1105   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1106
1107 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1108   assemble_name (stream, XSTR (sym, 0))
1109
1110 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
1111   assemble_name (stream, buf)
1112
1113 #define LOCAL_LABEL_PREFIX "."
1114
1115 #define REGISTER_NAMES \
1116 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
1117   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
1118   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1119   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
1120   "$AP",  "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1121   "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1122   "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1123   "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1124   "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1125   "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1126   "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1127   "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1128   "$fs62","$fs63",   "LB",   "LE",   "LC"                         \
1129 }
1130
1131 #define ADDITIONAL_REGISTER_NAMES                               \
1132 {                                                               \
1133   {"$r15", 15},                                                 \
1134   {"$r28", 28}, {"$r29", 29},   {"$r30", 30},   {"$r31", 31},   \
1135   {"$a0", 0},   {"$a1", 1},     {"$a2", 2},                     \
1136   {"$a3", 3},   {"$a4", 4},     {"$a5", 5},                     \
1137   {"$s0", 6},   {"$s1", 7},     {"$s2", 8},     {"$s3", 9},     \
1138   {"$s4", 10},  {"$s5", 11},    {"$s6", 12},    {"$s7", 13},    \
1139   {"$s8", 14},                                                  \
1140   {"$t0", 16},  {"$t1", 17},    {"$t2", 18},    {"$t3", 19},    \
1141   {"$t4", 20},  {"$t5", 21},    {"$t6", 22},    {"$t7", 23},    \
1142   {"$t8", 24},  {"$t9", 25},                                    \
1143   {"$p0", 26},  {"$p1", 27},                                    \
1144   {"$h0", 0},   {"$h1", 1},     {"$h2", 2},     {"$h3", 3},     \
1145   {"$h4", 4},   {"$h5", 5},     {"$h6", 6},     {"$h7", 7},     \
1146   {"$h8", 8},   {"$h9", 9},     {"$h10", 10},   {"$h11", 11},   \
1147   {"$h12", 16}, {"$h13", 17},   {"$h14", 18},   {"$h15", 19},   \
1148   {"$o0", 0},   {"$o1", 1},     {"$o2", 2},     {"$o3", 3},     \
1149   {"$o4", 4},   {"$o5", 5},     {"$o6", 6},     {"$o7", 7},     \
1150 }
1151
1152 #define OVERLAPPING_REGISTER_NAMES              \
1153 {                                               \
1154   {"$fd0",  NDS32_FIRST_FPR_REGNUM + 0,  2},    \
1155   {"$fd1",  NDS32_FIRST_FPR_REGNUM + 2,  2},    \
1156   {"$fd2",  NDS32_FIRST_FPR_REGNUM + 4,  2},    \
1157   {"$fd3",  NDS32_FIRST_FPR_REGNUM + 6,  2},    \
1158   {"$fd4",  NDS32_FIRST_FPR_REGNUM + 8,  2},    \
1159   {"$fd5",  NDS32_FIRST_FPR_REGNUM + 10, 2},    \
1160   {"$fd6",  NDS32_FIRST_FPR_REGNUM + 12, 2},    \
1161   {"$fd7",  NDS32_FIRST_FPR_REGNUM + 14, 2},    \
1162   {"$fd8",  NDS32_FIRST_FPR_REGNUM + 16, 2},    \
1163   {"$fd9",  NDS32_FIRST_FPR_REGNUM + 18, 2},    \
1164   {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2},    \
1165   {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2},    \
1166   {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2},    \
1167   {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2},    \
1168   {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2},    \
1169   {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2},    \
1170   {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2},    \
1171   {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2},    \
1172   {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2},    \
1173   {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2},    \
1174   {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2},    \
1175   {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2},    \
1176   {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2},    \
1177   {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2},    \
1178   {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2},    \
1179   {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2},    \
1180   {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2},    \
1181   {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2},    \
1182   {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2},    \
1183   {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2},    \
1184   {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2},    \
1185   {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2},    \
1186 }
1187
1188 /* Output normal jump table entry.  */
1189 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1190   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1191
1192 /* Output pc relative jump table entry.  */
1193 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
1194   do                                                                    \
1195     {                                                                   \
1196       switch (GET_MODE (body))                                          \
1197         {                                                               \
1198         case E_QImode:                                                    \
1199           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
1200           break;                                                        \
1201         case E_HImode:                                                    \
1202           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
1203           break;                                                        \
1204         case E_SImode:                                                    \
1205           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
1206           break;                                                        \
1207         default:                                                        \
1208           gcc_unreachable();                                            \
1209         }                                                               \
1210     } while (0)
1211
1212 /* We have to undef it first because elfos.h formerly define it
1213    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
1214 #undef  ASM_OUTPUT_CASE_LABEL
1215 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
1216   do                                                               \
1217     {                                                              \
1218       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
1219       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
1220     } while (0)
1221
1222 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
1223   do                                                   \
1224     {                                                  \
1225       /* Because our jump table is in text section,    \
1226          we need to make sure 2-byte alignment after   \
1227          the jump table for instructions fetch.  */    \
1228       if (GET_MODE (PATTERN (table)) == QImode)        \
1229         ASM_OUTPUT_ALIGN (stream, 1);                  \
1230       asm_fprintf (stream, "\t! Jump Table End\n");    \
1231     }  while (0)
1232
1233 /* This macro is not documented yet.
1234    But we do need it to make jump table vector aligned.  */
1235 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
1236
1237 #define DWARF2_UNWIND_INFO 1
1238
1239 #define JUMP_ALIGN(x) \
1240   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1241
1242 #define LOOP_ALIGN(x) \
1243   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1244
1245 #define LABEL_ALIGN(x) \
1246   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1247
1248 #define ASM_OUTPUT_ALIGN(stream, power) \
1249   fprintf (stream, "\t.align\t%d\n", power)
1250
1251 \f
1252 /* Controlling Debugging Information Format.  */
1253
1254 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1255
1256 #define DWARF2_DEBUGGING_INFO 1
1257
1258 #define DWARF2_ASM_LINE_DEBUG_INFO 1
1259
1260 \f
1261 /* Cross Compilation and Floating Point.  */
1262
1263 \f
1264 /* Mode Switching Instructions.  */
1265
1266 \f
1267 /* Defining target-specific uses of __attribute__.  */
1268
1269 \f
1270 /* Emulating TLS.  */
1271
1272 \f
1273 /* Defining coprocessor specifics for MIPS targets.  */
1274
1275 \f
1276 /* Parameters for Precompiled Header Validity Checking.  */
1277
1278 \f
1279 /* C++ ABI parameters.  */
1280
1281 \f
1282 /* Adding support for named address spaces.  */
1283
1284 \f
1285 /* Miscellaneous Parameters.  */
1286
1287 /* This is the machine mode that elements of a jump-table should have.  */
1288 #define CASE_VECTOR_MODE Pmode
1289
1290 /* Return the preferred mode for and addr_diff_vec when the mininum
1291    and maximum offset are known.  */
1292 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1293    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
1294    : (max_offset >= 100) ? HImode                               \
1295    : QImode)
1296
1297 /* Generate pc relative jump table when -fpic or -Os.  */
1298 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1299
1300 /* Define this macro if operations between registers with integral mode
1301    smaller than a word are always performed on the entire register.  */
1302 #define WORD_REGISTER_OPERATIONS 1
1303
1304 /* A C expression indicating when insns that read memory in mem_mode,
1305    an integral mode narrower than a word, set the bits outside of mem_mode
1306    to be either the sign-extension or the zero-extension of the data read.  */
1307 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1308
1309 /* The maximum number of bytes that a single instruction can move quickly
1310    between memory and registers or between two memory locations.  */
1311 #define MOVE_MAX 4
1312
1313 /* A C expression that is nonzero if on this machine the number of bits
1314    actually used for the count of a shift operation is equal to the number
1315    of bits needed to represent the size of the object being shifted.  */
1316 #define SHIFT_COUNT_TRUNCATED 1
1317
1318 /* A C expression describing the value returned by a comparison operator with
1319    an integral mode and stored by a store-flag instruction ('cstoremode4')
1320    when the condition is true.  */
1321 #define STORE_FLAG_VALUE 1
1322
1323 /* A C expression that indicates whether the architecture defines a value for
1324    clz or ctz with a zero operand.  In nds32 clz for 0 result 32 is defined
1325    in ISA spec */
1326 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
1327
1328 /* An alias for the machine mode for pointers.  */
1329 #define Pmode SImode
1330
1331 /* An alias for the machine mode used for memory references to functions
1332    being called, in call RTL expressions.  */
1333 #define FUNCTION_MODE SImode
1334
1335 /* ------------------------------------------------------------------------ */