1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2014 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* ------------------------------------------------------------------------ */
24 /* The following are auxiliary macros or structure declarations
25 that are used all over the nds32.c and nds32.h. */
28 /* Computing the Length of an Insn. */
29 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
30 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
32 /* Check instruction LS-37-FP-implied form.
33 Note: actually its immediate range is imm9u
34 since it is used for lwi37/swi37 instructions. */
35 #define NDS32_LS_37_FP_P(rt, ra, imm) \
36 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
37 && REGNO (ra) == FP_REGNUM \
38 && satisfies_constraint_Iu09 (imm))
40 /* Check instruction LS-37-SP-implied form.
41 Note: actually its immediate range is imm9u
42 since it is used for lwi37/swi37 instructions. */
43 #define NDS32_LS_37_SP_P(rt, ra, imm) \
44 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
45 && REGNO (ra) == SP_REGNUM \
46 && satisfies_constraint_Iu09 (imm))
49 /* Check load/store instruction form : Rt3, Ra3, imm3u. */
50 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
52 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
53 Note: no need to check ra because Ra5 means it covers all registers. */
54 #define NDS32_LS_450_P(rt, ra, imm) \
55 ((imm == const0_rtx) \
56 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
57 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
59 /* Check instruction RRI-333-form. */
60 #define NDS32_RRI_333_P(rt, ra, imm) \
61 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
62 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
63 && satisfies_constraint_Iu03 (imm))
65 /* Check instruction RI-45-form. */
66 #define NDS32_RI_45_P(rt, ra, imm) \
67 (REGNO (rt) == REGNO (ra) \
68 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
69 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
70 && satisfies_constraint_Iu05 (imm))
73 /* Check instruction RR-33-form. */
74 #define NDS32_RR_33_P(rt, ra) \
75 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
76 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
78 /* Check instruction RRR-333-form. */
79 #define NDS32_RRR_333_P(rt, ra, rb) \
80 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
81 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
82 && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
84 /* Check instruction RR-45-form.
85 Note: no need to check rb because Rb5 means it covers all registers. */
86 #define NDS32_RR_45_P(rt, ra, rb) \
87 (REGNO (rt) == REGNO (ra) \
88 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
89 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
91 /* Classifies address type to distinguish 16-bit/32-bit format. */
92 enum nds32_16bit_address_type
94 /* [reg]: 45 format address. */
96 /* [lo_reg + imm3u]: 333 format address. */
98 /* post_inc [lo_reg + imm3u]: 333 format address. */
99 ADDRESS_POST_INC_LO_REG_IMM3U
,
100 /* [$fp + imm7u]: fp imply address. */
102 /* [$sp + imm7u]: sp imply address. */
104 /* Other address format. */
105 ADDRESS_NOT_16BIT_FORMAT
109 /* ------------------------------------------------------------------------ */
111 /* Define maximum numbers of registers for passing arguments. */
112 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
114 /* Define the register number for first argument. */
115 #define NDS32_GPR_ARG_FIRST_REGNUM 0
117 /* Define the register number for return value. */
118 #define NDS32_GPR_RET_FIRST_REGNUM 0
120 /* Define the first integer register number. */
121 #define NDS32_FIRST_GPR_REGNUM 0
122 /* Define the last integer register number. */
123 #define NDS32_LAST_GPR_REGNUM 31
125 /* Define double word alignment bits. */
126 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
128 /* Define alignment checking macros for convenience. */
129 #define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
130 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
131 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
133 /* Get alignment according to mode or type information.
134 When 'type' is nonnull, there is no need to look at 'mode'. */
135 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
136 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
138 /* Round X up to the nearest double word. */
139 #define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
142 /* This macro is used to calculate the numbers of registers for
143 containing 'size' bytes of the argument.
144 The size of a register is a word in nds32 target.
145 So we use UNITS_PER_WORD to do the calculation. */
146 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
148 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
149 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
151 /* This macro is used to return the register number for passing argument.
152 We need to obey the following rules:
153 1. If it is required MORE THAN one register,
154 we need to further check if it really needs to be
155 aligned on double words.
156 a) If double word alignment is necessary,
157 the register number must be even value.
158 b) Otherwise, the register number can be odd or even value.
159 2. If it is required ONLY one register,
160 the register number can be odd or even value. */
161 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
162 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
163 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
164 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
165 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
166 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
168 /* This macro is to check if there are still available registers
169 for passing argument. */
170 #define NDS32_ARG_PASS_IN_REG_P(reg_offset, mode, type) \
171 (((reg_offset) < NDS32_MAX_GPR_REGS_FOR_ARGS) \
172 && ((reg_offset) + NDS32_NEED_N_REGS_FOR_ARG (mode, type) \
173 <= NDS32_MAX_GPR_REGS_FOR_ARGS))
175 /* This macro is to check if the register is required to be saved on stack.
176 If call_used_regs[regno] == 0, regno is the callee-saved register.
177 If df_regs_ever_live_p(regno) == true, it is used in the current function.
178 As long as the register satisfies both criteria above,
179 it is required to be saved. */
180 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
181 ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
183 /* ------------------------------------------------------------------------ */
185 /* A C structure for machine-specific, per-function data.
186 This is added to the cfun structure. */
187 struct GTY(()) machine_function
189 /* Number of bytes allocated on the stack for variadic args
190 if we want to push them into stack as pretend arguments by ourself. */
192 /* Number of bytes reserved on the stack for
193 local and temporary variables. */
195 /* Number of bytes allocated on the stack for outgoing arguments. */
198 /* Number of bytes on the stack for saving $fp. */
200 /* Number of bytes on the stack for saving $gp. */
202 /* Number of bytes on the stack for saving $lp. */
205 /* Number of bytes on the stack for saving callee-saved registers. */
206 int callee_saved_regs_size
;
207 /* The padding bytes in callee-saved area may be required. */
208 int callee_saved_area_padding_bytes
;
210 /* The first required callee-saved register. */
211 int callee_saved_regs_first_regno
;
212 /* The last required callee-saved register. */
213 int callee_saved_regs_last_regno
;
215 /* The padding bytes in varargs area may be required. */
216 int va_args_area_padding_bytes
;
218 /* The first required register that should be saved on stack for va_args. */
219 int va_args_first_regno
;
220 /* The last required register that should be saved on stack for va_args. */
221 int va_args_last_regno
;
223 /* Indicate that whether this function needs
224 prologue/epilogue code generation. */
226 /* Indicate that whether this function
227 uses fp_as_gp optimization. */
231 /* A C structure that contains the arguments information. */
234 unsigned int gpr_offset
;
235 } nds32_cumulative_args
;
237 /* ------------------------------------------------------------------------ */
239 /* The following we define C-ISR related stuff.
240 In nds32 architecture, we have 73 vectors for interrupt/exception.
241 For each vector (except for vector 0, which is used for reset behavior),
242 we allow users to set its register saving scheme and interrupt level. */
244 /* There are 73 vectors in nds32 architecture.
246 1-8 for exception handler,
247 and 9-72 for interrupt handler.
248 We use an array, which is defined in nds32.c, to record
249 essential information for each vector. */
250 #define NDS32_N_ISR_VECTORS 73
252 /* Define possible isr category. */
253 enum nds32_isr_category
261 /* Define isr register saving scheme. */
262 enum nds32_isr_save_reg
268 /* Define isr nested type. */
269 enum nds32_isr_nested_type
276 /* Define structure to record isr information.
277 The isr vector array 'isr_vectors[]' with this structure
278 is defined in nds32.c. */
279 struct nds32_isr_info
281 /* The field to identify isr category.
282 It should be set to NDS32_ISR_NONE by default.
283 If user specifies a function as isr by using attribute,
284 this field will be set accordingly. */
285 enum nds32_isr_category category
;
287 /* A string for the applied function name.
288 It should be set to empty string by default. */
291 /* The register saving scheme.
292 It should be set to NDS32_PARTIAL_SAVE by default
293 unless user specifies attribute to change it. */
294 enum nds32_isr_save_reg save_reg
;
297 It should be set to NDS32_NOT_NESTED by default
298 unless user specifies attribute to change it. */
299 enum nds32_isr_nested_type nested_type
;
302 The total vectors = interrupt + exception numbers + reset.
303 It should be set to 0 by default.
304 This field is ONLY used in NDS32_ISR_RESET category. */
305 unsigned int total_n_vectors
;
307 /* A string for nmi handler name.
308 It should be set to empty string by default.
309 This field is ONLY used in NDS32_ISR_RESET category. */
312 /* A string for warm handler name.
313 It should be set to empty string by default.
314 This field is ONLY used in NDS32_ISR_RESET category. */
318 /* ------------------------------------------------------------------------ */
320 /* Define code for all nds32 builtins. */
329 NDS32_BUILTIN_SETGIE_EN
,
330 NDS32_BUILTIN_SETGIE_DIS
333 /* ------------------------------------------------------------------------ */
335 #define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
336 #define TARGET_ISA_V3 (nds32_arch_option == ARCH_V3)
337 #define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
339 #define TARGET_SOFT_FLOAT 1
340 #define TARGET_HARD_FLOAT 0
342 /* ------------------------------------------------------------------------ */
344 /* Controlling the Compilation Driver. */
346 #define OPTION_DEFAULT_SPECS \
347 {"arch", "%{!march=*:-march=%(VALUE)}" }
353 " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
355 /* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
356 we need to pass '--relax' to linker.
357 Besides, for -mex9, we need to further pass '--mex9'. */
359 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
360 " %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
366 /* The option -mno-ctor-dtor can disable constructor/destructor feature
367 by applying different crt stuff. In the convention, crt0.o is the
368 startup file without constructor/destructor;
369 crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
370 startup files with constructor/destructor.
371 Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
372 by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
373 currently provided by GCC for nds32 target.
375 For nds32 target so far:
376 If -mno-ctor-dtor, we are going to link
377 "crt0.o [user objects]".
378 If general cases, we are going to link
379 "crt1.o crtbegin1.o [user objects] crtend1.o". */
380 #define STARTFILE_SPEC \
381 " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
382 " %{!mno-ctor-dtor:crtbegin1.o%s}"
383 #define ENDFILE_SPEC \
384 " %{!mno-ctor-dtor:crtend1.o%s}"
386 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we configure gcc
387 with --target=nds32be-* setting.
388 Check gcc/config.gcc for more information.
389 In addition, currently we only have elf toolchain,
390 where mgp-direct is always the default. */
391 #ifdef TARGET_BIG_ENDIAN_DEFAULT
392 #define MULTILIB_DEFAULTS { "mbig-endian", "mgp-direct" }
394 #define MULTILIB_DEFAULTS { "mlittle-endian", "mgp-direct" }
398 /* Run-time Target Specification. */
400 #define TARGET_CPU_CPP_BUILTINS() \
403 builtin_define ("__nds32__"); \
406 builtin_define ("__NDS32_ISA_V2__"); \
408 builtin_define ("__NDS32_ISA_V3__"); \
409 if (TARGET_ISA_V3M) \
410 builtin_define ("__NDS32_ISA_V3M__"); \
412 if (TARGET_BIG_ENDIAN) \
413 builtin_define ("__big_endian__"); \
414 if (TARGET_REDUCED_REGS) \
415 builtin_define ("__NDS32_REDUCED_REGS__"); \
417 builtin_define ("__NDS32_CMOV__"); \
418 if (TARGET_PERF_EXT) \
419 builtin_define ("__NDS32_PERF_EXT__"); \
421 builtin_define ("__NDS32_16_BIT__"); \
422 if (TARGET_GP_DIRECT) \
423 builtin_define ("__NDS32_GP_DIRECT__"); \
425 builtin_assert ("cpu=nds32"); \
426 builtin_assert ("machine=nds32"); \
430 /* Defining Data Structures for Per-function Information. */
432 /* This macro is called once per function,
433 before generation of any RTL has begun. */
434 #define INIT_EXPANDERS nds32_init_expanders ()
437 /* Storage Layout. */
439 #define BITS_BIG_ENDIAN 0
441 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
443 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
445 #define UNITS_PER_WORD 4
447 #define PROMOTE_MODE(m, unsignedp, type) \
448 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
453 #define PARM_BOUNDARY 32
455 #define STACK_BOUNDARY 64
457 #define FUNCTION_BOUNDARY 32
459 #define BIGGEST_ALIGNMENT 64
461 #define EMPTY_FIELD_BOUNDARY 32
463 #define STRUCTURE_SIZE_BOUNDARY 8
465 #define STRICT_ALIGNMENT 1
467 #define PCC_BITFIELD_TYPE_MATTERS 1
470 /* Layout of Source Language Data Types. */
472 #define INT_TYPE_SIZE 32
473 #define SHORT_TYPE_SIZE 16
474 #define LONG_TYPE_SIZE 32
475 #define LONG_LONG_TYPE_SIZE 64
477 #define FLOAT_TYPE_SIZE 32
478 #define DOUBLE_TYPE_SIZE 64
479 #define LONG_DOUBLE_TYPE_SIZE 64
481 #define DEFAULT_SIGNED_CHAR 1
483 #define SIZE_TYPE "long unsigned int"
484 #define PTRDIFF_TYPE "long int"
485 #define WCHAR_TYPE "short unsigned int"
486 #define WCHAR_TYPE_SIZE 16
489 /* Register Usage. */
491 /* Number of actual hardware registers.
492 The hardware registers are assigned numbers for the compiler
493 from 0 to just below FIRST_PSEUDO_REGISTER.
494 All registers that the compiler knows about must be given numbers,
495 even those that are not normally considered general registers. */
496 #define FIRST_PSEUDO_REGISTER 34
498 /* An initializer that says which registers are used for fixed
499 purposes all throughout the compiled code and are therefore
500 not available for general allocation.
507 caller-save registers: $r0 ~ $r5, $r16 ~ $r23
508 callee-save registers: $r6 ~ $r10, $r11 ~ $r14
510 reserved for assembler : $r15
511 reserved for other use : $r24, $r25, $r26, $r27 */
512 #define FIXED_REGISTERS \
513 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
514 0, 0, 0, 0, 0, 0, 0, 0, \
515 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
516 0, 0, 0, 0, 0, 0, 0, 1, \
517 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
518 0, 0, 0, 0, 0, 0, 0, 0, \
519 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
520 1, 1, 1, 1, 0, 1, 0, 1, \
521 /* ARG_POINTER:32 */ \
523 /* FRAME_POINTER:33 */ \
527 /* Identifies the registers that are not available for
528 general allocation of values that must live across
529 function calls -- so they are caller-save registers.
531 0 : callee-save registers
532 1 : caller-save registers */
533 #define CALL_USED_REGISTERS \
534 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
535 1, 1, 1, 1, 1, 1, 0, 0, \
536 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
537 0, 0, 0, 0, 0, 0, 0, 1, \
538 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
539 1, 1, 1, 1, 1, 1, 1, 1, \
540 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
541 1, 1, 1, 1, 0, 1, 0, 1, \
542 /* ARG_POINTER:32 */ \
544 /* FRAME_POINTER:33 */ \
548 /* In nds32 target, we have three levels of registers:
549 LOW_COST_REGS : $r0 ~ $r7
550 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
551 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
552 #define REG_ALLOC_ORDER \
554 0, 1, 2, 3, 4, 5, 6, 7, \
555 8, 9, 10, 11, 16, 17, 18, 19, \
556 12, 13, 14, 15, 20, 21, 22, 23, \
557 24, 25, 26, 27, 28, 29, 30, 31, \
562 /* Tell IRA to use the order we define rather than messing it up with its
563 own cost calculations. */
564 #define HONOR_REG_ALLOC_ORDER optimize_size
566 /* The number of consecutive hard regs needed starting at
567 reg "regno" for holding a value of mode "mode". */
568 #define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
570 /* Value is 1 if hard register "regno" can hold a value
571 of machine-mode "mode". */
572 #define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
574 /* A C expression that is nonzero if a value of mode1
575 is accessible in mode2 without copying.
576 Define this macro to return nonzero in as many cases as possible
577 since doing so will allow GCC to perform better register allocation.
578 We can use general registers to tie QI/HI/SI modes together. */
579 #define MODES_TIEABLE_P(mode1, mode2) \
580 (GET_MODE_CLASS (mode1) == MODE_INT \
581 && GET_MODE_CLASS (mode2) == MODE_INT \
582 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD \
583 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
586 /* Register Classes. */
588 /* In nds32 target, we have three levels of registers:
589 Low cost regsiters : $r0 ~ $r7
590 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
591 High cost registers : $r12 ~ $r14, $r20 ~ $r31
593 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
594 so that it provides more chance to use low cost registers. */
609 #define N_REG_CLASSES (int) LIM_REG_CLASSES
611 #define REG_CLASS_NAMES \
624 #define REG_CLASS_CONTENTS \
626 {0x00000000, 0x00000000}, /* NO_REGS : */ \
627 {0x00008000, 0x00000000}, /* R15_TA_REG : 15 */ \
628 {0x80000000, 0x00000000}, /* STACK_REG : 31 */ \
629 {0x000000ff, 0x00000000}, /* LOW_REGS : 0-7 */ \
630 {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19 */ \
631 {0xfff07000, 0x00000000}, /* HIGH_REGS : 12-14, 20-31 */ \
632 {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31 */ \
633 {0x00000000, 0x00000003}, /* FRAME_REGS : 32, 33 */ \
634 {0xffffffff, 0x00000003} /* ALL_REGS : 0-31, 32, 33 */ \
637 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
639 #define BASE_REG_CLASS GENERAL_REGS
640 #define INDEX_REG_CLASS GENERAL_REGS
642 /* Return nonzero if it is suitable for use as a
643 base register in operand addresses.
644 So far, we return nonzero only if "num" is a hard reg
645 of the suitable class or a pseudo register which is
646 allocated to a suitable hard reg. */
647 #define REGNO_OK_FOR_BASE_P(num) \
648 ((num) < 32 || (unsigned) reg_renumber[num] < 32)
650 /* Return nonzero if it is suitable for use as a
651 index register in operand addresses.
652 So far, we return nonzero only if "num" is a hard reg
653 of the suitable class or a pseudo register which is
654 allocated to a suitable hard reg.
655 The difference between an index register and a base register is that
656 the index register may be scaled. */
657 #define REGNO_OK_FOR_INDEX_P(num) \
658 ((num) < 32 || (unsigned) reg_renumber[num] < 32)
661 /* Obsolete Macros for Defining Constraints. */
664 /* Stack Layout and Calling Conventions. */
666 #define STACK_GROWS_DOWNWARD
668 #define FRAME_GROWS_DOWNWARD 1
670 #define STARTING_FRAME_OFFSET 0
672 #define STACK_POINTER_OFFSET 0
674 #define FIRST_PARM_OFFSET(fundecl) \
675 (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
677 #define RETURN_ADDR_RTX(count, frameaddr) \
678 nds32_return_addr_rtx (count, frameaddr)
680 /* A C expression whose value is RTL representing the location
681 of the incoming return address at the beginning of any function
683 If this RTL is REG, you should also define
684 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
685 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
686 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
688 #define STACK_POINTER_REGNUM SP_REGNUM
690 #define FRAME_POINTER_REGNUM 33
692 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
694 #define ARG_POINTER_REGNUM 32
696 #define STATIC_CHAIN_REGNUM 16
698 #define ELIMINABLE_REGS \
699 { { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
700 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
701 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
702 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
704 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
705 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
707 #define ACCUMULATE_OUTGOING_ARGS 1
709 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
711 #define CUMULATIVE_ARGS nds32_cumulative_args
713 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
714 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
716 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
717 We better cast REGNO into signed integer so that we can avoid
718 'comparison of unsigned expression >= 0 is always true' warning. */
719 #define FUNCTION_ARG_REGNO_P(regno) \
720 (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0) \
721 && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
723 #define DEFAULT_PCC_STRUCT_RETURN 0
725 /* EXIT_IGNORE_STACK should be nonzero if, when returning
726 from a function, the stack pointer does not matter.
727 The value is tested only in functions that have frame pointers.
728 In nds32 target, the function epilogue recovers the
729 stack pointer from the frame. */
730 #define EXIT_IGNORE_STACK 1
732 #define FUNCTION_PROFILER(file, labelno) \
733 fprintf (file, "/* profiler %d */", (labelno))
736 /* Implementing the Varargs Macros. */
739 /* Trampolines for Nested Functions. */
741 /* Giving A-function and B-function,
742 if B-function wants to call A-function's nested function,
743 we need to fill trampoline code into A-function's stack
744 so that B-function can execute the code in stack to indirectly
745 jump to (like 'trampoline' action) desired nested function.
747 The trampoline code for nds32 target must contains following parts:
749 1. instructions (4 * 4 = 16 bytes):
751 load chain_value to static chain register via $pc
752 load nested function address to $r15 via $pc
753 jump to desired nested function via $r15
754 2. data (4 * 2 = 8 bytes):
756 nested function address
758 Please check nds32.c implementation for more information. */
759 #define TRAMPOLINE_SIZE 24
761 /* Because all instructions/data in trampoline template are 4-byte size,
762 we set trampoline alignment 8*4=32 bits. */
763 #define TRAMPOLINE_ALIGNMENT 32
766 /* Implicit Calls to Library Routines. */
769 /* Addressing Modes. */
771 /* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
772 #define HAVE_POST_INCREMENT 1
773 /* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
774 #define HAVE_POST_DECREMENT 1
776 /* We have "LWI.bi Rt, [Ra], imm" instruction form. */
777 #define HAVE_POST_MODIFY_DISP 1
778 /* We have "LW.bi Rt, [Ra], Rb" instruction form. */
779 #define HAVE_POST_MODIFY_REG 1
781 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
783 #define MAX_REGS_PER_ADDRESS 2
786 /* Anchored Addresses. */
789 /* Condition Code Status. */
792 /* Describing Relative Costs of Operations. */
794 /* A C expression for the cost of a branch instruction.
795 A value of 1 is the default;
796 other values are interpreted relative to that. */
797 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
799 #define SLOW_BYTE_ACCESS 1
801 #define NO_FUNCTION_CSE
804 /* Adjusting the Instruction Scheduler. */
807 /* Dividing the Output into Sections (Texts, Data, . . . ). */
809 #define TEXT_SECTION_ASM_OP "\t.text"
810 #define DATA_SECTION_ASM_OP "\t.data"
812 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
813 So we use '.section .bss' alternatively. */
814 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
816 /* Define this macro to be an expression with a nonzero value if jump tables
817 (for tablejump insns) should be output in the text section,
818 along with the assembler instructions.
819 Otherwise, the readonly data section is used. */
820 #define JUMP_TABLES_IN_TEXT_SECTION 1
823 /* Position Independent Code. */
825 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
828 /* Defining the Output Assembler Language. */
830 #define ASM_COMMENT_START "!"
832 #define ASM_APP_ON "! #APP"
834 #define ASM_APP_OFF "! #NO_APP\n"
836 #define ASM_OUTPUT_LABELREF(stream, name) \
837 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
839 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
840 assemble_name (stream, XSTR (sym, 0))
842 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
843 assemble_name (stream, buf)
845 #define LOCAL_LABEL_PREFIX "."
847 #define REGISTER_NAMES \
849 "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
850 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
851 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
852 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
857 /* Output normal jump table entry. */
858 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
859 asm_fprintf (stream, "\t.word\t%LL%d\n", value)
861 /* Output pc relative jump table entry. */
862 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
865 switch (GET_MODE (body)) \
868 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
871 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
874 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
881 /* We have to undef it first because elfos.h formerly define it
882 check gcc/config.gcc and gcc/config/elfos.h for more information. */
883 #undef ASM_OUTPUT_CASE_LABEL
884 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
887 asm_fprintf (stream, "\t! Jump Table Begin\n"); \
888 (*targetm.asm_out.internal_label) (stream, prefix, num); \
891 #define ASM_OUTPUT_CASE_END(stream, num, table) \
894 /* Because our jump table is in text section, \
895 we need to make sure 2-byte alignment after \
896 the jump table for instructions fetch. */ \
897 if (GET_MODE (PATTERN (table)) == QImode) \
898 ASM_OUTPUT_ALIGN (stream, 1); \
899 asm_fprintf (stream, "\t! Jump Table End\n"); \
902 /* This macro is not documented yet.
903 But we do need it to make jump table vector aligned. */
904 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
906 #define DWARF2_UNWIND_INFO 1
908 #define JUMP_ALIGN(x) \
909 (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
911 #define LOOP_ALIGN(x) \
912 (align_loops_log ? align_loops_log : nds32_target_alignment (x))
914 #define LABEL_ALIGN(x) \
915 (align_labels_log ? align_labels_log : nds32_target_alignment (x))
917 #define ASM_OUTPUT_ALIGN(stream, power) \
918 fprintf (stream, "\t.align\t%d\n", power)
921 /* Controlling Debugging Information Format. */
923 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
925 #define DWARF2_DEBUGGING_INFO 1
927 #define DWARF2_ASM_LINE_DEBUG_INFO 1
930 /* Cross Compilation and Floating Point. */
933 /* Mode Switching Instructions. */
936 /* Defining target-specific uses of __attribute__. */
942 /* Defining coprocessor specifics for MIPS targets. */
945 /* Parameters for Precompiled Header Validity Checking. */
948 /* C++ ABI parameters. */
951 /* Adding support for named address spaces. */
954 /* Miscellaneous Parameters. */
956 /* This is the machine mode that elements of a jump-table should have. */
957 #define CASE_VECTOR_MODE Pmode
959 /* Return the preferred mode for and addr_diff_vec when the mininum
960 and maximum offset are known. */
961 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
962 ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
963 : (max_offset >= 100) ? HImode \
966 /* Generate pc relative jump table when -fpic or -Os. */
967 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
969 /* Define this macro if operations between registers with integral mode
970 smaller than a word are always performed on the entire register. */
971 #define WORD_REGISTER_OPERATIONS
973 /* A C expression indicating when insns that read memory in mem_mode,
974 an integral mode narrower than a word, set the bits outside of mem_mode
975 to be either the sign-extension or the zero-extension of the data read. */
976 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
978 /* The maximum number of bytes that a single instruction can move quickly
979 between memory and registers or between two memory locations. */
982 /* A C expression that is nonzero if on this machine the number of bits
983 actually used for the count of a shift operation is equal to the number
984 of bits needed to represent the size of the object being shifted. */
985 #define SHIFT_COUNT_TRUNCATED 1
987 /* A C expression which is nonzero if on this machine it is safe to "convert"
988 an integer of 'inprec' bits to one of 'outprec' bits by merely operating
989 on it as if it had only 'outprec' bits. */
990 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
992 /* A C expression describing the value returned by a comparison operator with
993 an integral mode and stored by a store-flag instruction ('cstoremode4')
994 when the condition is true. */
995 #define STORE_FLAG_VALUE 1
997 /* An alias for the machine mode for pointers. */
1000 /* An alias for the machine mode used for memory references to functions
1001 being called, in call RTL expressions. */
1002 #define FUNCTION_MODE SImode
1004 /* ------------------------------------------------------------------------ */