1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2015 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* ------------------------------------------------------------------------ */
24 /* The following are auxiliary macros or structure declarations
25 that are used all over the nds32.c and nds32.h. */
28 /* Computing the Length of an Insn. */
29 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
30 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
32 /* Check instruction LS-37-FP-implied form.
33 Note: actually its immediate range is imm9u
34 since it is used for lwi37/swi37 instructions. */
35 #define NDS32_LS_37_FP_P(rt, ra, imm) \
36 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
37 && REGNO (ra) == FP_REGNUM \
38 && satisfies_constraint_Iu09 (imm))
40 /* Check instruction LS-37-SP-implied form.
41 Note: actually its immediate range is imm9u
42 since it is used for lwi37/swi37 instructions. */
43 #define NDS32_LS_37_SP_P(rt, ra, imm) \
44 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
45 && REGNO (ra) == SP_REGNUM \
46 && satisfies_constraint_Iu09 (imm))
49 /* Check load/store instruction form : Rt3, Ra3, imm3u. */
50 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
52 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
53 Note: no need to check ra because Ra5 means it covers all registers. */
54 #define NDS32_LS_450_P(rt, ra, imm) \
55 ((imm == const0_rtx) \
56 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
57 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
59 /* Check instruction RRI-333-form. */
60 #define NDS32_RRI_333_P(rt, ra, imm) \
61 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
62 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
63 && satisfies_constraint_Iu03 (imm))
65 /* Check instruction RI-45-form. */
66 #define NDS32_RI_45_P(rt, ra, imm) \
67 (REGNO (rt) == REGNO (ra) \
68 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
69 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
70 && satisfies_constraint_Iu05 (imm))
73 /* Check instruction RR-33-form. */
74 #define NDS32_RR_33_P(rt, ra) \
75 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
76 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
78 /* Check instruction RRR-333-form. */
79 #define NDS32_RRR_333_P(rt, ra, rb) \
80 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
81 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
82 && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
84 /* Check instruction RR-45-form.
85 Note: no need to check rb because Rb5 means it covers all registers. */
86 #define NDS32_RR_45_P(rt, ra, rb) \
87 (REGNO (rt) == REGNO (ra) \
88 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
89 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
91 /* Classifies address type to distinguish 16-bit/32-bit format. */
92 enum nds32_16bit_address_type
94 /* [reg]: 45 format address. */
96 /* [lo_reg + imm3u]: 333 format address. */
98 /* post_inc [lo_reg + imm3u]: 333 format address. */
99 ADDRESS_POST_INC_LO_REG_IMM3U
,
100 /* [$fp + imm7u]: fp imply address. */
102 /* [$sp + imm7u]: sp imply address. */
104 /* Other address format. */
105 ADDRESS_NOT_16BIT_FORMAT
109 /* ------------------------------------------------------------------------ */
111 /* Define maximum numbers of registers for passing arguments. */
112 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
114 /* Define the register number for first argument. */
115 #define NDS32_GPR_ARG_FIRST_REGNUM 0
117 /* Define the register number for return value. */
118 #define NDS32_GPR_RET_FIRST_REGNUM 0
120 /* Define the first integer register number. */
121 #define NDS32_FIRST_GPR_REGNUM 0
122 /* Define the last integer register number. */
123 #define NDS32_LAST_GPR_REGNUM 31
125 /* Define double word alignment bits. */
126 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
128 /* Define alignment checking macros for convenience. */
129 #define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
130 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
131 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
133 /* Get alignment according to mode or type information.
134 When 'type' is nonnull, there is no need to look at 'mode'. */
135 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
136 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
138 /* Round X up to the nearest double word. */
139 #define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
142 /* This macro is used to calculate the numbers of registers for
143 containing 'size' bytes of the argument.
144 The size of a register is a word in nds32 target.
145 So we use UNITS_PER_WORD to do the calculation. */
146 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
148 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
149 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
151 /* This macro is used to return the register number for passing argument.
152 We need to obey the following rules:
153 1. If it is required MORE THAN one register,
154 we need to further check if it really needs to be
155 aligned on double words.
156 a) If double word alignment is necessary,
157 the register number must be even value.
158 b) Otherwise, the register number can be odd or even value.
159 2. If it is required ONLY one register,
160 the register number can be odd or even value. */
161 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
162 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
163 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
164 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
165 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
166 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
168 /* This macro is to check if there are still available registers
169 for passing argument, which must be entirely in registers. */
170 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \
171 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
172 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
173 <= (NDS32_GPR_ARG_FIRST_REGNUM \
174 + NDS32_MAX_GPR_REGS_FOR_ARGS))
176 /* This macro is to check if there are still available registers
177 for passing argument, either entirely in registers or partially
179 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
180 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
181 < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
183 /* This macro is to check if the register is required to be saved on stack.
184 If call_used_regs[regno] == 0, regno is the callee-saved register.
185 If df_regs_ever_live_p(regno) == true, it is used in the current function.
186 As long as the register satisfies both criteria above,
187 it is required to be saved. */
188 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
189 ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
191 /* ------------------------------------------------------------------------ */
193 /* A C structure for machine-specific, per-function data.
194 This is added to the cfun structure. */
195 struct GTY(()) machine_function
197 /* Number of bytes allocated on the stack for variadic args
198 if we want to push them into stack as pretend arguments by ourself. */
200 /* Number of bytes reserved on the stack for
201 local and temporary variables. */
203 /* Number of bytes allocated on the stack for outgoing arguments. */
206 /* Number of bytes on the stack for saving $fp. */
208 /* Number of bytes on the stack for saving $gp. */
210 /* Number of bytes on the stack for saving $lp. */
213 /* Number of bytes on the stack for saving callee-saved registers. */
214 int callee_saved_regs_size
;
215 /* The padding bytes in callee-saved area may be required. */
216 int callee_saved_area_padding_bytes
;
218 /* The first required callee-saved register. */
219 int callee_saved_regs_first_regno
;
220 /* The last required callee-saved register. */
221 int callee_saved_regs_last_regno
;
223 /* The padding bytes in varargs area may be required. */
224 int va_args_area_padding_bytes
;
226 /* The first required register that should be saved on stack for va_args. */
227 int va_args_first_regno
;
228 /* The last required register that should be saved on stack for va_args. */
229 int va_args_last_regno
;
231 /* Indicate that whether this function needs
232 prologue/epilogue code generation. */
234 /* Indicate that whether this function
235 uses fp_as_gp optimization. */
239 /* A C structure that contains the arguments information. */
242 unsigned int gpr_offset
;
243 } nds32_cumulative_args
;
245 /* ------------------------------------------------------------------------ */
247 /* The following we define C-ISR related stuff.
248 In nds32 architecture, we have 73 vectors for interrupt/exception.
249 For each vector (except for vector 0, which is used for reset behavior),
250 we allow users to set its register saving scheme and interrupt level. */
252 /* There are 73 vectors in nds32 architecture.
254 1-8 for exception handler,
255 and 9-72 for interrupt handler.
256 We use an array, which is defined in nds32.c, to record
257 essential information for each vector. */
258 #define NDS32_N_ISR_VECTORS 73
260 /* Define possible isr category. */
261 enum nds32_isr_category
269 /* Define isr register saving scheme. */
270 enum nds32_isr_save_reg
276 /* Define isr nested type. */
277 enum nds32_isr_nested_type
284 /* Define structure to record isr information.
285 The isr vector array 'isr_vectors[]' with this structure
286 is defined in nds32.c. */
287 struct nds32_isr_info
289 /* The field to identify isr category.
290 It should be set to NDS32_ISR_NONE by default.
291 If user specifies a function as isr by using attribute,
292 this field will be set accordingly. */
293 enum nds32_isr_category category
;
295 /* A string for the applied function name.
296 It should be set to empty string by default. */
299 /* The register saving scheme.
300 It should be set to NDS32_PARTIAL_SAVE by default
301 unless user specifies attribute to change it. */
302 enum nds32_isr_save_reg save_reg
;
305 It should be set to NDS32_NOT_NESTED by default
306 unless user specifies attribute to change it. */
307 enum nds32_isr_nested_type nested_type
;
310 The total vectors = interrupt + exception numbers + reset.
311 It should be set to 0 by default.
312 This field is ONLY used in NDS32_ISR_RESET category. */
313 unsigned int total_n_vectors
;
315 /* A string for nmi handler name.
316 It should be set to empty string by default.
317 This field is ONLY used in NDS32_ISR_RESET category. */
320 /* A string for warm handler name.
321 It should be set to empty string by default.
322 This field is ONLY used in NDS32_ISR_RESET category. */
326 /* ------------------------------------------------------------------------ */
328 /* Define code for all nds32 builtins. */
337 NDS32_BUILTIN_SETGIE_EN
,
338 NDS32_BUILTIN_SETGIE_DIS
341 /* ------------------------------------------------------------------------ */
343 #define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
344 #define TARGET_ISA_V3 (nds32_arch_option == ARCH_V3)
345 #define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
347 #define TARGET_SOFT_FLOAT 1
348 #define TARGET_HARD_FLOAT 0
350 /* ------------------------------------------------------------------------ */
352 /* Controlling the Compilation Driver. */
354 #define OPTION_DEFAULT_SPECS \
355 {"arch", "%{!march=*:-march=%(VALUE)}" }
361 " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
363 /* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
364 we need to pass '--relax' to linker.
365 Besides, for -mex9, we need to further pass '--mex9'. */
367 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
368 " %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
374 /* The option -mno-ctor-dtor can disable constructor/destructor feature
375 by applying different crt stuff. In the convention, crt0.o is the
376 startup file without constructor/destructor;
377 crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
378 startup files with constructor/destructor.
379 Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
380 by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
381 currently provided by GCC for nds32 target.
383 For nds32 target so far:
384 If -mno-ctor-dtor, we are going to link
385 "crt0.o [user objects]".
386 If general cases, we are going to link
387 "crt1.o crtbegin1.o [user objects] crtend1.o". */
388 #define STARTFILE_SPEC \
389 " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
390 " %{!mno-ctor-dtor:crtbegin1.o%s}"
391 #define ENDFILE_SPEC \
392 " %{!mno-ctor-dtor:crtend1.o%s}"
394 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we configure gcc
395 with --target=nds32be-* setting.
396 Check gcc/config.gcc for more information.
397 In addition, currently we only have elf toolchain,
398 where mgp-direct is always the default. */
399 #ifdef TARGET_BIG_ENDIAN_DEFAULT
400 #define MULTILIB_DEFAULTS { "mbig-endian", "mgp-direct" }
402 #define MULTILIB_DEFAULTS { "mlittle-endian", "mgp-direct" }
406 /* Run-time Target Specification. */
408 #define TARGET_CPU_CPP_BUILTINS() \
411 builtin_define ("__nds32__"); \
414 builtin_define ("__NDS32_ISA_V2__"); \
416 builtin_define ("__NDS32_ISA_V3__"); \
417 if (TARGET_ISA_V3M) \
418 builtin_define ("__NDS32_ISA_V3M__"); \
420 if (TARGET_BIG_ENDIAN) \
421 builtin_define ("__big_endian__"); \
422 if (TARGET_REDUCED_REGS) \
423 builtin_define ("__NDS32_REDUCED_REGS__"); \
425 builtin_define ("__NDS32_CMOV__"); \
426 if (TARGET_PERF_EXT) \
427 builtin_define ("__NDS32_PERF_EXT__"); \
429 builtin_define ("__NDS32_16_BIT__"); \
430 if (TARGET_GP_DIRECT) \
431 builtin_define ("__NDS32_GP_DIRECT__"); \
433 builtin_assert ("cpu=nds32"); \
434 builtin_assert ("machine=nds32"); \
438 /* Defining Data Structures for Per-function Information. */
440 /* This macro is called once per function,
441 before generation of any RTL has begun. */
442 #define INIT_EXPANDERS nds32_init_expanders ()
445 /* Storage Layout. */
447 #define BITS_BIG_ENDIAN 0
449 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
451 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
453 #define UNITS_PER_WORD 4
455 #define PROMOTE_MODE(m, unsignedp, type) \
456 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
461 #define PARM_BOUNDARY 32
463 #define STACK_BOUNDARY 64
465 #define FUNCTION_BOUNDARY 32
467 #define BIGGEST_ALIGNMENT 64
469 #define EMPTY_FIELD_BOUNDARY 32
471 #define STRUCTURE_SIZE_BOUNDARY 8
473 #define STRICT_ALIGNMENT 1
475 #define PCC_BITFIELD_TYPE_MATTERS 1
478 /* Layout of Source Language Data Types. */
480 #define INT_TYPE_SIZE 32
481 #define SHORT_TYPE_SIZE 16
482 #define LONG_TYPE_SIZE 32
483 #define LONG_LONG_TYPE_SIZE 64
485 #define FLOAT_TYPE_SIZE 32
486 #define DOUBLE_TYPE_SIZE 64
487 #define LONG_DOUBLE_TYPE_SIZE 64
489 #define DEFAULT_SIGNED_CHAR 1
491 #define SIZE_TYPE "long unsigned int"
492 #define PTRDIFF_TYPE "long int"
493 #define WCHAR_TYPE "short unsigned int"
494 #define WCHAR_TYPE_SIZE 16
497 /* Register Usage. */
499 /* Number of actual hardware registers.
500 The hardware registers are assigned numbers for the compiler
501 from 0 to just below FIRST_PSEUDO_REGISTER.
502 All registers that the compiler knows about must be given numbers,
503 even those that are not normally considered general registers. */
504 #define FIRST_PSEUDO_REGISTER 34
506 /* An initializer that says which registers are used for fixed
507 purposes all throughout the compiled code and are therefore
508 not available for general allocation.
515 caller-save registers: $r0 ~ $r5, $r16 ~ $r23
516 callee-save registers: $r6 ~ $r10, $r11 ~ $r14
518 reserved for assembler : $r15
519 reserved for other use : $r24, $r25, $r26, $r27 */
520 #define FIXED_REGISTERS \
521 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
522 0, 0, 0, 0, 0, 0, 0, 0, \
523 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
524 0, 0, 0, 0, 0, 0, 0, 1, \
525 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
526 0, 0, 0, 0, 0, 0, 0, 0, \
527 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
528 1, 1, 1, 1, 0, 1, 0, 1, \
529 /* ARG_POINTER:32 */ \
531 /* FRAME_POINTER:33 */ \
535 /* Identifies the registers that are not available for
536 general allocation of values that must live across
537 function calls -- so they are caller-save registers.
539 0 : callee-save registers
540 1 : caller-save registers */
541 #define CALL_USED_REGISTERS \
542 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
543 1, 1, 1, 1, 1, 1, 0, 0, \
544 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
545 0, 0, 0, 0, 0, 0, 0, 1, \
546 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
547 1, 1, 1, 1, 1, 1, 1, 1, \
548 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
549 1, 1, 1, 1, 0, 1, 0, 1, \
550 /* ARG_POINTER:32 */ \
552 /* FRAME_POINTER:33 */ \
556 /* In nds32 target, we have three levels of registers:
557 LOW_COST_REGS : $r0 ~ $r7
558 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
559 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
560 #define REG_ALLOC_ORDER \
562 0, 1, 2, 3, 4, 5, 6, 7, \
563 8, 9, 10, 11, 16, 17, 18, 19, \
564 12, 13, 14, 15, 20, 21, 22, 23, \
565 24, 25, 26, 27, 28, 29, 30, 31, \
570 /* Tell IRA to use the order we define rather than messing it up with its
571 own cost calculations. */
572 #define HONOR_REG_ALLOC_ORDER optimize_size
574 /* The number of consecutive hard regs needed starting at
575 reg "regno" for holding a value of mode "mode". */
576 #define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
578 /* Value is 1 if hard register "regno" can hold a value
579 of machine-mode "mode". */
580 #define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
582 /* A C expression that is nonzero if a value of mode1
583 is accessible in mode2 without copying.
584 Define this macro to return nonzero in as many cases as possible
585 since doing so will allow GCC to perform better register allocation.
586 We can use general registers to tie QI/HI/SI modes together. */
587 #define MODES_TIEABLE_P(mode1, mode2) \
588 (GET_MODE_CLASS (mode1) == MODE_INT \
589 && GET_MODE_CLASS (mode2) == MODE_INT \
590 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD \
591 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
594 /* Register Classes. */
596 /* In nds32 target, we have three levels of registers:
597 Low cost regsiters : $r0 ~ $r7
598 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
599 High cost registers : $r12 ~ $r14, $r20 ~ $r31
601 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
602 so that it provides more chance to use low cost registers. */
617 #define N_REG_CLASSES (int) LIM_REG_CLASSES
619 #define REG_CLASS_NAMES \
632 #define REG_CLASS_CONTENTS \
634 {0x00000000, 0x00000000}, /* NO_REGS : */ \
635 {0x00008000, 0x00000000}, /* R15_TA_REG : 15 */ \
636 {0x80000000, 0x00000000}, /* STACK_REG : 31 */ \
637 {0x000000ff, 0x00000000}, /* LOW_REGS : 0-7 */ \
638 {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19 */ \
639 {0xfff07000, 0x00000000}, /* HIGH_REGS : 12-14, 20-31 */ \
640 {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31 */ \
641 {0x00000000, 0x00000003}, /* FRAME_REGS : 32, 33 */ \
642 {0xffffffff, 0x00000003} /* ALL_REGS : 0-31, 32, 33 */ \
645 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
647 #define BASE_REG_CLASS GENERAL_REGS
648 #define INDEX_REG_CLASS GENERAL_REGS
650 /* Return nonzero if it is suitable for use as a
651 base register in operand addresses.
652 So far, we return nonzero only if "num" is a hard reg
653 of the suitable class or a pseudo register which is
654 allocated to a suitable hard reg. */
655 #define REGNO_OK_FOR_BASE_P(num) \
656 ((num) < 32 || (unsigned) reg_renumber[num] < 32)
658 /* Return nonzero if it is suitable for use as a
659 index register in operand addresses.
660 So far, we return nonzero only if "num" is a hard reg
661 of the suitable class or a pseudo register which is
662 allocated to a suitable hard reg.
663 The difference between an index register and a base register is that
664 the index register may be scaled. */
665 #define REGNO_OK_FOR_INDEX_P(num) \
666 ((num) < 32 || (unsigned) reg_renumber[num] < 32)
669 /* Obsolete Macros for Defining Constraints. */
672 /* Stack Layout and Calling Conventions. */
674 #define STACK_GROWS_DOWNWARD
676 #define FRAME_GROWS_DOWNWARD 1
678 #define STARTING_FRAME_OFFSET 0
680 #define STACK_POINTER_OFFSET 0
682 #define FIRST_PARM_OFFSET(fundecl) \
683 (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
685 #define RETURN_ADDR_RTX(count, frameaddr) \
686 nds32_return_addr_rtx (count, frameaddr)
688 /* A C expression whose value is RTL representing the location
689 of the incoming return address at the beginning of any function
691 If this RTL is REG, you should also define
692 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
693 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
694 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
696 #define STACK_POINTER_REGNUM SP_REGNUM
698 #define FRAME_POINTER_REGNUM 33
700 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
702 #define ARG_POINTER_REGNUM 32
704 #define STATIC_CHAIN_REGNUM 16
706 #define ELIMINABLE_REGS \
707 { { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
708 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
709 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
710 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
712 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
713 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
715 #define ACCUMULATE_OUTGOING_ARGS 1
717 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
719 #define CUMULATIVE_ARGS nds32_cumulative_args
721 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
722 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
724 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
725 We better cast REGNO into signed integer so that we can avoid
726 'comparison of unsigned expression >= 0 is always true' warning. */
727 #define FUNCTION_ARG_REGNO_P(regno) \
728 (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0) \
729 && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
731 #define DEFAULT_PCC_STRUCT_RETURN 0
733 /* EXIT_IGNORE_STACK should be nonzero if, when returning
734 from a function, the stack pointer does not matter.
735 The value is tested only in functions that have frame pointers.
736 In nds32 target, the function epilogue recovers the
737 stack pointer from the frame. */
738 #define EXIT_IGNORE_STACK 1
740 #define FUNCTION_PROFILER(file, labelno) \
741 fprintf (file, "/* profiler %d */", (labelno))
744 /* Implementing the Varargs Macros. */
747 /* Trampolines for Nested Functions. */
749 /* Giving A-function and B-function,
750 if B-function wants to call A-function's nested function,
751 we need to fill trampoline code into A-function's stack
752 so that B-function can execute the code in stack to indirectly
753 jump to (like 'trampoline' action) desired nested function.
755 The trampoline code for nds32 target must contains following parts:
757 1. instructions (4 * 4 = 16 bytes):
759 load chain_value to static chain register via $pc
760 load nested function address to $r15 via $pc
761 jump to desired nested function via $r15
762 2. data (4 * 2 = 8 bytes):
764 nested function address
766 Please check nds32.c implementation for more information. */
767 #define TRAMPOLINE_SIZE 24
769 /* Because all instructions/data in trampoline template are 4-byte size,
770 we set trampoline alignment 8*4=32 bits. */
771 #define TRAMPOLINE_ALIGNMENT 32
774 /* Implicit Calls to Library Routines. */
777 /* Addressing Modes. */
779 /* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
780 #define HAVE_POST_INCREMENT 1
781 /* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
782 #define HAVE_POST_DECREMENT 1
784 /* We have "LWI.bi Rt, [Ra], imm" instruction form. */
785 #define HAVE_POST_MODIFY_DISP 1
786 /* We have "LW.bi Rt, [Ra], Rb" instruction form. */
787 #define HAVE_POST_MODIFY_REG 1
789 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
791 #define MAX_REGS_PER_ADDRESS 2
794 /* Anchored Addresses. */
797 /* Condition Code Status. */
800 /* Describing Relative Costs of Operations. */
802 /* A C expression for the cost of a branch instruction.
803 A value of 1 is the default;
804 other values are interpreted relative to that. */
805 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
807 #define SLOW_BYTE_ACCESS 1
809 #define NO_FUNCTION_CSE
812 /* Adjusting the Instruction Scheduler. */
815 /* Dividing the Output into Sections (Texts, Data, . . . ). */
817 #define TEXT_SECTION_ASM_OP "\t.text"
818 #define DATA_SECTION_ASM_OP "\t.data"
820 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
821 So we use '.section .bss' alternatively. */
822 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
824 /* Define this macro to be an expression with a nonzero value if jump tables
825 (for tablejump insns) should be output in the text section,
826 along with the assembler instructions.
827 Otherwise, the readonly data section is used. */
828 #define JUMP_TABLES_IN_TEXT_SECTION 1
831 /* Position Independent Code. */
833 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
836 /* Defining the Output Assembler Language. */
838 #define ASM_COMMENT_START "!"
840 #define ASM_APP_ON "! #APP"
842 #define ASM_APP_OFF "! #NO_APP\n"
844 #define ASM_OUTPUT_LABELREF(stream, name) \
845 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
847 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
848 assemble_name (stream, XSTR (sym, 0))
850 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
851 assemble_name (stream, buf)
853 #define LOCAL_LABEL_PREFIX "."
855 #define REGISTER_NAMES \
857 "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
858 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
859 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
860 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
865 /* Output normal jump table entry. */
866 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
867 asm_fprintf (stream, "\t.word\t%LL%d\n", value)
869 /* Output pc relative jump table entry. */
870 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
873 switch (GET_MODE (body)) \
876 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
879 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
882 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
889 /* We have to undef it first because elfos.h formerly define it
890 check gcc/config.gcc and gcc/config/elfos.h for more information. */
891 #undef ASM_OUTPUT_CASE_LABEL
892 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
895 asm_fprintf (stream, "\t! Jump Table Begin\n"); \
896 (*targetm.asm_out.internal_label) (stream, prefix, num); \
899 #define ASM_OUTPUT_CASE_END(stream, num, table) \
902 /* Because our jump table is in text section, \
903 we need to make sure 2-byte alignment after \
904 the jump table for instructions fetch. */ \
905 if (GET_MODE (PATTERN (table)) == QImode) \
906 ASM_OUTPUT_ALIGN (stream, 1); \
907 asm_fprintf (stream, "\t! Jump Table End\n"); \
910 /* This macro is not documented yet.
911 But we do need it to make jump table vector aligned. */
912 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
914 #define DWARF2_UNWIND_INFO 1
916 #define JUMP_ALIGN(x) \
917 (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
919 #define LOOP_ALIGN(x) \
920 (align_loops_log ? align_loops_log : nds32_target_alignment (x))
922 #define LABEL_ALIGN(x) \
923 (align_labels_log ? align_labels_log : nds32_target_alignment (x))
925 #define ASM_OUTPUT_ALIGN(stream, power) \
926 fprintf (stream, "\t.align\t%d\n", power)
929 /* Controlling Debugging Information Format. */
931 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
933 #define DWARF2_DEBUGGING_INFO 1
935 #define DWARF2_ASM_LINE_DEBUG_INFO 1
938 /* Cross Compilation and Floating Point. */
941 /* Mode Switching Instructions. */
944 /* Defining target-specific uses of __attribute__. */
950 /* Defining coprocessor specifics for MIPS targets. */
953 /* Parameters for Precompiled Header Validity Checking. */
956 /* C++ ABI parameters. */
959 /* Adding support for named address spaces. */
962 /* Miscellaneous Parameters. */
964 /* This is the machine mode that elements of a jump-table should have. */
965 #define CASE_VECTOR_MODE Pmode
967 /* Return the preferred mode for and addr_diff_vec when the mininum
968 and maximum offset are known. */
969 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
970 ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
971 : (max_offset >= 100) ? HImode \
974 /* Generate pc relative jump table when -fpic or -Os. */
975 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
977 /* Define this macro if operations between registers with integral mode
978 smaller than a word are always performed on the entire register. */
979 #define WORD_REGISTER_OPERATIONS
981 /* A C expression indicating when insns that read memory in mem_mode,
982 an integral mode narrower than a word, set the bits outside of mem_mode
983 to be either the sign-extension or the zero-extension of the data read. */
984 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
986 /* The maximum number of bytes that a single instruction can move quickly
987 between memory and registers or between two memory locations. */
990 /* A C expression that is nonzero if on this machine the number of bits
991 actually used for the count of a shift operation is equal to the number
992 of bits needed to represent the size of the object being shifted. */
993 #define SHIFT_COUNT_TRUNCATED 1
995 /* A C expression which is nonzero if on this machine it is safe to "convert"
996 an integer of 'inprec' bits to one of 'outprec' bits by merely operating
997 on it as if it had only 'outprec' bits. */
998 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
1000 /* A C expression describing the value returned by a comparison operator with
1001 an integral mode and stored by a store-flag instruction ('cstoremode4')
1002 when the condition is true. */
1003 #define STORE_FLAG_VALUE 1
1005 /* An alias for the machine mode for pointers. */
1006 #define Pmode SImode
1008 /* An alias for the machine mode used for memory references to functions
1009 being called, in call RTL expressions. */
1010 #define FUNCTION_MODE SImode
1012 /* ------------------------------------------------------------------------ */