gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  28    It is used in nds32_encode_section_info() to store flag in symbol_ref
  29    in case the symbol should be placed in .rodata section.
  30    So that we can check it in nds32_legitimate_address_p().  */
  31 #define NDS32_SYMBOL_FLAG_RODATA \
  32   (SYMBOL_FLAG_MACH_DEP << 0)
  33 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  34   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  35
  36 /* Computing the Length of an Insn.  */
  37 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  38   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  39
  40 /* Check instruction LS-37-FP-implied form.
  41    Note: actually its immediate range is imm9u
  42          since it is used for lwi37/swi37 instructions.  */
  43 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  44   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  45    && REGNO (ra) == FP_REGNUM               \
  46    && satisfies_constraint_Iu09 (imm))
  47
  48 /* Check instruction LS-37-SP-implied form.
  49    Note: actually its immediate range is imm9u
  50          since it is used for lwi37/swi37 instructions.  */
  51 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  52   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  53    && REGNO (ra) == SP_REGNUM               \
  54    && satisfies_constraint_Iu09 (imm))
  55
  56
  57 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  58 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  59
  60 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  61    Note: no need to check ra because Ra5 means it covers all registers.  */
  62 #define NDS32_LS_450_P(rt, ra, imm)                     \
  63   ((imm == const0_rtx)                                  \
  64    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  65        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  66
  67 /* Check instruction RRI-333-form.  */
  68 #define NDS32_RRI_333_P(rt, ra, imm)           \
  69   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  70    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  71    && satisfies_constraint_Iu03 (imm))
  72
  73 /* Check instruction RI-45-form.  */
  74 #define NDS32_RI_45_P(rt, ra, imm)                     \
  75   (REGNO (rt) == REGNO (ra)                            \
  76    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  77        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  78    && satisfies_constraint_Iu05 (imm))
  79
  80
  81 /* Check instruction RR-33-form.  */
  82 #define NDS32_RR_33_P(rt, ra)                   \
  83   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  84    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  85
  86 /* Check instruction RRR-333-form.  */
  87 #define NDS32_RRR_333_P(rt, ra, rb)             \
  88   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  89    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  90    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  91
  92 /* Check instruction RR-45-form.
  93    Note: no need to check rb because Rb5 means it covers all registers.  */
  94 #define NDS32_RR_45_P(rt, ra, rb)               \
  95   (REGNO (rt) == REGNO (ra)                     \
  96    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  97        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  98
  99 /* Classifies address type to distinguish 16-bit/32-bit format.  */
 100 enum nds32_16bit_address_type
 101 {
 102   /* [reg]: 45 format address.  */
 103   ADDRESS_REG,
 104   /* [lo_reg + imm3u]: 333 format address.  */
 105   ADDRESS_LO_REG_IMM3U,
 106   /* post_inc [lo_reg + imm3u]: 333 format address.  */
 107   ADDRESS_POST_INC_LO_REG_IMM3U,
 108   /* [$fp + imm7u]: fp imply address.  */
 109   ADDRESS_FP_IMM7U,
 110   /* [$sp + imm7u]: sp imply address.  */
 111   ADDRESS_SP_IMM7U,
 112   /* Other address format.  */
 113   ADDRESS_NOT_16BIT_FORMAT
 114 };
 115
 116
 117 /* ------------------------------------------------------------------------ */
 118
 119 /* Define maximum numbers of registers for passing arguments.  */
 120 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 121
 122 /* Define the register number for first argument.  */
 123 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 124
 125 /* Define the register number for return value.  */
 126 #define NDS32_GPR_RET_FIRST_REGNUM 0
 127
 128 /* Define the first integer register number.  */
 129 #define NDS32_FIRST_GPR_REGNUM 0
 130 /* Define the last integer register number.  */
 131 #define NDS32_LAST_GPR_REGNUM 31
 132
 133 /* Define double word alignment bits.  */
 134 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 135
 136 /* Define alignment checking macros for convenience.  */
 137 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 138 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 139 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 140
 141 /* Get alignment according to mode or type information.
 142    When 'type' is nonnull, there is no need to look at 'mode'.  */
 143 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 144   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 145
 146 /* Round X up to the nearest double word.  */
 147 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 148
 149
 150 /* This macro is used to calculate the numbers of registers for
 151    containing 'size' bytes of the argument.
 152    The size of a register is a word in nds32 target.
 153    So we use UNITS_PER_WORD to do the calculation.  */
 154 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 155   ((mode == BLKmode)                                                     \
 156    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 157    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 158
 159 /* This macro is used to return the register number for passing argument.
 160    We need to obey the following rules:
 161      1. If it is required MORE THAN one register,
 162         we need to further check if it really needs to be
 163         aligned on double words.
 164           a) If double word alignment is necessary,
 165              the register number must be even value.
 166           b) Otherwise, the register number can be odd or even value.
 167      2. If it is required ONLY one register,
 168         the register number can be odd or even value.  */
 169 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 170   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 171    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 172       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 173       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 174    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 175
 176 /* This macro is to check if there are still available registers
 177    for passing argument, which must be entirely in registers.  */
 178 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 179   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 180     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 181    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 182        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 183
 184 /* This macro is to check if there are still available registers
 185    for passing argument, either entirely in registers or partially
 186    in registers.  */
 187 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 188   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 189    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 190
 191 /* This macro is to check if the register is required to be saved on stack.
 192    If call_used_regs[regno] == 0, regno is the callee-saved register.
 193    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 194    As long as the register satisfies both criteria above,
 195    it is required to be saved.  */
 196 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 197   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 198
 199 /* ------------------------------------------------------------------------ */
 200
 201 /* A C structure for machine-specific, per-function data.
 202    This is added to the cfun structure.  */
 203 struct GTY(()) machine_function
 204 {
 205   /* Number of bytes allocated on the stack for variadic args
 206      if we want to push them into stack as pretend arguments by ourself.  */
 207   int va_args_size;
 208   /* Number of bytes reserved on the stack for
 209      local and temporary variables.  */
 210   int local_size;
 211   /* Number of bytes allocated on the stack for outgoing arguments.  */
 212   int out_args_size;
 213
 214   /* Number of bytes on the stack for saving $fp.  */
 215   int fp_size;
 216   /* Number of bytes on the stack for saving $gp.  */
 217   int gp_size;
 218   /* Number of bytes on the stack for saving $lp.  */
 219   int lp_size;
 220
 221   /* Number of bytes on the stack for saving general purpose
 222      callee-saved registers.  */
 223   int callee_saved_gpr_regs_size;
 224
 225   /* The padding bytes in callee-saved area may be required.  */
 226   int callee_saved_area_gpr_padding_bytes;
 227
 228   /* The first required general purpose callee-saved register.  */
 229   int callee_saved_first_gpr_regno;
 230   /* The last required general purpose callee-saved register.  */
 231   int callee_saved_last_gpr_regno;
 232
 233   /* The padding bytes in varargs area may be required.  */
 234   int va_args_area_padding_bytes;
 235
 236   /* The first required register that should be saved on stack for va_args.  */
 237   int va_args_first_regno;
 238   /* The last required register that should be saved on stack for va_args.  */
 239   int va_args_last_regno;
 240
 241   /* Indicate that whether this function needs
 242      prologue/epilogue code generation.  */
 243   int naked_p;
 244   /* Indicate that whether this function
 245      uses fp_as_gp optimization.  */
 246   int fp_as_gp_p;
 247 };
 248
 249 /* A C structure that contains the arguments information.  */
 250 typedef struct
 251 {
 252   unsigned int gpr_offset;
 253 } nds32_cumulative_args;
 254
 255 /* ------------------------------------------------------------------------ */
 256
 257 /* The following we define C-ISR related stuff.
 258    In nds32 architecture, we have 73 vectors for interrupt/exception.
 259    For each vector (except for vector 0, which is used for reset behavior),
 260    we allow users to set its register saving scheme and interrupt level.  */
 261
 262 /* There are 73 vectors in nds32 architecture.
 263    0 for reset handler,
 264    1-8 for exception handler,
 265    and 9-72 for interrupt handler.
 266    We use an array, which is defined in nds32.c, to record
 267    essential information for each vector.  */
 268 #define NDS32_N_ISR_VECTORS 73
 269
 270 /* Define possible isr category.  */
 271 enum nds32_isr_category
 272 {
 273   NDS32_ISR_NONE,
 274   NDS32_ISR_INTERRUPT,
 275   NDS32_ISR_EXCEPTION,
 276   NDS32_ISR_RESET
 277 };
 278
 279 /* Define isr register saving scheme.  */
 280 enum nds32_isr_save_reg
 281 {
 282   NDS32_SAVE_ALL,
 283   NDS32_PARTIAL_SAVE
 284 };
 285
 286 /* Define isr nested type.  */
 287 enum nds32_isr_nested_type
 288 {
 289   NDS32_NESTED,
 290   NDS32_NOT_NESTED,
 291   NDS32_NESTED_READY
 292 };
 293
 294 /* Define structure to record isr information.
 295    The isr vector array 'isr_vectors[]' with this structure
 296    is defined in nds32.c.  */
 297 struct nds32_isr_info
 298 {
 299   /* The field to identify isr category.
 300      It should be set to NDS32_ISR_NONE by default.
 301      If user specifies a function as isr by using attribute,
 302      this field will be set accordingly.  */
 303   enum nds32_isr_category category;
 304
 305   /* A string for the applied function name.
 306      It should be set to empty string by default.  */
 307   char func_name[100];
 308
 309   /* The register saving scheme.
 310      It should be set to NDS32_PARTIAL_SAVE by default
 311      unless user specifies attribute to change it.  */
 312   enum nds32_isr_save_reg save_reg;
 313
 314   /* The nested type.
 315      It should be set to NDS32_NOT_NESTED by default
 316      unless user specifies attribute to change it.  */
 317   enum nds32_isr_nested_type nested_type;
 318
 319   /* Total vectors.
 320      The total vectors = interrupt + exception numbers + reset.
 321      It should be set to 0 by default.
 322      This field is ONLY used in NDS32_ISR_RESET category.  */
 323   unsigned int total_n_vectors;
 324
 325   /* A string for nmi handler name.
 326      It should be set to empty string by default.
 327      This field is ONLY used in NDS32_ISR_RESET category.  */
 328   char nmi_name[100];
 329
 330   /* A string for warm handler name.
 331      It should be set to empty string by default.
 332      This field is ONLY used in NDS32_ISR_RESET category.  */
 333   char warm_name[100];
 334 };
 335
 336 /* ------------------------------------------------------------------------ */
 337
 338 /* Define code for all nds32 builtins.  */
 339 enum nds32_builtins
 340 {
 341   NDS32_BUILTIN_ISYNC,
 342   NDS32_BUILTIN_ISB,
 343   NDS32_BUILTIN_MFSR,
 344   NDS32_BUILTIN_MFUSR,
 345   NDS32_BUILTIN_MTSR,
 346   NDS32_BUILTIN_MTUSR,
 347   NDS32_BUILTIN_SETGIE_EN,
 348   NDS32_BUILTIN_SETGIE_DIS,
 349   NDS32_BUILTIN_FFB,
 350   NDS32_BUILTIN_FFMISM,
 351   NDS32_BUILTIN_FLMISM,
 352   NDS32_BUILTIN_UALOAD_HW,
 353   NDS32_BUILTIN_UALOAD_W,
 354   NDS32_BUILTIN_UALOAD_DW,
 355   NDS32_BUILTIN_UASTORE_HW,
 356   NDS32_BUILTIN_UASTORE_W,
 357   NDS32_BUILTIN_UASTORE_DW,
 358   NDS32_BUILTIN_COUNT
 359 };
 360
 361 /* ------------------------------------------------------------------------ */
 362
 363 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 364 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 365 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 366
 367 #define TARGET_CMODEL_SMALL \
 368    (nds32_cmodel_option == CMODEL_SMALL)
 369 #define TARGET_CMODEL_MEDIUM \
 370    (nds32_cmodel_option == CMODEL_MEDIUM)
 371 #define TARGET_CMODEL_LARGE \
 372    (nds32_cmodel_option == CMODEL_LARGE)
 373
 374 /* When -mcmodel=small or -mcmodel=medium,
 375    compiler may generate gp-base instruction directly.  */
 376 #define TARGET_GP_DIRECT \
 377    (nds32_cmodel_option == CMODEL_SMALL\
 378     || nds32_cmodel_option == CMODEL_MEDIUM)
 379
 380 #define TARGET_SOFT_FLOAT 1
 381 #define TARGET_HARD_FLOAT 0
 382
 383 /* ------------------------------------------------------------------------ */
 384 \f
 385 /* Controlling the Compilation Driver.  */
 386
 387 #define OPTION_DEFAULT_SPECS \
 388   {"arch", "%{!march=*:-march=%(VALUE)}" }
 389
 390 #define CC1_SPEC \
 391   ""
 392
 393 #define ASM_SPEC \
 394   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 395
 396 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 397 #define LINK_SPEC \
 398   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 399   " %{mrelax:--relax}"
 400
 401 #define LIB_SPEC \
 402   " -lc -lgloss"
 403
 404 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 405    by applying different crt stuff.  In the convention, crt0.o is the
 406    startup file without constructor/destructor;
 407    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 408    startup files with constructor/destructor.
 409    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 410    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 411    currently provided by GCC for nds32 target.
 412
 413    For nds32 target so far:
 414    If -mno-ctor-dtor, we are going to link
 415    "crt0.o [user objects]".
 416    If general cases, we are going to link
 417    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 418 #define STARTFILE_SPEC \
 419   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 420   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 421 #define ENDFILE_SPEC \
 422   " %{!mno-ctor-dtor:crtend1.o%s}"
 423
 424 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 425    configure gcc with --target=nds32be-* setting.
 426    Check gcc/config.gcc for more information.  */
 427 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 428 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 429 #else
 430 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 431 #endif
 432
 433 /* Currently we only have elf toolchain,
 434    where -mcmodel=medium is always the default.  */
 435 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 436
 437 #define MULTILIB_DEFAULTS \
 438   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 439
 440 \f
 441 /* Run-time Target Specification.  */
 442
 443 #define TARGET_CPU_CPP_BUILTINS() \
 444   nds32_cpu_cpp_builtins (pfile)
 445
 446 \f
 447 /* Defining Data Structures for Per-function Information.  */
 448
 449 /* This macro is called once per function,
 450    before generation of any RTL has begun.  */
 451 #define INIT_EXPANDERS  nds32_init_expanders ()
 452
 453 \f
 454 /* Storage Layout.  */
 455
 456 #define BITS_BIG_ENDIAN 0
 457
 458 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 459
 460 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 461
 462 #define UNITS_PER_WORD 4
 463
 464 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 465   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 466     {                                                                       \
 467       (m) = SImode;                                                         \
 468     }
 469
 470 #define PARM_BOUNDARY 32
 471
 472 #define STACK_BOUNDARY 64
 473
 474 #define FUNCTION_BOUNDARY 32
 475
 476 #define BIGGEST_ALIGNMENT 64
 477
 478 #define EMPTY_FIELD_BOUNDARY 32
 479
 480 #define STRUCTURE_SIZE_BOUNDARY 8
 481
 482 #define STRICT_ALIGNMENT 1
 483
 484 #define PCC_BITFIELD_TYPE_MATTERS 1
 485
 486 \f
 487 /* Layout of Source Language Data Types.  */
 488
 489 #define INT_TYPE_SIZE           32
 490 #define SHORT_TYPE_SIZE         16
 491 #define LONG_TYPE_SIZE          32
 492 #define LONG_LONG_TYPE_SIZE     64
 493
 494 #define FLOAT_TYPE_SIZE         32
 495 #define DOUBLE_TYPE_SIZE        64
 496 #define LONG_DOUBLE_TYPE_SIZE   64
 497
 498 #define DEFAULT_SIGNED_CHAR 1
 499
 500 #define SIZE_TYPE "long unsigned int"
 501 #define PTRDIFF_TYPE "long int"
 502 #define WCHAR_TYPE "short unsigned int"
 503 #define WCHAR_TYPE_SIZE 16
 504
 505 \f
 506 /* Register Usage.  */
 507
 508 /* Number of actual hardware registers.
 509    The hardware registers are assigned numbers for the compiler
 510    from 0 to just below FIRST_PSEUDO_REGISTER.
 511    All registers that the compiler knows about must be given numbers,
 512    even those that are not normally considered general registers.  */
 513 #define FIRST_PSEUDO_REGISTER 101
 514
 515 /* An initializer that says which registers are used for fixed
 516    purposes all throughout the compiled code and are therefore
 517    not available for general allocation.
 518
 519    $r28 : $fp
 520    $r29 : $gp
 521    $r30 : $lp
 522    $r31 : $sp
 523
 524    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 525    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 526
 527    reserved for assembler : $r15
 528    reserved for other use : $r24, $r25, $r26, $r27 */
 529 #define FIXED_REGISTERS \
 530 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 531       0,   0,   0,   0,   0,   0,   0,   0,     \
 532   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 533       0,   0,   0,   0,   0,   0,   0,   1,     \
 534   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 535       0,   0,   0,   0,   0,   0,   0,   0,     \
 536   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 537       1,   1,   1,   1,   0,   1,   0,   1,     \
 538   /* AP   FP    Reserved.................... */ \
 539       1,   1,   1,   1,   1,   1,   1,   1,     \
 540   /* Reserved............................... */ \
 541       1,   1,   1,   1,   1,   1,   1,   1,     \
 542   /* Reserved............................... */ \
 543       1,   1,   1,   1,   1,   1,   1,   1,     \
 544   /* Reserved............................... */ \
 545       1,   1,   1,   1,   1,   1,   1,   1,     \
 546   /* Reserved............................... */ \
 547       1,   1,   1,   1,   1,   1,   1,   1,     \
 548   /* Reserved............................... */ \
 549       1,   1,   1,   1,   1,   1,   1,   1,     \
 550   /* Reserved............................... */ \
 551       1,   1,   1,   1,   1,   1,   1,   1,     \
 552   /* Reserved............................... */ \
 553       1,   1,   1,   1,   1,   1,   1,   1,     \
 554   /* Reserved............................... */ \
 555       1,   1,   1,   1,   1                     \
 556 }
 557
 558 /* Identifies the registers that are not available for
 559    general allocation of values that must live across
 560    function calls -- so they are caller-save registers.
 561
 562    0 : callee-save registers
 563    1 : caller-save registers */
 564 #define CALL_USED_REGISTERS \
 565 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 566       1,   1,   1,   1,   1,   1,   0,   0,     \
 567   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 568       0,   0,   0,   0,   0,   0,   0,   1,     \
 569   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 570       1,   1,   1,   1,   1,   1,   1,   1,     \
 571   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 572       1,   1,   1,   1,   0,   1,   0,   1,     \
 573   /* AP   FP    Reserved.................... */ \
 574       1,   1,   1,   1,   1,   1,   1,   1,     \
 575   /* Reserved............................... */ \
 576       1,   1,   1,   1,   1,   1,   1,   1,     \
 577   /* Reserved............................... */ \
 578       1,   1,   1,   1,   1,   1,   1,   1,     \
 579   /* Reserved............................... */ \
 580       1,   1,   1,   1,   1,   1,   1,   1,     \
 581   /* Reserved............................... */ \
 582       1,   1,   1,   1,   1,   1,   1,   1,     \
 583   /* Reserved............................... */ \
 584       1,   1,   1,   1,   1,   1,   1,   1,     \
 585   /* Reserved............................... */ \
 586       1,   1,   1,   1,   1,   1,   1,   1,     \
 587   /* Reserved............................... */ \
 588       1,   1,   1,   1,   1,   1,   1,   1,     \
 589   /* Reserved............................... */ \
 590       1,   1,   1,   1,   1                     \
 591 }
 592
 593 /* In nds32 target, we have three levels of registers:
 594      LOW_COST_REGS    : $r0 ~ $r7
 595      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 596      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 597 #define REG_ALLOC_ORDER \
 598 {   0,   1,   2,   3,   4,   5,   6,   7, \
 599    16,  17,  18,  19,   9,  10,  11,  12, \
 600    13,  14,  8,   15,  20,  21,  22,  23, \
 601    24,  25,  26,  27,  28,  29,  30,  31, \
 602    32,  33,  34,  35,  36,  37,  38,  39, \
 603    40,  41,  42,  43,  44,  45,  46,  47, \
 604    48,  49,  50,  51,  52,  53,  54,  55, \
 605    56,  57,  58,  59,  60,  61,  62,  63, \
 606    64,  65,  66,  67,  68,  69,  70,  71, \
 607    72,  73,  74,  75,  76,  77,  78,  79, \
 608    80,  81,  82,  83,  84,  85,  86,  87, \
 609    88,  89,  90,  91,  92,  93,  94,  95, \
 610    96,  97,  98,  99, 100,                \
 611 }
 612
 613 /* Tell IRA to use the order we define rather than messing it up with its
 614    own cost calculations.  */
 615 #define HONOR_REG_ALLOC_ORDER optimize_size
 616
 617 \f
 618 /* Register Classes.  */
 619
 620 /* In nds32 target, we have three levels of registers:
 621      Low cost regsiters    : $r0 ~ $r7
 622      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 623      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 624
 625    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 626    so that it provides more chance to use low cost registers.  */
 627 enum reg_class
 628 {
 629   NO_REGS,
 630   R5_REG,
 631   R8_REG,
 632   R15_TA_REG,
 633   STACK_REG,
 634   FRAME_POINTER_REG,
 635   LOW_REGS,
 636   MIDDLE_REGS,
 637   HIGH_REGS,
 638   GENERAL_REGS,
 639   FRAME_REGS,
 640   ALL_REGS,
 641   LIM_REG_CLASSES
 642 };
 643
 644 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 645
 646 #define REG_CLASS_NAMES \
 647 {                       \
 648   "NO_REGS",            \
 649   "R5_REG",             \
 650   "R8_REG",             \
 651   "R15_TA_REG",         \
 652   "STACK_REG",          \
 653   "FRAME_POINTER_REG",  \
 654   "LOW_REGS",           \
 655   "MIDDLE_REGS",        \
 656   "HIGH_REGS",          \
 657   "GENERAL_REGS",       \
 658   "FRAME_REGS",         \
 659   "ALL_REGS"            \
 660 }
 661
 662 #define REG_CLASS_CONTENTS \
 663 { /* NO_REGS                                    */  \
 664   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
 665   /* R5_REG              : 5                    */  \
 666   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
 667   /* R8_REG              : 8                    */  \
 668   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
 669   /* R15_TA_REG          : 15                   */  \
 670   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
 671   /* STACK_REG           : 31                   */  \
 672   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
 673   /* FRAME_POINTER_REG   : 28                   */  \
 674   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
 675   /* LOW_REGS            : 0-7                  */  \
 676   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
 677   /* MIDDLE_REGS         : 0-11, 16-19          */  \
 678   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
 679   /* HIGH_REGS           : 12-14, 20-31         */  \
 680   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
 681   /* GENERAL_REGS        : 0-31                 */  \
 682   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
 683   /* FRAME_REGS          : 32, 33               */  \
 684   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
 685   /* ALL_REGS            : 0-100                */  \
 686   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
 687 }
 688
 689 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 690
 691 #define BASE_REG_CLASS GENERAL_REGS
 692 #define INDEX_REG_CLASS GENERAL_REGS
 693
 694 /* Return nonzero if it is suitable for use as a
 695    base register in operand addresses.
 696    So far, we return nonzero only if "num" is a hard reg
 697    of the suitable class or a pseudo register which is
 698    allocated to a suitable hard reg.  */
 699 #define REGNO_OK_FOR_BASE_P(num) \
 700   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 701
 702 /* Return nonzero if it is suitable for use as a
 703    index register in operand addresses.
 704    So far, we return nonzero only if "num" is a hard reg
 705    of the suitable class or a pseudo register which is
 706    allocated to a suitable hard reg.
 707    The difference between an index register and a base register is that
 708    the index register may be scaled.  */
 709 #define REGNO_OK_FOR_INDEX_P(num) \
 710   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 711
 712 \f
 713 /* Obsolete Macros for Defining Constraints.  */
 714
 715 \f
 716 /* Stack Layout and Calling Conventions.  */
 717
 718 #define STACK_GROWS_DOWNWARD 1
 719
 720 #define FRAME_GROWS_DOWNWARD 1
 721
 722 #define STACK_POINTER_OFFSET 0
 723
 724 #define FIRST_PARM_OFFSET(fundecl) \
 725   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 726
 727 #define RETURN_ADDR_RTX(count, frameaddr) \
 728   nds32_return_addr_rtx (count, frameaddr)
 729
 730 /* A C expression whose value is RTL representing the location
 731    of the incoming return address at the beginning of any function
 732    before the prologue.
 733    If this RTL is REG, you should also define
 734    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 735 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 736 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 737
 738 #define STACK_POINTER_REGNUM SP_REGNUM
 739
 740 #define FRAME_POINTER_REGNUM 33
 741
 742 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 743
 744 #define ARG_POINTER_REGNUM 32
 745
 746 #define STATIC_CHAIN_REGNUM 16
 747
 748 #define ELIMINABLE_REGS                                \
 749 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 750   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 751   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 752   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 753
 754 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 755   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 756
 757 #define ACCUMULATE_OUTGOING_ARGS 1
 758
 759 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 760
 761 #define CUMULATIVE_ARGS nds32_cumulative_args
 762
 763 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 764   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 765
 766 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 767    We better cast REGNO into signed integer so that we can avoid
 768    'comparison of unsigned expression >= 0 is always true' warning.  */
 769 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 770   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 771    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
 772
 773 #define DEFAULT_PCC_STRUCT_RETURN 0
 774
 775 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 776    from a function, the stack pointer does not matter.
 777    The value is tested only in functions that have frame pointers.
 778    In nds32 target, the function epilogue recovers the
 779    stack pointer from the frame.  */
 780 #define EXIT_IGNORE_STACK 1
 781
 782 #define FUNCTION_PROFILER(file, labelno) \
 783   fprintf (file, "/* profiler %d */", (labelno))
 784
 785 \f
 786 /* Implementing the Varargs Macros.  */
 787
 788 \f
 789 /* Trampolines for Nested Functions.  */
 790
 791 /* Giving A-function and B-function,
 792    if B-function wants to call A-function's nested function,
 793    we need to fill trampoline code into A-function's stack
 794    so that B-function can execute the code in stack to indirectly
 795    jump to (like 'trampoline' action) desired nested function.
 796
 797    The trampoline code for nds32 target must contains following parts:
 798
 799      1. instructions (4 * 4 = 16 bytes):
 800           get $pc first
 801           load chain_value to static chain register via $pc
 802           load nested function address to $r15 via $pc
 803           jump to desired nested function via $r15
 804      2. data (4 * 2 = 8 bytes):
 805           chain_value
 806           nested function address
 807
 808    Please check nds32.c implementation for more information.  */
 809 #define TRAMPOLINE_SIZE 24
 810
 811 /* Because all instructions/data in trampoline template are 4-byte size,
 812    we set trampoline alignment 8*4=32 bits.  */
 813 #define TRAMPOLINE_ALIGNMENT 32
 814
 815 \f
 816 /* Implicit Calls to Library Routines.  */
 817
 818 \f
 819 /* Addressing Modes.  */
 820
 821 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 822 #define HAVE_POST_INCREMENT 1
 823 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 824 #define HAVE_POST_DECREMENT 1
 825
 826 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 827 #define HAVE_POST_MODIFY_DISP 1
 828 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 829 #define HAVE_POST_MODIFY_REG  1
 830
 831 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 832
 833 #define MAX_REGS_PER_ADDRESS 2
 834
 835 \f
 836 /* Anchored Addresses.  */
 837
 838 \f
 839 /* Condition Code Status.  */
 840
 841 \f
 842 /* Describing Relative Costs of Operations.  */
 843
 844 /* A C expression for the cost of a branch instruction.
 845    A value of 1 is the default;
 846    other values are interpreted relative to that.  */
 847 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
 848
 849 #define SLOW_BYTE_ACCESS 1
 850
 851 #define NO_FUNCTION_CSE 1
 852
 853 \f
 854 /* Adjusting the Instruction Scheduler.  */
 855
 856 \f
 857 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 858
 859 #define TEXT_SECTION_ASM_OP     "\t.text"
 860 #define DATA_SECTION_ASM_OP     "\t.data"
 861
 862 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 863    So we use '.section .bss' alternatively.  */
 864 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 865
 866 /* Define this macro to be an expression with a nonzero value if jump tables
 867    (for tablejump insns) should be output in the text section,
 868    along with the assembler instructions.
 869    Otherwise, the readonly data section is used.  */
 870 #define JUMP_TABLES_IN_TEXT_SECTION 1
 871
 872 \f
 873 /* Position Independent Code.  */
 874
 875 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
 876
 877 \f
 878 /* Defining the Output Assembler Language.  */
 879
 880 #define ASM_COMMENT_START "!"
 881
 882 #define ASM_APP_ON "! #APP"
 883
 884 #define ASM_APP_OFF "! #NO_APP\n"
 885
 886 #define ASM_OUTPUT_LABELREF(stream, name) \
 887   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 888
 889 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 890   assemble_name (stream, XSTR (sym, 0))
 891
 892 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 893   assemble_name (stream, buf)
 894
 895 #define LOCAL_LABEL_PREFIX "."
 896
 897 #define REGISTER_NAMES \
 898 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 899   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 900   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 901   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 902   "$AP",  "$SFP", "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 903   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 904   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 905   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 906   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 907   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 908   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 909   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 910   "NA",   "NA",   "NA",   "NA",   "NA"                            \
 911 }
 912
 913 /* Output normal jump table entry.  */
 914 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 915   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 916
 917 /* Output pc relative jump table entry.  */
 918 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 919   do                                                                    \
 920     {                                                                   \
 921       switch (GET_MODE (body))                                          \
 922         {                                                               \
 923         case E_QImode:                                                    \
 924           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 925           break;                                                        \
 926         case E_HImode:                                                    \
 927           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 928           break;                                                        \
 929         case E_SImode:                                                    \
 930           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 931           break;                                                        \
 932         default:                                                        \
 933           gcc_unreachable();                                            \
 934         }                                                               \
 935     } while (0)
 936
 937 /* We have to undef it first because elfos.h formerly define it
 938    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 939 #undef  ASM_OUTPUT_CASE_LABEL
 940 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 941   do                                                               \
 942     {                                                              \
 943       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 944       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 945     } while (0)
 946
 947 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 948   do                                                   \
 949     {                                                  \
 950       /* Because our jump table is in text section,    \
 951          we need to make sure 2-byte alignment after   \
 952          the jump table for instructions fetch.  */    \
 953       if (GET_MODE (PATTERN (table)) == QImode)        \
 954         ASM_OUTPUT_ALIGN (stream, 1);                  \
 955       asm_fprintf (stream, "\t! Jump Table End\n");    \
 956     }  while (0)
 957
 958 /* This macro is not documented yet.
 959    But we do need it to make jump table vector aligned.  */
 960 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
 961
 962 #define DWARF2_UNWIND_INFO 1
 963
 964 #define JUMP_ALIGN(x) \
 965   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
 966
 967 #define LOOP_ALIGN(x) \
 968   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
 969
 970 #define LABEL_ALIGN(x) \
 971   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
 972
 973 #define ASM_OUTPUT_ALIGN(stream, power) \
 974   fprintf (stream, "\t.align\t%d\n", power)
 975
 976 \f
 977 /* Controlling Debugging Information Format.  */
 978
 979 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 980
 981 #define DWARF2_DEBUGGING_INFO 1
 982
 983 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 984
 985 \f
 986 /* Cross Compilation and Floating Point.  */
 987
 988 \f
 989 /* Mode Switching Instructions.  */
 990
 991 \f
 992 /* Defining target-specific uses of __attribute__.  */
 993
 994 \f
 995 /* Emulating TLS.  */
 996
 997 \f
 998 /* Defining coprocessor specifics for MIPS targets.  */
 999
1000 \f
1001 /* Parameters for Precompiled Header Validity Checking.  */
1002
1003 \f
1004 /* C++ ABI parameters.  */
1005
1006 \f
1007 /* Adding support for named address spaces.  */
1008
1009 \f
1010 /* Miscellaneous Parameters.  */
1011
1012 /* This is the machine mode that elements of a jump-table should have.  */
1013 #define CASE_VECTOR_MODE Pmode
1014
1015 /* Return the preferred mode for and addr_diff_vec when the mininum
1016    and maximum offset are known.  */
1017 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1018    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
1019    : (max_offset >= 100) ? HImode                               \
1020    : QImode)
1021
1022 /* Generate pc relative jump table when -fpic or -Os.  */
1023 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1024
1025 /* Define this macro if operations between registers with integral mode
1026    smaller than a word are always performed on the entire register.  */
1027 #define WORD_REGISTER_OPERATIONS 1
1028
1029 /* A C expression indicating when insns that read memory in mem_mode,
1030    an integral mode narrower than a word, set the bits outside of mem_mode
1031    to be either the sign-extension or the zero-extension of the data read.  */
1032 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1033
1034 /* The maximum number of bytes that a single instruction can move quickly
1035    between memory and registers or between two memory locations.  */
1036 #define MOVE_MAX 4
1037
1038 /* A C expression that is nonzero if on this machine the number of bits
1039    actually used for the count of a shift operation is equal to the number
1040    of bits needed to represent the size of the object being shifted.  */
1041 #define SHIFT_COUNT_TRUNCATED 1
1042
1043 /* A C expression describing the value returned by a comparison operator with
1044    an integral mode and stored by a store-flag instruction ('cstoremode4')
1045    when the condition is true.  */
1046 #define STORE_FLAG_VALUE 1
1047
1048 /* An alias for the machine mode for pointers.  */
1049 #define Pmode SImode
1050
1051 /* An alias for the machine mode used for memory references to functions
1052    being called, in call RTL expressions.  */
1053 #define FUNCTION_MODE SImode
1054
1055 /* ------------------------------------------------------------------------ */