gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  28    It is used in nds32_encode_section_info() to store flag in symbol_ref
  29    in case the symbol should be placed in .rodata section.
  30    So that we can check it in nds32_legitimate_address_p().  */
  31 #define NDS32_SYMBOL_FLAG_RODATA \
  32   (SYMBOL_FLAG_MACH_DEP << 0)
  33 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  34   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  35
  36 /* Computing the Length of an Insn.  */
  37 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  38   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  39
  40 /* Check instruction LS-37-FP-implied form.
  41    Note: actually its immediate range is imm9u
  42          since it is used for lwi37/swi37 instructions.  */
  43 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  44   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  45    && REGNO (ra) == FP_REGNUM               \
  46    && satisfies_constraint_Iu09 (imm))
  47
  48 /* Check instruction LS-37-SP-implied form.
  49    Note: actually its immediate range is imm9u
  50          since it is used for lwi37/swi37 instructions.  */
  51 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  52   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  53    && REGNO (ra) == SP_REGNUM               \
  54    && satisfies_constraint_Iu09 (imm))
  55
  56
  57 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  58 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  59
  60 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  61    Note: no need to check ra because Ra5 means it covers all registers.  */
  62 #define NDS32_LS_450_P(rt, ra, imm)                     \
  63   ((imm == const0_rtx)                                  \
  64    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  65        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  66
  67 /* Check instruction RRI-333-form.  */
  68 #define NDS32_RRI_333_P(rt, ra, imm)           \
  69   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  70    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  71    && satisfies_constraint_Iu03 (imm))
  72
  73 /* Check instruction RI-45-form.  */
  74 #define NDS32_RI_45_P(rt, ra, imm)                     \
  75   (REGNO (rt) == REGNO (ra)                            \
  76    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  77        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  78    && satisfies_constraint_Iu05 (imm))
  79
  80
  81 /* Check instruction RR-33-form.  */
  82 #define NDS32_RR_33_P(rt, ra)                   \
  83   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  84    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  85
  86 /* Check instruction RRR-333-form.  */
  87 #define NDS32_RRR_333_P(rt, ra, rb)             \
  88   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  89    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  90    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  91
  92 /* Check instruction RR-45-form.
  93    Note: no need to check rb because Rb5 means it covers all registers.  */
  94 #define NDS32_RR_45_P(rt, ra, rb)               \
  95   (REGNO (rt) == REGNO (ra)                     \
  96    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  97        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  98
  99 /* Classifies address type to distinguish 16-bit/32-bit format.  */
 100 enum nds32_16bit_address_type
 101 {
 102   /* [reg]: 45 format address.  */
 103   ADDRESS_REG,
 104   /* [lo_reg + imm3u]: 333 format address.  */
 105   ADDRESS_LO_REG_IMM3U,
 106   /* post_inc [lo_reg + imm3u]: 333 format address.  */
 107   ADDRESS_POST_INC_LO_REG_IMM3U,
 108   /* [$fp + imm7u]: fp imply address.  */
 109   ADDRESS_FP_IMM7U,
 110   /* [$sp + imm7u]: sp imply address.  */
 111   ADDRESS_SP_IMM7U,
 112   /* Other address format.  */
 113   ADDRESS_NOT_16BIT_FORMAT
 114 };
 115
 116
 117 /* ------------------------------------------------------------------------ */
 118
 119 /* Define maximum numbers of registers for passing arguments.  */
 120 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 121
 122 /* Define the register number for first argument.  */
 123 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 124
 125 /* Define the register number for return value.  */
 126 #define NDS32_GPR_RET_FIRST_REGNUM 0
 127
 128 /* Define the first integer register number.  */
 129 #define NDS32_FIRST_GPR_REGNUM 0
 130 /* Define the last integer register number.  */
 131 #define NDS32_LAST_GPR_REGNUM 31
 132
 133 /* Define double word alignment bits.  */
 134 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 135
 136 /* Define alignment checking macros for convenience.  */
 137 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 138 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 139 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 140
 141 /* Get alignment according to mode or type information.
 142    When 'type' is nonnull, there is no need to look at 'mode'.  */
 143 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 144   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 145
 146 /* Round X up to the nearest double word.  */
 147 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 148
 149
 150 /* This macro is used to calculate the numbers of registers for
 151    containing 'size' bytes of the argument.
 152    The size of a register is a word in nds32 target.
 153    So we use UNITS_PER_WORD to do the calculation.  */
 154 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 155   ((mode == BLKmode)                                                     \
 156    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 157    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 158
 159 /* This macro is used to return the register number for passing argument.
 160    We need to obey the following rules:
 161      1. If it is required MORE THAN one register,
 162         we need to further check if it really needs to be
 163         aligned on double words.
 164           a) If double word alignment is necessary,
 165              the register number must be even value.
 166           b) Otherwise, the register number can be odd or even value.
 167      2. If it is required ONLY one register,
 168         the register number can be odd or even value.  */
 169 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 170   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 171    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 172       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 173       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 174    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 175
 176 /* This macro is to check if there are still available registers
 177    for passing argument, which must be entirely in registers.  */
 178 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 179   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 180     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 181    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 182        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 183
 184 /* This macro is to check if there are still available registers
 185    for passing argument, either entirely in registers or partially
 186    in registers.  */
 187 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 188   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 189    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 190
 191 /* This macro is to check if the register is required to be saved on stack.
 192    If call_used_regs[regno] == 0, regno is the callee-saved register.
 193    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 194    As long as the register satisfies both criteria above,
 195    it is required to be saved.  */
 196 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 197   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 198
 199 /* ------------------------------------------------------------------------ */
 200
 201 /* A C structure for machine-specific, per-function data.
 202    This is added to the cfun structure.  */
 203 struct GTY(()) machine_function
 204 {
 205   /* Number of bytes allocated on the stack for variadic args
 206      if we want to push them into stack as pretend arguments by ourself.  */
 207   int va_args_size;
 208   /* Number of bytes reserved on the stack for
 209      local and temporary variables.  */
 210   int local_size;
 211   /* Number of bytes allocated on the stack for outgoing arguments.  */
 212   int out_args_size;
 213
 214   /* Number of bytes on the stack for saving $fp.  */
 215   int fp_size;
 216   /* Number of bytes on the stack for saving $gp.  */
 217   int gp_size;
 218   /* Number of bytes on the stack for saving $lp.  */
 219   int lp_size;
 220
 221   /* Number of bytes on the stack for saving general purpose
 222      callee-saved registers.  */
 223   int callee_saved_gpr_regs_size;
 224
 225   /* The padding bytes in callee-saved area may be required.  */
 226   int callee_saved_area_gpr_padding_bytes;
 227
 228   /* The first required general purpose callee-saved register.  */
 229   int callee_saved_first_gpr_regno;
 230   /* The last required general purpose callee-saved register.  */
 231   int callee_saved_last_gpr_regno;
 232
 233   /* The padding bytes in varargs area may be required.  */
 234   int va_args_area_padding_bytes;
 235
 236   /* The first required register that should be saved on stack for va_args.  */
 237   int va_args_first_regno;
 238   /* The last required register that should be saved on stack for va_args.  */
 239   int va_args_last_regno;
 240
 241   /* Indicate that whether this function needs
 242      prologue/epilogue code generation.  */
 243   int naked_p;
 244   /* Indicate that whether this function
 245      uses fp_as_gp optimization.  */
 246   int fp_as_gp_p;
 247 };
 248
 249 /* A C structure that contains the arguments information.  */
 250 typedef struct
 251 {
 252   unsigned int gpr_offset;
 253 } nds32_cumulative_args;
 254
 255 /* ------------------------------------------------------------------------ */
 256
 257 /* The following we define C-ISR related stuff.
 258    In nds32 architecture, we have 73 vectors for interrupt/exception.
 259    For each vector (except for vector 0, which is used for reset behavior),
 260    we allow users to set its register saving scheme and interrupt level.  */
 261
 262 /* There are 73 vectors in nds32 architecture.
 263    0 for reset handler,
 264    1-8 for exception handler,
 265    and 9-72 for interrupt handler.
 266    We use an array, which is defined in nds32.c, to record
 267    essential information for each vector.  */
 268 #define NDS32_N_ISR_VECTORS 73
 269
 270 /* Define possible isr category.  */
 271 enum nds32_isr_category
 272 {
 273   NDS32_ISR_NONE,
 274   NDS32_ISR_INTERRUPT,
 275   NDS32_ISR_EXCEPTION,
 276   NDS32_ISR_RESET
 277 };
 278
 279 /* Define isr register saving scheme.  */
 280 enum nds32_isr_save_reg
 281 {
 282   NDS32_SAVE_ALL,
 283   NDS32_PARTIAL_SAVE
 284 };
 285
 286 /* Define isr nested type.  */
 287 enum nds32_isr_nested_type
 288 {
 289   NDS32_NESTED,
 290   NDS32_NOT_NESTED,
 291   NDS32_NESTED_READY
 292 };
 293
 294 /* Define structure to record isr information.
 295    The isr vector array 'isr_vectors[]' with this structure
 296    is defined in nds32.c.  */
 297 struct nds32_isr_info
 298 {
 299   /* The field to identify isr category.
 300      It should be set to NDS32_ISR_NONE by default.
 301      If user specifies a function as isr by using attribute,
 302      this field will be set accordingly.  */
 303   enum nds32_isr_category category;
 304
 305   /* A string for the applied function name.
 306      It should be set to empty string by default.  */
 307   char func_name[100];
 308
 309   /* The register saving scheme.
 310      It should be set to NDS32_PARTIAL_SAVE by default
 311      unless user specifies attribute to change it.  */
 312   enum nds32_isr_save_reg save_reg;
 313
 314   /* The nested type.
 315      It should be set to NDS32_NOT_NESTED by default
 316      unless user specifies attribute to change it.  */
 317   enum nds32_isr_nested_type nested_type;
 318
 319   /* Total vectors.
 320      The total vectors = interrupt + exception numbers + reset.
 321      It should be set to 0 by default.
 322      This field is ONLY used in NDS32_ISR_RESET category.  */
 323   unsigned int total_n_vectors;
 324
 325   /* A string for nmi handler name.
 326      It should be set to empty string by default.
 327      This field is ONLY used in NDS32_ISR_RESET category.  */
 328   char nmi_name[100];
 329
 330   /* A string for warm handler name.
 331      It should be set to empty string by default.
 332      This field is ONLY used in NDS32_ISR_RESET category.  */
 333   char warm_name[100];
 334 };
 335
 336 /* ------------------------------------------------------------------------ */
 337
 338 /* Define code for all nds32 builtins.  */
 339 enum nds32_builtins
 340 {
 341   NDS32_BUILTIN_ISYNC,
 342   NDS32_BUILTIN_ISB,
 343   NDS32_BUILTIN_MFSR,
 344   NDS32_BUILTIN_MFUSR,
 345   NDS32_BUILTIN_MTSR,
 346   NDS32_BUILTIN_MTUSR,
 347   NDS32_BUILTIN_SETGIE_EN,
 348   NDS32_BUILTIN_SETGIE_DIS,
 349   NDS32_BUILTIN_COUNT
 350 };
 351
 352 /* ------------------------------------------------------------------------ */
 353
 354 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 355 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 356 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 357
 358 #define TARGET_CMODEL_SMALL \
 359    (nds32_cmodel_option == CMODEL_SMALL)
 360 #define TARGET_CMODEL_MEDIUM \
 361    (nds32_cmodel_option == CMODEL_MEDIUM)
 362 #define TARGET_CMODEL_LARGE \
 363    (nds32_cmodel_option == CMODEL_LARGE)
 364
 365 /* When -mcmodel=small or -mcmodel=medium,
 366    compiler may generate gp-base instruction directly.  */
 367 #define TARGET_GP_DIRECT \
 368    (nds32_cmodel_option == CMODEL_SMALL\
 369     || nds32_cmodel_option == CMODEL_MEDIUM)
 370
 371 #define TARGET_SOFT_FLOAT 1
 372 #define TARGET_HARD_FLOAT 0
 373
 374 /* ------------------------------------------------------------------------ */
 375 \f
 376 /* Controlling the Compilation Driver.  */
 377
 378 #define OPTION_DEFAULT_SPECS \
 379   {"arch", "%{!march=*:-march=%(VALUE)}" }
 380
 381 #define CC1_SPEC \
 382   ""
 383
 384 #define ASM_SPEC \
 385   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 386
 387 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 388 #define LINK_SPEC \
 389   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 390   " %{mrelax:--relax}"
 391
 392 #define LIB_SPEC \
 393   " -lc -lgloss"
 394
 395 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 396    by applying different crt stuff.  In the convention, crt0.o is the
 397    startup file without constructor/destructor;
 398    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 399    startup files with constructor/destructor.
 400    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 401    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 402    currently provided by GCC for nds32 target.
 403
 404    For nds32 target so far:
 405    If -mno-ctor-dtor, we are going to link
 406    "crt0.o [user objects]".
 407    If general cases, we are going to link
 408    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 409 #define STARTFILE_SPEC \
 410   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 411   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 412 #define ENDFILE_SPEC \
 413   " %{!mno-ctor-dtor:crtend1.o%s}"
 414
 415 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 416    configure gcc with --target=nds32be-* setting.
 417    Check gcc/config.gcc for more information.  */
 418 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 419 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 420 #else
 421 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 422 #endif
 423
 424 /* Currently we only have elf toolchain,
 425    where -mcmodel=medium is always the default.  */
 426 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 427
 428 #define MULTILIB_DEFAULTS \
 429   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 430
 431 \f
 432 /* Run-time Target Specification.  */
 433
 434 #define TARGET_CPU_CPP_BUILTINS()                     \
 435   do                                                  \
 436     {                                                 \
 437       builtin_define ("__nds32__");                   \
 438                                                       \
 439       if (TARGET_ISA_V2)                              \
 440         builtin_define ("__NDS32_ISA_V2__");          \
 441       if (TARGET_ISA_V3)                              \
 442         builtin_define ("__NDS32_ISA_V3__");          \
 443       if (TARGET_ISA_V3M)                             \
 444         builtin_define ("__NDS32_ISA_V3M__");         \
 445                                                       \
 446       if (TARGET_BIG_ENDIAN)                          \
 447         builtin_define ("__big_endian__");            \
 448       if (TARGET_REDUCED_REGS)                        \
 449         builtin_define ("__NDS32_REDUCED_REGS__");    \
 450       if (TARGET_CMOV)                                \
 451         builtin_define ("__NDS32_CMOV__");            \
 452       if (TARGET_EXT_PERF)                            \
 453         builtin_define ("__NDS32_EXT_PERF__");        \
 454       if (TARGET_EXT_PERF2)                           \
 455         builtin_define ("__NDS32_EXT_PERF2__");       \
 456       if (TARGET_EXT_STRING)                          \
 457         builtin_define ("__NDS32_EXT_STRING__");      \
 458       if (TARGET_16_BIT)                              \
 459         builtin_define ("__NDS32_16_BIT__");          \
 460       if (TARGET_GP_DIRECT)                           \
 461         builtin_define ("__NDS32_GP_DIRECT__");       \
 462                                                       \
 463       builtin_assert ("cpu=nds32");                   \
 464       builtin_assert ("machine=nds32");               \
 465     } while (0)
 466
 467 \f
 468 /* Defining Data Structures for Per-function Information.  */
 469
 470 /* This macro is called once per function,
 471    before generation of any RTL has begun.  */
 472 #define INIT_EXPANDERS  nds32_init_expanders ()
 473
 474 \f
 475 /* Storage Layout.  */
 476
 477 #define BITS_BIG_ENDIAN 0
 478
 479 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 480
 481 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 482
 483 #define UNITS_PER_WORD 4
 484
 485 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 486   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 487     {                                                                       \
 488       (m) = SImode;                                                         \
 489     }
 490
 491 #define PARM_BOUNDARY 32
 492
 493 #define STACK_BOUNDARY 64
 494
 495 #define FUNCTION_BOUNDARY 32
 496
 497 #define BIGGEST_ALIGNMENT 64
 498
 499 #define EMPTY_FIELD_BOUNDARY 32
 500
 501 #define STRUCTURE_SIZE_BOUNDARY 8
 502
 503 #define STRICT_ALIGNMENT 1
 504
 505 #define PCC_BITFIELD_TYPE_MATTERS 1
 506
 507 \f
 508 /* Layout of Source Language Data Types.  */
 509
 510 #define INT_TYPE_SIZE           32
 511 #define SHORT_TYPE_SIZE         16
 512 #define LONG_TYPE_SIZE          32
 513 #define LONG_LONG_TYPE_SIZE     64
 514
 515 #define FLOAT_TYPE_SIZE         32
 516 #define DOUBLE_TYPE_SIZE        64
 517 #define LONG_DOUBLE_TYPE_SIZE   64
 518
 519 #define DEFAULT_SIGNED_CHAR 1
 520
 521 #define SIZE_TYPE "long unsigned int"
 522 #define PTRDIFF_TYPE "long int"
 523 #define WCHAR_TYPE "short unsigned int"
 524 #define WCHAR_TYPE_SIZE 16
 525
 526 \f
 527 /* Register Usage.  */
 528
 529 /* Number of actual hardware registers.
 530    The hardware registers are assigned numbers for the compiler
 531    from 0 to just below FIRST_PSEUDO_REGISTER.
 532    All registers that the compiler knows about must be given numbers,
 533    even those that are not normally considered general registers.  */
 534 #define FIRST_PSEUDO_REGISTER 101
 535
 536 /* An initializer that says which registers are used for fixed
 537    purposes all throughout the compiled code and are therefore
 538    not available for general allocation.
 539
 540    $r28 : $fp
 541    $r29 : $gp
 542    $r30 : $lp
 543    $r31 : $sp
 544
 545    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 546    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 547
 548    reserved for assembler : $r15
 549    reserved for other use : $r24, $r25, $r26, $r27 */
 550 #define FIXED_REGISTERS \
 551 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 552       0,   0,   0,   0,   0,   0,   0,   0,     \
 553   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 554       0,   0,   0,   0,   0,   0,   0,   1,     \
 555   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 556       0,   0,   0,   0,   0,   0,   0,   0,     \
 557   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 558       1,   1,   1,   1,   0,   1,   0,   1,     \
 559   /* AP   FP    Reserved.................... */ \
 560       1,   1,   1,   1,   1,   1,   1,   1,     \
 561   /* Reserved............................... */ \
 562       1,   1,   1,   1,   1,   1,   1,   1,     \
 563   /* Reserved............................... */ \
 564       1,   1,   1,   1,   1,   1,   1,   1,     \
 565   /* Reserved............................... */ \
 566       1,   1,   1,   1,   1,   1,   1,   1,     \
 567   /* Reserved............................... */ \
 568       1,   1,   1,   1,   1,   1,   1,   1,     \
 569   /* Reserved............................... */ \
 570       1,   1,   1,   1,   1,   1,   1,   1,     \
 571   /* Reserved............................... */ \
 572       1,   1,   1,   1,   1,   1,   1,   1,     \
 573   /* Reserved............................... */ \
 574       1,   1,   1,   1,   1,   1,   1,   1,     \
 575   /* Reserved............................... */ \
 576       1,   1,   1,   1,   1                     \
 577 }
 578
 579 /* Identifies the registers that are not available for
 580    general allocation of values that must live across
 581    function calls -- so they are caller-save registers.
 582
 583    0 : callee-save registers
 584    1 : caller-save registers */
 585 #define CALL_USED_REGISTERS \
 586 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 587       1,   1,   1,   1,   1,   1,   0,   0,     \
 588   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 589       0,   0,   0,   0,   0,   0,   0,   1,     \
 590   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 591       1,   1,   1,   1,   1,   1,   1,   1,     \
 592   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 593       1,   1,   1,   1,   0,   1,   0,   1,     \
 594   /* AP   FP    Reserved.................... */ \
 595       1,   1,   1,   1,   1,   1,   1,   1,     \
 596   /* Reserved............................... */ \
 597       1,   1,   1,   1,   1,   1,   1,   1,     \
 598   /* Reserved............................... */ \
 599       1,   1,   1,   1,   1,   1,   1,   1,     \
 600   /* Reserved............................... */ \
 601       1,   1,   1,   1,   1,   1,   1,   1,     \
 602   /* Reserved............................... */ \
 603       1,   1,   1,   1,   1,   1,   1,   1,     \
 604   /* Reserved............................... */ \
 605       1,   1,   1,   1,   1,   1,   1,   1,     \
 606   /* Reserved............................... */ \
 607       1,   1,   1,   1,   1,   1,   1,   1,     \
 608   /* Reserved............................... */ \
 609       1,   1,   1,   1,   1,   1,   1,   1,     \
 610   /* Reserved............................... */ \
 611       1,   1,   1,   1,   1                     \
 612 }
 613
 614 /* In nds32 target, we have three levels of registers:
 615      LOW_COST_REGS    : $r0 ~ $r7
 616      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 617      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 618 #define REG_ALLOC_ORDER \
 619 {   0,   1,   2,   3,   4,   5,   6,   7, \
 620    16,  17,  18,  19,   9,  10,  11,  12, \
 621    13,  14,  8,   15,  20,  21,  22,  23, \
 622    24,  25,  26,  27,  28,  29,  30,  31, \
 623    32,  33,  34,  35,  36,  37,  38,  39, \
 624    40,  41,  42,  43,  44,  45,  46,  47, \
 625    48,  49,  50,  51,  52,  53,  54,  55, \
 626    56,  57,  58,  59,  60,  61,  62,  63, \
 627    64,  65,  66,  67,  68,  69,  70,  71, \
 628    72,  73,  74,  75,  76,  77,  78,  79, \
 629    80,  81,  82,  83,  84,  85,  86,  87, \
 630    88,  89,  90,  91,  92,  93,  94,  95, \
 631    96,  97,  98,  99, 100,                \
 632 }
 633
 634 /* Tell IRA to use the order we define rather than messing it up with its
 635    own cost calculations.  */
 636 #define HONOR_REG_ALLOC_ORDER optimize_size
 637
 638 \f
 639 /* Register Classes.  */
 640
 641 /* In nds32 target, we have three levels of registers:
 642      Low cost regsiters    : $r0 ~ $r7
 643      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 644      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 645
 646    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 647    so that it provides more chance to use low cost registers.  */
 648 enum reg_class
 649 {
 650   NO_REGS,
 651   R5_REG,
 652   R8_REG,
 653   R15_TA_REG,
 654   STACK_REG,
 655   FRAME_POINTER_REG,
 656   LOW_REGS,
 657   MIDDLE_REGS,
 658   HIGH_REGS,
 659   GENERAL_REGS,
 660   FRAME_REGS,
 661   ALL_REGS,
 662   LIM_REG_CLASSES
 663 };
 664
 665 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 666
 667 #define REG_CLASS_NAMES \
 668 {                       \
 669   "NO_REGS",            \
 670   "R5_REG",             \
 671   "R8_REG",             \
 672   "R15_TA_REG",         \
 673   "STACK_REG",          \
 674   "FRAME_POINTER_REG",  \
 675   "LOW_REGS",           \
 676   "MIDDLE_REGS",        \
 677   "HIGH_REGS",          \
 678   "GENERAL_REGS",       \
 679   "FRAME_REGS",         \
 680   "ALL_REGS"            \
 681 }
 682
 683 #define REG_CLASS_CONTENTS \
 684 { /* NO_REGS                                    */  \
 685   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
 686   /* R5_REG              : 5                    */  \
 687   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
 688   /* R8_REG              : 8                    */  \
 689   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
 690   /* R15_TA_REG          : 15                   */  \
 691   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
 692   /* STACK_REG           : 31                   */  \
 693   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
 694   /* FRAME_POINTER_REG   : 28                   */  \
 695   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
 696   /* LOW_REGS            : 0-7                  */  \
 697   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
 698   /* MIDDLE_REGS         : 0-11, 16-19          */  \
 699   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
 700   /* HIGH_REGS           : 12-14, 20-31         */  \
 701   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
 702   /* GENERAL_REGS        : 0-31                 */  \
 703   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
 704   /* FRAME_REGS          : 32, 33               */  \
 705   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
 706   /* ALL_REGS            : 0-100                */  \
 707   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
 708 }
 709
 710 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 711
 712 #define BASE_REG_CLASS GENERAL_REGS
 713 #define INDEX_REG_CLASS GENERAL_REGS
 714
 715 /* Return nonzero if it is suitable for use as a
 716    base register in operand addresses.
 717    So far, we return nonzero only if "num" is a hard reg
 718    of the suitable class or a pseudo register which is
 719    allocated to a suitable hard reg.  */
 720 #define REGNO_OK_FOR_BASE_P(num) \
 721   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 722
 723 /* Return nonzero if it is suitable for use as a
 724    index register in operand addresses.
 725    So far, we return nonzero only if "num" is a hard reg
 726    of the suitable class or a pseudo register which is
 727    allocated to a suitable hard reg.
 728    The difference between an index register and a base register is that
 729    the index register may be scaled.  */
 730 #define REGNO_OK_FOR_INDEX_P(num) \
 731   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 732
 733 \f
 734 /* Obsolete Macros for Defining Constraints.  */
 735
 736 \f
 737 /* Stack Layout and Calling Conventions.  */
 738
 739 #define STACK_GROWS_DOWNWARD 1
 740
 741 #define FRAME_GROWS_DOWNWARD 1
 742
 743 #define STACK_POINTER_OFFSET 0
 744
 745 #define FIRST_PARM_OFFSET(fundecl) \
 746   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 747
 748 #define RETURN_ADDR_RTX(count, frameaddr) \
 749   nds32_return_addr_rtx (count, frameaddr)
 750
 751 /* A C expression whose value is RTL representing the location
 752    of the incoming return address at the beginning of any function
 753    before the prologue.
 754    If this RTL is REG, you should also define
 755    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 756 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 757 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 758
 759 #define STACK_POINTER_REGNUM SP_REGNUM
 760
 761 #define FRAME_POINTER_REGNUM 33
 762
 763 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 764
 765 #define ARG_POINTER_REGNUM 32
 766
 767 #define STATIC_CHAIN_REGNUM 16
 768
 769 #define ELIMINABLE_REGS                                \
 770 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 771   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 772   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 773   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 774
 775 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 776   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 777
 778 #define ACCUMULATE_OUTGOING_ARGS 1
 779
 780 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 781
 782 #define CUMULATIVE_ARGS nds32_cumulative_args
 783
 784 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 785   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 786
 787 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 788    We better cast REGNO into signed integer so that we can avoid
 789    'comparison of unsigned expression >= 0 is always true' warning.  */
 790 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 791   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 792    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
 793
 794 #define DEFAULT_PCC_STRUCT_RETURN 0
 795
 796 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 797    from a function, the stack pointer does not matter.
 798    The value is tested only in functions that have frame pointers.
 799    In nds32 target, the function epilogue recovers the
 800    stack pointer from the frame.  */
 801 #define EXIT_IGNORE_STACK 1
 802
 803 #define FUNCTION_PROFILER(file, labelno) \
 804   fprintf (file, "/* profiler %d */", (labelno))
 805
 806 \f
 807 /* Implementing the Varargs Macros.  */
 808
 809 \f
 810 /* Trampolines for Nested Functions.  */
 811
 812 /* Giving A-function and B-function,
 813    if B-function wants to call A-function's nested function,
 814    we need to fill trampoline code into A-function's stack
 815    so that B-function can execute the code in stack to indirectly
 816    jump to (like 'trampoline' action) desired nested function.
 817
 818    The trampoline code for nds32 target must contains following parts:
 819
 820      1. instructions (4 * 4 = 16 bytes):
 821           get $pc first
 822           load chain_value to static chain register via $pc
 823           load nested function address to $r15 via $pc
 824           jump to desired nested function via $r15
 825      2. data (4 * 2 = 8 bytes):
 826           chain_value
 827           nested function address
 828
 829    Please check nds32.c implementation for more information.  */
 830 #define TRAMPOLINE_SIZE 24
 831
 832 /* Because all instructions/data in trampoline template are 4-byte size,
 833    we set trampoline alignment 8*4=32 bits.  */
 834 #define TRAMPOLINE_ALIGNMENT 32
 835
 836 \f
 837 /* Implicit Calls to Library Routines.  */
 838
 839 \f
 840 /* Addressing Modes.  */
 841
 842 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 843 #define HAVE_POST_INCREMENT 1
 844 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 845 #define HAVE_POST_DECREMENT 1
 846
 847 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 848 #define HAVE_POST_MODIFY_DISP 1
 849 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 850 #define HAVE_POST_MODIFY_REG  1
 851
 852 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 853
 854 #define MAX_REGS_PER_ADDRESS 2
 855
 856 \f
 857 /* Anchored Addresses.  */
 858
 859 \f
 860 /* Condition Code Status.  */
 861
 862 \f
 863 /* Describing Relative Costs of Operations.  */
 864
 865 /* A C expression for the cost of a branch instruction.
 866    A value of 1 is the default;
 867    other values are interpreted relative to that.  */
 868 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
 869
 870 #define SLOW_BYTE_ACCESS 1
 871
 872 #define NO_FUNCTION_CSE 1
 873
 874 \f
 875 /* Adjusting the Instruction Scheduler.  */
 876
 877 \f
 878 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 879
 880 #define TEXT_SECTION_ASM_OP     "\t.text"
 881 #define DATA_SECTION_ASM_OP     "\t.data"
 882
 883 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 884    So we use '.section .bss' alternatively.  */
 885 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 886
 887 /* Define this macro to be an expression with a nonzero value if jump tables
 888    (for tablejump insns) should be output in the text section,
 889    along with the assembler instructions.
 890    Otherwise, the readonly data section is used.  */
 891 #define JUMP_TABLES_IN_TEXT_SECTION 1
 892
 893 \f
 894 /* Position Independent Code.  */
 895
 896 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
 897
 898 \f
 899 /* Defining the Output Assembler Language.  */
 900
 901 #define ASM_COMMENT_START "!"
 902
 903 #define ASM_APP_ON "! #APP"
 904
 905 #define ASM_APP_OFF "! #NO_APP\n"
 906
 907 #define ASM_OUTPUT_LABELREF(stream, name) \
 908   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 909
 910 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 911   assemble_name (stream, XSTR (sym, 0))
 912
 913 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 914   assemble_name (stream, buf)
 915
 916 #define LOCAL_LABEL_PREFIX "."
 917
 918 #define REGISTER_NAMES \
 919 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 920   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 921   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 922   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 923   "$AP",  "$SFP", "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 924   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 925   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 926   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 927   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 928   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 929   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 930   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 931   "NA",   "NA",   "NA",   "NA",   "NA"                            \
 932 }
 933
 934 /* Output normal jump table entry.  */
 935 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 936   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 937
 938 /* Output pc relative jump table entry.  */
 939 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 940   do                                                                    \
 941     {                                                                   \
 942       switch (GET_MODE (body))                                          \
 943         {                                                               \
 944         case E_QImode:                                                    \
 945           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 946           break;                                                        \
 947         case E_HImode:                                                    \
 948           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 949           break;                                                        \
 950         case E_SImode:                                                    \
 951           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 952           break;                                                        \
 953         default:                                                        \
 954           gcc_unreachable();                                            \
 955         }                                                               \
 956     } while (0)
 957
 958 /* We have to undef it first because elfos.h formerly define it
 959    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 960 #undef  ASM_OUTPUT_CASE_LABEL
 961 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 962   do                                                               \
 963     {                                                              \
 964       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 965       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 966     } while (0)
 967
 968 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 969   do                                                   \
 970     {                                                  \
 971       /* Because our jump table is in text section,    \
 972          we need to make sure 2-byte alignment after   \
 973          the jump table for instructions fetch.  */    \
 974       if (GET_MODE (PATTERN (table)) == QImode)        \
 975         ASM_OUTPUT_ALIGN (stream, 1);                  \
 976       asm_fprintf (stream, "\t! Jump Table End\n");    \
 977     }  while (0)
 978
 979 /* This macro is not documented yet.
 980    But we do need it to make jump table vector aligned.  */
 981 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
 982
 983 #define DWARF2_UNWIND_INFO 1
 984
 985 #define JUMP_ALIGN(x) \
 986   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
 987
 988 #define LOOP_ALIGN(x) \
 989   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
 990
 991 #define LABEL_ALIGN(x) \
 992   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
 993
 994 #define ASM_OUTPUT_ALIGN(stream, power) \
 995   fprintf (stream, "\t.align\t%d\n", power)
 996
 997 \f
 998 /* Controlling Debugging Information Format.  */
 999
1000 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1001
1002 #define DWARF2_DEBUGGING_INFO 1
1003
1004 #define DWARF2_ASM_LINE_DEBUG_INFO 1
1005
1006 \f
1007 /* Cross Compilation and Floating Point.  */
1008
1009 \f
1010 /* Mode Switching Instructions.  */
1011
1012 \f
1013 /* Defining target-specific uses of __attribute__.  */
1014
1015 \f
1016 /* Emulating TLS.  */
1017
1018 \f
1019 /* Defining coprocessor specifics for MIPS targets.  */
1020
1021 \f
1022 /* Parameters for Precompiled Header Validity Checking.  */
1023
1024 \f
1025 /* C++ ABI parameters.  */
1026
1027 \f
1028 /* Adding support for named address spaces.  */
1029
1030 \f
1031 /* Miscellaneous Parameters.  */
1032
1033 /* This is the machine mode that elements of a jump-table should have.  */
1034 #define CASE_VECTOR_MODE Pmode
1035
1036 /* Return the preferred mode for and addr_diff_vec when the mininum
1037    and maximum offset are known.  */
1038 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1039    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
1040    : (max_offset >= 100) ? HImode                               \
1041    : QImode)
1042
1043 /* Generate pc relative jump table when -fpic or -Os.  */
1044 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1045
1046 /* Define this macro if operations between registers with integral mode
1047    smaller than a word are always performed on the entire register.  */
1048 #define WORD_REGISTER_OPERATIONS 1
1049
1050 /* A C expression indicating when insns that read memory in mem_mode,
1051    an integral mode narrower than a word, set the bits outside of mem_mode
1052    to be either the sign-extension or the zero-extension of the data read.  */
1053 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1054
1055 /* The maximum number of bytes that a single instruction can move quickly
1056    between memory and registers or between two memory locations.  */
1057 #define MOVE_MAX 4
1058
1059 /* A C expression that is nonzero if on this machine the number of bits
1060    actually used for the count of a shift operation is equal to the number
1061    of bits needed to represent the size of the object being shifted.  */
1062 #define SHIFT_COUNT_TRUNCATED 1
1063
1064 /* A C expression describing the value returned by a comparison operator with
1065    an integral mode and stored by a store-flag instruction ('cstoremode4')
1066    when the condition is true.  */
1067 #define STORE_FLAG_VALUE 1
1068
1069 /* An alias for the machine mode for pointers.  */
1070 #define Pmode SImode
1071
1072 /* An alias for the machine mode used for memory references to functions
1073    being called, in call RTL expressions.  */
1074 #define FUNCTION_MODE SImode
1075
1076 /* ------------------------------------------------------------------------ */