gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  28   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  29
  30 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  31    It is used in nds32_encode_section_info() to store flag in symbol_ref
  32    in case the symbol should be placed in .rodata section.
  33    So that we can check it in nds32_legitimate_address_p().  */
  34 #define NDS32_SYMBOL_FLAG_RODATA \
  35   (SYMBOL_FLAG_MACH_DEP << 0)
  36 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  37   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  38
  39 /* Classifies expand result for expand helper function.  */
  40 enum nds32_expand_result_type
  41 {
  42   EXPAND_DONE,
  43   EXPAND_FAIL,
  44   EXPAND_CREATE_TEMPLATE
  45 };
  46
  47 /* Classifies address type to distinguish 16-bit/32-bit format.  */
  48 enum nds32_16bit_address_type
  49 {
  50   /* [reg]: 45 format address.  */
  51   ADDRESS_REG,
  52   /* [lo_reg + imm3u]: 333 format address.  */
  53   ADDRESS_LO_REG_IMM3U,
  54   /* post_inc [lo_reg + imm3u]: 333 format address.  */
  55   ADDRESS_POST_INC_LO_REG_IMM3U,
  56   /* post_modify [lo_reg + imm3u]: 333 format address.  */
  57   ADDRESS_POST_MODIFY_LO_REG_IMM3U,
  58   /* [$r8 + imm7u]: r8 imply address.  */
  59   ADDRESS_R8_IMM7U,
  60   /* [$fp + imm7u]: fp imply address.  */
  61   ADDRESS_FP_IMM7U,
  62   /* [$sp + imm7u]: sp imply address.  */
  63   ADDRESS_SP_IMM7U,
  64   /* Other address format.  */
  65   ADDRESS_NOT_16BIT_FORMAT
  66 };
  67
  68
  69 /* ------------------------------------------------------------------------ */
  70
  71 /* Define maximum numbers of registers for passing arguments.  */
  72 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
  73 #define NDS32_MAX_FPR_REGS_FOR_ARGS 6
  74
  75 /* Define the register number for first argument.  */
  76 #define NDS32_GPR_ARG_FIRST_REGNUM 0
  77 #define NDS32_FPR_ARG_FIRST_REGNUM 34
  78
  79 /* Define the register number for return value.  */
  80 #define NDS32_GPR_RET_FIRST_REGNUM 0
  81 #define NDS32_FPR_RET_FIRST_REGNUM 34
  82
  83 /* Define the first integer register number.  */
  84 #define NDS32_FIRST_GPR_REGNUM 0
  85 /* Define the last integer register number.  */
  86 #define NDS32_LAST_GPR_REGNUM 31
  87
  88 #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
  89 #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
  90   (TARGET_REDUCED_REGS ? 10 : 14)
  91
  92 /* Define the floating-point number of registers.  */
  93 #define NDS32_FLOAT_REGISTER_NUMBER                           \
  94  (((nds32_fp_regnum == NDS32_CONFIG_FPU_0)              \
  95    || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8      \
  96   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1)            \
  97     || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16    \
  98   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2)            \
  99     || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32    \
 100   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3)            \
 101     || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64    \
 102   : 32)
 103
 104 #define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
 105
 106 /* Define the first floating-point register number.  */
 107 #define NDS32_FIRST_FPR_REGNUM 34
 108 /* Define the last floating-point register number.  */
 109 #define NDS32_LAST_FPR_REGNUM \
 110   (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
 111
 112
 113 #define NDS32_IS_EXT_FPR_REGNUM(regno) \
 114   (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
 115    && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
 116
 117 #define NDS32_IS_FPR_REGNUM(regno) \
 118   (((regno) >= NDS32_FIRST_FPR_REGNUM) \
 119    && ((regno) <= NDS32_LAST_FPR_REGNUM))
 120
 121 #define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
 122   ((regno) <= NDS32_LAST_FPR_REGNUM)
 123
 124 #define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
 125   ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
 126
 127 #define NDS32_IS_GPR_REGNUM(regno) \
 128   (((regno) <= NDS32_LAST_GPR_REGNUM))
 129
 130 /* Define double word alignment bits.  */
 131 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 132
 133 /* Define alignment checking macros for convenience.  */
 134 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 135 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 136 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 137
 138 /* Determine whether we would like to have code generation strictly aligned.
 139    We set it strictly aligned when -malways-align is enabled.
 140    Check gcc/common/config/nds32/nds32-common.c for the optimizations that
 141    apply -malways-align.  */
 142 #define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
 143
 144 #define NDS32_EXT_DSP_P() (TARGET_EXT_DSP && !TARGET_FORCE_NO_EXT_DSP)
 145
 146 /* Get alignment according to mode or type information.
 147    When 'type' is nonnull, there is no need to look at 'mode'.  */
 148 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 149   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 150
 151 /* Round X up to the nearest double word.  */
 152 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 153
 154
 155 /* This macro is used to calculate the numbers of registers for
 156    containing 'size' bytes of the argument.
 157    The size of a register is a word in nds32 target.
 158    So we use UNITS_PER_WORD to do the calculation.  */
 159 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 160   ((mode == BLKmode)                                                     \
 161    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 162    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 163
 164 /* This macro is used to return the register number for passing argument.
 165    We need to obey the following rules:
 166      1. If it is required MORE THAN one register,
 167         we need to further check if it really needs to be
 168         aligned on double words.
 169           a) If double word alignment is necessary,
 170              the register number must be even value.
 171           b) Otherwise, the register number can be odd or even value.
 172      2. If it is required ONLY one register,
 173         the register number can be odd or even value.  */
 174 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 175   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 176    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 177       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 178       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 179    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 180
 181 #define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
 182   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 183    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 184       ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 185       : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))               \
 186    : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
 187
 188 /* These two macros are to check if there are still available registers
 189    for passing argument, which must be entirely in registers.  */
 190 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 191   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 192     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 193    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 194        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 195
 196 #define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type)   \
 197   ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 198     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 199    <= (NDS32_FPR_ARG_FIRST_REGNUM                               \
 200        + NDS32_MAX_FPR_REGS_FOR_ARGS))
 201
 202 /* These two macros are to check if there are still available registers
 203    for passing argument, either entirely in registers or partially
 204    in registers.  */
 205 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 206   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 207    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 208
 209 #define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
 210   (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 211    < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
 212
 213 /* This macro is to check if the register is required to be saved on stack.
 214    If call_used_regs[regno] == 0, regno is the callee-saved register.
 215    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 216    As long as the register satisfies both criteria above,
 217    it is required to be saved.  */
 218 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 219   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 220
 221 /* This macro is to check if the push25/pop25 are available to be used
 222    for code generation.  Because pop25 also performs return behavior,
 223    the instructions may not be available for some cases.
 224    If we want to use push25/pop25, all the following conditions must
 225    be satisfied:
 226      1. TARGET_V3PUSH is set.
 227      2. Current function is not an ISR function.
 228      3. Current function is not a variadic function.*/
 229 #define NDS32_V3PUSH_AVAILABLE_P  \
 230   (TARGET_V3PUSH \
 231    && !nds32_isr_function_p (current_function_decl) \
 232    && (cfun->machine->va_args_size == 0))
 233
 234 /* ------------------------------------------------------------------------ */
 235
 236 /* A C structure for machine-specific, per-function data.
 237    This is added to the cfun structure.  */
 238 struct GTY(()) machine_function
 239 {
 240   /* Number of bytes allocated on the stack for variadic args
 241      if we want to push them into stack as pretend arguments by ourself.  */
 242   int va_args_size;
 243   /* Number of bytes reserved on the stack for
 244      local and temporary variables.  */
 245   int local_size;
 246   /* Number of bytes allocated on the stack for outgoing arguments.  */
 247   int out_args_size;
 248
 249   /* Number of bytes on the stack for saving $fp.  */
 250   int fp_size;
 251   /* Number of bytes on the stack for saving $gp.  */
 252   int gp_size;
 253   /* Number of bytes on the stack for saving $lp.  */
 254   int lp_size;
 255
 256   /* Number of bytes on the stack for saving general purpose
 257      callee-saved registers.  */
 258   int callee_saved_gpr_regs_size;
 259
 260   /* Number of bytes on the stack for saving floating-point
 261      callee-saved registers.  */
 262   int callee_saved_fpr_regs_size;
 263
 264   /* The padding bytes in callee-saved area may be required.  */
 265   int callee_saved_area_gpr_padding_bytes;
 266
 267   /* The first required general purpose callee-saved register.  */
 268   int callee_saved_first_gpr_regno;
 269   /* The last required general purpose callee-saved register.  */
 270   int callee_saved_last_gpr_regno;
 271
 272   /* The first required floating-point callee-saved register.  */
 273   int callee_saved_first_fpr_regno;
 274   /* The last required floating-point callee-saved register.  */
 275   int callee_saved_last_fpr_regno;
 276
 277   /* The padding bytes in varargs area may be required.  */
 278   int va_args_area_padding_bytes;
 279
 280   /* The first required register that should be saved on stack for va_args.  */
 281   int va_args_first_regno;
 282   /* The last required register that should be saved on stack for va_args.  */
 283   int va_args_last_regno;
 284
 285   /* Number of bytes on the stack for saving exception handling registers.  */
 286   int eh_return_data_regs_size;
 287   /* The first register of passing exception handling information.  */
 288   int eh_return_data_first_regno;
 289   /* The last register of passing exception handling information.  */
 290   int eh_return_data_last_regno;
 291
 292   /* Indicate that whether this function
 293      calls __builtin_eh_return.  */
 294   int use_eh_return_p;
 295
 296   /* Indicate that whether this function needs
 297      prologue/epilogue code generation.  */
 298   int naked_p;
 299   /* Indicate that whether this function
 300      uses fp_as_gp optimization.  */
 301   int fp_as_gp_p;
 302   /* Indicate that whether this function is under strictly aligned
 303      situation for legitimate address checking.  This flag informs
 304      nds32_legitimate_address_p() how to treat offset alignment:
 305        1. The IVOPT phase needs to detect available range for memory access,
 306           such as checking [base + 32767] ~ [base + (-32768)].
 307           For this case we do not want address to be strictly aligned.
 308        2. The rtl lowering and optimization are close to target code.
 309           For this case we need address to be strictly aligned.  */
 310   int strict_aligned_p;
 311 };
 312
 313 /* A C structure that contains the arguments information.  */
 314 typedef struct
 315 {
 316   unsigned int gpr_offset;
 317   unsigned int fpr_offset;
 318 } nds32_cumulative_args;
 319
 320 /* ------------------------------------------------------------------------ */
 321
 322 /* The following we define C-ISR related stuff.
 323    In nds32 architecture, we have 73 vectors for interrupt/exception.
 324    For each vector (except for vector 0, which is used for reset behavior),
 325    we allow users to set its register saving scheme and interrupt level.  */
 326
 327 /* There are 73 vectors in nds32 architecture.
 328    0 for reset handler,
 329    1-8 for exception handler,
 330    and 9-72 for interrupt handler.
 331    We use an array, which is defined in nds32.c, to record
 332    essential information for each vector.  */
 333 #define NDS32_N_ISR_VECTORS 73
 334
 335 /* Define possible isr category.  */
 336 enum nds32_isr_category
 337 {
 338   NDS32_ISR_NONE,
 339   NDS32_ISR_INTERRUPT,
 340   NDS32_ISR_EXCEPTION,
 341   NDS32_ISR_RESET
 342 };
 343
 344 /* Define isr register saving scheme.  */
 345 enum nds32_isr_save_reg
 346 {
 347   NDS32_SAVE_ALL,
 348   NDS32_PARTIAL_SAVE
 349 };
 350
 351 /* Define isr nested type.  */
 352 enum nds32_isr_nested_type
 353 {
 354   NDS32_NESTED,
 355   NDS32_NOT_NESTED,
 356   NDS32_NESTED_READY
 357 };
 358
 359 /* Define structure to record isr information.
 360    The isr vector array 'isr_vectors[]' with this structure
 361    is defined in nds32.c.  */
 362 struct nds32_isr_info
 363 {
 364   /* The field to identify isr category.
 365      It should be set to NDS32_ISR_NONE by default.
 366      If user specifies a function as isr by using attribute,
 367      this field will be set accordingly.  */
 368   enum nds32_isr_category category;
 369
 370   /* A string for the applied function name.
 371      It should be set to empty string by default.  */
 372   char func_name[100];
 373
 374   /* The register saving scheme.
 375      It should be set to NDS32_PARTIAL_SAVE by default
 376      unless user specifies attribute to change it.  */
 377   enum nds32_isr_save_reg save_reg;
 378
 379   /* The nested type.
 380      It should be set to NDS32_NOT_NESTED by default
 381      unless user specifies attribute to change it.  */
 382   enum nds32_isr_nested_type nested_type;
 383
 384   /* Total vectors.
 385      The total vectors = interrupt + exception numbers + reset.
 386      It should be set to 0 by default.
 387      This field is ONLY used in NDS32_ISR_RESET category.  */
 388   unsigned int total_n_vectors;
 389
 390   /* A string for nmi handler name.
 391      It should be set to empty string by default.
 392      This field is ONLY used in NDS32_ISR_RESET category.  */
 393   char nmi_name[100];
 394
 395   /* A string for warm handler name.
 396      It should be set to empty string by default.
 397      This field is ONLY used in NDS32_ISR_RESET category.  */
 398   char warm_name[100];
 399 };
 400
 401 /* ------------------------------------------------------------------------ */
 402
 403 /* Define code for all nds32 builtins.  */
 404 enum nds32_builtins
 405 {
 406   NDS32_BUILTIN_ISYNC,
 407   NDS32_BUILTIN_ISB,
 408   NDS32_BUILTIN_DSB,
 409   NDS32_BUILTIN_MSYNC_ALL,
 410   NDS32_BUILTIN_MSYNC_STORE,
 411   NDS32_BUILTIN_MFSR,
 412   NDS32_BUILTIN_MFUSR,
 413   NDS32_BUILTIN_MTSR,
 414   NDS32_BUILTIN_MTSR_ISB,
 415   NDS32_BUILTIN_MTSR_DSB,
 416   NDS32_BUILTIN_MTUSR,
 417   NDS32_BUILTIN_SETGIE_EN,
 418   NDS32_BUILTIN_SETGIE_DIS,
 419   NDS32_BUILTIN_FMFCFG,
 420   NDS32_BUILTIN_FMFCSR,
 421   NDS32_BUILTIN_FMTCSR,
 422   NDS32_BUILTIN_FCPYNSS,
 423   NDS32_BUILTIN_FCPYSS,
 424   NDS32_BUILTIN_FCPYNSD,
 425   NDS32_BUILTIN_FCPYSD,
 426   NDS32_BUILTIN_ABS,
 427   NDS32_BUILTIN_AVE,
 428   NDS32_BUILTIN_BCLR,
 429   NDS32_BUILTIN_BSET,
 430   NDS32_BUILTIN_BTGL,
 431   NDS32_BUILTIN_BTST,
 432   NDS32_BUILTIN_CLIP,
 433   NDS32_BUILTIN_CLIPS,
 434   NDS32_BUILTIN_CLZ,
 435   NDS32_BUILTIN_CLO,
 436   NDS32_BUILTIN_MAX,
 437   NDS32_BUILTIN_MIN,
 438   NDS32_BUILTIN_PBSAD,
 439   NDS32_BUILTIN_PBSADA,
 440   NDS32_BUILTIN_BSE,
 441   NDS32_BUILTIN_BSP,
 442   NDS32_BUILTIN_FFB,
 443   NDS32_BUILTIN_FFMISM,
 444   NDS32_BUILTIN_FLMISM,
 445   NDS32_BUILTIN_KADDW,
 446   NDS32_BUILTIN_KSUBW,
 447   NDS32_BUILTIN_KADDH,
 448   NDS32_BUILTIN_KSUBH,
 449   NDS32_BUILTIN_KDMBB,
 450   NDS32_BUILTIN_V_KDMBB,
 451   NDS32_BUILTIN_KDMBT,
 452   NDS32_BUILTIN_V_KDMBT,
 453   NDS32_BUILTIN_KDMTB,
 454   NDS32_BUILTIN_V_KDMTB,
 455   NDS32_BUILTIN_KDMTT,
 456   NDS32_BUILTIN_V_KDMTT,
 457   NDS32_BUILTIN_KHMBB,
 458   NDS32_BUILTIN_V_KHMBB,
 459   NDS32_BUILTIN_KHMBT,
 460   NDS32_BUILTIN_V_KHMBT,
 461   NDS32_BUILTIN_KHMTB,
 462   NDS32_BUILTIN_V_KHMTB,
 463   NDS32_BUILTIN_KHMTT,
 464   NDS32_BUILTIN_V_KHMTT,
 465   NDS32_BUILTIN_KSLRAW,
 466   NDS32_BUILTIN_KSLRAW_U,
 467   NDS32_BUILTIN_RDOV,
 468   NDS32_BUILTIN_CLROV,
 469   NDS32_BUILTIN_ROTR,
 470   NDS32_BUILTIN_SVA,
 471   NDS32_BUILTIN_SVS,
 472   NDS32_BUILTIN_WSBH,
 473   NDS32_BUILTIN_JR_ITOFF,
 474   NDS32_BUILTIN_JR_TOFF,
 475   NDS32_BUILTIN_JRAL_ITON,
 476   NDS32_BUILTIN_JRAL_TON,
 477   NDS32_BUILTIN_RET_ITOFF,
 478   NDS32_BUILTIN_RET_TOFF,
 479   NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
 480   NDS32_BUILTIN_STANDBY_WAKE_GRANT,
 481   NDS32_BUILTIN_STANDBY_WAKE_DONE,
 482   NDS32_BUILTIN_TEQZ,
 483   NDS32_BUILTIN_TNEZ,
 484   NDS32_BUILTIN_TRAP,
 485   NDS32_BUILTIN_SETEND_BIG,
 486   NDS32_BUILTIN_SETEND_LITTLE,
 487   NDS32_BUILTIN_SYSCALL,
 488   NDS32_BUILTIN_BREAK,
 489   NDS32_BUILTIN_NOP,
 490   NDS32_BUILTIN_SCHE_BARRIER,
 491   NDS32_BUILTIN_GET_CURRENT_SP,
 492   NDS32_BUILTIN_SET_CURRENT_SP,
 493   NDS32_BUILTIN_RETURN_ADDRESS,
 494   NDS32_BUILTIN_LLW,
 495   NDS32_BUILTIN_LWUP,
 496   NDS32_BUILTIN_LBUP,
 497   NDS32_BUILTIN_SCW,
 498   NDS32_BUILTIN_SWUP,
 499   NDS32_BUILTIN_SBUP,
 500   NDS32_BUILTIN_CCTL_VA_LCK,
 501   NDS32_BUILTIN_CCTL_IDX_WBINVAL,
 502   NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
 503   NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
 504   NDS32_BUILTIN_CCTL_IDX_READ,
 505   NDS32_BUILTIN_CCTL_IDX_WRITE,
 506   NDS32_BUILTIN_CCTL_L1D_INVALALL,
 507   NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
 508   NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
 509   NDS32_BUILTIN_DPREF_QW,
 510   NDS32_BUILTIN_DPREF_HW,
 511   NDS32_BUILTIN_DPREF_W,
 512   NDS32_BUILTIN_DPREF_DW,
 513   NDS32_BUILTIN_TLBOP_TRD,
 514   NDS32_BUILTIN_TLBOP_TWR,
 515   NDS32_BUILTIN_TLBOP_RWR,
 516   NDS32_BUILTIN_TLBOP_RWLK,
 517   NDS32_BUILTIN_TLBOP_UNLK,
 518   NDS32_BUILTIN_TLBOP_PB,
 519   NDS32_BUILTIN_TLBOP_INV,
 520   NDS32_BUILTIN_TLBOP_FLUA,
 521   NDS32_BUILTIN_UALOAD_HW,
 522   NDS32_BUILTIN_UALOAD_W,
 523   NDS32_BUILTIN_UALOAD_DW,
 524   NDS32_BUILTIN_UASTORE_HW,
 525   NDS32_BUILTIN_UASTORE_W,
 526   NDS32_BUILTIN_UASTORE_DW,
 527   NDS32_BUILTIN_GIE_DIS,
 528   NDS32_BUILTIN_GIE_EN,
 529   NDS32_BUILTIN_ENABLE_INT,
 530   NDS32_BUILTIN_DISABLE_INT,
 531   NDS32_BUILTIN_SET_PENDING_SWINT,
 532   NDS32_BUILTIN_CLR_PENDING_SWINT,
 533   NDS32_BUILTIN_CLR_PENDING_HWINT,
 534   NDS32_BUILTIN_GET_ALL_PENDING_INT,
 535   NDS32_BUILTIN_GET_PENDING_INT,
 536   NDS32_BUILTIN_SET_INT_PRIORITY,
 537   NDS32_BUILTIN_GET_INT_PRIORITY,
 538   NDS32_BUILTIN_SET_TRIG_LEVEL,
 539   NDS32_BUILTIN_SET_TRIG_EDGE,
 540   NDS32_BUILTIN_GET_TRIG_TYPE,
 541   NDS32_BUILTIN_DSP_BEGIN,
 542   NDS32_BUILTIN_ADD16,
 543   NDS32_BUILTIN_V_UADD16,
 544   NDS32_BUILTIN_V_SADD16,
 545   NDS32_BUILTIN_RADD16,
 546   NDS32_BUILTIN_V_RADD16,
 547   NDS32_BUILTIN_URADD16,
 548   NDS32_BUILTIN_V_URADD16,
 549   NDS32_BUILTIN_KADD16,
 550   NDS32_BUILTIN_V_KADD16,
 551   NDS32_BUILTIN_UKADD16,
 552   NDS32_BUILTIN_V_UKADD16,
 553   NDS32_BUILTIN_SUB16,
 554   NDS32_BUILTIN_V_USUB16,
 555   NDS32_BUILTIN_V_SSUB16,
 556   NDS32_BUILTIN_RSUB16,
 557   NDS32_BUILTIN_V_RSUB16,
 558   NDS32_BUILTIN_URSUB16,
 559   NDS32_BUILTIN_V_URSUB16,
 560   NDS32_BUILTIN_KSUB16,
 561   NDS32_BUILTIN_V_KSUB16,
 562   NDS32_BUILTIN_UKSUB16,
 563   NDS32_BUILTIN_V_UKSUB16,
 564   NDS32_BUILTIN_CRAS16,
 565   NDS32_BUILTIN_V_UCRAS16,
 566   NDS32_BUILTIN_V_SCRAS16,
 567   NDS32_BUILTIN_RCRAS16,
 568   NDS32_BUILTIN_V_RCRAS16,
 569   NDS32_BUILTIN_URCRAS16,
 570   NDS32_BUILTIN_V_URCRAS16,
 571   NDS32_BUILTIN_KCRAS16,
 572   NDS32_BUILTIN_V_KCRAS16,
 573   NDS32_BUILTIN_UKCRAS16,
 574   NDS32_BUILTIN_V_UKCRAS16,
 575   NDS32_BUILTIN_CRSA16,
 576   NDS32_BUILTIN_V_UCRSA16,
 577   NDS32_BUILTIN_V_SCRSA16,
 578   NDS32_BUILTIN_RCRSA16,
 579   NDS32_BUILTIN_V_RCRSA16,
 580   NDS32_BUILTIN_URCRSA16,
 581   NDS32_BUILTIN_V_URCRSA16,
 582   NDS32_BUILTIN_KCRSA16,
 583   NDS32_BUILTIN_V_KCRSA16,
 584   NDS32_BUILTIN_UKCRSA16,
 585   NDS32_BUILTIN_V_UKCRSA16,
 586   NDS32_BUILTIN_ADD8,
 587   NDS32_BUILTIN_V_UADD8,
 588   NDS32_BUILTIN_V_SADD8,
 589   NDS32_BUILTIN_RADD8,
 590   NDS32_BUILTIN_V_RADD8,
 591   NDS32_BUILTIN_URADD8,
 592   NDS32_BUILTIN_V_URADD8,
 593   NDS32_BUILTIN_KADD8,
 594   NDS32_BUILTIN_V_KADD8,
 595   NDS32_BUILTIN_UKADD8,
 596   NDS32_BUILTIN_V_UKADD8,
 597   NDS32_BUILTIN_SUB8,
 598   NDS32_BUILTIN_V_USUB8,
 599   NDS32_BUILTIN_V_SSUB8,
 600   NDS32_BUILTIN_RSUB8,
 601   NDS32_BUILTIN_V_RSUB8,
 602   NDS32_BUILTIN_URSUB8,
 603   NDS32_BUILTIN_V_URSUB8,
 604   NDS32_BUILTIN_KSUB8,
 605   NDS32_BUILTIN_V_KSUB8,
 606   NDS32_BUILTIN_UKSUB8,
 607   NDS32_BUILTIN_V_UKSUB8,
 608   NDS32_BUILTIN_SRA16,
 609   NDS32_BUILTIN_V_SRA16,
 610   NDS32_BUILTIN_SRA16_U,
 611   NDS32_BUILTIN_V_SRA16_U,
 612   NDS32_BUILTIN_SRL16,
 613   NDS32_BUILTIN_V_SRL16,
 614   NDS32_BUILTIN_SRL16_U,
 615   NDS32_BUILTIN_V_SRL16_U,
 616   NDS32_BUILTIN_SLL16,
 617   NDS32_BUILTIN_V_SLL16,
 618   NDS32_BUILTIN_KSLL16,
 619   NDS32_BUILTIN_V_KSLL16,
 620   NDS32_BUILTIN_KSLRA16,
 621   NDS32_BUILTIN_V_KSLRA16,
 622   NDS32_BUILTIN_KSLRA16_U,
 623   NDS32_BUILTIN_V_KSLRA16_U,
 624   NDS32_BUILTIN_CMPEQ16,
 625   NDS32_BUILTIN_V_SCMPEQ16,
 626   NDS32_BUILTIN_V_UCMPEQ16,
 627   NDS32_BUILTIN_SCMPLT16,
 628   NDS32_BUILTIN_V_SCMPLT16,
 629   NDS32_BUILTIN_SCMPLE16,
 630   NDS32_BUILTIN_V_SCMPLE16,
 631   NDS32_BUILTIN_UCMPLT16,
 632   NDS32_BUILTIN_V_UCMPLT16,
 633   NDS32_BUILTIN_UCMPLE16,
 634   NDS32_BUILTIN_V_UCMPLE16,
 635   NDS32_BUILTIN_CMPEQ8,
 636   NDS32_BUILTIN_V_SCMPEQ8,
 637   NDS32_BUILTIN_V_UCMPEQ8,
 638   NDS32_BUILTIN_SCMPLT8,
 639   NDS32_BUILTIN_V_SCMPLT8,
 640   NDS32_BUILTIN_SCMPLE8,
 641   NDS32_BUILTIN_V_SCMPLE8,
 642   NDS32_BUILTIN_UCMPLT8,
 643   NDS32_BUILTIN_V_UCMPLT8,
 644   NDS32_BUILTIN_UCMPLE8,
 645   NDS32_BUILTIN_V_UCMPLE8,
 646   NDS32_BUILTIN_SMIN16,
 647   NDS32_BUILTIN_V_SMIN16,
 648   NDS32_BUILTIN_UMIN16,
 649   NDS32_BUILTIN_V_UMIN16,
 650   NDS32_BUILTIN_SMAX16,
 651   NDS32_BUILTIN_V_SMAX16,
 652   NDS32_BUILTIN_UMAX16,
 653   NDS32_BUILTIN_V_UMAX16,
 654   NDS32_BUILTIN_SCLIP16,
 655   NDS32_BUILTIN_V_SCLIP16,
 656   NDS32_BUILTIN_UCLIP16,
 657   NDS32_BUILTIN_V_UCLIP16,
 658   NDS32_BUILTIN_KHM16,
 659   NDS32_BUILTIN_V_KHM16,
 660   NDS32_BUILTIN_KHMX16,
 661   NDS32_BUILTIN_V_KHMX16,
 662   NDS32_BUILTIN_KABS16,
 663   NDS32_BUILTIN_V_KABS16,
 664   NDS32_BUILTIN_SMIN8,
 665   NDS32_BUILTIN_V_SMIN8,
 666   NDS32_BUILTIN_UMIN8,
 667   NDS32_BUILTIN_V_UMIN8,
 668   NDS32_BUILTIN_SMAX8,
 669   NDS32_BUILTIN_V_SMAX8,
 670   NDS32_BUILTIN_UMAX8,
 671   NDS32_BUILTIN_V_UMAX8,
 672   NDS32_BUILTIN_KABS8,
 673   NDS32_BUILTIN_V_KABS8,
 674   NDS32_BUILTIN_SUNPKD810,
 675   NDS32_BUILTIN_V_SUNPKD810,
 676   NDS32_BUILTIN_SUNPKD820,
 677   NDS32_BUILTIN_V_SUNPKD820,
 678   NDS32_BUILTIN_SUNPKD830,
 679   NDS32_BUILTIN_V_SUNPKD830,
 680   NDS32_BUILTIN_SUNPKD831,
 681   NDS32_BUILTIN_V_SUNPKD831,
 682   NDS32_BUILTIN_ZUNPKD810,
 683   NDS32_BUILTIN_V_ZUNPKD810,
 684   NDS32_BUILTIN_ZUNPKD820,
 685   NDS32_BUILTIN_V_ZUNPKD820,
 686   NDS32_BUILTIN_ZUNPKD830,
 687   NDS32_BUILTIN_V_ZUNPKD830,
 688   NDS32_BUILTIN_ZUNPKD831,
 689   NDS32_BUILTIN_V_ZUNPKD831,
 690   NDS32_BUILTIN_RADDW,
 691   NDS32_BUILTIN_URADDW,
 692   NDS32_BUILTIN_RSUBW,
 693   NDS32_BUILTIN_URSUBW,
 694   NDS32_BUILTIN_SRA_U,
 695   NDS32_BUILTIN_KSLL,
 696   NDS32_BUILTIN_PKBB16,
 697   NDS32_BUILTIN_V_PKBB16,
 698   NDS32_BUILTIN_PKBT16,
 699   NDS32_BUILTIN_V_PKBT16,
 700   NDS32_BUILTIN_PKTB16,
 701   NDS32_BUILTIN_V_PKTB16,
 702   NDS32_BUILTIN_PKTT16,
 703   NDS32_BUILTIN_V_PKTT16,
 704   NDS32_BUILTIN_SMMUL,
 705   NDS32_BUILTIN_SMMUL_U,
 706   NDS32_BUILTIN_KMMAC,
 707   NDS32_BUILTIN_KMMAC_U,
 708   NDS32_BUILTIN_KMMSB,
 709   NDS32_BUILTIN_KMMSB_U,
 710   NDS32_BUILTIN_KWMMUL,
 711   NDS32_BUILTIN_KWMMUL_U,
 712   NDS32_BUILTIN_SMMWB,
 713   NDS32_BUILTIN_V_SMMWB,
 714   NDS32_BUILTIN_SMMWB_U,
 715   NDS32_BUILTIN_V_SMMWB_U,
 716   NDS32_BUILTIN_SMMWT,
 717   NDS32_BUILTIN_V_SMMWT,
 718   NDS32_BUILTIN_SMMWT_U,
 719   NDS32_BUILTIN_V_SMMWT_U,
 720   NDS32_BUILTIN_KMMAWB,
 721   NDS32_BUILTIN_V_KMMAWB,
 722   NDS32_BUILTIN_KMMAWB_U,
 723   NDS32_BUILTIN_V_KMMAWB_U,
 724   NDS32_BUILTIN_KMMAWT,
 725   NDS32_BUILTIN_V_KMMAWT,
 726   NDS32_BUILTIN_KMMAWT_U,
 727   NDS32_BUILTIN_V_KMMAWT_U,
 728   NDS32_BUILTIN_SMBB,
 729   NDS32_BUILTIN_V_SMBB,
 730   NDS32_BUILTIN_SMBT,
 731   NDS32_BUILTIN_V_SMBT,
 732   NDS32_BUILTIN_SMTT,
 733   NDS32_BUILTIN_V_SMTT,
 734   NDS32_BUILTIN_KMDA,
 735   NDS32_BUILTIN_V_KMDA,
 736   NDS32_BUILTIN_KMXDA,
 737   NDS32_BUILTIN_V_KMXDA,
 738   NDS32_BUILTIN_SMDS,
 739   NDS32_BUILTIN_V_SMDS,
 740   NDS32_BUILTIN_SMDRS,
 741   NDS32_BUILTIN_V_SMDRS,
 742   NDS32_BUILTIN_SMXDS,
 743   NDS32_BUILTIN_V_SMXDS,
 744   NDS32_BUILTIN_KMABB,
 745   NDS32_BUILTIN_V_KMABB,
 746   NDS32_BUILTIN_KMABT,
 747   NDS32_BUILTIN_V_KMABT,
 748   NDS32_BUILTIN_KMATT,
 749   NDS32_BUILTIN_V_KMATT,
 750   NDS32_BUILTIN_KMADA,
 751   NDS32_BUILTIN_V_KMADA,
 752   NDS32_BUILTIN_KMAXDA,
 753   NDS32_BUILTIN_V_KMAXDA,
 754   NDS32_BUILTIN_KMADS,
 755   NDS32_BUILTIN_V_KMADS,
 756   NDS32_BUILTIN_KMADRS,
 757   NDS32_BUILTIN_V_KMADRS,
 758   NDS32_BUILTIN_KMAXDS,
 759   NDS32_BUILTIN_V_KMAXDS,
 760   NDS32_BUILTIN_KMSDA,
 761   NDS32_BUILTIN_V_KMSDA,
 762   NDS32_BUILTIN_KMSXDA,
 763   NDS32_BUILTIN_V_KMSXDA,
 764   NDS32_BUILTIN_SMAL,
 765   NDS32_BUILTIN_V_SMAL,
 766   NDS32_BUILTIN_BITREV,
 767   NDS32_BUILTIN_WEXT,
 768   NDS32_BUILTIN_BPICK,
 769   NDS32_BUILTIN_INSB,
 770   NDS32_BUILTIN_SADD64,
 771   NDS32_BUILTIN_UADD64,
 772   NDS32_BUILTIN_RADD64,
 773   NDS32_BUILTIN_URADD64,
 774   NDS32_BUILTIN_KADD64,
 775   NDS32_BUILTIN_UKADD64,
 776   NDS32_BUILTIN_SSUB64,
 777   NDS32_BUILTIN_USUB64,
 778   NDS32_BUILTIN_RSUB64,
 779   NDS32_BUILTIN_URSUB64,
 780   NDS32_BUILTIN_KSUB64,
 781   NDS32_BUILTIN_UKSUB64,
 782   NDS32_BUILTIN_SMAR64,
 783   NDS32_BUILTIN_SMSR64,
 784   NDS32_BUILTIN_UMAR64,
 785   NDS32_BUILTIN_UMSR64,
 786   NDS32_BUILTIN_KMAR64,
 787   NDS32_BUILTIN_KMSR64,
 788   NDS32_BUILTIN_UKMAR64,
 789   NDS32_BUILTIN_UKMSR64,
 790   NDS32_BUILTIN_SMALBB,
 791   NDS32_BUILTIN_V_SMALBB,
 792   NDS32_BUILTIN_SMALBT,
 793   NDS32_BUILTIN_V_SMALBT,
 794   NDS32_BUILTIN_SMALTT,
 795   NDS32_BUILTIN_V_SMALTT,
 796   NDS32_BUILTIN_SMALDA,
 797   NDS32_BUILTIN_V_SMALDA,
 798   NDS32_BUILTIN_SMALXDA,
 799   NDS32_BUILTIN_V_SMALXDA,
 800   NDS32_BUILTIN_SMALDS,
 801   NDS32_BUILTIN_V_SMALDS,
 802   NDS32_BUILTIN_SMALDRS,
 803   NDS32_BUILTIN_V_SMALDRS,
 804   NDS32_BUILTIN_SMALXDS,
 805   NDS32_BUILTIN_V_SMALXDS,
 806   NDS32_BUILTIN_SMUL16,
 807   NDS32_BUILTIN_V_SMUL16,
 808   NDS32_BUILTIN_SMULX16,
 809   NDS32_BUILTIN_V_SMULX16,
 810   NDS32_BUILTIN_UMUL16,
 811   NDS32_BUILTIN_V_UMUL16,
 812   NDS32_BUILTIN_UMULX16,
 813   NDS32_BUILTIN_V_UMULX16,
 814   NDS32_BUILTIN_SMSLDA,
 815   NDS32_BUILTIN_V_SMSLDA,
 816   NDS32_BUILTIN_SMSLXDA,
 817   NDS32_BUILTIN_V_SMSLXDA,
 818   NDS32_BUILTIN_UCLIP32,
 819   NDS32_BUILTIN_SCLIP32,
 820   NDS32_BUILTIN_KABS,
 821   NDS32_BUILTIN_UALOAD_U16,
 822   NDS32_BUILTIN_UALOAD_S16,
 823   NDS32_BUILTIN_UALOAD_U8,
 824   NDS32_BUILTIN_UALOAD_S8,
 825   NDS32_BUILTIN_UASTORE_U16,
 826   NDS32_BUILTIN_UASTORE_S16,
 827   NDS32_BUILTIN_UASTORE_U8,
 828   NDS32_BUILTIN_UASTORE_S8,
 829   NDS32_BUILTIN_DSP_END,
 830   NDS32_BUILTIN_UNALIGNED_FEATURE,
 831   NDS32_BUILTIN_ENABLE_UNALIGNED,
 832   NDS32_BUILTIN_DISABLE_UNALIGNED,
 833   NDS32_BUILTIN_COUNT
 834 };
 835
 836 /* ------------------------------------------------------------------------ */
 837
 838 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 839
 840 #define TARGET_ISA_V3 \
 841   (nds32_arch_option == ARCH_V3 \
 842    || nds32_arch_option == ARCH_V3F \
 843    || nds32_arch_option == ARCH_V3S)
 844 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 845
 846 #define TARGET_PIPELINE_N9 \
 847   (nds32_cpu_option == CPU_N9)
 848 #define TARGET_PIPELINE_SIMPLE \
 849   (nds32_cpu_option == CPU_SIMPLE)
 850
 851 #define TARGET_CMODEL_SMALL \
 852    (nds32_cmodel_option == CMODEL_SMALL)
 853 #define TARGET_CMODEL_MEDIUM \
 854    (nds32_cmodel_option == CMODEL_MEDIUM)
 855 #define TARGET_CMODEL_LARGE \
 856    (nds32_cmodel_option == CMODEL_LARGE)
 857
 858 #define TARGET_ICT_MODEL_SMALL \
 859    (nds32_ict_model == ICT_MODEL_SMALL)
 860
 861 #define TARGET_ICT_MODEL_LARGE \
 862    (nds32_ict_model == ICT_MODEL_LARGE)
 863
 864 /* When -mcmodel=small or -mcmodel=medium,
 865    compiler may generate gp-base instruction directly.  */
 866 #define TARGET_GP_DIRECT \
 867    (nds32_cmodel_option == CMODEL_SMALL\
 868     || nds32_cmodel_option == CMODEL_MEDIUM)
 869
 870 #define TARGET_MUL_SLOW \
 871   (nds32_mul_config == MUL_TYPE_SLOW)
 872
 873 /* Run-time Target Specification.  */
 874 #define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
 875 /* Use hardware floating point calling convention.  */
 876 #define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
 877
 878 /* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
 879    1 means  hard ABI and using full floating-point instruction,
 880    2 means hard ABI and only using single-precision floating-point
 881    instruction  */
 882 #if TARGET_ARCH_DEFAULT == 1
 883 #  define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 884 #  define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
 885 #  define TARGET_DEFAULT_FPU_FMA 0
 886 #else
 887 #  if TARGET_ARCH_DEFAULT == 2
 888 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 889 #    define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
 890 #    define TARGET_DEFAULT_FPU_FMA 0
 891 #  else
 892 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2
 893 #    define TARGET_DEFAULT_FPU_ISA 0
 894 #    define TARGET_DEFAULT_FPU_FMA 0
 895 #  endif
 896 #endif
 897
 898 #define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
 899
 900 #ifdef TARGET_DEFAULT_EXT_DSP
 901 #  define NDS32_EXT_DSP_SPEC " %{!mno-ext-dsp:-mext-dsp}"
 902 #else
 903 #  define NDS32_EXT_DSP_SPEC ""
 904 #endif
 905
 906 /* ------------------------------------------------------------------------ */
 907 \f
 908 /* Controlling the Compilation Driver.  */
 909
 910 #define OPTION_DEFAULT_SPECS \
 911   {"arch", " %{!march=*:-march=%(VALUE)}" \
 912            " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 913            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
 914            " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
 915            " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 916            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
 917   {"cpu",  "%{!mcpu=*:-mcpu=%(VALUE)}" },   \
 918   {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
 919
 920 #define CC1_SPEC \
 921   NDS32_EXT_DSP_SPEC
 922
 923 #define ASM_SPEC \
 924   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 925   " %{march=*:-march=%*}" \
 926   " %{mabi=*:-mabi=v%*}" \
 927   " %{mconfig-fpu=*:-mfpu-freg=%*}" \
 928   " %{mext-fpu-mac:-mmac}" \
 929   " %{mno-ext-fpu-mac:-mno-mac}" \
 930   " %{mext-fpu-sp:-mfpu-sp-ext}" \
 931   " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
 932   " %{mext-fpu-dp:-mfpu-dp-ext}" \
 933   " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" \
 934   " %{mext-dsp:-mdsp-ext}"
 935
 936 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 937 #define LINK_SPEC \
 938   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 939   " %{mrelax:--relax}"
 940
 941 #define LIB_SPEC \
 942   " -lc -lgloss"
 943
 944 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 945    by applying different crt stuff.  In the convention, crt0.o is the
 946    startup file without constructor/destructor;
 947    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 948    startup files with constructor/destructor.
 949    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 950    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 951    currently provided by GCC for nds32 target.
 952
 953    For nds32 target so far:
 954    If -mno-ctor-dtor, we are going to link
 955    "crt0.o [user objects]".
 956    If general cases, we are going to link
 957    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 958 #define STARTFILE_SPEC \
 959   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 960   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 961 #define ENDFILE_SPEC \
 962   " %{!mno-ctor-dtor:crtend1.o%s}"
 963
 964 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 965    configure gcc with --target=nds32be-* setting.
 966    Check gcc/config.gcc for more information.  */
 967 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 968 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 969 #else
 970 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 971 #endif
 972
 973 /* Currently we only have elf toolchain,
 974    where -mcmodel=medium is always the default.  */
 975 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 976
 977 #define MULTILIB_DEFAULTS \
 978   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 979
 980 \f
 981 /* Run-time Target Specification.  */
 982
 983 #define TARGET_CPU_CPP_BUILTINS() \
 984   nds32_cpu_cpp_builtins (pfile)
 985
 986 \f
 987 /* Defining Data Structures for Per-function Information.  */
 988
 989 /* This macro is called once per function,
 990    before generation of any RTL has begun.  */
 991 #define INIT_EXPANDERS  nds32_init_expanders ()
 992
 993 \f
 994 /* Storage Layout.  */
 995
 996 #define BITS_BIG_ENDIAN 0
 997
 998 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 999
1000 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
1001
1002 #define UNITS_PER_WORD 4
1003
1004 #define PROMOTE_MODE(m, unsignedp, type)                                    \
1005   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
1006     {                                                                       \
1007       (m) = SImode;                                                         \
1008     }
1009
1010 #define PARM_BOUNDARY 32
1011
1012 #define STACK_BOUNDARY 64
1013
1014 #define FUNCTION_BOUNDARY \
1015   ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16)
1016
1017 #define BIGGEST_ALIGNMENT 64
1018
1019 #define DATA_ALIGNMENT(constant, basic_align) \
1020   nds32_data_alignment (constant, basic_align)
1021
1022 #define LOCAL_ALIGNMENT(type, basic_align) \
1023   nds32_local_alignment (type, basic_align)
1024
1025 #define EMPTY_FIELD_BOUNDARY 32
1026
1027 #define STRUCTURE_SIZE_BOUNDARY 8
1028
1029 #define STRICT_ALIGNMENT 1
1030
1031 #define PCC_BITFIELD_TYPE_MATTERS 1
1032
1033 \f
1034 /* Layout of Source Language Data Types.  */
1035
1036 #define INT_TYPE_SIZE           32
1037 #define SHORT_TYPE_SIZE         16
1038 #define LONG_TYPE_SIZE          32
1039 #define LONG_LONG_TYPE_SIZE     64
1040
1041 #define FLOAT_TYPE_SIZE         32
1042 #define DOUBLE_TYPE_SIZE        64
1043 #define LONG_DOUBLE_TYPE_SIZE   64
1044
1045 #define DEFAULT_SIGNED_CHAR 1
1046
1047 #define SIZE_TYPE "long unsigned int"
1048 #define PTRDIFF_TYPE "long int"
1049 #define WCHAR_TYPE "unsigned int"
1050 #define WCHAR_TYPE_SIZE 32
1051
1052 \f
1053 /* Register Usage.  */
1054
1055 /* Number of actual hardware registers.
1056    The hardware registers are assigned numbers for the compiler
1057    from 0 to just below FIRST_PSEUDO_REGISTER.
1058    All registers that the compiler knows about must be given numbers,
1059    even those that are not normally considered general registers.  */
1060 #define FIRST_PSEUDO_REGISTER 101
1061
1062 /* An initializer that says which registers are used for fixed
1063    purposes all throughout the compiled code and are therefore
1064    not available for general allocation.
1065
1066    $r28 : $fp
1067    $r29 : $gp
1068    $r30 : $lp
1069    $r31 : $sp
1070
1071    caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
1072    callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
1073
1074    reserved for assembler : $r15
1075    reserved for other use : $r24, $r25, $r26, $r27 */
1076 #define FIXED_REGISTERS \
1077 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
1078       0,   0,   0,   0,   0,   0,   0,   0,     \
1079   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
1080       0,   0,   0,   0,   0,   0,   0,   1,     \
1081   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
1082       0,   0,   0,   0,   0,   0,   0,   0,     \
1083   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
1084       1,   1,   1,   1,   0,   1,   0,   1,     \
1085   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
1086       1,   1,   1,   1,   1,   1,   1,   1,     \
1087   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
1088       1,   1,   1,   1,   1,   1,   1,   1,     \
1089   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
1090       1,   1,   1,   1,   1,   1,   1,   1,     \
1091   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
1092       1,   1,   1,   1,   1,   1,   1,   1,     \
1093   /* fs30 fs31 fd16      fd17      fd18      */ \
1094       1,   1,   1,   1,   1,   1,   1,   1,     \
1095   /* fd19      fd20      fd21      fd22      */ \
1096       1,   1,   1,   1,   1,   1,   1,   1,     \
1097   /* fd23      fd24      fd25      fd26      */ \
1098       1,   1,   1,   1,   1,   1,   1,   1,     \
1099   /* fd27      fd28      fd29      fd30      */ \
1100       1,   1,   1,   1,   1,   1,   1,   1,     \
1101   /* fd31      Reserved..................... */ \
1102       1,   1,   1,   1,   1                     \
1103 }
1104
1105 /* Identifies the registers that are not available for
1106    general allocation of values that must live across
1107    function calls -- so they are caller-save registers.
1108
1109    0 : callee-save registers
1110    1 : caller-save registers */
1111 #define CALL_USED_REGISTERS \
1112 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
1113       1,   1,   1,   1,   1,   1,   0,   0,     \
1114   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
1115       0,   0,   0,   0,   0,   0,   0,   1,     \
1116   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
1117       1,   1,   1,   1,   1,   1,   1,   1,     \
1118   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
1119       1,   1,   1,   1,   0,   1,   0,   1,     \
1120   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
1121       1,   1,   1,   1,   1,   1,   1,   1,     \
1122   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
1123       1,   1,   1,   1,   1,   1,   1,   1,     \
1124   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
1125       1,   1,   1,   1,   1,   1,   1,   1,     \
1126   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
1127       1,   1,   1,   1,   1,   1,   1,   1,     \
1128   /* fs30 fs31 fd16      fd17      fd18      */ \
1129       1,   1,   1,   1,   1,   1,   1,   1,     \
1130   /* fd19      fd20      fd21      fd22      */ \
1131       1,   1,   1,   1,   1,   1,   1,   1,     \
1132   /* fd23      fd24      fd25      fd26      */ \
1133       1,   1,   1,   1,   1,   1,   1,   1,     \
1134   /* fd27      fd28      fd29      fd30      */ \
1135       1,   1,   1,   1,   1,   1,   1,   1,     \
1136   /* fd31      Reserved..................... */ \
1137       1,   1,   1,   1,   1                     \
1138 }
1139
1140 /* In nds32 target, we have three levels of registers:
1141      LOW_COST_REGS    : $r0 ~ $r7
1142      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
1143      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
1144 #define REG_ALLOC_ORDER \
1145 {   0,   1,   2,   3,   4,   5,   6,   7, \
1146    16,  17,  18,  19,   9,  10,  11,  12, \
1147    13,  14,  8,   15,  20,  21,  22,  23, \
1148    24,  25,  26,  27,  28,  29,  30,  31, \
1149    32,  33,  34,  35,  36,  37,  38,  39, \
1150    40,  41,  42,  43,  44,  45,  46,  47, \
1151    48,  49,  50,  51,  52,  53,  54,  55, \
1152    56,  57,  58,  59,  60,  61,  62,  63, \
1153    64,  65,  66,  67,  68,  69,  70,  71, \
1154    72,  73,  74,  75,  76,  77,  78,  79, \
1155    80,  81,  82,  83,  84,  85,  86,  87, \
1156    88,  89,  90,  91,  92,  93,  94,  95, \
1157    96,  97,  98,  99, 100,                \
1158 }
1159
1160 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1161    to be rearranged based on optimizing for speed or size.  */
1162 #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
1163
1164 /* Tell IRA to use the order we define rather than messing it up with its
1165    own cost calculations.  */
1166 #define HONOR_REG_ALLOC_ORDER optimize_size
1167
1168 \f
1169 /* Register Classes.  */
1170
1171 /* In nds32 target, we have three levels of registers:
1172      Low cost regsiters    : $r0 ~ $r7
1173      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
1174      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
1175
1176    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
1177    so that it provides more chance to use low cost registers.  */
1178 enum reg_class
1179 {
1180   NO_REGS,
1181   R5_REG,
1182   R8_REG,
1183   R15_TA_REG,
1184   STACK_REG,
1185   FRAME_POINTER_REG,
1186   LOW_REGS,
1187   MIDDLE_REGS,
1188   HIGH_REGS,
1189   GENERAL_REGS,
1190   FRAME_REGS,
1191   FP_REGS,
1192   ALL_REGS,
1193   LIM_REG_CLASSES
1194 };
1195
1196 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1197
1198 #define REG_CLASS_NAMES \
1199 {                       \
1200   "NO_REGS",            \
1201   "R5_REG",             \
1202   "R8_REG",             \
1203   "R15_TA_REG",         \
1204   "STACK_REG",          \
1205   "FRAME_POINTER_REG",  \
1206   "LOW_REGS",           \
1207   "MIDDLE_REGS",        \
1208   "HIGH_REGS",          \
1209   "GENERAL_REGS",       \
1210   "FRAME_REGS",         \
1211   "FP_REGS",            \
1212   "ALL_REGS"            \
1213 }
1214
1215 #define REG_CLASS_CONTENTS \
1216 { /* NO_REGS                                    */  \
1217   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
1218   /* R5_REG              : 5                    */  \
1219   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
1220   /* R8_REG              : 8                    */  \
1221   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
1222   /* R15_TA_REG          : 15                   */  \
1223   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
1224   /* STACK_REG           : 31                   */  \
1225   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
1226   /* FRAME_POINTER_REG   : 28                   */  \
1227   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
1228   /* LOW_REGS            : 0-7                  */  \
1229   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
1230   /* MIDDLE_REGS         : 0-11, 16-19          */  \
1231   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
1232   /* HIGH_REGS           : 12-14, 20-31         */  \
1233   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
1234   /* GENERAL_REGS        : 0-31                 */  \
1235   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
1236   /* FRAME_REGS          : 32, 33               */  \
1237   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
1238   /* FP_REGS             : 34-98                */  \
1239   {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
1240   /* ALL_REGS            : 0-100                */  \
1241   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
1242 }
1243
1244 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
1245
1246 #define BASE_REG_CLASS GENERAL_REGS
1247 #define INDEX_REG_CLASS GENERAL_REGS
1248
1249 #define TEST_REGNO(R, TEST, VALUE) \
1250   ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1251
1252 /* Return nonzero if it is suitable for use as a
1253    base register in operand addresses.
1254    So far, we return nonzero only if "num" is a hard reg
1255    of the suitable class or a pseudo register which is
1256    allocated to a suitable hard reg.  */
1257 #define REGNO_OK_FOR_BASE_P(num) \
1258   (TEST_REGNO (num, <, 32) \
1259    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
1260    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
1261
1262 /* Return nonzero if it is suitable for use as a
1263    index register in operand addresses.
1264    So far, we return nonzero only if "num" is a hard reg
1265    of the suitable class or a pseudo register which is
1266    allocated to a suitable hard reg.
1267    The difference between an index register and a base register is that
1268    the index register may be scaled.  */
1269 #define REGNO_OK_FOR_INDEX_P(num) \
1270   (TEST_REGNO (num, <, 32) \
1271    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
1272    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
1273
1274 \f
1275 /* Obsolete Macros for Defining Constraints.  */
1276
1277 \f
1278 /* Stack Layout and Calling Conventions.  */
1279
1280 #define STACK_GROWS_DOWNWARD 1
1281
1282 #define FRAME_GROWS_DOWNWARD 1
1283
1284 #define STACK_POINTER_OFFSET 0
1285
1286 #define FIRST_PARM_OFFSET(fundecl) \
1287   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
1288
1289 /* A C expression whose value is RTL representing the address in a stack frame
1290    where the pointer to the caller's frame is stored.  */
1291 #define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
1292   nds32_dynamic_chain_address (frameaddr)
1293
1294 #define RETURN_ADDR_RTX(count, frameaddr) \
1295   nds32_return_addr_rtx (count, frameaddr)
1296
1297 /* A C expression whose value is RTL representing the location
1298    of the incoming return address at the beginning of any function
1299    before the prologue.
1300    If this RTL is REG, you should also define
1301    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
1302 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
1303 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
1304
1305 /* Use $r0 $r1 to pass exception handling information.  */
1306 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
1307 /* The register $r2 that represents a location in which to store a stack
1308    adjustment to be applied before function return.
1309    This is used to unwind the stack to an exception handler's call frame.  */
1310 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1311
1312 #define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
1313
1314 #define STACK_POINTER_REGNUM SP_REGNUM
1315
1316 #define FRAME_POINTER_REGNUM 33
1317
1318 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
1319
1320 #define ARG_POINTER_REGNUM 32
1321
1322 #define STATIC_CHAIN_REGNUM 16
1323
1324 #define ELIMINABLE_REGS                                \
1325 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
1326   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
1327   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
1328   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
1329
1330 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
1331   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
1332
1333 #define ACCUMULATE_OUTGOING_ARGS 1
1334
1335 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
1336
1337 #define CUMULATIVE_ARGS nds32_cumulative_args
1338
1339 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
1340   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
1341
1342 #define FUNCTION_ARG_REGNO_P(regno)                                           \
1343  (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
1344   || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)                                \
1345       && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM,                       \
1346                    NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
1347
1348 #define DEFAULT_PCC_STRUCT_RETURN 0
1349
1350 /* EXIT_IGNORE_STACK should be nonzero if, when returning
1351    from a function, the stack pointer does not matter.
1352    The value is tested only in functions that have frame pointers.
1353    In nds32 target, the function epilogue recovers the
1354    stack pointer from the frame.  */
1355 #define EXIT_IGNORE_STACK 1
1356
1357 #define FUNCTION_PROFILER(file, labelno) \
1358   fprintf (file, "/* profiler %d */\n", (labelno))
1359
1360 #define PROFILE_HOOK(LABEL)                                             \
1361   {                                                                     \
1362     rtx fun, lp;                                                        \
1363     lp = get_hard_reg_initial_val (Pmode, LP_REGNUM);                   \
1364     fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount");                        \
1365     emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode);           \
1366   }
1367
1368 \f
1369 /* Implementing the Varargs Macros.  */
1370
1371 \f
1372 /* Trampolines for Nested Functions.  */
1373
1374 /* Giving A-function and B-function,
1375    if B-function wants to call A-function's nested function,
1376    we need to fill trampoline code into A-function's stack
1377    so that B-function can execute the code in stack to indirectly
1378    jump to (like 'trampoline' action) desired nested function.
1379
1380    The trampoline code for nds32 target must contains following parts:
1381
1382      1. instructions (4 * 4 = 16 bytes):
1383           get $pc first
1384           load chain_value to static chain register via $pc
1385           load nested function address to $r15 via $pc
1386           jump to desired nested function via $r15
1387      2. data (4 * 2 = 8 bytes):
1388           chain_value
1389           nested function address
1390
1391    Please check nds32.c implementation for more information.  */
1392 #define TRAMPOLINE_SIZE 24
1393
1394 /* Because all instructions/data in trampoline template are 4-byte size,
1395    we set trampoline alignment 8*4=32 bits.  */
1396 #define TRAMPOLINE_ALIGNMENT 32
1397
1398 \f
1399 /* Implicit Calls to Library Routines.  */
1400
1401 \f
1402 /* Addressing Modes.  */
1403
1404 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
1405 #define HAVE_POST_INCREMENT 1
1406 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
1407 #define HAVE_POST_DECREMENT 1
1408
1409 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
1410 #define HAVE_POST_MODIFY_DISP 1
1411 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
1412 #define HAVE_POST_MODIFY_REG  1
1413
1414 #define USE_LOAD_POST_INCREMENT(mode) \
1415   nds32_use_load_post_increment(mode)
1416 #define USE_LOAD_POST_DECREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1417 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1418 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1419
1420 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1421
1422 #define MAX_REGS_PER_ADDRESS 3
1423
1424 \f
1425 /* Anchored Addresses.  */
1426
1427 \f
1428 /* Condition Code Status.  */
1429
1430 \f
1431 /* Describing Relative Costs of Operations.  */
1432
1433 /* A C expression for the cost of a branch instruction.
1434    A value of 1 is the default;
1435    other values are interpreted relative to that.  */
1436 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
1437
1438 /* Override BRANCH_COST heuristic which empirically produces worse
1439    performance for removing short circuiting from the logical ops.  */
1440 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1441
1442 #define SLOW_BYTE_ACCESS 1
1443
1444 #define NO_FUNCTION_CSE 1
1445
1446 \f
1447 /* Adjusting the Instruction Scheduler.  */
1448
1449 \f
1450 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
1451
1452 #define TEXT_SECTION_ASM_OP     "\t.text"
1453 #define DATA_SECTION_ASM_OP     "\t.data"
1454
1455 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1456    So we use '.section .bss' alternatively.  */
1457 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
1458
1459 /* Define this macro to be an expression with a nonzero value if jump tables
1460    (for tablejump insns) should be output in the text section,
1461    along with the assembler instructions.
1462    Otherwise, the readonly data section is used.  */
1463 #define JUMP_TABLES_IN_TEXT_SECTION 1
1464
1465 \f
1466 /* Position Independent Code.  */
1467
1468 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1469
1470 #define SYMBOLIC_CONST_P(X)     \
1471 (GET_CODE (X) == SYMBOL_REF                                             \
1472  || GET_CODE (X) == LABEL_REF                                           \
1473  || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1474
1475 \f
1476 /* Defining the Output Assembler Language.  */
1477
1478 #define ASM_COMMENT_START "!"
1479
1480 #define ASM_APP_ON "! #APP\n"
1481
1482 #define ASM_APP_OFF "! #NO_APP\n"
1483
1484 #define ASM_OUTPUT_LABELREF(stream, name) \
1485   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1486
1487 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1488   assemble_name (stream, XSTR (sym, 0))
1489
1490 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
1491   assemble_name (stream, buf)
1492
1493 #define LOCAL_LABEL_PREFIX "."
1494
1495 #define REGISTER_NAMES \
1496 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
1497   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
1498   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1499   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
1500   "$AP",  "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1501   "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1502   "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1503   "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1504   "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1505   "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1506   "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1507   "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1508   "$fs62","$fs63",   "LB",   "LE",   "LC"                         \
1509 }
1510
1511 #define ADDITIONAL_REGISTER_NAMES                               \
1512 {                                                               \
1513   {"$r15", 15},                                                 \
1514   {"$r28", 28}, {"$r29", 29},   {"$r30", 30},   {"$r31", 31},   \
1515   {"$a0", 0},   {"$a1", 1},     {"$a2", 2},                     \
1516   {"$a3", 3},   {"$a4", 4},     {"$a5", 5},                     \
1517   {"$s0", 6},   {"$s1", 7},     {"$s2", 8},     {"$s3", 9},     \
1518   {"$s4", 10},  {"$s5", 11},    {"$s6", 12},    {"$s7", 13},    \
1519   {"$s8", 14},                                                  \
1520   {"$t0", 16},  {"$t1", 17},    {"$t2", 18},    {"$t3", 19},    \
1521   {"$t4", 20},  {"$t5", 21},    {"$t6", 22},    {"$t7", 23},    \
1522   {"$t8", 24},  {"$t9", 25},                                    \
1523   {"$p0", 26},  {"$p1", 27},                                    \
1524   {"$h0", 0},   {"$h1", 1},     {"$h2", 2},     {"$h3", 3},     \
1525   {"$h4", 4},   {"$h5", 5},     {"$h6", 6},     {"$h7", 7},     \
1526   {"$h8", 8},   {"$h9", 9},     {"$h10", 10},   {"$h11", 11},   \
1527   {"$h12", 16}, {"$h13", 17},   {"$h14", 18},   {"$h15", 19},   \
1528   {"$o0", 0},   {"$o1", 1},     {"$o2", 2},     {"$o3", 3},     \
1529   {"$o4", 4},   {"$o5", 5},     {"$o6", 6},     {"$o7", 7},     \
1530 }
1531
1532 #define OVERLAPPING_REGISTER_NAMES              \
1533 {                                               \
1534   {"$fd0",  NDS32_FIRST_FPR_REGNUM + 0,  2},    \
1535   {"$fd1",  NDS32_FIRST_FPR_REGNUM + 2,  2},    \
1536   {"$fd2",  NDS32_FIRST_FPR_REGNUM + 4,  2},    \
1537   {"$fd3",  NDS32_FIRST_FPR_REGNUM + 6,  2},    \
1538   {"$fd4",  NDS32_FIRST_FPR_REGNUM + 8,  2},    \
1539   {"$fd5",  NDS32_FIRST_FPR_REGNUM + 10, 2},    \
1540   {"$fd6",  NDS32_FIRST_FPR_REGNUM + 12, 2},    \
1541   {"$fd7",  NDS32_FIRST_FPR_REGNUM + 14, 2},    \
1542   {"$fd8",  NDS32_FIRST_FPR_REGNUM + 16, 2},    \
1543   {"$fd9",  NDS32_FIRST_FPR_REGNUM + 18, 2},    \
1544   {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2},    \
1545   {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2},    \
1546   {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2},    \
1547   {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2},    \
1548   {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2},    \
1549   {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2},    \
1550   {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2},    \
1551   {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2},    \
1552   {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2},    \
1553   {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2},    \
1554   {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2},    \
1555   {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2},    \
1556   {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2},    \
1557   {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2},    \
1558   {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2},    \
1559   {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2},    \
1560   {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2},    \
1561   {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2},    \
1562   {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2},    \
1563   {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2},    \
1564   {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2},    \
1565   {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2},    \
1566 }
1567
1568 /* Output normal jump table entry.  */
1569 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1570   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1571
1572 /* Output pc relative jump table entry.  */
1573 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
1574   do                                                                    \
1575     {                                                                   \
1576       switch (GET_MODE (body))                                          \
1577         {                                                               \
1578         case E_QImode:                                                    \
1579           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
1580           break;                                                        \
1581         case E_HImode:                                                    \
1582           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
1583           break;                                                        \
1584         case E_SImode:                                                    \
1585           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
1586           break;                                                        \
1587         default:                                                        \
1588           gcc_unreachable();                                            \
1589         }                                                               \
1590     } while (0)
1591
1592 /* We have to undef it first because elfos.h formerly define it
1593    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
1594 #undef  ASM_OUTPUT_CASE_LABEL
1595 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
1596   do                                                               \
1597     {                                                              \
1598       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
1599       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
1600     } while (0)
1601
1602 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
1603   do                                                   \
1604     {                                                  \
1605       /* Because our jump table is in text section,    \
1606          we need to make sure 2-byte alignment after   \
1607          the jump table for instructions fetch.  */    \
1608       if (GET_MODE (PATTERN (table)) == QImode)        \
1609         ASM_OUTPUT_ALIGN (stream, 1);                  \
1610       asm_fprintf (stream, "\t! Jump Table End\n");    \
1611     }  while (0)
1612
1613 /* This macro is not documented yet.
1614    But we do need it to make jump table vector aligned.  */
1615 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
1616
1617 #define DWARF2_UNWIND_INFO 1
1618
1619 #define JUMP_ALIGN(x) \
1620   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1621
1622 #define LOOP_ALIGN(x) \
1623   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1624
1625 #define LABEL_ALIGN(x) \
1626   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1627
1628 #define ASM_OUTPUT_ALIGN(stream, power) \
1629   fprintf (stream, "\t.align\t%d\n", power)
1630
1631 \f
1632 /* Controlling Debugging Information Format.  */
1633
1634 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1635
1636 #define DWARF2_DEBUGGING_INFO 1
1637
1638 #define DWARF2_ASM_LINE_DEBUG_INFO 1
1639
1640 \f
1641 /* Cross Compilation and Floating Point.  */
1642
1643 \f
1644 /* Mode Switching Instructions.  */
1645
1646 \f
1647 /* Defining target-specific uses of __attribute__.  */
1648
1649 \f
1650 /* Emulating TLS.  */
1651
1652 \f
1653 /* Defining coprocessor specifics for MIPS targets.  */
1654
1655 \f
1656 /* Parameters for Precompiled Header Validity Checking.  */
1657
1658 \f
1659 /* C++ ABI parameters.  */
1660
1661 \f
1662 /* Adding support for named address spaces.  */
1663
1664 \f
1665 /* Miscellaneous Parameters.  */
1666
1667 /* This is the machine mode that elements of a jump-table should have.  */
1668 #define CASE_VECTOR_MODE Pmode
1669
1670 /* Return the preferred mode for and addr_diff_vec when the mininum
1671    and maximum offset are known.  */
1672 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1673   nds32_case_vector_shorten_mode (min_offset, max_offset, body)
1674
1675 /* Generate pc relative jump table when -fpic or -Os.  */
1676 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1677
1678 /* Define this macro if operations between registers with integral mode
1679    smaller than a word are always performed on the entire register.  */
1680 #define WORD_REGISTER_OPERATIONS 1
1681
1682 /* A C expression indicating when insns that read memory in mem_mode,
1683    an integral mode narrower than a word, set the bits outside of mem_mode
1684    to be either the sign-extension or the zero-extension of the data read.  */
1685 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1686
1687 /* The maximum number of bytes that a single instruction can move quickly
1688    between memory and registers or between two memory locations.  */
1689 #define MOVE_MAX 4
1690
1691 /* A C expression that is nonzero if on this machine the number of bits
1692    actually used for the count of a shift operation is equal to the number
1693    of bits needed to represent the size of the object being shifted.  */
1694 #define SHIFT_COUNT_TRUNCATED 1
1695
1696 /* A C expression describing the value returned by a comparison operator with
1697    an integral mode and stored by a store-flag instruction ('cstoremode4')
1698    when the condition is true.  */
1699 #define STORE_FLAG_VALUE 1
1700
1701 /* A C expression that indicates whether the architecture defines a value for
1702    clz or ctz with a zero operand.  In nds32 clz for 0 result 32 is defined
1703    in ISA spec */
1704 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
1705
1706 /* An alias for the machine mode for pointers.  */
1707 #define Pmode SImode
1708
1709 /* An alias for the machine mode used for memory references to functions
1710    being called, in call RTL expressions.  */
1711 #define FUNCTION_MODE SImode
1712
1713 /* ------------------------------------------------------------------------ */