gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  28    It is used in nds32_encode_section_info() to store flag in symbol_ref
  29    in case the symbol should be placed in .rodata section.
  30    So that we can check it in nds32_legitimate_address_p().  */
  31 #define NDS32_SYMBOL_FLAG_RODATA \
  32   (SYMBOL_FLAG_MACH_DEP << 0)
  33 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  34   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  35
  36 /* Classifies expand result for expand helper function.  */
  37 enum nds32_expand_result_type
  38 {
  39   EXPAND_DONE,
  40   EXPAND_FAIL,
  41   EXPAND_CREATE_TEMPLATE
  42 };
  43
  44 /* Computing the Length of an Insn.  */
  45 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  46   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  47
  48 /* Check instruction LS-37-FP-implied form.
  49    Note: actually its immediate range is imm9u
  50          since it is used for lwi37/swi37 instructions.  */
  51 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  52   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  53    && REGNO (ra) == FP_REGNUM               \
  54    && satisfies_constraint_Iu09 (imm))
  55
  56 /* Check instruction LS-37-SP-implied form.
  57    Note: actually its immediate range is imm9u
  58          since it is used for lwi37/swi37 instructions.  */
  59 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  60   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  61    && REGNO (ra) == SP_REGNUM               \
  62    && satisfies_constraint_Iu09 (imm))
  63
  64
  65 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  66 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  67
  68 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  69    Note: no need to check ra because Ra5 means it covers all registers.  */
  70 #define NDS32_LS_450_P(rt, ra, imm)                     \
  71   ((imm == const0_rtx)                                  \
  72    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  73        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  74
  75 /* Check instruction RRI-333-form.  */
  76 #define NDS32_RRI_333_P(rt, ra, imm)           \
  77   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  78    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  79    && satisfies_constraint_Iu03 (imm))
  80
  81 /* Check instruction RI-45-form.  */
  82 #define NDS32_RI_45_P(rt, ra, imm)                     \
  83   (REGNO (rt) == REGNO (ra)                            \
  84    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  85        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  86    && satisfies_constraint_Iu05 (imm))
  87
  88
  89 /* Check instruction RR-33-form.  */
  90 #define NDS32_RR_33_P(rt, ra)                   \
  91   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  92    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  93
  94 /* Check instruction RRR-333-form.  */
  95 #define NDS32_RRR_333_P(rt, ra, rb)             \
  96   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  97    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  98    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  99
 100 /* Check instruction RR-45-form.
 101    Note: no need to check rb because Rb5 means it covers all registers.  */
 102 #define NDS32_RR_45_P(rt, ra, rb)               \
 103   (REGNO (rt) == REGNO (ra)                     \
 104    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
 105        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
 106
 107 /* Classifies address type to distinguish 16-bit/32-bit format.  */
 108 enum nds32_16bit_address_type
 109 {
 110   /* [reg]: 45 format address.  */
 111   ADDRESS_REG,
 112   /* [lo_reg + imm3u]: 333 format address.  */
 113   ADDRESS_LO_REG_IMM3U,
 114   /* post_inc [lo_reg + imm3u]: 333 format address.  */
 115   ADDRESS_POST_INC_LO_REG_IMM3U,
 116   /* [$r8 + imm7u]: r8 imply address.  */
 117   ADDRESS_R8_IMM7U,
 118   /* [$fp + imm7u]: fp imply address.  */
 119   ADDRESS_FP_IMM7U,
 120   /* [$sp + imm7u]: sp imply address.  */
 121   ADDRESS_SP_IMM7U,
 122   /* Other address format.  */
 123   ADDRESS_NOT_16BIT_FORMAT
 124 };
 125
 126
 127 /* ------------------------------------------------------------------------ */
 128
 129 /* Define maximum numbers of registers for passing arguments.  */
 130 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 131
 132 /* Define the register number for first argument.  */
 133 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 134
 135 /* Define the register number for return value.  */
 136 #define NDS32_GPR_RET_FIRST_REGNUM 0
 137
 138 /* Define the first integer register number.  */
 139 #define NDS32_FIRST_GPR_REGNUM 0
 140 /* Define the last integer register number.  */
 141 #define NDS32_LAST_GPR_REGNUM 31
 142
 143 #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
 144 #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
 145   (TARGET_REDUCED_REGS ? 10 : 14)
 146
 147 /* Define double word alignment bits.  */
 148 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 149
 150 /* Define alignment checking macros for convenience.  */
 151 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 152 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 153 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 154
 155 /* Get alignment according to mode or type information.
 156    When 'type' is nonnull, there is no need to look at 'mode'.  */
 157 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 158   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 159
 160 /* Round X up to the nearest double word.  */
 161 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 162
 163
 164 /* This macro is used to calculate the numbers of registers for
 165    containing 'size' bytes of the argument.
 166    The size of a register is a word in nds32 target.
 167    So we use UNITS_PER_WORD to do the calculation.  */
 168 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 169   ((mode == BLKmode)                                                     \
 170    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 171    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 172
 173 /* This macro is used to return the register number for passing argument.
 174    We need to obey the following rules:
 175      1. If it is required MORE THAN one register,
 176         we need to further check if it really needs to be
 177         aligned on double words.
 178           a) If double word alignment is necessary,
 179              the register number must be even value.
 180           b) Otherwise, the register number can be odd or even value.
 181      2. If it is required ONLY one register,
 182         the register number can be odd or even value.  */
 183 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 184   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 185    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 186       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 187       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 188    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 189
 190 /* This macro is to check if there are still available registers
 191    for passing argument, which must be entirely in registers.  */
 192 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 193   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 194     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 195    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 196        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 197
 198 /* This macro is to check if there are still available registers
 199    for passing argument, either entirely in registers or partially
 200    in registers.  */
 201 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 202   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 203    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 204
 205 /* This macro is to check if the register is required to be saved on stack.
 206    If call_used_regs[regno] == 0, regno is the callee-saved register.
 207    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 208    As long as the register satisfies both criteria above,
 209    it is required to be saved.  */
 210 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 211   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 212
 213 /* This macro is to check if the push25/pop25 are available to be used
 214    for code generation.  Because pop25 also performs return behavior,
 215    the instructions may not be available for some cases.
 216    If we want to use push25/pop25, all the following conditions must
 217    be satisfied:
 218      1. TARGET_V3PUSH is set.
 219      2. Current function is not an ISR function.
 220      3. Current function is not a variadic function.*/
 221 #define NDS32_V3PUSH_AVAILABLE_P  \
 222   (TARGET_V3PUSH \
 223    && !nds32_isr_function_p (current_function_decl) \
 224    && (cfun->machine->va_args_size == 0))
 225
 226 /* ------------------------------------------------------------------------ */
 227
 228 /* A C structure for machine-specific, per-function data.
 229    This is added to the cfun structure.  */
 230 struct GTY(()) machine_function
 231 {
 232   /* Number of bytes allocated on the stack for variadic args
 233      if we want to push them into stack as pretend arguments by ourself.  */
 234   int va_args_size;
 235   /* Number of bytes reserved on the stack for
 236      local and temporary variables.  */
 237   int local_size;
 238   /* Number of bytes allocated on the stack for outgoing arguments.  */
 239   int out_args_size;
 240
 241   /* Number of bytes on the stack for saving $fp.  */
 242   int fp_size;
 243   /* Number of bytes on the stack for saving $gp.  */
 244   int gp_size;
 245   /* Number of bytes on the stack for saving $lp.  */
 246   int lp_size;
 247
 248   /* Number of bytes on the stack for saving general purpose
 249      callee-saved registers.  */
 250   int callee_saved_gpr_regs_size;
 251
 252   /* The padding bytes in callee-saved area may be required.  */
 253   int callee_saved_area_gpr_padding_bytes;
 254
 255   /* The first required general purpose callee-saved register.  */
 256   int callee_saved_first_gpr_regno;
 257   /* The last required general purpose callee-saved register.  */
 258   int callee_saved_last_gpr_regno;
 259
 260   /* The padding bytes in varargs area may be required.  */
 261   int va_args_area_padding_bytes;
 262
 263   /* The first required register that should be saved on stack for va_args.  */
 264   int va_args_first_regno;
 265   /* The last required register that should be saved on stack for va_args.  */
 266   int va_args_last_regno;
 267
 268   /* Indicate that whether this function needs
 269      prologue/epilogue code generation.  */
 270   int naked_p;
 271   /* Indicate that whether this function
 272      uses fp_as_gp optimization.  */
 273   int fp_as_gp_p;
 274 };
 275
 276 /* A C structure that contains the arguments information.  */
 277 typedef struct
 278 {
 279   unsigned int gpr_offset;
 280 } nds32_cumulative_args;
 281
 282 /* ------------------------------------------------------------------------ */
 283
 284 /* The following we define C-ISR related stuff.
 285    In nds32 architecture, we have 73 vectors for interrupt/exception.
 286    For each vector (except for vector 0, which is used for reset behavior),
 287    we allow users to set its register saving scheme and interrupt level.  */
 288
 289 /* There are 73 vectors in nds32 architecture.
 290    0 for reset handler,
 291    1-8 for exception handler,
 292    and 9-72 for interrupt handler.
 293    We use an array, which is defined in nds32.c, to record
 294    essential information for each vector.  */
 295 #define NDS32_N_ISR_VECTORS 73
 296
 297 /* Define possible isr category.  */
 298 enum nds32_isr_category
 299 {
 300   NDS32_ISR_NONE,
 301   NDS32_ISR_INTERRUPT,
 302   NDS32_ISR_EXCEPTION,
 303   NDS32_ISR_RESET
 304 };
 305
 306 /* Define isr register saving scheme.  */
 307 enum nds32_isr_save_reg
 308 {
 309   NDS32_SAVE_ALL,
 310   NDS32_PARTIAL_SAVE
 311 };
 312
 313 /* Define isr nested type.  */
 314 enum nds32_isr_nested_type
 315 {
 316   NDS32_NESTED,
 317   NDS32_NOT_NESTED,
 318   NDS32_NESTED_READY
 319 };
 320
 321 /* Define structure to record isr information.
 322    The isr vector array 'isr_vectors[]' with this structure
 323    is defined in nds32.c.  */
 324 struct nds32_isr_info
 325 {
 326   /* The field to identify isr category.
 327      It should be set to NDS32_ISR_NONE by default.
 328      If user specifies a function as isr by using attribute,
 329      this field will be set accordingly.  */
 330   enum nds32_isr_category category;
 331
 332   /* A string for the applied function name.
 333      It should be set to empty string by default.  */
 334   char func_name[100];
 335
 336   /* The register saving scheme.
 337      It should be set to NDS32_PARTIAL_SAVE by default
 338      unless user specifies attribute to change it.  */
 339   enum nds32_isr_save_reg save_reg;
 340
 341   /* The nested type.
 342      It should be set to NDS32_NOT_NESTED by default
 343      unless user specifies attribute to change it.  */
 344   enum nds32_isr_nested_type nested_type;
 345
 346   /* Total vectors.
 347      The total vectors = interrupt + exception numbers + reset.
 348      It should be set to 0 by default.
 349      This field is ONLY used in NDS32_ISR_RESET category.  */
 350   unsigned int total_n_vectors;
 351
 352   /* A string for nmi handler name.
 353      It should be set to empty string by default.
 354      This field is ONLY used in NDS32_ISR_RESET category.  */
 355   char nmi_name[100];
 356
 357   /* A string for warm handler name.
 358      It should be set to empty string by default.
 359      This field is ONLY used in NDS32_ISR_RESET category.  */
 360   char warm_name[100];
 361 };
 362
 363 /* ------------------------------------------------------------------------ */
 364
 365 /* Define code for all nds32 builtins.  */
 366 enum nds32_builtins
 367 {
 368   NDS32_BUILTIN_ISYNC,
 369   NDS32_BUILTIN_ISB,
 370   NDS32_BUILTIN_MFSR,
 371   NDS32_BUILTIN_MFUSR,
 372   NDS32_BUILTIN_MTSR,
 373   NDS32_BUILTIN_MTUSR,
 374   NDS32_BUILTIN_SETGIE_EN,
 375   NDS32_BUILTIN_SETGIE_DIS,
 376   NDS32_BUILTIN_FFB,
 377   NDS32_BUILTIN_FFMISM,
 378   NDS32_BUILTIN_FLMISM,
 379   NDS32_BUILTIN_UALOAD_HW,
 380   NDS32_BUILTIN_UALOAD_W,
 381   NDS32_BUILTIN_UALOAD_DW,
 382   NDS32_BUILTIN_UASTORE_HW,
 383   NDS32_BUILTIN_UASTORE_W,
 384   NDS32_BUILTIN_UASTORE_DW,
 385   NDS32_BUILTIN_COUNT
 386 };
 387
 388 /* ------------------------------------------------------------------------ */
 389
 390 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 391 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 392 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 393
 394 #define TARGET_CMODEL_SMALL \
 395    (nds32_cmodel_option == CMODEL_SMALL)
 396 #define TARGET_CMODEL_MEDIUM \
 397    (nds32_cmodel_option == CMODEL_MEDIUM)
 398 #define TARGET_CMODEL_LARGE \
 399    (nds32_cmodel_option == CMODEL_LARGE)
 400
 401 /* When -mcmodel=small or -mcmodel=medium,
 402    compiler may generate gp-base instruction directly.  */
 403 #define TARGET_GP_DIRECT \
 404    (nds32_cmodel_option == CMODEL_SMALL\
 405     || nds32_cmodel_option == CMODEL_MEDIUM)
 406
 407 #define TARGET_SOFT_FLOAT 1
 408 #define TARGET_HARD_FLOAT 0
 409
 410 /* ------------------------------------------------------------------------ */
 411 \f
 412 /* Controlling the Compilation Driver.  */
 413
 414 #define OPTION_DEFAULT_SPECS \
 415   {"arch", "%{!march=*:-march=%(VALUE)}" }
 416
 417 #define CC1_SPEC \
 418   ""
 419
 420 #define ASM_SPEC \
 421   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 422
 423 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 424 #define LINK_SPEC \
 425   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 426   " %{mrelax:--relax}"
 427
 428 #define LIB_SPEC \
 429   " -lc -lgloss"
 430
 431 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 432    by applying different crt stuff.  In the convention, crt0.o is the
 433    startup file without constructor/destructor;
 434    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 435    startup files with constructor/destructor.
 436    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 437    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 438    currently provided by GCC for nds32 target.
 439
 440    For nds32 target so far:
 441    If -mno-ctor-dtor, we are going to link
 442    "crt0.o [user objects]".
 443    If general cases, we are going to link
 444    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 445 #define STARTFILE_SPEC \
 446   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 447   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 448 #define ENDFILE_SPEC \
 449   " %{!mno-ctor-dtor:crtend1.o%s}"
 450
 451 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 452    configure gcc with --target=nds32be-* setting.
 453    Check gcc/config.gcc for more information.  */
 454 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 455 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 456 #else
 457 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 458 #endif
 459
 460 /* Currently we only have elf toolchain,
 461    where -mcmodel=medium is always the default.  */
 462 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 463
 464 #define MULTILIB_DEFAULTS \
 465   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 466
 467 \f
 468 /* Run-time Target Specification.  */
 469
 470 #define TARGET_CPU_CPP_BUILTINS() \
 471   nds32_cpu_cpp_builtins (pfile)
 472
 473 \f
 474 /* Defining Data Structures for Per-function Information.  */
 475
 476 /* This macro is called once per function,
 477    before generation of any RTL has begun.  */
 478 #define INIT_EXPANDERS  nds32_init_expanders ()
 479
 480 \f
 481 /* Storage Layout.  */
 482
 483 #define BITS_BIG_ENDIAN 0
 484
 485 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 486
 487 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 488
 489 #define UNITS_PER_WORD 4
 490
 491 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 492   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 493     {                                                                       \
 494       (m) = SImode;                                                         \
 495     }
 496
 497 #define PARM_BOUNDARY 32
 498
 499 #define STACK_BOUNDARY 64
 500
 501 #define FUNCTION_BOUNDARY 32
 502
 503 #define BIGGEST_ALIGNMENT 64
 504
 505 #define EMPTY_FIELD_BOUNDARY 32
 506
 507 #define STRUCTURE_SIZE_BOUNDARY 8
 508
 509 #define STRICT_ALIGNMENT 1
 510
 511 #define PCC_BITFIELD_TYPE_MATTERS 1
 512
 513 \f
 514 /* Layout of Source Language Data Types.  */
 515
 516 #define INT_TYPE_SIZE           32
 517 #define SHORT_TYPE_SIZE         16
 518 #define LONG_TYPE_SIZE          32
 519 #define LONG_LONG_TYPE_SIZE     64
 520
 521 #define FLOAT_TYPE_SIZE         32
 522 #define DOUBLE_TYPE_SIZE        64
 523 #define LONG_DOUBLE_TYPE_SIZE   64
 524
 525 #define DEFAULT_SIGNED_CHAR 1
 526
 527 #define SIZE_TYPE "long unsigned int"
 528 #define PTRDIFF_TYPE "long int"
 529 #define WCHAR_TYPE "unsigned int"
 530 #define WCHAR_TYPE_SIZE 32
 531
 532 \f
 533 /* Register Usage.  */
 534
 535 /* Number of actual hardware registers.
 536    The hardware registers are assigned numbers for the compiler
 537    from 0 to just below FIRST_PSEUDO_REGISTER.
 538    All registers that the compiler knows about must be given numbers,
 539    even those that are not normally considered general registers.  */
 540 #define FIRST_PSEUDO_REGISTER 101
 541
 542 /* An initializer that says which registers are used for fixed
 543    purposes all throughout the compiled code and are therefore
 544    not available for general allocation.
 545
 546    $r28 : $fp
 547    $r29 : $gp
 548    $r30 : $lp
 549    $r31 : $sp
 550
 551    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 552    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 553
 554    reserved for assembler : $r15
 555    reserved for other use : $r24, $r25, $r26, $r27 */
 556 #define FIXED_REGISTERS \
 557 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 558       0,   0,   0,   0,   0,   0,   0,   0,     \
 559   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 560       0,   0,   0,   0,   0,   0,   0,   1,     \
 561   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 562       0,   0,   0,   0,   0,   0,   0,   0,     \
 563   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 564       1,   1,   1,   1,   0,   1,   0,   1,     \
 565   /* AP   FP    Reserved.................... */ \
 566       1,   1,   1,   1,   1,   1,   1,   1,     \
 567   /* Reserved............................... */ \
 568       1,   1,   1,   1,   1,   1,   1,   1,     \
 569   /* Reserved............................... */ \
 570       1,   1,   1,   1,   1,   1,   1,   1,     \
 571   /* Reserved............................... */ \
 572       1,   1,   1,   1,   1,   1,   1,   1,     \
 573   /* Reserved............................... */ \
 574       1,   1,   1,   1,   1,   1,   1,   1,     \
 575   /* Reserved............................... */ \
 576       1,   1,   1,   1,   1,   1,   1,   1,     \
 577   /* Reserved............................... */ \
 578       1,   1,   1,   1,   1,   1,   1,   1,     \
 579   /* Reserved............................... */ \
 580       1,   1,   1,   1,   1,   1,   1,   1,     \
 581   /* Reserved............................... */ \
 582       1,   1,   1,   1,   1                     \
 583 }
 584
 585 /* Identifies the registers that are not available for
 586    general allocation of values that must live across
 587    function calls -- so they are caller-save registers.
 588
 589    0 : callee-save registers
 590    1 : caller-save registers */
 591 #define CALL_USED_REGISTERS \
 592 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 593       1,   1,   1,   1,   1,   1,   0,   0,     \
 594   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 595       0,   0,   0,   0,   0,   0,   0,   1,     \
 596   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 597       1,   1,   1,   1,   1,   1,   1,   1,     \
 598   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 599       1,   1,   1,   1,   0,   1,   0,   1,     \
 600   /* AP   FP    Reserved.................... */ \
 601       1,   1,   1,   1,   1,   1,   1,   1,     \
 602   /* Reserved............................... */ \
 603       1,   1,   1,   1,   1,   1,   1,   1,     \
 604   /* Reserved............................... */ \
 605       1,   1,   1,   1,   1,   1,   1,   1,     \
 606   /* Reserved............................... */ \
 607       1,   1,   1,   1,   1,   1,   1,   1,     \
 608   /* Reserved............................... */ \
 609       1,   1,   1,   1,   1,   1,   1,   1,     \
 610   /* Reserved............................... */ \
 611       1,   1,   1,   1,   1,   1,   1,   1,     \
 612   /* Reserved............................... */ \
 613       1,   1,   1,   1,   1,   1,   1,   1,     \
 614   /* Reserved............................... */ \
 615       1,   1,   1,   1,   1,   1,   1,   1,     \
 616   /* Reserved............................... */ \
 617       1,   1,   1,   1,   1                     \
 618 }
 619
 620 /* In nds32 target, we have three levels of registers:
 621      LOW_COST_REGS    : $r0 ~ $r7
 622      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 623      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 624 #define REG_ALLOC_ORDER \
 625 {   0,   1,   2,   3,   4,   5,   6,   7, \
 626    16,  17,  18,  19,   9,  10,  11,  12, \
 627    13,  14,  8,   15,  20,  21,  22,  23, \
 628    24,  25,  26,  27,  28,  29,  30,  31, \
 629    32,  33,  34,  35,  36,  37,  38,  39, \
 630    40,  41,  42,  43,  44,  45,  46,  47, \
 631    48,  49,  50,  51,  52,  53,  54,  55, \
 632    56,  57,  58,  59,  60,  61,  62,  63, \
 633    64,  65,  66,  67,  68,  69,  70,  71, \
 634    72,  73,  74,  75,  76,  77,  78,  79, \
 635    80,  81,  82,  83,  84,  85,  86,  87, \
 636    88,  89,  90,  91,  92,  93,  94,  95, \
 637    96,  97,  98,  99, 100,                \
 638 }
 639
 640 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
 641    to be rearranged based on optimizing for speed or size.  */
 642 #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
 643
 644 /* Tell IRA to use the order we define rather than messing it up with its
 645    own cost calculations.  */
 646 #define HONOR_REG_ALLOC_ORDER optimize_size
 647
 648 \f
 649 /* Register Classes.  */
 650
 651 /* In nds32 target, we have three levels of registers:
 652      Low cost regsiters    : $r0 ~ $r7
 653      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 654      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 655
 656    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 657    so that it provides more chance to use low cost registers.  */
 658 enum reg_class
 659 {
 660   NO_REGS,
 661   R5_REG,
 662   R8_REG,
 663   R15_TA_REG,
 664   STACK_REG,
 665   FRAME_POINTER_REG,
 666   LOW_REGS,
 667   MIDDLE_REGS,
 668   HIGH_REGS,
 669   GENERAL_REGS,
 670   FRAME_REGS,
 671   ALL_REGS,
 672   LIM_REG_CLASSES
 673 };
 674
 675 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 676
 677 #define REG_CLASS_NAMES \
 678 {                       \
 679   "NO_REGS",            \
 680   "R5_REG",             \
 681   "R8_REG",             \
 682   "R15_TA_REG",         \
 683   "STACK_REG",          \
 684   "FRAME_POINTER_REG",  \
 685   "LOW_REGS",           \
 686   "MIDDLE_REGS",        \
 687   "HIGH_REGS",          \
 688   "GENERAL_REGS",       \
 689   "FRAME_REGS",         \
 690   "ALL_REGS"            \
 691 }
 692
 693 #define REG_CLASS_CONTENTS \
 694 { /* NO_REGS                                    */  \
 695   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
 696   /* R5_REG              : 5                    */  \
 697   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
 698   /* R8_REG              : 8                    */  \
 699   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
 700   /* R15_TA_REG          : 15                   */  \
 701   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
 702   /* STACK_REG           : 31                   */  \
 703   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
 704   /* FRAME_POINTER_REG   : 28                   */  \
 705   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
 706   /* LOW_REGS            : 0-7                  */  \
 707   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
 708   /* MIDDLE_REGS         : 0-11, 16-19          */  \
 709   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
 710   /* HIGH_REGS           : 12-14, 20-31         */  \
 711   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
 712   /* GENERAL_REGS        : 0-31                 */  \
 713   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
 714   /* FRAME_REGS          : 32, 33               */  \
 715   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
 716   /* ALL_REGS            : 0-100                */  \
 717   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
 718 }
 719
 720 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 721
 722 #define BASE_REG_CLASS GENERAL_REGS
 723 #define INDEX_REG_CLASS GENERAL_REGS
 724
 725 /* Return nonzero if it is suitable for use as a
 726    base register in operand addresses.
 727    So far, we return nonzero only if "num" is a hard reg
 728    of the suitable class or a pseudo register which is
 729    allocated to a suitable hard reg.  */
 730 #define REGNO_OK_FOR_BASE_P(num) \
 731   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 732
 733 /* Return nonzero if it is suitable for use as a
 734    index register in operand addresses.
 735    So far, we return nonzero only if "num" is a hard reg
 736    of the suitable class or a pseudo register which is
 737    allocated to a suitable hard reg.
 738    The difference between an index register and a base register is that
 739    the index register may be scaled.  */
 740 #define REGNO_OK_FOR_INDEX_P(num) \
 741   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 742
 743 \f
 744 /* Obsolete Macros for Defining Constraints.  */
 745
 746 \f
 747 /* Stack Layout and Calling Conventions.  */
 748
 749 #define STACK_GROWS_DOWNWARD 1
 750
 751 #define FRAME_GROWS_DOWNWARD 1
 752
 753 #define STACK_POINTER_OFFSET 0
 754
 755 #define FIRST_PARM_OFFSET(fundecl) \
 756   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 757
 758 #define RETURN_ADDR_RTX(count, frameaddr) \
 759   nds32_return_addr_rtx (count, frameaddr)
 760
 761 /* A C expression whose value is RTL representing the location
 762    of the incoming return address at the beginning of any function
 763    before the prologue.
 764    If this RTL is REG, you should also define
 765    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 766 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 767 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 768
 769 #define STACK_POINTER_REGNUM SP_REGNUM
 770
 771 #define FRAME_POINTER_REGNUM 33
 772
 773 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 774
 775 #define ARG_POINTER_REGNUM 32
 776
 777 #define STATIC_CHAIN_REGNUM 16
 778
 779 #define ELIMINABLE_REGS                                \
 780 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 781   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 782   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 783   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 784
 785 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 786   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 787
 788 #define ACCUMULATE_OUTGOING_ARGS 1
 789
 790 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 791
 792 #define CUMULATIVE_ARGS nds32_cumulative_args
 793
 794 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 795   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 796
 797 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 798    We better cast REGNO into signed integer so that we can avoid
 799    'comparison of unsigned expression >= 0 is always true' warning.  */
 800 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 801   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 802    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
 803
 804 #define DEFAULT_PCC_STRUCT_RETURN 0
 805
 806 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 807    from a function, the stack pointer does not matter.
 808    The value is tested only in functions that have frame pointers.
 809    In nds32 target, the function epilogue recovers the
 810    stack pointer from the frame.  */
 811 #define EXIT_IGNORE_STACK 1
 812
 813 #define FUNCTION_PROFILER(file, labelno) \
 814   fprintf (file, "/* profiler %d */\n", (labelno))
 815
 816 #define PROFILE_HOOK(LABEL)                                             \
 817   {                                                                     \
 818     rtx fun, lp;                                                        \
 819     lp = get_hard_reg_initial_val (Pmode, LP_REGNUM);                   \
 820     fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount");                        \
 821     emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode);           \
 822   }
 823
 824 \f
 825 /* Implementing the Varargs Macros.  */
 826
 827 \f
 828 /* Trampolines for Nested Functions.  */
 829
 830 /* Giving A-function and B-function,
 831    if B-function wants to call A-function's nested function,
 832    we need to fill trampoline code into A-function's stack
 833    so that B-function can execute the code in stack to indirectly
 834    jump to (like 'trampoline' action) desired nested function.
 835
 836    The trampoline code for nds32 target must contains following parts:
 837
 838      1. instructions (4 * 4 = 16 bytes):
 839           get $pc first
 840           load chain_value to static chain register via $pc
 841           load nested function address to $r15 via $pc
 842           jump to desired nested function via $r15
 843      2. data (4 * 2 = 8 bytes):
 844           chain_value
 845           nested function address
 846
 847    Please check nds32.c implementation for more information.  */
 848 #define TRAMPOLINE_SIZE 24
 849
 850 /* Because all instructions/data in trampoline template are 4-byte size,
 851    we set trampoline alignment 8*4=32 bits.  */
 852 #define TRAMPOLINE_ALIGNMENT 32
 853
 854 \f
 855 /* Implicit Calls to Library Routines.  */
 856
 857 \f
 858 /* Addressing Modes.  */
 859
 860 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 861 #define HAVE_POST_INCREMENT 1
 862 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 863 #define HAVE_POST_DECREMENT 1
 864
 865 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 866 #define HAVE_POST_MODIFY_DISP 1
 867 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 868 #define HAVE_POST_MODIFY_REG  1
 869
 870 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 871
 872 #define MAX_REGS_PER_ADDRESS 3
 873
 874 \f
 875 /* Anchored Addresses.  */
 876
 877 \f
 878 /* Condition Code Status.  */
 879
 880 \f
 881 /* Describing Relative Costs of Operations.  */
 882
 883 /* A C expression for the cost of a branch instruction.
 884    A value of 1 is the default;
 885    other values are interpreted relative to that.  */
 886 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
 887
 888 /* Override BRANCH_COST heuristic which empirically produces worse
 889    performance for removing short circuiting from the logical ops.  */
 890 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 891
 892 #define SLOW_BYTE_ACCESS 1
 893
 894 #define NO_FUNCTION_CSE 1
 895
 896 \f
 897 /* Adjusting the Instruction Scheduler.  */
 898
 899 \f
 900 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 901
 902 #define TEXT_SECTION_ASM_OP     "\t.text"
 903 #define DATA_SECTION_ASM_OP     "\t.data"
 904
 905 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 906    So we use '.section .bss' alternatively.  */
 907 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 908
 909 /* Define this macro to be an expression with a nonzero value if jump tables
 910    (for tablejump insns) should be output in the text section,
 911    along with the assembler instructions.
 912    Otherwise, the readonly data section is used.  */
 913 #define JUMP_TABLES_IN_TEXT_SECTION 1
 914
 915 \f
 916 /* Position Independent Code.  */
 917
 918 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
 919
 920 \f
 921 /* Defining the Output Assembler Language.  */
 922
 923 #define ASM_COMMENT_START "!"
 924
 925 #define ASM_APP_ON "! #APP"
 926
 927 #define ASM_APP_OFF "! #NO_APP\n"
 928
 929 #define ASM_OUTPUT_LABELREF(stream, name) \
 930   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 931
 932 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 933   assemble_name (stream, XSTR (sym, 0))
 934
 935 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 936   assemble_name (stream, buf)
 937
 938 #define LOCAL_LABEL_PREFIX "."
 939
 940 #define REGISTER_NAMES \
 941 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 942   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 943   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 944   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 945   "$AP",  "$SFP", "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 946   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 947   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 948   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 949   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 950   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 951   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 952   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 953   "NA",   "NA",   "NA",   "NA",   "NA"                            \
 954 }
 955
 956 /* Output normal jump table entry.  */
 957 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 958   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 959
 960 /* Output pc relative jump table entry.  */
 961 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 962   do                                                                    \
 963     {                                                                   \
 964       switch (GET_MODE (body))                                          \
 965         {                                                               \
 966         case E_QImode:                                                    \
 967           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 968           break;                                                        \
 969         case E_HImode:                                                    \
 970           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 971           break;                                                        \
 972         case E_SImode:                                                    \
 973           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 974           break;                                                        \
 975         default:                                                        \
 976           gcc_unreachable();                                            \
 977         }                                                               \
 978     } while (0)
 979
 980 /* We have to undef it first because elfos.h formerly define it
 981    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 982 #undef  ASM_OUTPUT_CASE_LABEL
 983 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 984   do                                                               \
 985     {                                                              \
 986       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 987       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 988     } while (0)
 989
 990 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 991   do                                                   \
 992     {                                                  \
 993       /* Because our jump table is in text section,    \
 994          we need to make sure 2-byte alignment after   \
 995          the jump table for instructions fetch.  */    \
 996       if (GET_MODE (PATTERN (table)) == QImode)        \
 997         ASM_OUTPUT_ALIGN (stream, 1);                  \
 998       asm_fprintf (stream, "\t! Jump Table End\n");    \
 999     }  while (0)
1000
1001 /* This macro is not documented yet.
1002    But we do need it to make jump table vector aligned.  */
1003 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
1004
1005 #define DWARF2_UNWIND_INFO 1
1006
1007 #define JUMP_ALIGN(x) \
1008   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1009
1010 #define LOOP_ALIGN(x) \
1011   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1012
1013 #define LABEL_ALIGN(x) \
1014   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1015
1016 #define ASM_OUTPUT_ALIGN(stream, power) \
1017   fprintf (stream, "\t.align\t%d\n", power)
1018
1019 \f
1020 /* Controlling Debugging Information Format.  */
1021
1022 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1023
1024 #define DWARF2_DEBUGGING_INFO 1
1025
1026 #define DWARF2_ASM_LINE_DEBUG_INFO 1
1027
1028 \f
1029 /* Cross Compilation and Floating Point.  */
1030
1031 \f
1032 /* Mode Switching Instructions.  */
1033
1034 \f
1035 /* Defining target-specific uses of __attribute__.  */
1036
1037 \f
1038 /* Emulating TLS.  */
1039
1040 \f
1041 /* Defining coprocessor specifics for MIPS targets.  */
1042
1043 \f
1044 /* Parameters for Precompiled Header Validity Checking.  */
1045
1046 \f
1047 /* C++ ABI parameters.  */
1048
1049 \f
1050 /* Adding support for named address spaces.  */
1051
1052 \f
1053 /* Miscellaneous Parameters.  */
1054
1055 /* This is the machine mode that elements of a jump-table should have.  */
1056 #define CASE_VECTOR_MODE Pmode
1057
1058 /* Return the preferred mode for and addr_diff_vec when the mininum
1059    and maximum offset are known.  */
1060 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1061    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
1062    : (max_offset >= 100) ? HImode                               \
1063    : QImode)
1064
1065 /* Generate pc relative jump table when -fpic or -Os.  */
1066 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1067
1068 /* Define this macro if operations between registers with integral mode
1069    smaller than a word are always performed on the entire register.  */
1070 #define WORD_REGISTER_OPERATIONS 1
1071
1072 /* A C expression indicating when insns that read memory in mem_mode,
1073    an integral mode narrower than a word, set the bits outside of mem_mode
1074    to be either the sign-extension or the zero-extension of the data read.  */
1075 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1076
1077 /* The maximum number of bytes that a single instruction can move quickly
1078    between memory and registers or between two memory locations.  */
1079 #define MOVE_MAX 4
1080
1081 /* A C expression that is nonzero if on this machine the number of bits
1082    actually used for the count of a shift operation is equal to the number
1083    of bits needed to represent the size of the object being shifted.  */
1084 #define SHIFT_COUNT_TRUNCATED 1
1085
1086 /* A C expression describing the value returned by a comparison operator with
1087    an integral mode and stored by a store-flag instruction ('cstoremode4')
1088    when the condition is true.  */
1089 #define STORE_FLAG_VALUE 1
1090
1091 /* A C expression that indicates whether the architecture defines a value for
1092    clz or ctz with a zero operand.  In nds32 clz for 0 result 32 is defined
1093    in ISA spec */
1094 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
1095
1096 /* An alias for the machine mode for pointers.  */
1097 #define Pmode SImode
1098
1099 /* An alias for the machine mode used for memory references to functions
1100    being called, in call RTL expressions.  */
1101 #define FUNCTION_MODE SImode
1102
1103 /* ------------------------------------------------------------------------ */