gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  28    It is used in nds32_encode_section_info() to store flag in symbol_ref
  29    in case the symbol should be placed in .rodata section.
  30    So that we can check it in nds32_legitimate_address_p().  */
  31 #define NDS32_SYMBOL_FLAG_RODATA \
  32   (SYMBOL_FLAG_MACH_DEP << 0)
  33 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  34   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  35
  36 /* Computing the Length of an Insn.  */
  37 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  38   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  39
  40 /* Check instruction LS-37-FP-implied form.
  41    Note: actually its immediate range is imm9u
  42          since it is used for lwi37/swi37 instructions.  */
  43 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  44   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  45    && REGNO (ra) == FP_REGNUM               \
  46    && satisfies_constraint_Iu09 (imm))
  47
  48 /* Check instruction LS-37-SP-implied form.
  49    Note: actually its immediate range is imm9u
  50          since it is used for lwi37/swi37 instructions.  */
  51 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  52   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  53    && REGNO (ra) == SP_REGNUM               \
  54    && satisfies_constraint_Iu09 (imm))
  55
  56
  57 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  58 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  59
  60 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  61    Note: no need to check ra because Ra5 means it covers all registers.  */
  62 #define NDS32_LS_450_P(rt, ra, imm)                     \
  63   ((imm == const0_rtx)                                  \
  64    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  65        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  66
  67 /* Check instruction RRI-333-form.  */
  68 #define NDS32_RRI_333_P(rt, ra, imm)           \
  69   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  70    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  71    && satisfies_constraint_Iu03 (imm))
  72
  73 /* Check instruction RI-45-form.  */
  74 #define NDS32_RI_45_P(rt, ra, imm)                     \
  75   (REGNO (rt) == REGNO (ra)                            \
  76    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  77        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  78    && satisfies_constraint_Iu05 (imm))
  79
  80
  81 /* Check instruction RR-33-form.  */
  82 #define NDS32_RR_33_P(rt, ra)                   \
  83   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  84    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  85
  86 /* Check instruction RRR-333-form.  */
  87 #define NDS32_RRR_333_P(rt, ra, rb)             \
  88   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  89    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  90    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  91
  92 /* Check instruction RR-45-form.
  93    Note: no need to check rb because Rb5 means it covers all registers.  */
  94 #define NDS32_RR_45_P(rt, ra, rb)               \
  95   (REGNO (rt) == REGNO (ra)                     \
  96    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  97        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  98
  99 /* Classifies address type to distinguish 16-bit/32-bit format.  */
 100 enum nds32_16bit_address_type
 101 {
 102   /* [reg]: 45 format address.  */
 103   ADDRESS_REG,
 104   /* [lo_reg + imm3u]: 333 format address.  */
 105   ADDRESS_LO_REG_IMM3U,
 106   /* post_inc [lo_reg + imm3u]: 333 format address.  */
 107   ADDRESS_POST_INC_LO_REG_IMM3U,
 108   /* [$fp + imm7u]: fp imply address.  */
 109   ADDRESS_FP_IMM7U,
 110   /* [$sp + imm7u]: sp imply address.  */
 111   ADDRESS_SP_IMM7U,
 112   /* Other address format.  */
 113   ADDRESS_NOT_16BIT_FORMAT
 114 };
 115
 116
 117 /* ------------------------------------------------------------------------ */
 118
 119 /* Define maximum numbers of registers for passing arguments.  */
 120 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 121
 122 /* Define the register number for first argument.  */
 123 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 124
 125 /* Define the register number for return value.  */
 126 #define NDS32_GPR_RET_FIRST_REGNUM 0
 127
 128 /* Define the first integer register number.  */
 129 #define NDS32_FIRST_GPR_REGNUM 0
 130 /* Define the last integer register number.  */
 131 #define NDS32_LAST_GPR_REGNUM 31
 132
 133 #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
 134 #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
 135   (TARGET_REDUCED_REGS ? 10 : 14)
 136
 137 /* Define double word alignment bits.  */
 138 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 139
 140 /* Define alignment checking macros for convenience.  */
 141 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 142 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 143 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 144
 145 /* Get alignment according to mode or type information.
 146    When 'type' is nonnull, there is no need to look at 'mode'.  */
 147 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 148   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 149
 150 /* Round X up to the nearest double word.  */
 151 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 152
 153
 154 /* This macro is used to calculate the numbers of registers for
 155    containing 'size' bytes of the argument.
 156    The size of a register is a word in nds32 target.
 157    So we use UNITS_PER_WORD to do the calculation.  */
 158 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 159   ((mode == BLKmode)                                                     \
 160    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 161    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 162
 163 /* This macro is used to return the register number for passing argument.
 164    We need to obey the following rules:
 165      1. If it is required MORE THAN one register,
 166         we need to further check if it really needs to be
 167         aligned on double words.
 168           a) If double word alignment is necessary,
 169              the register number must be even value.
 170           b) Otherwise, the register number can be odd or even value.
 171      2. If it is required ONLY one register,
 172         the register number can be odd or even value.  */
 173 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 174   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 175    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 176       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 177       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 178    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 179
 180 /* This macro is to check if there are still available registers
 181    for passing argument, which must be entirely in registers.  */
 182 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 183   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 184     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 185    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 186        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 187
 188 /* This macro is to check if there are still available registers
 189    for passing argument, either entirely in registers or partially
 190    in registers.  */
 191 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 192   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 193    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 194
 195 /* This macro is to check if the register is required to be saved on stack.
 196    If call_used_regs[regno] == 0, regno is the callee-saved register.
 197    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 198    As long as the register satisfies both criteria above,
 199    it is required to be saved.  */
 200 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 201   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 202
 203 /* This macro is to check if the push25/pop25 are available to be used
 204    for code generation.  Because pop25 also performs return behavior,
 205    the instructions may not be available for some cases.
 206    If we want to use push25/pop25, all the following conditions must
 207    be satisfied:
 208      1. TARGET_V3PUSH is set.
 209      2. Current function is not an ISR function.
 210      3. Current function is not a variadic function.*/
 211 #define NDS32_V3PUSH_AVAILABLE_P  \
 212   (TARGET_V3PUSH \
 213    && !nds32_isr_function_p (current_function_decl) \
 214    && (cfun->machine->va_args_size == 0))
 215
 216 /* ------------------------------------------------------------------------ */
 217
 218 /* A C structure for machine-specific, per-function data.
 219    This is added to the cfun structure.  */
 220 struct GTY(()) machine_function
 221 {
 222   /* Number of bytes allocated on the stack for variadic args
 223      if we want to push them into stack as pretend arguments by ourself.  */
 224   int va_args_size;
 225   /* Number of bytes reserved on the stack for
 226      local and temporary variables.  */
 227   int local_size;
 228   /* Number of bytes allocated on the stack for outgoing arguments.  */
 229   int out_args_size;
 230
 231   /* Number of bytes on the stack for saving $fp.  */
 232   int fp_size;
 233   /* Number of bytes on the stack for saving $gp.  */
 234   int gp_size;
 235   /* Number of bytes on the stack for saving $lp.  */
 236   int lp_size;
 237
 238   /* Number of bytes on the stack for saving general purpose
 239      callee-saved registers.  */
 240   int callee_saved_gpr_regs_size;
 241
 242   /* The padding bytes in callee-saved area may be required.  */
 243   int callee_saved_area_gpr_padding_bytes;
 244
 245   /* The first required general purpose callee-saved register.  */
 246   int callee_saved_first_gpr_regno;
 247   /* The last required general purpose callee-saved register.  */
 248   int callee_saved_last_gpr_regno;
 249
 250   /* The padding bytes in varargs area may be required.  */
 251   int va_args_area_padding_bytes;
 252
 253   /* The first required register that should be saved on stack for va_args.  */
 254   int va_args_first_regno;
 255   /* The last required register that should be saved on stack for va_args.  */
 256   int va_args_last_regno;
 257
 258   /* Indicate that whether this function needs
 259      prologue/epilogue code generation.  */
 260   int naked_p;
 261   /* Indicate that whether this function
 262      uses fp_as_gp optimization.  */
 263   int fp_as_gp_p;
 264 };
 265
 266 /* A C structure that contains the arguments information.  */
 267 typedef struct
 268 {
 269   unsigned int gpr_offset;
 270 } nds32_cumulative_args;
 271
 272 /* ------------------------------------------------------------------------ */
 273
 274 /* The following we define C-ISR related stuff.
 275    In nds32 architecture, we have 73 vectors for interrupt/exception.
 276    For each vector (except for vector 0, which is used for reset behavior),
 277    we allow users to set its register saving scheme and interrupt level.  */
 278
 279 /* There are 73 vectors in nds32 architecture.
 280    0 for reset handler,
 281    1-8 for exception handler,
 282    and 9-72 for interrupt handler.
 283    We use an array, which is defined in nds32.c, to record
 284    essential information for each vector.  */
 285 #define NDS32_N_ISR_VECTORS 73
 286
 287 /* Define possible isr category.  */
 288 enum nds32_isr_category
 289 {
 290   NDS32_ISR_NONE,
 291   NDS32_ISR_INTERRUPT,
 292   NDS32_ISR_EXCEPTION,
 293   NDS32_ISR_RESET
 294 };
 295
 296 /* Define isr register saving scheme.  */
 297 enum nds32_isr_save_reg
 298 {
 299   NDS32_SAVE_ALL,
 300   NDS32_PARTIAL_SAVE
 301 };
 302
 303 /* Define isr nested type.  */
 304 enum nds32_isr_nested_type
 305 {
 306   NDS32_NESTED,
 307   NDS32_NOT_NESTED,
 308   NDS32_NESTED_READY
 309 };
 310
 311 /* Define structure to record isr information.
 312    The isr vector array 'isr_vectors[]' with this structure
 313    is defined in nds32.c.  */
 314 struct nds32_isr_info
 315 {
 316   /* The field to identify isr category.
 317      It should be set to NDS32_ISR_NONE by default.
 318      If user specifies a function as isr by using attribute,
 319      this field will be set accordingly.  */
 320   enum nds32_isr_category category;
 321
 322   /* A string for the applied function name.
 323      It should be set to empty string by default.  */
 324   char func_name[100];
 325
 326   /* The register saving scheme.
 327      It should be set to NDS32_PARTIAL_SAVE by default
 328      unless user specifies attribute to change it.  */
 329   enum nds32_isr_save_reg save_reg;
 330
 331   /* The nested type.
 332      It should be set to NDS32_NOT_NESTED by default
 333      unless user specifies attribute to change it.  */
 334   enum nds32_isr_nested_type nested_type;
 335
 336   /* Total vectors.
 337      The total vectors = interrupt + exception numbers + reset.
 338      It should be set to 0 by default.
 339      This field is ONLY used in NDS32_ISR_RESET category.  */
 340   unsigned int total_n_vectors;
 341
 342   /* A string for nmi handler name.
 343      It should be set to empty string by default.
 344      This field is ONLY used in NDS32_ISR_RESET category.  */
 345   char nmi_name[100];
 346
 347   /* A string for warm handler name.
 348      It should be set to empty string by default.
 349      This field is ONLY used in NDS32_ISR_RESET category.  */
 350   char warm_name[100];
 351 };
 352
 353 /* ------------------------------------------------------------------------ */
 354
 355 /* Define code for all nds32 builtins.  */
 356 enum nds32_builtins
 357 {
 358   NDS32_BUILTIN_ISYNC,
 359   NDS32_BUILTIN_ISB,
 360   NDS32_BUILTIN_MFSR,
 361   NDS32_BUILTIN_MFUSR,
 362   NDS32_BUILTIN_MTSR,
 363   NDS32_BUILTIN_MTUSR,
 364   NDS32_BUILTIN_SETGIE_EN,
 365   NDS32_BUILTIN_SETGIE_DIS,
 366   NDS32_BUILTIN_FFB,
 367   NDS32_BUILTIN_FFMISM,
 368   NDS32_BUILTIN_FLMISM,
 369   NDS32_BUILTIN_UALOAD_HW,
 370   NDS32_BUILTIN_UALOAD_W,
 371   NDS32_BUILTIN_UALOAD_DW,
 372   NDS32_BUILTIN_UASTORE_HW,
 373   NDS32_BUILTIN_UASTORE_W,
 374   NDS32_BUILTIN_UASTORE_DW,
 375   NDS32_BUILTIN_COUNT
 376 };
 377
 378 /* ------------------------------------------------------------------------ */
 379
 380 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 381 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 382 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 383
 384 #define TARGET_CMODEL_SMALL \
 385    (nds32_cmodel_option == CMODEL_SMALL)
 386 #define TARGET_CMODEL_MEDIUM \
 387    (nds32_cmodel_option == CMODEL_MEDIUM)
 388 #define TARGET_CMODEL_LARGE \
 389    (nds32_cmodel_option == CMODEL_LARGE)
 390
 391 /* When -mcmodel=small or -mcmodel=medium,
 392    compiler may generate gp-base instruction directly.  */
 393 #define TARGET_GP_DIRECT \
 394    (nds32_cmodel_option == CMODEL_SMALL\
 395     || nds32_cmodel_option == CMODEL_MEDIUM)
 396
 397 #define TARGET_SOFT_FLOAT 1
 398 #define TARGET_HARD_FLOAT 0
 399
 400 /* ------------------------------------------------------------------------ */
 401 \f
 402 /* Controlling the Compilation Driver.  */
 403
 404 #define OPTION_DEFAULT_SPECS \
 405   {"arch", "%{!march=*:-march=%(VALUE)}" }
 406
 407 #define CC1_SPEC \
 408   ""
 409
 410 #define ASM_SPEC \
 411   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 412
 413 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 414 #define LINK_SPEC \
 415   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 416   " %{mrelax:--relax}"
 417
 418 #define LIB_SPEC \
 419   " -lc -lgloss"
 420
 421 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 422    by applying different crt stuff.  In the convention, crt0.o is the
 423    startup file without constructor/destructor;
 424    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 425    startup files with constructor/destructor.
 426    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 427    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 428    currently provided by GCC for nds32 target.
 429
 430    For nds32 target so far:
 431    If -mno-ctor-dtor, we are going to link
 432    "crt0.o [user objects]".
 433    If general cases, we are going to link
 434    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 435 #define STARTFILE_SPEC \
 436   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 437   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 438 #define ENDFILE_SPEC \
 439   " %{!mno-ctor-dtor:crtend1.o%s}"
 440
 441 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 442    configure gcc with --target=nds32be-* setting.
 443    Check gcc/config.gcc for more information.  */
 444 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 445 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 446 #else
 447 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 448 #endif
 449
 450 /* Currently we only have elf toolchain,
 451    where -mcmodel=medium is always the default.  */
 452 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 453
 454 #define MULTILIB_DEFAULTS \
 455   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 456
 457 \f
 458 /* Run-time Target Specification.  */
 459
 460 #define TARGET_CPU_CPP_BUILTINS() \
 461   nds32_cpu_cpp_builtins (pfile)
 462
 463 \f
 464 /* Defining Data Structures for Per-function Information.  */
 465
 466 /* This macro is called once per function,
 467    before generation of any RTL has begun.  */
 468 #define INIT_EXPANDERS  nds32_init_expanders ()
 469
 470 \f
 471 /* Storage Layout.  */
 472
 473 #define BITS_BIG_ENDIAN 0
 474
 475 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 476
 477 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 478
 479 #define UNITS_PER_WORD 4
 480
 481 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 482   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 483     {                                                                       \
 484       (m) = SImode;                                                         \
 485     }
 486
 487 #define PARM_BOUNDARY 32
 488
 489 #define STACK_BOUNDARY 64
 490
 491 #define FUNCTION_BOUNDARY 32
 492
 493 #define BIGGEST_ALIGNMENT 64
 494
 495 #define EMPTY_FIELD_BOUNDARY 32
 496
 497 #define STRUCTURE_SIZE_BOUNDARY 8
 498
 499 #define STRICT_ALIGNMENT 1
 500
 501 #define PCC_BITFIELD_TYPE_MATTERS 1
 502
 503 \f
 504 /* Layout of Source Language Data Types.  */
 505
 506 #define INT_TYPE_SIZE           32
 507 #define SHORT_TYPE_SIZE         16
 508 #define LONG_TYPE_SIZE          32
 509 #define LONG_LONG_TYPE_SIZE     64
 510
 511 #define FLOAT_TYPE_SIZE         32
 512 #define DOUBLE_TYPE_SIZE        64
 513 #define LONG_DOUBLE_TYPE_SIZE   64
 514
 515 #define DEFAULT_SIGNED_CHAR 1
 516
 517 #define SIZE_TYPE "long unsigned int"
 518 #define PTRDIFF_TYPE "long int"
 519 #define WCHAR_TYPE "unsigned int"
 520 #define WCHAR_TYPE_SIZE 32
 521
 522 \f
 523 /* Register Usage.  */
 524
 525 /* Number of actual hardware registers.
 526    The hardware registers are assigned numbers for the compiler
 527    from 0 to just below FIRST_PSEUDO_REGISTER.
 528    All registers that the compiler knows about must be given numbers,
 529    even those that are not normally considered general registers.  */
 530 #define FIRST_PSEUDO_REGISTER 101
 531
 532 /* An initializer that says which registers are used for fixed
 533    purposes all throughout the compiled code and are therefore
 534    not available for general allocation.
 535
 536    $r28 : $fp
 537    $r29 : $gp
 538    $r30 : $lp
 539    $r31 : $sp
 540
 541    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 542    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 543
 544    reserved for assembler : $r15
 545    reserved for other use : $r24, $r25, $r26, $r27 */
 546 #define FIXED_REGISTERS \
 547 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 548       0,   0,   0,   0,   0,   0,   0,   0,     \
 549   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 550       0,   0,   0,   0,   0,   0,   0,   1,     \
 551   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 552       0,   0,   0,   0,   0,   0,   0,   0,     \
 553   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 554       1,   1,   1,   1,   0,   1,   0,   1,     \
 555   /* AP   FP    Reserved.................... */ \
 556       1,   1,   1,   1,   1,   1,   1,   1,     \
 557   /* Reserved............................... */ \
 558       1,   1,   1,   1,   1,   1,   1,   1,     \
 559   /* Reserved............................... */ \
 560       1,   1,   1,   1,   1,   1,   1,   1,     \
 561   /* Reserved............................... */ \
 562       1,   1,   1,   1,   1,   1,   1,   1,     \
 563   /* Reserved............................... */ \
 564       1,   1,   1,   1,   1,   1,   1,   1,     \
 565   /* Reserved............................... */ \
 566       1,   1,   1,   1,   1,   1,   1,   1,     \
 567   /* Reserved............................... */ \
 568       1,   1,   1,   1,   1,   1,   1,   1,     \
 569   /* Reserved............................... */ \
 570       1,   1,   1,   1,   1,   1,   1,   1,     \
 571   /* Reserved............................... */ \
 572       1,   1,   1,   1,   1                     \
 573 }
 574
 575 /* Identifies the registers that are not available for
 576    general allocation of values that must live across
 577    function calls -- so they are caller-save registers.
 578
 579    0 : callee-save registers
 580    1 : caller-save registers */
 581 #define CALL_USED_REGISTERS \
 582 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 583       1,   1,   1,   1,   1,   1,   0,   0,     \
 584   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 585       0,   0,   0,   0,   0,   0,   0,   1,     \
 586   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 587       1,   1,   1,   1,   1,   1,   1,   1,     \
 588   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 589       1,   1,   1,   1,   0,   1,   0,   1,     \
 590   /* AP   FP    Reserved.................... */ \
 591       1,   1,   1,   1,   1,   1,   1,   1,     \
 592   /* Reserved............................... */ \
 593       1,   1,   1,   1,   1,   1,   1,   1,     \
 594   /* Reserved............................... */ \
 595       1,   1,   1,   1,   1,   1,   1,   1,     \
 596   /* Reserved............................... */ \
 597       1,   1,   1,   1,   1,   1,   1,   1,     \
 598   /* Reserved............................... */ \
 599       1,   1,   1,   1,   1,   1,   1,   1,     \
 600   /* Reserved............................... */ \
 601       1,   1,   1,   1,   1,   1,   1,   1,     \
 602   /* Reserved............................... */ \
 603       1,   1,   1,   1,   1,   1,   1,   1,     \
 604   /* Reserved............................... */ \
 605       1,   1,   1,   1,   1,   1,   1,   1,     \
 606   /* Reserved............................... */ \
 607       1,   1,   1,   1,   1                     \
 608 }
 609
 610 /* In nds32 target, we have three levels of registers:
 611      LOW_COST_REGS    : $r0 ~ $r7
 612      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 613      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 614 #define REG_ALLOC_ORDER \
 615 {   0,   1,   2,   3,   4,   5,   6,   7, \
 616    16,  17,  18,  19,   9,  10,  11,  12, \
 617    13,  14,  8,   15,  20,  21,  22,  23, \
 618    24,  25,  26,  27,  28,  29,  30,  31, \
 619    32,  33,  34,  35,  36,  37,  38,  39, \
 620    40,  41,  42,  43,  44,  45,  46,  47, \
 621    48,  49,  50,  51,  52,  53,  54,  55, \
 622    56,  57,  58,  59,  60,  61,  62,  63, \
 623    64,  65,  66,  67,  68,  69,  70,  71, \
 624    72,  73,  74,  75,  76,  77,  78,  79, \
 625    80,  81,  82,  83,  84,  85,  86,  87, \
 626    88,  89,  90,  91,  92,  93,  94,  95, \
 627    96,  97,  98,  99, 100,                \
 628 }
 629
 630 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
 631    to be rearranged based on optimizing for speed or size.  */
 632 #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
 633
 634 /* Tell IRA to use the order we define rather than messing it up with its
 635    own cost calculations.  */
 636 #define HONOR_REG_ALLOC_ORDER optimize_size
 637
 638 \f
 639 /* Register Classes.  */
 640
 641 /* In nds32 target, we have three levels of registers:
 642      Low cost regsiters    : $r0 ~ $r7
 643      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 644      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 645
 646    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 647    so that it provides more chance to use low cost registers.  */
 648 enum reg_class
 649 {
 650   NO_REGS,
 651   R5_REG,
 652   R8_REG,
 653   R15_TA_REG,
 654   STACK_REG,
 655   FRAME_POINTER_REG,
 656   LOW_REGS,
 657   MIDDLE_REGS,
 658   HIGH_REGS,
 659   GENERAL_REGS,
 660   FRAME_REGS,
 661   ALL_REGS,
 662   LIM_REG_CLASSES
 663 };
 664
 665 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 666
 667 #define REG_CLASS_NAMES \
 668 {                       \
 669   "NO_REGS",            \
 670   "R5_REG",             \
 671   "R8_REG",             \
 672   "R15_TA_REG",         \
 673   "STACK_REG",          \
 674   "FRAME_POINTER_REG",  \
 675   "LOW_REGS",           \
 676   "MIDDLE_REGS",        \
 677   "HIGH_REGS",          \
 678   "GENERAL_REGS",       \
 679   "FRAME_REGS",         \
 680   "ALL_REGS"            \
 681 }
 682
 683 #define REG_CLASS_CONTENTS \
 684 { /* NO_REGS                                    */  \
 685   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
 686   /* R5_REG              : 5                    */  \
 687   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
 688   /* R8_REG              : 8                    */  \
 689   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
 690   /* R15_TA_REG          : 15                   */  \
 691   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
 692   /* STACK_REG           : 31                   */  \
 693   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
 694   /* FRAME_POINTER_REG   : 28                   */  \
 695   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
 696   /* LOW_REGS            : 0-7                  */  \
 697   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
 698   /* MIDDLE_REGS         : 0-11, 16-19          */  \
 699   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
 700   /* HIGH_REGS           : 12-14, 20-31         */  \
 701   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
 702   /* GENERAL_REGS        : 0-31                 */  \
 703   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
 704   /* FRAME_REGS          : 32, 33               */  \
 705   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
 706   /* ALL_REGS            : 0-100                */  \
 707   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
 708 }
 709
 710 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 711
 712 #define BASE_REG_CLASS GENERAL_REGS
 713 #define INDEX_REG_CLASS GENERAL_REGS
 714
 715 /* Return nonzero if it is suitable for use as a
 716    base register in operand addresses.
 717    So far, we return nonzero only if "num" is a hard reg
 718    of the suitable class or a pseudo register which is
 719    allocated to a suitable hard reg.  */
 720 #define REGNO_OK_FOR_BASE_P(num) \
 721   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 722
 723 /* Return nonzero if it is suitable for use as a
 724    index register in operand addresses.
 725    So far, we return nonzero only if "num" is a hard reg
 726    of the suitable class or a pseudo register which is
 727    allocated to a suitable hard reg.
 728    The difference between an index register and a base register is that
 729    the index register may be scaled.  */
 730 #define REGNO_OK_FOR_INDEX_P(num) \
 731   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 732
 733 \f
 734 /* Obsolete Macros for Defining Constraints.  */
 735
 736 \f
 737 /* Stack Layout and Calling Conventions.  */
 738
 739 #define STACK_GROWS_DOWNWARD 1
 740
 741 #define FRAME_GROWS_DOWNWARD 1
 742
 743 #define STACK_POINTER_OFFSET 0
 744
 745 #define FIRST_PARM_OFFSET(fundecl) \
 746   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 747
 748 #define RETURN_ADDR_RTX(count, frameaddr) \
 749   nds32_return_addr_rtx (count, frameaddr)
 750
 751 /* A C expression whose value is RTL representing the location
 752    of the incoming return address at the beginning of any function
 753    before the prologue.
 754    If this RTL is REG, you should also define
 755    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 756 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 757 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 758
 759 #define STACK_POINTER_REGNUM SP_REGNUM
 760
 761 #define FRAME_POINTER_REGNUM 33
 762
 763 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 764
 765 #define ARG_POINTER_REGNUM 32
 766
 767 #define STATIC_CHAIN_REGNUM 16
 768
 769 #define ELIMINABLE_REGS                                \
 770 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 771   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 772   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 773   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 774
 775 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 776   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 777
 778 #define ACCUMULATE_OUTGOING_ARGS 1
 779
 780 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 781
 782 #define CUMULATIVE_ARGS nds32_cumulative_args
 783
 784 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 785   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 786
 787 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 788    We better cast REGNO into signed integer so that we can avoid
 789    'comparison of unsigned expression >= 0 is always true' warning.  */
 790 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 791   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 792    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
 793
 794 #define DEFAULT_PCC_STRUCT_RETURN 0
 795
 796 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 797    from a function, the stack pointer does not matter.
 798    The value is tested only in functions that have frame pointers.
 799    In nds32 target, the function epilogue recovers the
 800    stack pointer from the frame.  */
 801 #define EXIT_IGNORE_STACK 1
 802
 803 #define FUNCTION_PROFILER(file, labelno) \
 804   fprintf (file, "/* profiler %d */\n", (labelno))
 805
 806 #define PROFILE_HOOK(LABEL)                                             \
 807   {                                                                     \
 808     rtx fun, lp;                                                        \
 809     lp = get_hard_reg_initial_val (Pmode, LP_REGNUM);                   \
 810     fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount");                        \
 811     emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode);           \
 812   }
 813
 814 \f
 815 /* Implementing the Varargs Macros.  */
 816
 817 \f
 818 /* Trampolines for Nested Functions.  */
 819
 820 /* Giving A-function and B-function,
 821    if B-function wants to call A-function's nested function,
 822    we need to fill trampoline code into A-function's stack
 823    so that B-function can execute the code in stack to indirectly
 824    jump to (like 'trampoline' action) desired nested function.
 825
 826    The trampoline code for nds32 target must contains following parts:
 827
 828      1. instructions (4 * 4 = 16 bytes):
 829           get $pc first
 830           load chain_value to static chain register via $pc
 831           load nested function address to $r15 via $pc
 832           jump to desired nested function via $r15
 833      2. data (4 * 2 = 8 bytes):
 834           chain_value
 835           nested function address
 836
 837    Please check nds32.c implementation for more information.  */
 838 #define TRAMPOLINE_SIZE 24
 839
 840 /* Because all instructions/data in trampoline template are 4-byte size,
 841    we set trampoline alignment 8*4=32 bits.  */
 842 #define TRAMPOLINE_ALIGNMENT 32
 843
 844 \f
 845 /* Implicit Calls to Library Routines.  */
 846
 847 \f
 848 /* Addressing Modes.  */
 849
 850 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 851 #define HAVE_POST_INCREMENT 1
 852 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 853 #define HAVE_POST_DECREMENT 1
 854
 855 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 856 #define HAVE_POST_MODIFY_DISP 1
 857 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 858 #define HAVE_POST_MODIFY_REG  1
 859
 860 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 861
 862 #define MAX_REGS_PER_ADDRESS 3
 863
 864 \f
 865 /* Anchored Addresses.  */
 866
 867 \f
 868 /* Condition Code Status.  */
 869
 870 \f
 871 /* Describing Relative Costs of Operations.  */
 872
 873 /* A C expression for the cost of a branch instruction.
 874    A value of 1 is the default;
 875    other values are interpreted relative to that.  */
 876 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
 877
 878 /* Override BRANCH_COST heuristic which empirically produces worse
 879    performance for removing short circuiting from the logical ops.  */
 880 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 881
 882 #define SLOW_BYTE_ACCESS 1
 883
 884 #define NO_FUNCTION_CSE 1
 885
 886 \f
 887 /* Adjusting the Instruction Scheduler.  */
 888
 889 \f
 890 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 891
 892 #define TEXT_SECTION_ASM_OP     "\t.text"
 893 #define DATA_SECTION_ASM_OP     "\t.data"
 894
 895 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 896    So we use '.section .bss' alternatively.  */
 897 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 898
 899 /* Define this macro to be an expression with a nonzero value if jump tables
 900    (for tablejump insns) should be output in the text section,
 901    along with the assembler instructions.
 902    Otherwise, the readonly data section is used.  */
 903 #define JUMP_TABLES_IN_TEXT_SECTION 1
 904
 905 \f
 906 /* Position Independent Code.  */
 907
 908 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
 909
 910 \f
 911 /* Defining the Output Assembler Language.  */
 912
 913 #define ASM_COMMENT_START "!"
 914
 915 #define ASM_APP_ON "! #APP"
 916
 917 #define ASM_APP_OFF "! #NO_APP\n"
 918
 919 #define ASM_OUTPUT_LABELREF(stream, name) \
 920   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 921
 922 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 923   assemble_name (stream, XSTR (sym, 0))
 924
 925 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 926   assemble_name (stream, buf)
 927
 928 #define LOCAL_LABEL_PREFIX "."
 929
 930 #define REGISTER_NAMES \
 931 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 932   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 933   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 934   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 935   "$AP",  "$SFP", "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 936   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 937   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 938   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 939   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 940   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 941   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 942   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   "NA",   \
 943   "NA",   "NA",   "NA",   "NA",   "NA"                            \
 944 }
 945
 946 /* Output normal jump table entry.  */
 947 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 948   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 949
 950 /* Output pc relative jump table entry.  */
 951 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 952   do                                                                    \
 953     {                                                                   \
 954       switch (GET_MODE (body))                                          \
 955         {                                                               \
 956         case E_QImode:                                                    \
 957           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 958           break;                                                        \
 959         case E_HImode:                                                    \
 960           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 961           break;                                                        \
 962         case E_SImode:                                                    \
 963           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 964           break;                                                        \
 965         default:                                                        \
 966           gcc_unreachable();                                            \
 967         }                                                               \
 968     } while (0)
 969
 970 /* We have to undef it first because elfos.h formerly define it
 971    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 972 #undef  ASM_OUTPUT_CASE_LABEL
 973 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 974   do                                                               \
 975     {                                                              \
 976       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 977       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 978     } while (0)
 979
 980 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 981   do                                                   \
 982     {                                                  \
 983       /* Because our jump table is in text section,    \
 984          we need to make sure 2-byte alignment after   \
 985          the jump table for instructions fetch.  */    \
 986       if (GET_MODE (PATTERN (table)) == QImode)        \
 987         ASM_OUTPUT_ALIGN (stream, 1);                  \
 988       asm_fprintf (stream, "\t! Jump Table End\n");    \
 989     }  while (0)
 990
 991 /* This macro is not documented yet.
 992    But we do need it to make jump table vector aligned.  */
 993 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
 994
 995 #define DWARF2_UNWIND_INFO 1
 996
 997 #define JUMP_ALIGN(x) \
 998   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
 999
1000 #define LOOP_ALIGN(x) \
1001   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1002
1003 #define LABEL_ALIGN(x) \
1004   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1005
1006 #define ASM_OUTPUT_ALIGN(stream, power) \
1007   fprintf (stream, "\t.align\t%d\n", power)
1008
1009 \f
1010 /* Controlling Debugging Information Format.  */
1011
1012 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1013
1014 #define DWARF2_DEBUGGING_INFO 1
1015
1016 #define DWARF2_ASM_LINE_DEBUG_INFO 1
1017
1018 \f
1019 /* Cross Compilation and Floating Point.  */
1020
1021 \f
1022 /* Mode Switching Instructions.  */
1023
1024 \f
1025 /* Defining target-specific uses of __attribute__.  */
1026
1027 \f
1028 /* Emulating TLS.  */
1029
1030 \f
1031 /* Defining coprocessor specifics for MIPS targets.  */
1032
1033 \f
1034 /* Parameters for Precompiled Header Validity Checking.  */
1035
1036 \f
1037 /* C++ ABI parameters.  */
1038
1039 \f
1040 /* Adding support for named address spaces.  */
1041
1042 \f
1043 /* Miscellaneous Parameters.  */
1044
1045 /* This is the machine mode that elements of a jump-table should have.  */
1046 #define CASE_VECTOR_MODE Pmode
1047
1048 /* Return the preferred mode for and addr_diff_vec when the mininum
1049    and maximum offset are known.  */
1050 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1051    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
1052    : (max_offset >= 100) ? HImode                               \
1053    : QImode)
1054
1055 /* Generate pc relative jump table when -fpic or -Os.  */
1056 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1057
1058 /* Define this macro if operations between registers with integral mode
1059    smaller than a word are always performed on the entire register.  */
1060 #define WORD_REGISTER_OPERATIONS 1
1061
1062 /* A C expression indicating when insns that read memory in mem_mode,
1063    an integral mode narrower than a word, set the bits outside of mem_mode
1064    to be either the sign-extension or the zero-extension of the data read.  */
1065 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1066
1067 /* The maximum number of bytes that a single instruction can move quickly
1068    between memory and registers or between two memory locations.  */
1069 #define MOVE_MAX 4
1070
1071 /* A C expression that is nonzero if on this machine the number of bits
1072    actually used for the count of a shift operation is equal to the number
1073    of bits needed to represent the size of the object being shifted.  */
1074 #define SHIFT_COUNT_TRUNCATED 1
1075
1076 /* A C expression describing the value returned by a comparison operator with
1077    an integral mode and stored by a store-flag instruction ('cstoremode4')
1078    when the condition is true.  */
1079 #define STORE_FLAG_VALUE 1
1080
1081 /* A C expression that indicates whether the architecture defines a value for
1082    clz or ctz with a zero operand.  In nds32 clz for 0 result 32 is defined
1083    in ISA spec */
1084 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
1085
1086 /* An alias for the machine mode for pointers.  */
1087 #define Pmode SImode
1088
1089 /* An alias for the machine mode used for memory references to functions
1090    being called, in call RTL expressions.  */
1091 #define FUNCTION_MODE SImode
1092
1093 /* ------------------------------------------------------------------------ */