1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2014 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* ------------------------------------------------------------------------ */
24 /* The following are auxiliary macros or structure declarations
25 that are used all over the nds32.c and nds32.h. */
28 /* Computing the Length of an Insn. */
29 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
30 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
32 /* Check instruction LS-37-FP-implied form.
33 Note: actually its immediate range is imm9u
34 since it is used for lwi37/swi37 instructions. */
35 #define NDS32_LS_37_FP_P(rt, ra, imm) \
36 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
37 && REGNO (ra) == FP_REGNUM \
38 && satisfies_constraint_Iu09 (imm))
40 /* Check instruction LS-37-SP-implied form.
41 Note: actually its immediate range is imm9u
42 since it is used for lwi37/swi37 instructions. */
43 #define NDS32_LS_37_SP_P(rt, ra, imm) \
44 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
45 && REGNO (ra) == SP_REGNUM \
46 && satisfies_constraint_Iu09 (imm))
49 /* Check load/store instruction form : Rt3, Ra3, imm3u. */
50 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
52 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
53 Note: no need to check ra because Ra5 means it covers all registers. */
54 #define NDS32_LS_450_P(rt, ra, imm) \
55 ((imm == const0_rtx) \
56 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
57 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
59 /* Check instruction RRI-333-form. */
60 #define NDS32_RRI_333_P(rt, ra, imm) \
61 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
62 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
63 && satisfies_constraint_Iu03 (imm))
65 /* Check instruction RI-45-form. */
66 #define NDS32_RI_45_P(rt, ra, imm) \
67 (REGNO (rt) == REGNO (ra) \
68 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
69 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
70 && satisfies_constraint_Iu05 (imm))
73 /* Check instruction RR-33-form. */
74 #define NDS32_RR_33_P(rt, ra) \
75 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
76 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
78 /* Check instruction RRR-333-form. */
79 #define NDS32_RRR_333_P(rt, ra, rb) \
80 (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
81 && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
82 && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
84 /* Check instruction RR-45-form.
85 Note: no need to check rb because Rb5 means it covers all registers. */
86 #define NDS32_RR_45_P(rt, ra, rb) \
87 (REGNO (rt) == REGNO (ra) \
88 && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
89 || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
91 /* Classifies address type to distinguish 16-bit/32-bit format. */
92 enum nds32_16bit_address_type
94 /* [reg]: 45 format address. */
96 /* [lo_reg + imm3u]: 333 format address. */
98 /* post_inc [lo_reg + imm3u]: 333 format address. */
99 ADDRESS_POST_INC_LO_REG_IMM3U
,
100 /* [$fp + imm7u]: fp imply address. */
102 /* [$sp + imm7u]: sp imply address. */
104 /* Other address format. */
105 ADDRESS_NOT_16BIT_FORMAT
109 /* ------------------------------------------------------------------------ */
111 /* Define maximum numbers of registers for passing arguments. */
112 #define NDS32_MAX_REGS_FOR_ARGS 6
114 /* Define the register number for first argument. */
115 #define NDS32_GPR_ARG_FIRST_REGNUM 0
117 /* Define the register number for return value. */
118 #define NDS32_GPR_RET_FIRST_REGNUM 0
121 /* Define double word alignment bits. */
122 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
124 /* Define alignment checking macros for convenience. */
125 #define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
126 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
127 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
129 /* Get alignment according to mode or type information.
130 When 'type' is nonnull, there is no need to look at 'mode'. */
131 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
132 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
134 /* Round X up to the nearest double word. */
135 #define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
138 /* This macro is used to calculate the numbers of registers for
139 containing 'size' bytes of the argument.
140 The size of a register is a word in nds32 target.
141 So we use UNITS_PER_WORD to do the calculation. */
142 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
144 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
145 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
147 /* This macro is used to return the register number for passing argument.
148 We need to obey the following rules:
149 1. If it is required MORE THAN one register,
150 we need to further check if it really needs to be
151 aligned on double words.
152 a) If double word alignment is necessary,
153 the register number must be even value.
154 b) Otherwise, the register number can be odd or even value.
155 2. If it is required ONLY one register,
156 the register number can be odd or even value. */
157 #define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \
158 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
159 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
160 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
161 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
162 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
164 /* This macro is to check if there are still available registers
165 for passing argument. */
166 #define NDS32_ARG_PASS_IN_REG_P(reg_offset, mode, type) \
167 (((reg_offset) < NDS32_MAX_REGS_FOR_ARGS) \
168 && ((reg_offset) + NDS32_NEED_N_REGS_FOR_ARG (mode, type) \
169 <= NDS32_MAX_REGS_FOR_ARGS))
171 /* This macro is to check if the register is required to be saved on stack.
172 If call_used_regs[regno] == 0, regno is the callee-saved register.
173 If df_regs_ever_live_p(regno) == true, it is used in the current function.
174 As long as the register satisfies both criteria above,
175 it is required to be saved. */
176 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
177 ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
179 /* ------------------------------------------------------------------------ */
181 /* A C structure for machine-specific, per-function data.
182 This is added to the cfun structure. */
183 struct GTY(()) machine_function
185 /* Number of bytes allocated on the stack for variadic args
186 if we want to push them into stack as pretend arguments by ourself. */
188 /* Number of bytes reserved on the stack for
189 local and temporary variables. */
191 /* Number of bytes allocated on the stack for outgoing arguments. */
194 /* Number of bytes on the stack for saving $fp. */
196 /* Number of bytes on the stack for saving $gp. */
198 /* Number of bytes on the stack for saving $lp. */
201 /* Number of bytes on the stack for saving callee-saved registers. */
202 int callee_saved_regs_size
;
203 /* The padding bytes in callee-saved area may be required. */
204 int callee_saved_area_padding_bytes
;
206 /* The first required register that should be saved on stack
207 for va_args (one named argument + nameless arguments). */
208 int va_args_first_regno
;
209 /* The last required register that should be saved on stack
210 for va_args (one named argument + nameless arguments). */
211 int va_args_last_regno
;
213 /* The first required callee-saved register. */
214 int callee_saved_regs_first_regno
;
215 /* The last required callee-saved register. */
216 int callee_saved_regs_last_regno
;
218 /* Indicate that whether this function needs
219 prologue/epilogue code generation. */
221 /* Indicate that whether this function
222 uses fp_as_gp optimization. */
226 /* A C structure that contains the arguments information. */
229 unsigned int reg_offset
;
230 } nds32_cumulative_args
;
232 /* ------------------------------------------------------------------------ */
234 /* The following we define C-ISR related stuff.
235 In nds32 architecture, we have 73 vectors for interrupt/exception.
236 For each vector (except for vector 0, which is used for reset behavior),
237 we allow users to set its register saving scheme and interrupt level. */
239 /* There are 73 vectors in nds32 architecture.
241 1-8 for exception handler,
242 and 9-72 for interrupt handler.
243 We use an array, which is defined in nds32.c, to record
244 essential information for each vector. */
245 #define NDS32_N_ISR_VECTORS 73
247 /* Define possible isr category. */
248 enum nds32_isr_category
256 /* Define isr register saving scheme. */
257 enum nds32_isr_save_reg
263 /* Define isr nested type. */
264 enum nds32_isr_nested_type
271 /* Define structure to record isr information.
272 The isr vector array 'isr_vectors[]' with this structure
273 is defined in nds32.c. */
274 struct nds32_isr_info
276 /* The field to identify isr category.
277 It should be set to NDS32_ISR_NONE by default.
278 If user specifies a function as isr by using attribute,
279 this field will be set accordingly. */
280 enum nds32_isr_category category
;
282 /* A string for the applied function name.
283 It should be set to empty string by default. */
286 /* The register saving scheme.
287 It should be set to NDS32_PARTIAL_SAVE by default
288 unless user specifies attribute to change it. */
289 enum nds32_isr_save_reg save_reg
;
292 It should be set to NDS32_NOT_NESTED by default
293 unless user specifies attribute to change it. */
294 enum nds32_isr_nested_type nested_type
;
297 The total vectors = interrupt + exception numbers + reset.
298 It should be set to 0 by default.
299 This field is ONLY used in NDS32_ISR_RESET category. */
300 unsigned int total_n_vectors
;
302 /* A string for nmi handler name.
303 It should be set to empty string by default.
304 This field is ONLY used in NDS32_ISR_RESET category. */
307 /* A string for warm handler name.
308 It should be set to empty string by default.
309 This field is ONLY used in NDS32_ISR_RESET category. */
313 /* ------------------------------------------------------------------------ */
315 /* Define code for all nds32 builtins. */
324 NDS32_BUILTIN_SETGIE_EN
,
325 NDS32_BUILTIN_SETGIE_DIS
328 /* ------------------------------------------------------------------------ */
330 #define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
331 #define TARGET_ISA_V3 (nds32_arch_option == ARCH_V3)
332 #define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
334 /* ------------------------------------------------------------------------ */
336 /* Controlling the Compilation Driver. */
338 #define OPTION_DEFAULT_SPECS \
339 {"arch", "%{!march=*:-march=%(VALUE)}" }
345 " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
347 /* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
348 we need to pass '--relax' to linker.
349 Besides, for -mex9, we need to further pass '--mex9'. */
351 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
352 " %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
358 /* The option -mno-ctor-dtor can disable constructor/destructor feature
359 by applying different crt stuff. In the convention, crt0.o is the
360 startup file without constructor/destructor;
361 crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
362 startup files with constructor/destructor.
363 Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
364 by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
365 currently provided by GCC for nds32 target.
367 For nds32 target so far:
368 If -mno-ctor-dtor, we are going to link
369 "crt0.o [user objects]".
370 If general cases, we are going to link
371 "crt1.o crtbegin1.o [user objects] crtend1.o". */
372 #define STARTFILE_SPEC \
373 " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
374 " %{!mno-ctor-dtor:crtbegin1.o%s}"
375 #define ENDFILE_SPEC \
376 " %{!mno-ctor-dtor:crtend1.o%s}"
378 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we configure gcc
379 with --target=nds32be-* setting.
380 Check gcc/config.gcc for more information.
381 In addition, currently we only have elf toolchain,
382 where mgp-direct is always the default. */
383 #ifdef TARGET_BIG_ENDIAN_DEFAULT
384 #define MULTILIB_DEFAULTS { "mbig-endian", "mgp-direct" }
386 #define MULTILIB_DEFAULTS { "mlittle-endian", "mgp-direct" }
390 /* Run-time Target Specification. */
392 #define TARGET_CPU_CPP_BUILTINS() \
395 builtin_define ("__nds32__"); \
398 builtin_define ("__NDS32_ISA_V2__"); \
400 builtin_define ("__NDS32_ISA_V3__"); \
401 if (TARGET_ISA_V3M) \
402 builtin_define ("__NDS32_ISA_V3M__"); \
404 if (TARGET_BIG_ENDIAN) \
405 builtin_define ("__big_endian__"); \
406 if (TARGET_REDUCED_REGS) \
407 builtin_define ("__NDS32_REDUCED_REGS__"); \
409 builtin_define ("__NDS32_CMOV__"); \
410 if (TARGET_PERF_EXT) \
411 builtin_define ("__NDS32_PERF_EXT__"); \
413 builtin_define ("__NDS32_16_BIT__"); \
414 if (TARGET_GP_DIRECT) \
415 builtin_define ("__NDS32_GP_DIRECT__"); \
417 builtin_assert ("cpu=nds32"); \
418 builtin_assert ("machine=nds32"); \
422 /* Defining Data Structures for Per-function Information. */
424 /* This macro is called once per function,
425 before generation of any RTL has begun. */
426 #define INIT_EXPANDERS nds32_init_expanders ()
429 /* Storage Layout. */
431 #define BITS_BIG_ENDIAN 0
433 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
435 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
437 #define UNITS_PER_WORD 4
439 #define PROMOTE_MODE(m, unsignedp, type) \
440 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
445 #define PARM_BOUNDARY 32
447 #define STACK_BOUNDARY 64
449 #define FUNCTION_BOUNDARY 32
451 #define BIGGEST_ALIGNMENT 64
453 #define EMPTY_FIELD_BOUNDARY 32
455 #define STRUCTURE_SIZE_BOUNDARY 8
457 #define STRICT_ALIGNMENT 1
459 #define PCC_BITFIELD_TYPE_MATTERS 1
462 /* Layout of Source Language Data Types. */
464 #define INT_TYPE_SIZE 32
465 #define SHORT_TYPE_SIZE 16
466 #define LONG_TYPE_SIZE 32
467 #define LONG_LONG_TYPE_SIZE 64
469 #define FLOAT_TYPE_SIZE 32
470 #define DOUBLE_TYPE_SIZE 64
471 #define LONG_DOUBLE_TYPE_SIZE 64
473 #define DEFAULT_SIGNED_CHAR 1
475 #define SIZE_TYPE "long unsigned int"
476 #define PTRDIFF_TYPE "long int"
477 #define WCHAR_TYPE "short unsigned int"
478 #define WCHAR_TYPE_SIZE 16
481 /* Register Usage. */
483 /* Number of actual hardware registers.
484 The hardware registers are assigned numbers for the compiler
485 from 0 to just below FIRST_PSEUDO_REGISTER.
486 All registers that the compiler knows about must be given numbers,
487 even those that are not normally considered general registers. */
488 #define FIRST_PSEUDO_REGISTER 34
490 /* An initializer that says which registers are used for fixed
491 purposes all throughout the compiled code and are therefore
492 not available for general allocation.
499 caller-save registers: $r0 ~ $r5, $r16 ~ $r23
500 callee-save registers: $r6 ~ $r10, $r11 ~ $r14
502 reserved for assembler : $r15
503 reserved for other use : $r24, $r25, $r26, $r27 */
504 #define FIXED_REGISTERS \
505 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
506 0, 0, 0, 0, 0, 0, 0, 0, \
507 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
508 0, 0, 0, 0, 0, 0, 0, 1, \
509 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
510 0, 0, 0, 0, 0, 0, 0, 0, \
511 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
512 1, 1, 1, 1, 0, 1, 0, 1, \
513 /* ARG_POINTER:32 */ \
515 /* FRAME_POINTER:33 */ \
519 /* Identifies the registers that are not available for
520 general allocation of values that must live across
521 function calls -- so they are caller-save registers.
523 0 : callee-save registers
524 1 : caller-save registers */
525 #define CALL_USED_REGISTERS \
526 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
527 1, 1, 1, 1, 1, 1, 0, 0, \
528 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
529 0, 0, 0, 0, 0, 0, 0, 1, \
530 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
531 1, 1, 1, 1, 1, 1, 1, 1, \
532 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
533 1, 1, 1, 1, 0, 1, 0, 1, \
534 /* ARG_POINTER:32 */ \
536 /* FRAME_POINTER:33 */ \
540 /* In nds32 target, we have three levels of registers:
541 LOW_COST_REGS : $r0 ~ $r7
542 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
543 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
544 #define REG_ALLOC_ORDER \
546 0, 1, 2, 3, 4, 5, 6, 7, \
547 8, 9, 10, 11, 16, 17, 18, 19, \
548 12, 13, 14, 15, 20, 21, 22, 23, \
549 24, 25, 26, 27, 28, 29, 30, 31, \
554 /* Tell IRA to use the order we define rather than messing it up with its
555 own cost calculations. */
556 #define HONOR_REG_ALLOC_ORDER 1
558 /* The number of consecutive hard regs needed starting at
559 reg "regno" for holding a value of mode "mode". */
560 #define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
562 /* Value is 1 if hard register "regno" can hold a value
563 of machine-mode "mode". */
564 #define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
566 /* A C expression that is nonzero if a value of mode1
567 is accessible in mode2 without copying.
568 Define this macro to return nonzero in as many cases as possible
569 since doing so will allow GCC to perform better register allocation.
570 We can use general registers to tie QI/HI/SI modes together. */
571 #define MODES_TIEABLE_P(mode1, mode2) \
572 (GET_MODE_CLASS (mode1) == MODE_INT \
573 && GET_MODE_CLASS (mode2) == MODE_INT \
574 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD \
575 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
578 /* Register Classes. */
580 /* In nds32 target, we have three levels of registers:
581 Low cost regsiters : $r0 ~ $r7
582 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
583 High cost registers : $r12 ~ $r14, $r20 ~ $r31
585 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
586 so that it provides more chance to use low cost registers. */
601 #define N_REG_CLASSES (int) LIM_REG_CLASSES
603 #define REG_CLASS_NAMES \
616 #define REG_CLASS_CONTENTS \
618 {0x00000000, 0x00000000}, /* NO_REGS : */ \
619 {0x00008000, 0x00000000}, /* R15_TA_REG : 15 */ \
620 {0x80000000, 0x00000000}, /* STACK_REG : 31 */ \
621 {0x000000ff, 0x00000000}, /* LOW_REGS : 0-7 */ \
622 {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19 */ \
623 {0xfff07000, 0x00000000}, /* HIGH_REGS : 12-14, 20-31 */ \
624 {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31 */ \
625 {0x00000000, 0x00000003}, /* FRAME_REGS : 32, 33 */ \
626 {0xffffffff, 0x00000003} /* ALL_REGS : 0-31, 32, 33 */ \
629 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
631 #define BASE_REG_CLASS GENERAL_REGS
632 #define INDEX_REG_CLASS GENERAL_REGS
634 /* Return nonzero if it is suitable for use as a
635 base register in operand addresses.
636 So far, we return nonzero only if "num" is a hard reg
637 of the suitable class or a pseudo register which is
638 allocated to a suitable hard reg. */
639 #define REGNO_OK_FOR_BASE_P(num) \
640 ((num) < 32 || (unsigned) reg_renumber[num] < 32)
642 /* Return nonzero if it is suitable for use as a
643 index register in operand addresses.
644 So far, we return nonzero only if "num" is a hard reg
645 of the suitable class or a pseudo register which is
646 allocated to a suitable hard reg.
647 The difference between an index register and a base register is that
648 the index register may be scaled. */
649 #define REGNO_OK_FOR_INDEX_P(num) \
650 ((num) < 32 || (unsigned) reg_renumber[num] < 32)
653 /* Obsolete Macros for Defining Constraints. */
656 /* Stack Layout and Calling Conventions. */
658 #define STACK_GROWS_DOWNWARD
660 #define FRAME_GROWS_DOWNWARD 1
662 #define STARTING_FRAME_OFFSET 0
664 #define STACK_POINTER_OFFSET 0
666 #define FIRST_PARM_OFFSET(fundecl) 0
668 #define RETURN_ADDR_RTX(count, frameaddr) \
669 nds32_return_addr_rtx (count, frameaddr)
671 /* A C expression whose value is RTL representing the location
672 of the incoming return address at the beginning of any function
674 If this RTL is REG, you should also define
675 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
676 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
677 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
679 #define STACK_POINTER_REGNUM SP_REGNUM
681 #define FRAME_POINTER_REGNUM 33
683 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
685 #define ARG_POINTER_REGNUM 32
687 #define STATIC_CHAIN_REGNUM 16
689 #define ELIMINABLE_REGS \
690 { { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
691 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
692 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
693 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
695 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
696 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
698 #define ACCUMULATE_OUTGOING_ARGS 1
700 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
702 #define CUMULATIVE_ARGS nds32_cumulative_args
704 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
705 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
707 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
708 We better cast REGNO into signed integer so that we can avoid
709 'comparison of unsigned expression >= 0 is always true' warning. */
710 #define FUNCTION_ARG_REGNO_P(regno) \
711 (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0) \
712 && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_REGS_FOR_ARGS))
714 #define DEFAULT_PCC_STRUCT_RETURN 0
716 /* EXIT_IGNORE_STACK should be nonzero if, when returning
717 from a function, the stack pointer does not matter.
718 The value is tested only in functions that have frame pointers.
719 In nds32 target, the function epilogue recovers the
720 stack pointer from the frame. */
721 #define EXIT_IGNORE_STACK 1
723 #define FUNCTION_PROFILER(file, labelno) \
724 fprintf (file, "/* profiler %d */", (labelno))
727 /* Implementing the Varargs Macros. */
730 /* Trampolines for Nested Functions. */
732 /* Giving A-function and B-function,
733 if B-function wants to call A-function's nested function,
734 we need to fill trampoline code into A-function's stack
735 so that B-function can execute the code in stack to indirectly
736 jump to (like 'trampoline' action) desired nested function.
738 The trampoline code for nds32 target must contains following parts:
740 1. instructions (4 * 4 = 16 bytes):
742 load chain_value to static chain register via $pc
743 load nested function address to $r15 via $pc
744 jump to desired nested function via $r15
745 2. data (4 * 2 = 8 bytes):
747 nested function address
749 Please check nds32.c implementation for more information. */
750 #define TRAMPOLINE_SIZE 24
752 /* Because all instructions/data in trampoline template are 4-byte size,
753 we set trampoline alignment 8*4=32 bits. */
754 #define TRAMPOLINE_ALIGNMENT 32
757 /* Implicit Calls to Library Routines. */
760 /* Addressing Modes. */
762 /* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
763 #define HAVE_POST_INCREMENT 1
764 /* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
765 #define HAVE_POST_DECREMENT 1
767 /* We have "LWI.bi Rt, [Ra], imm" instruction form. */
768 #define HAVE_POST_MODIFY_DISP 1
769 /* We have "LW.bi Rt, [Ra], Rb" instruction form. */
770 #define HAVE_POST_MODIFY_REG 1
772 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
774 #define MAX_REGS_PER_ADDRESS 2
777 /* Anchored Addresses. */
780 /* Condition Code Status. */
783 /* Describing Relative Costs of Operations. */
785 /* A C expression for the cost of a branch instruction.
786 A value of 1 is the default;
787 other values are interpreted relative to that. */
788 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
790 #define SLOW_BYTE_ACCESS 1
792 #define NO_FUNCTION_CSE
795 /* Adjusting the Instruction Scheduler. */
798 /* Dividing the Output into Sections (Texts, Data, . . . ). */
800 #define TEXT_SECTION_ASM_OP "\t.text"
801 #define DATA_SECTION_ASM_OP "\t.data"
803 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
804 So we use '.section .bss' alternatively. */
805 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
807 /* Define this macro to be an expression with a nonzero value if jump tables
808 (for tablejump insns) should be output in the text section,
809 along with the assembler instructions.
810 Otherwise, the readonly data section is used. */
811 #define JUMP_TABLES_IN_TEXT_SECTION 1
814 /* Position Independent Code. */
817 /* Defining the Output Assembler Language. */
819 #define ASM_COMMENT_START "!"
821 #define ASM_APP_ON "! #APP"
823 #define ASM_APP_OFF "! #NO_APP\n"
825 #define ASM_OUTPUT_LABELREF(stream, name) \
826 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
828 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
829 assemble_name (stream, XSTR (sym, 0))
831 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
832 assemble_name (stream, buf)
834 #define LOCAL_LABEL_PREFIX "."
836 #define REGISTER_NAMES \
838 "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
839 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
840 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
841 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
846 /* Output normal jump table entry. */
847 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
848 asm_fprintf (stream, "\t.word\t%LL%d\n", value)
850 /* Output pc relative jump table entry. */
851 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
854 switch (GET_MODE (body)) \
857 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
860 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
863 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
870 /* We have to undef it first because elfos.h formerly define it
871 check gcc/config.gcc and gcc/config/elfos.h for more information. */
872 #undef ASM_OUTPUT_CASE_LABEL
873 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
876 asm_fprintf (stream, "\t! Jump Table Begin\n"); \
877 (*targetm.asm_out.internal_label) (stream, prefix, num); \
880 #define ASM_OUTPUT_CASE_END(stream, num, table) \
883 /* Because our jump table is in text section, \
884 we need to make sure 2-byte alignment after \
885 the jump table for instructions fetch. */ \
886 if (GET_MODE (PATTERN (table)) == QImode) \
887 ASM_OUTPUT_ALIGN (stream, 1); \
888 asm_fprintf (stream, "\t! Jump Table End\n"); \
891 /* This macro is not documented yet.
892 But we do need it to make jump table vector aligned. */
893 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
895 #define DWARF2_UNWIND_INFO 1
897 #define JUMP_ALIGN(x) \
898 (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
900 #define LOOP_ALIGN(x) \
901 (align_loops_log ? align_loops_log : nds32_target_alignment (x))
903 #define LABEL_ALIGN(x) \
904 (align_labels_log ? align_labels_log : nds32_target_alignment (x))
906 #define ASM_OUTPUT_ALIGN(stream, power) \
907 fprintf (stream, "\t.align\t%d\n", power)
910 /* Controlling Debugging Information Format. */
912 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
914 #define DWARF2_DEBUGGING_INFO 1
916 #define DWARF2_ASM_LINE_DEBUG_INFO 1
919 /* Cross Compilation and Floating Point. */
922 /* Mode Switching Instructions. */
925 /* Defining target-specific uses of __attribute__. */
931 /* Defining coprocessor specifics for MIPS targets. */
934 /* Parameters for Precompiled Header Validity Checking. */
937 /* C++ ABI parameters. */
940 /* Adding support for named address spaces. */
943 /* Miscellaneous Parameters. */
945 /* This is the machine mode that elements of a jump-table should have. */
946 #define CASE_VECTOR_MODE Pmode
948 /* Return the preferred mode for and addr_diff_vec when the mininum
949 and maximum offset are known. */
950 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
951 ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
952 : (max_offset >= 100) ? HImode \
955 /* Generate pc relative jump table when -fpic or -Os. */
956 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
958 /* Define this macro if operations between registers with integral mode
959 smaller than a word are always performed on the entire register. */
960 #define WORD_REGISTER_OPERATIONS
962 /* A C expression indicating when insns that read memory in mem_mode,
963 an integral mode narrower than a word, set the bits outside of mem_mode
964 to be either the sign-extension or the zero-extension of the data read. */
965 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
967 /* The maximum number of bytes that a single instruction can move quickly
968 between memory and registers or between two memory locations. */
971 /* A C expression that is nonzero if on this machine the number of bits
972 actually used for the count of a shift operation is equal to the number
973 of bits needed to represent the size of the object being shifted. */
974 #define SHIFT_COUNT_TRUNCATED 1
976 /* A C expression which is nonzero if on this machine it is safe to "convert"
977 an integer of 'inprec' bits to one of 'outprec' bits by merely operating
978 on it as if it had only 'outprec' bits. */
979 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
981 /* A C expression describing the value returned by a comparison operator with
982 an integral mode and stored by a store-flag instruction ('cstoremode4')
983 when the condition is true. */
984 #define STORE_FLAG_VALUE 1
986 /* An alias for the machine mode for pointers. */
989 /* An alias for the machine mode used for memory references to functions
990 being called, in call RTL expressions. */
991 #define FUNCTION_MODE SImode
993 /* ------------------------------------------------------------------------ */