1 ; Options of Andes NDS32 cpu for GNU compiler
2 ; Copyright (C) 2012-2019 Free Software Foundation, Inc.
3 ; Contributed by Andes Technology Corporation.
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15 ; License for more details.
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22 config/nds32/nds32-opts.h
24 ; ---------------------------------------------------------------
25 ; The following options are designed for aliasing and compatibility options.
28 Target RejectNegative Alias(mbig-endian)
29 Generate code in big-endian mode.
32 Target RejectNegative Alias(mlittle-endian)
33 Generate code in little-endian mode.
36 Target RejectNegative Alias(mforce-fp-as-gp)
37 Force performing fp-as-gp optimization.
40 Target RejectNegative Alias(mforbid-fp-as-gp)
41 Forbid performing fp-as-gp optimization.
43 ; ---------------------------------------------------------------
46 Target RejectNegative Joined Enum(abi_type) Var(nds32_abi) Init(TARGET_DEFAULT_ABI)
47 Specify which ABI type to generate code for: 2, 2fp+.
50 Name(abi_type) Type(enum abi_type)
51 Known ABIs (for use with the -mabi= option):
54 Enum(abi_type) String(2) Value(NDS32_ABI_V2)
57 Enum(abi_type) String(2fp+) Value(NDS32_ABI_V2_FP_PLUS)
60 Target RejectNegative Alias(mabi=, 2)
61 Specify use soft floating point ABI which mean alias to -mabi=2.
64 Target RejectNegative Alias(mabi=, 2fp+)
65 Specify use soft floating point ABI which mean alias to -mabi=2fp+.
67 ; ---------------------------------------------------------------
70 Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
71 Use reduced-set registers for register allocation.
74 Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
75 Use full-set registers for register allocation.
77 ; ---------------------------------------------------------------
80 Target Mask(ALWAYS_ALIGN)
81 Always align function entry, jump target and return address.
84 Target Mask(ALIGN_FUNCTION)
85 Align function entry to 4 byte.
88 Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
89 Generate code in big-endian mode.
92 Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
93 Generate code in little-endian mode.
96 Target Undocumented Mask(FORCE_FP_AS_GP)
97 Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization.
100 Target Undocumented Mask(FORBID_FP_AS_GP)
101 Forbid using $fp to access static and global variables. This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'.
104 Target Undocumented RejectNegative Joined Enum(nds32_ict_model_type) Var(nds32_ict_model) Init(ICT_MODEL_SMALL)
105 Specify the address generation strategy for ICT call's code model.
108 Name(nds32_ict_model_type) Type(enum nds32_ict_model_type)
109 Known cmodel types (for use with the -mict-model= option):
112 Enum(nds32_ict_model_type) String(small) Value(ICT_MODEL_SMALL)
115 Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE)
118 Target Report Mask(CMOV)
119 Generate conditional move instructions.
122 Target Report Mask(HW_ABS)
123 Generate hardware abs instructions.
126 Target Report Mask(EXT_PERF)
127 Generate performance extension instructions.
130 Target Report Mask(EXT_PERF2)
131 Generate performance extension version 2 instructions.
134 Target Report Mask(EXT_STRING)
135 Generate string extension instructions.
138 Target Report Mask(EXT_DSP)
139 Generate DSP extension instructions.
142 Target Report Mask(V3PUSH)
143 Generate v3 push25/pop25 instructions.
146 Target Report Mask(16_BIT)
147 Generate 16-bit instructions.
150 Target Report Mask(RELAX_HINT)
151 Insert relax hint for linker to do relaxation.
154 Target Report Mask(VH) Condition(!TARGET_LINUX_ABI)
155 Enable Virtual Hosting support.
158 Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
159 Specify the size of each interrupt vector, which must be 4 or 16.
162 Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0)
163 Specify the security level of c-isr for the whole file.
166 Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
167 Specify the size of each cache block, which must be a power of 2 between 4 and 512.
170 Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
171 Specify the name of the target architecture.
174 Name(nds32_arch_type) Type(enum nds32_arch_type)
175 Known arch types (for use with the -march= option):
178 Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
181 Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
184 Enum(nds32_arch_type) String(v3j) Value(ARCH_V3J)
187 Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
190 Enum(nds32_arch_type) String(v3f) Value(ARCH_V3F)
193 Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S)
196 Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9)
197 Specify the cpu for pipeline model.
200 Name(nds32_cpu_type) Type(enum nds32_cpu_type)
201 Known cpu types (for use with the -mcpu= option):
204 Enum(nds32_cpu_type) String(n6) Value(CPU_N6)
207 Enum(nds32_cpu_type) String(n650) Value(CPU_N6)
210 Enum(nds32_cpu_type) String(n7) Value(CPU_N7)
213 Enum(nds32_cpu_type) String(n705) Value(CPU_N7)
216 Enum(nds32_cpu_type) String(n8) Value(CPU_N8)
219 Enum(nds32_cpu_type) String(n801) Value(CPU_N8)
222 Enum(nds32_cpu_type) String(sn8) Value(CPU_N8)
225 Enum(nds32_cpu_type) String(sn801) Value(CPU_N8)
228 Enum(nds32_cpu_type) String(s8) Value(CPU_N8)
231 Enum(nds32_cpu_type) String(s801) Value(CPU_N8)
234 Enum(nds32_cpu_type) String(e8) Value(CPU_E8)
237 Enum(nds32_cpu_type) String(e801) Value(CPU_E8)
240 Enum(nds32_cpu_type) String(n820) Value(CPU_E8)
243 Enum(nds32_cpu_type) String(s830) Value(CPU_E8)
246 Enum(nds32_cpu_type) String(e830) Value(CPU_E8)
249 Enum(nds32_cpu_type) String(n9) Value(CPU_N9)
252 Enum(nds32_cpu_type) String(n903) Value(CPU_N9)
255 Enum(nds32_cpu_type) String(n903a) Value(CPU_N9)
258 Enum(nds32_cpu_type) String(n968) Value(CPU_N9)
261 Enum(nds32_cpu_type) String(n968a) Value(CPU_N9)
264 Enum(nds32_cpu_type) String(n10) Value(CPU_N10)
267 Enum(nds32_cpu_type) String(n1033) Value(CPU_N10)
270 Enum(nds32_cpu_type) String(n1033a) Value(CPU_N10)
273 Enum(nds32_cpu_type) String(n1033-fpu) Value(CPU_N10)
276 Enum(nds32_cpu_type) String(n1033-spu) Value(CPU_N10)
279 Enum(nds32_cpu_type) String(n1068) Value(CPU_N10)
282 Enum(nds32_cpu_type) String(n1068a) Value(CPU_N10)
285 Enum(nds32_cpu_type) String(n1068-fpu) Value(CPU_N10)
288 Enum(nds32_cpu_type) String(n1068a-fpu) Value(CPU_N10)
291 Enum(nds32_cpu_type) String(n1068-spu) Value(CPU_N10)
294 Enum(nds32_cpu_type) String(n1068a-spu) Value(CPU_N10)
297 Enum(nds32_cpu_type) String(d10) Value(CPU_N10)
300 Enum(nds32_cpu_type) String(d1088) Value(CPU_N10)
303 Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10)
306 Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10)
309 Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF)
312 Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF)
315 Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF)
318 Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF)
321 Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF)
324 Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF)
327 Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF)
330 Enum(nds32_cpu_type) String(n12) Value(CPU_N12)
333 Enum(nds32_cpu_type) String(n1213) Value(CPU_N12)
336 Enum(nds32_cpu_type) String(n1233) Value(CPU_N12)
339 Enum(nds32_cpu_type) String(n1233-fpu) Value(CPU_N12)
342 Enum(nds32_cpu_type) String(n1233-spu) Value(CPU_N12)
345 Enum(nds32_cpu_type) String(n13) Value(CPU_N13)
348 Enum(nds32_cpu_type) String(n1337) Value(CPU_N13)
351 Enum(nds32_cpu_type) String(n1337-fpu) Value(CPU_N13)
354 Enum(nds32_cpu_type) String(n1337-spu) Value(CPU_N13)
357 Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE)
360 Target RejectNegative Joined Enum(float_reg_number) Var(nds32_fp_regnum) Init(TARGET_CONFIG_FPU_DEFAULT)
361 Specify a fpu configuration value from 0 to 7; 0-3 is as FPU spec says, and 4-7 is corresponding to 0-3.
364 Name(float_reg_number) Type(enum float_reg_number)
365 Known floating-point number of registers (for use with the -mconfig-fpu= option):
368 Enum(float_reg_number) String(0) Value(NDS32_CONFIG_FPU_0)
371 Enum(float_reg_number) String(1) Value(NDS32_CONFIG_FPU_1)
374 Enum(float_reg_number) String(2) Value(NDS32_CONFIG_FPU_2)
377 Enum(float_reg_number) String(3) Value(NDS32_CONFIG_FPU_3)
380 Enum(float_reg_number) String(4) Value(NDS32_CONFIG_FPU_4)
383 Enum(float_reg_number) String(5) Value(NDS32_CONFIG_FPU_5)
386 Enum(float_reg_number) String(6) Value(NDS32_CONFIG_FPU_6)
389 Enum(float_reg_number) String(7) Value(NDS32_CONFIG_FPU_7)
392 Target RejectNegative Joined Enum(nds32_mul_type) Var(nds32_mul_config) Init(MUL_TYPE_FAST_1)
393 Specify configuration of instruction mul: fast1, fast2 or slow. The default is fast1.
396 Name(nds32_mul_type) Type(enum nds32_mul_type)
399 Enum(nds32_mul_type) String(fast) Value(MUL_TYPE_FAST_1)
402 Enum(nds32_mul_type) String(fast1) Value(MUL_TYPE_FAST_1)
405 Enum(nds32_mul_type) String(fast2) Value(MUL_TYPE_FAST_2)
408 Enum(nds32_mul_type) String(slow) Value(MUL_TYPE_SLOW)
410 mconfig-register-ports=
411 Target RejectNegative Joined Enum(nds32_register_ports) Var(nds32_register_ports_config) Init(REG_PORT_3R2W)
412 Specify how many read/write ports for n9/n10 cores. The value should be 3r2w or 2r1w.
415 Name(nds32_register_ports) Type(enum nds32_register_ports)
418 Enum(nds32_register_ports) String(3r2w) Value(REG_PORT_3R2W)
421 Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)
425 Enable constructor/destructor feature.
429 Guide linker to relax instructions.
432 Target Report Mask(EXT_FPU_FMA)
433 Generate floating-point multiply-accumulation instructions.
436 Target Report Mask(FPU_SINGLE)
437 Generate single-precision floating-point instructions.
440 Target Report Mask(FPU_DOUBLE)
441 Generate double-precision floating-point instructions.
444 Target Undocumented Report Mask(FORCE_NO_EXT_DSP)
445 Force disable hardware loop, even use -mext-dsp.
448 Target Var(flag_sched_prolog_epilog) Init(0)
449 Permit scheduling of a function's prologue and epilogue sequence.
452 Target Var(flag_ret_in_naked_func) Init(1)
453 Generate return instruction in naked function.
456 Target Var(flag_always_save_lp) Init(0)
457 Always save $lp in the stack.
460 Target Report Var(flag_unaligned_access) Init(0)
461 Enable unaligned word and halfword accesses to packed data.
464 Target Report Var(flag_inline_asm_r15) Init(0)
465 Allow use r15 for inline ASM.