gcc/config/nds32/nds32_isr.h

   1 /* Intrinsic definitions of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2019 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    Under Section 7 of GPL version 3, you are granted additional
  18    permissions described in the GCC Runtime Library Exception, version
  19    3.1, as published by the Free Software Foundation.
  20
  21    You should have received a copy of the GNU General Public License and
  22    a copy of the GCC Runtime Library Exception along with this program;
  23    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  24    <http://www.gnu.org/licenses/>.  */
  25
  26 #ifndef _NDS32_ISR_H
  27 #define _NDS32_ISR_H
  28
  29 /* Attribute of a interrupt or exception handler:
  30
  31    NDS32_READY_NESTED: This handler is interruptible if user re-enable GIE bit.
  32    NDS32_NESTED      : This handler is interruptible.  This is not suitable
  33                        exception handler.
  34    NDS32_NOT_NESTED  : This handler is NOT interruptible.  Users have to do
  35                        some work if nested is wanted
  36    NDS32_CRITICAL    : This handler is critical ISR, which means it is small
  37                        and efficient.  */
  38 #define NDS32_READY_NESTED   0
  39 #define NDS32_NESTED         1
  40 #define NDS32_NOT_NESTED     2
  41 #define NDS32_CRITICAL       3
  42
  43 /* Attribute of a interrupt or exception handler:
  44
  45    NDS32_SAVE_ALL_REGS    : Save all registers in a table.
  46    NDS32_SAVE_PARTIAL_REGS: Save partial registers.  */
  47 #define NDS32_SAVE_CALLER_REGS   0
  48 #define NDS32_SAVE_ALL_REGS      1
  49
  50 /* There are two version of Register table for interrupt and exception handler,
  51    one for 16-register CPU the other for 32-register CPU.  These structures are
  52    used for context switching or system call handling.  The address of this
  53    data can be get from the input argument of the handler functions.
  54
  55    For system call handling, r0 to r5 are used to pass arguments.  If more
  56    arguments are used they are put into the stack and its starting address is
  57    in sp.  Return value of system call can be put into r0 and r1 upon exit from
  58    system call handler.  System call ID is in a system register and it can be
  59    fetched via intrinsic function.  For more information please read ABI and
  60    other related documents.
  61
  62    For context switching, at least 2 values need to saved in kernel.  One is
  63    IPC and the other is the stack address of current task.  Use intrinsic
  64    function to get IPC and  the input argument of the handler functions + 8 to
  65    get stack address of current task.  To do context switching, you replace
  66    new_sp with the stack address of new task and replace IPC system register
  67    with IPC of new task, then, just return from handler.  The context switching
  68    will happen.  */
  69
  70 /* Register table for exception handler; 32-register version.  */
  71 typedef struct
  72 {
  73   int r0;
  74   int r1;
  75   int r2;
  76   int r3;
  77   int r4;
  78   int r5;
  79   int r6;
  80   int r7;
  81   int r8;
  82   int r9;
  83   int r10;
  84   int r11;
  85   int r12;
  86   int r13;
  87   int r14;
  88   int r15;
  89   int r16;
  90   int r17;
  91   int r18;
  92   int r19;
  93   int r20;
  94   int r21;
  95   int r22;
  96   int r23;
  97   int r24;
  98   int r25;
  99   int r26;
 100   int r27;
 101   int fp;
 102   int gp;
 103   int lp;
 104   int sp;
 105 } NDS32_GPR32;
 106
 107 /* Register table for exception handler; 16-register version.  */
 108 typedef struct
 109 {
 110   int r0;
 111   int r1;
 112   int r2;
 113   int r3;
 114   int r4;
 115   int r5;
 116   int r6;
 117   int r7;
 118   int r8;
 119   int r9;
 120   int r10;
 121   int r15;
 122   int fp;
 123   int gp;
 124   int lp;
 125   int sp;
 126 } NDS32_GPR16;
 127
 128
 129 /* Use NDS32_REG32_TAB or NDS32_REG16_TAB in your program to
 130    access register table.  */
 131 typedef struct
 132 {
 133   union
 134     {
 135       int          reg_a[32] ;
 136       NDS32_GPR32  reg_s ;
 137     } u ;
 138 } NDS32_REG32_TAB;
 139
 140 typedef struct
 141 {
 142   union
 143     {
 144       int          reg_a[16] ;
 145       NDS32_GPR16  reg_s ;
 146     } u ;
 147 } NDS32_REG16_TAB;
 148
 149 typedef struct
 150 {
 151   int    d0lo;
 152   int    d0hi;
 153   int    d1lo;
 154   int    d1hi;
 155 } NDS32_DX_TAB;
 156
 157 typedef struct
 158 {
 159 #ifdef __NDS32_EB__
 160   float    fsr0;
 161   float    fsr1;
 162   float    fsr2;
 163   float    fsr3;
 164   float    fsr4;
 165   float    fsr5;
 166   float    fsr6;
 167   float    fsr7;
 168 #else
 169   float    fsr1;
 170   float    fsr0;
 171   float    fsr3;
 172   float    fsr2;
 173   float    fsr5;
 174   float    fsr4;
 175   float    fsr7;
 176   float    fsr6;
 177 #endif
 178 } NDS32_FSR8;
 179
 180 typedef struct
 181 {
 182   double   dsr0;
 183   double   dsr1;
 184   double   dsr2;
 185   double   dsr3;
 186 } NDS32_DSR4;
 187
 188 typedef struct
 189 {
 190 #ifdef __NDS32_EB__
 191   float    fsr0;
 192   float    fsr1;
 193   float    fsr2;
 194   float    fsr3;
 195   float    fsr4;
 196   float    fsr5;
 197   float    fsr6;
 198   float    fsr7;
 199   float    fsr8;
 200   float    fsr9;
 201   float    fsr10;
 202   float    fsr11;
 203   float    fsr12;
 204   float    fsr13;
 205   float    fsr14;
 206   float    fsr15;
 207 #else
 208   float    fsr1;
 209   float    fsr0;
 210   float    fsr3;
 211   float    fsr2;
 212   float    fsr5;
 213   float    fsr4;
 214   float    fsr7;
 215   float    fsr6;
 216   float    fsr9;
 217   float    fsr8;
 218   float    fsr11;
 219   float    fsr10;
 220   float    fsr13;
 221   float    fsr12;
 222   float    fsr15;
 223   float    fsr14;
 224 #endif
 225 } NDS32_FSR16;
 226
 227 typedef struct
 228 {
 229   double   dsr0;
 230   double   dsr1;
 231   double   dsr2;
 232   double   dsr3;
 233   double   dsr4;
 234   double   dsr5;
 235   double   dsr6;
 236   double   dsr7;
 237 } NDS32_DSR8;
 238
 239 typedef struct
 240 {
 241 #ifdef __NDS32_EB__
 242   float    fsr0;
 243   float    fsr1;
 244   float    fsr2;
 245   float    fsr3;
 246   float    fsr4;
 247   float    fsr5;
 248   float    fsr6;
 249   float    fsr7;
 250   float    fsr8;
 251   float    fsr9;
 252   float    fsr10;
 253   float    fsr11;
 254   float    fsr12;
 255   float    fsr13;
 256   float    fsr14;
 257   float    fsr15;
 258   float    fsr16;
 259   float    fsr17;
 260   float    fsr18;
 261   float    fsr19;
 262   float    fsr20;
 263   float    fsr21;
 264   float    fsr22;
 265   float    fsr23;
 266   float    fsr24;
 267   float    fsr25;
 268   float    fsr26;
 269   float    fsr27;
 270   float    fsr28;
 271   float    fsr29;
 272   float    fsr30;
 273   float    fsr31;
 274 #else
 275   float    fsr1;
 276   float    fsr0;
 277   float    fsr3;
 278   float    fsr2;
 279   float    fsr5;
 280   float    fsr4;
 281   float    fsr7;
 282   float    fsr6;
 283   float    fsr9;
 284   float    fsr8;
 285   float    fsr11;
 286   float    fsr10;
 287   float    fsr13;
 288   float    fsr12;
 289   float    fsr15;
 290   float    fsr14;
 291   float    fsr17;
 292   float    fsr16;
 293   float    fsr19;
 294   float    fsr18;
 295   float    fsr21;
 296   float    fsr20;
 297   float    fsr23;
 298   float    fsr22;
 299   float    fsr25;
 300   float    fsr24;
 301   float    fsr27;
 302   float    fsr26;
 303   float    fsr29;
 304   float    fsr28;
 305   float    fsr31;
 306   float    fsr30;
 307 #endif
 308 } NDS32_FSR32;
 309
 310 typedef struct
 311 {
 312   double   dsr0;
 313   double   dsr1;
 314   double   dsr2;
 315   double   dsr3;
 316   double   dsr4;
 317   double   dsr5;
 318   double   dsr6;
 319   double   dsr7;
 320   double   dsr8;
 321   double   dsr9;
 322   double   dsr10;
 323   double   dsr11;
 324   double   dsr12;
 325   double   dsr13;
 326   double   dsr14;
 327   double   dsr15;
 328 } NDS32_DSR16;
 329
 330 typedef struct
 331 {
 332   double   dsr0;
 333   double   dsr1;
 334   double   dsr2;
 335   double   dsr3;
 336   double   dsr4;
 337   double   dsr5;
 338   double   dsr6;
 339   double   dsr7;
 340   double   dsr8;
 341   double   dsr9;
 342   double   dsr10;
 343   double   dsr11;
 344   double   dsr12;
 345   double   dsr13;
 346   double   dsr14;
 347   double   dsr15;
 348   double   dsr16;
 349   double   dsr17;
 350   double   dsr18;
 351   double   dsr19;
 352   double   dsr20;
 353   double   dsr21;
 354   double   dsr22;
 355   double   dsr23;
 356   double   dsr24;
 357   double   dsr25;
 358   double   dsr26;
 359   double   dsr27;
 360   double   dsr28;
 361   double   dsr29;
 362   double   dsr30;
 363   double   dsr31;
 364 } NDS32_DSR32;
 365
 366 typedef struct
 367 {
 368   union
 369     {
 370       NDS32_FSR8   fsr_s ;
 371       NDS32_DSR4   dsr_s ;
 372     } u ;
 373 } NDS32_FPU8_TAB;
 374
 375 typedef struct
 376 {
 377   union
 378     {
 379       NDS32_FSR16  fsr_s ;
 380       NDS32_DSR8   dsr_s ;
 381     } u ;
 382 } NDS32_FPU16_TAB;
 383
 384 typedef struct
 385 {
 386   union
 387     {
 388       NDS32_FSR32  fsr_s ;
 389       NDS32_DSR16  dsr_s ;
 390     } u ;
 391 } NDS32_FPU32_TAB;
 392
 393 typedef struct
 394 {
 395   union
 396     {
 397       NDS32_FSR32  fsr_s ;
 398       NDS32_DSR32  dsr_s ;
 399     } u ;
 400 } NDS32_FPU64_TAB;
 401
 402 typedef struct
 403 {
 404   int    ipc;
 405   int    ipsw;
 406 #if defined(NDS32_EXT_FPU_CONFIG_0)
 407   NDS32_FPU8_TAB fpr;
 408 #elif defined(NDS32_EXT_FPU_CONFIG_1)
 409   NDS32_FPU16_TAB fpr;
 410 #elif defined(NDS32_EXT_FPU_CONFIG_2)
 411   NDS32_FPU32_TAB fpr;
 412 #elif defined(NDS32_EXT_FPU_CONFIG_3)
 413   NDS32_FPU64_TAB fpr;
 414 #endif
 415 #if __NDS32_DX_REGS__
 416   NDS32_DX_TAB dxr;
 417 #endif
 418 #if __NDS32_EXT_IFC__
 419   int    ifc_lp;
 420   int    filler;
 421 #endif
 422 #if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
 423   NDS32_REG16_TAB gpr;
 424 #else
 425   NDS32_REG32_TAB gpr;
 426 #endif
 427 } NDS32_CONTEXT;
 428
 429 /* Predefined Vector Definition.
 430
 431    For IVIC Mode: 9 to 14 are for hardware interrupt
 432                   and 15 is for software interrupt.
 433    For EVIC Mode: 9 to 72 are for hardware interrupt
 434                   and software interrupt can be routed to any one of them.
 435
 436    You may want to define your hardware interrupts in the following way
 437    for easy maintainance.
 438
 439      IVIC mode:
 440        #define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1
 441        #define MY_HW_IVIC_USB   NDS32_VECTOR_INTERRUPT_HW0 + 3
 442      EVIC mode:
 443      #define MY_HW_EVIC_DMA   NDS32_VECTOR_INTERRUPT_HW0 + 2
 444      #define MY_HW_EVIC_SWI   NDS32_VECTOR_INTERRUPT_HW0 + 10 */
 445 #define NDS32_VECTOR_RESET               0
 446 #define NDS32_VECTOR_TLB_FILL            1
 447 #define NDS32_VECTOR_PTE_NOT_PRESENT     2
 448 #define NDS32_VECTOR_TLB_MISC            3
 449 #define NDS32_VECTOR_TLB_VLPT_MISS       4
 450 #define NDS32_VECTOR_MACHINE_ERROR       5
 451 #define NDS32_VECTOR_DEBUG_RELATED       6
 452 #define NDS32_VECTOR_GENERAL_EXCEPTION   7
 453 #define NDS32_VECTOR_SYSCALL             8
 454 #define NDS32_VECTOR_INTERRUPT_HW0       9
 455 #define NDS32_VECTOR_INTERRUPT_HW1       10
 456 #define NDS32_VECTOR_INTERRUPT_HW2       11
 457 #define NDS32_VECTOR_INTERRUPT_HW3       12
 458 #define NDS32_VECTOR_INTERRUPT_HW4       13
 459 #define NDS32_VECTOR_INTERRUPT_HW5       14
 460 #define NDS32_VECTOR_INTERRUPT_HW6       15
 461 #define NDS32_VECTOR_SWI                 15  /* THIS IS FOR IVIC MODE ONLY */
 462 #define NDS32_VECTOR_INTERRUPT_HW7       16
 463 #define NDS32_VECTOR_INTERRUPT_HW8       17
 464 #define NDS32_VECTOR_INTERRUPT_HW9       18
 465 #define NDS32_VECTOR_INTERRUPT_HW10      19
 466 #define NDS32_VECTOR_INTERRUPT_HW11      20
 467 #define NDS32_VECTOR_INTERRUPT_HW12      21
 468 #define NDS32_VECTOR_INTERRUPT_HW13      22
 469 #define NDS32_VECTOR_INTERRUPT_HW14      23
 470 #define NDS32_VECTOR_INTERRUPT_HW15      24
 471 #define NDS32_VECTOR_INTERRUPT_HW16      25
 472 #define NDS32_VECTOR_INTERRUPT_HW17      26
 473 #define NDS32_VECTOR_INTERRUPT_HW18      27
 474 #define NDS32_VECTOR_INTERRUPT_HW19      28
 475 #define NDS32_VECTOR_INTERRUPT_HW20      29
 476 #define NDS32_VECTOR_INTERRUPT_HW21      30
 477 #define NDS32_VECTOR_INTERRUPT_HW22      31
 478 #define NDS32_VECTOR_INTERRUPT_HW23      32
 479 #define NDS32_VECTOR_INTERRUPT_HW24      33
 480 #define NDS32_VECTOR_INTERRUPT_HW25      34
 481 #define NDS32_VECTOR_INTERRUPT_HW26      35
 482 #define NDS32_VECTOR_INTERRUPT_HW27      36
 483 #define NDS32_VECTOR_INTERRUPT_HW28      37
 484 #define NDS32_VECTOR_INTERRUPT_HW29      38
 485 #define NDS32_VECTOR_INTERRUPT_HW30      39
 486 #define NDS32_VECTOR_INTERRUPT_HW31      40
 487 #define NDS32_VECTOR_INTERRUPT_HW32      41
 488 #define NDS32_VECTOR_INTERRUPT_HW33      42
 489 #define NDS32_VECTOR_INTERRUPT_HW34      43
 490 #define NDS32_VECTOR_INTERRUPT_HW35      44
 491 #define NDS32_VECTOR_INTERRUPT_HW36      45
 492 #define NDS32_VECTOR_INTERRUPT_HW37      46
 493 #define NDS32_VECTOR_INTERRUPT_HW38      47
 494 #define NDS32_VECTOR_INTERRUPT_HW39      48
 495 #define NDS32_VECTOR_INTERRUPT_HW40      49
 496 #define NDS32_VECTOR_INTERRUPT_HW41      50
 497 #define NDS32_VECTOR_INTERRUPT_HW42      51
 498 #define NDS32_VECTOR_INTERRUPT_HW43      52
 499 #define NDS32_VECTOR_INTERRUPT_HW44      53
 500 #define NDS32_VECTOR_INTERRUPT_HW45      54
 501 #define NDS32_VECTOR_INTERRUPT_HW46      55
 502 #define NDS32_VECTOR_INTERRUPT_HW47      56
 503 #define NDS32_VECTOR_INTERRUPT_HW48      57
 504 #define NDS32_VECTOR_INTERRUPT_HW49      58
 505 #define NDS32_VECTOR_INTERRUPT_HW50      59
 506 #define NDS32_VECTOR_INTERRUPT_HW51      60
 507 #define NDS32_VECTOR_INTERRUPT_HW52      61
 508 #define NDS32_VECTOR_INTERRUPT_HW53      62
 509 #define NDS32_VECTOR_INTERRUPT_HW54      63
 510 #define NDS32_VECTOR_INTERRUPT_HW55      64
 511 #define NDS32_VECTOR_INTERRUPT_HW56      65
 512 #define NDS32_VECTOR_INTERRUPT_HW57      66
 513 #define NDS32_VECTOR_INTERRUPT_HW58      67
 514 #define NDS32_VECTOR_INTERRUPT_HW59      68
 515 #define NDS32_VECTOR_INTERRUPT_HW60      69
 516 #define NDS32_VECTOR_INTERRUPT_HW61      70
 517 #define NDS32_VECTOR_INTERRUPT_HW62      71
 518 #define NDS32_VECTOR_INTERRUPT_HW63      72
 519
 520 #define NDS32ATTR_RESET(option)          __attribute__((reset(option)))
 521 #define NDS32ATTR_EXCEPT(type)           __attribute__((exception(type)))
 522 #define NDS32ATTR_EXCEPTION(type)        __attribute__((exception(type)))
 523 #define NDS32ATTR_INTERRUPT(type)        __attribute__((interrupt(type)))
 524 #define NDS32ATTR_ISR(type)              __attribute__((interrupt(type)))
 525
 526 #endif /* nds32_isr.h */