1 ;;- Machine description for GNU compiler, ns32000 Version
2 ;; Copyright (C) 1988, 1994, 1996, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
25 ;; Insert no-op between an insn with memory read-write operands
26 ;; following by a scale-indexing operation.
27 ;; The Sequent assembler does not allow addresses to be used
28 ;; except in insns which explicitly compute an effective address.
29 ;; I.e., one cannot say "cmpd _p,@_x"
30 ;; Implement unsigned multiplication??
32 ;;- Instruction patterns. When multiple patterns apply,
33 ;;- the first one in the file is chosen.
35 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
37 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38 ;;- updates for most instructions.
40 ;; We don't want to allow a constant operand for test insns because
41 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
42 ;; be folded while optimizing anyway.
44 ;; In order for pic mode to work we cannot generate, for example
48 ;; instead we must force gcc to generate something like
53 ;; This was done through operand constraints (using "rmn" in place of "g"),
54 ;; but with the proper definition of LEGITIMATE_PIC_OPERAND (ns32k.h)
55 ;; this is unnecessary.
58 ;; It seems that in current CVS (2000-01-11), at least with
59 ;; libgcc2.a, that register allocation gets worse when changing
60 ;; "general_operand" "0" to "nonimmediate_operand" "0" (and
61 ;; similar "0"-containing constraints), if operand 0 is (e.g.)
62 ;; "nonimmediate_operand" "=rm". Revisit and test later.
66 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
69 { cc_status.flags |= CC_REVERSED;
70 operands[1] = const0_rtx;
71 return \"cmpqd %1,%0\"; }")
75 (match_operand:HI 0 "nonimmediate_operand" "rm"))]
78 { cc_status.flags |= CC_REVERSED;
79 operands[1] = const0_rtx;
80 return \"cmpqw %1,%0\"; }")
84 (match_operand:QI 0 "nonimmediate_operand" "rm"))]
87 { cc_status.flags |= CC_REVERSED;
88 operands[1] = const0_rtx;
89 return \"cmpqb %1,%0\"; }")
93 (match_operand:DF 0 "general_operand" "lmF"))]
96 { cc_status.flags |= CC_REVERSED;
97 if (TARGET_IEEE_COMPARE)
98 cc_status.flags |= CC_UNORD;
99 operands[1] = CONST0_RTX (DFmode);
100 return \"cmpl %1,%0\"; }")
104 (match_operand:SF 0 "general_operand" "fmF"))]
107 { cc_status.flags |= CC_REVERSED;
108 if (TARGET_IEEE_COMPARE)
109 cc_status.flags |= CC_UNORD;
110 operands[1] = CONST0_RTX (SFmode);
111 return \"cmpf %1,%0\"; }")
116 (compare (match_operand:SI 0 "general_operand" "g")
117 (match_operand:SI 1 "general_operand" "g")))]
121 if (GET_CODE (operands[1]) == CONST_INT)
123 int i = INTVAL (operands[1]);
124 if (i <= 7 && i >= -8)
126 cc_status.flags |= CC_REVERSED;
127 return \"cmpqd %1,%0\";
130 cc_status.flags &= ~CC_REVERSED;
131 if (GET_CODE (operands[0]) == CONST_INT)
133 int i = INTVAL (operands[0]);
134 if (i <= 7 && i >= -8)
135 return \"cmpqd %0,%1\";
137 return \"cmpd %0,%1\";
142 (compare (match_operand:HI 0 "general_operand" "g")
143 (match_operand:HI 1 "general_operand" "g")))]
147 if (GET_CODE (operands[1]) == CONST_INT)
149 short i = INTVAL (operands[1]);
150 if (i <= 7 && i >= -8)
152 cc_status.flags |= CC_REVERSED;
153 if (INTVAL (operands[1]) > 7)
154 operands[1] = GEN_INT (i);
155 return \"cmpqw %1,%0\";
158 cc_status.flags &= ~CC_REVERSED;
159 if (GET_CODE (operands[0]) == CONST_INT)
161 short i = INTVAL (operands[0]);
162 if (i <= 7 && i >= -8)
164 if (INTVAL (operands[0]) > 7)
165 operands[0] = GEN_INT (i);
166 return \"cmpqw %0,%1\";
169 return \"cmpw %0,%1\";
174 (compare (match_operand:QI 0 "general_operand" "g")
175 (match_operand:QI 1 "general_operand" "g")))]
179 if (GET_CODE (operands[1]) == CONST_INT)
181 char i = INTVAL (operands[1]);
182 if (i <= 7 && i >= -8)
184 cc_status.flags |= CC_REVERSED;
185 if (INTVAL (operands[1]) > 7)
186 operands[1] = GEN_INT (i);
187 return \"cmpqb %1,%0\";
190 cc_status.flags &= ~CC_REVERSED;
191 if (GET_CODE (operands[0]) == CONST_INT)
193 char i = INTVAL (operands[0]);
194 if (i <= 7 && i >= -8)
196 if (INTVAL (operands[0]) > 7)
197 operands[0] = GEN_INT (i);
198 return \"cmpqb %0,%1\";
201 return \"cmpb %0,%1\";
206 (compare (match_operand:DF 0 "general_operand" "lmF")
207 (match_operand:DF 1 "general_operand" "lmF")))]
211 if (TARGET_IEEE_COMPARE)
212 cc_status.flags |= CC_UNORD;
213 return \"cmpl %0,%1\";}")
217 (compare (match_operand:SF 0 "general_operand" "fmF")
218 (match_operand:SF 1 "general_operand" "fmF")))]
222 if (TARGET_IEEE_COMPARE)
223 cc_status.flags |= CC_UNORD;
224 return \"cmpf %0,%1\";}")
226 ;; movdf and movsf copy between general and floating registers using
227 ;; the stack. In principle, we could get better code not allowing
228 ;; that case in the constraints and defining SECONDARY_MEMORY_NEEDED
229 ;; in practice, though the stack slots used are not available for
232 [(set (match_operand:DF 0 "nonimmediate_operand" "=lrm<")
233 (match_operand:DF 1 "general_operand" "lFg"))]
237 if (FP_REG_P (operands[0]))
239 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
240 return \"movl %1,%0\";
241 if (REG_P (operands[1]))
244 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
245 output_asm_insn (\"movd %1,tos\", xoperands);
246 output_asm_insn (\"movd %1,tos\", operands);
247 return \"movl tos,%0\";
249 return \"movl %1,%0\";
251 else if (FP_REG_P (operands[1]))
253 if (REG_P (operands[0]))
255 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
256 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
257 return \"movd tos,%0\";
260 return \"movl %1,%0\";
262 return output_move_double (operands);
266 [(set (match_operand:SF 0 "nonimmediate_operand" "=frm<")
267 (match_operand:SF 1 "general_operand" "fFg"))]
271 if (FP_REG_P (operands[0]))
273 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
274 return \"movd %1,tos\;movf tos,%0\";
276 return \"movf %1,%0\";
278 else if (FP_REG_P (operands[1]))
280 if (REG_P (operands[0]))
281 return \"movf %1,tos\;movd tos,%0\";
282 return \"movf %1,%0\";
284 #if 0 /* Someone suggested this for the Sequent. Is it needed? */
285 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
286 return \"movf %1,%0\";
288 /* There was a #if 0 around this, but that was erroneous
289 for many machines -- rms. */
290 #ifndef MOVD_FLOAT_OK
291 /* GAS understands floating constants in ordinary movd instructions
292 but other assemblers might object. */
293 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
295 union {int i[2]; float f; double d;} convrt;
296 convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
297 convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
300 /* Is there a better machine-independent way to to this? */
301 operands[1] = GEN_INT (convrt.i[0]);
302 return \"movd %1,%0\";
305 else return \"movd %1,%0\";
308 (define_insn "*movti"
309 [(set (match_operand:TI 0 "memory_operand" "=m")
310 (match_operand:TI 1 "memory_operand" "m"))]
315 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm<,*f,rm")
316 (match_operand:DI 1 "general_operand" "gF,g,*f"))]
320 if (FP_REG_P (operands[0]))
322 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
323 return \"movl %1,%0\";
324 if (REG_P (operands[1]))
327 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
328 output_asm_insn (\"movd %1,tos\", xoperands);
329 output_asm_insn (\"movd %1,tos\", operands);
330 return \"movl tos,%0\";
332 return \"movl %1,%0\";
334 else if (FP_REG_P (operands[1]))
336 if (REG_P (operands[0]))
338 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
339 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
340 return \"movd tos,%0\";
343 return \"movl %1,%0\";
345 return output_move_double (operands);
348 ;; This special case must precede movsi.
351 (match_operand:SI 0 "general_operand" "g"))]
356 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<,rm<,*f,rm,x")
357 (match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
363 if (FP_REG_P (operands[0]))
365 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
366 return \"movd %1,tos\;movf tos,%0\";
368 return \"movf %1,%0\";
370 else if (FP_REG_P (operands[1]))
372 if (REG_P (operands[0]))
373 return \"movf %1,tos\;movd tos,%0\";
374 return \"movf %1,%0\";
376 if (GET_CODE (operands[0]) == REG
377 && REGNO (operands[0]) == FRAME_POINTER_REGNUM)
378 return \"lprd fp,%1\";
379 if (GET_CODE (operands[1]) == CONST_DOUBLE)
380 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
381 if (GET_CODE (operands[1]) == CONST_INT)
383 int i = INTVAL (operands[1]);
386 if (i <= 7 && i >= -8)
387 return \"movqd %1,%0\";
388 if (NS32K_DISPLACEMENT_P (i))
389 #if defined (GNX_V3) || defined (UTEK_ASM)
390 return \"addr %c1,%0\";
392 return \"addr @%c1,%0\";
394 return \"movd %1,%0\";
397 return output_move_dconst(i, \"%1,%0\");
399 else if (GET_CODE (operands[1]) == CONST && ! flag_pic)
401 /* Must contain symbols so we don't know how big it is. In
402 * that case addr might lead to overflow. For PIC symbolic
403 * address loads always have to be done with addr.
405 return \"movd %1,%0\";
407 else if (GET_CODE (operands[1]) == REG)
409 if (REGNO (operands[1]) < F0_REGNUM)
410 return \"movd %1,%0\";
411 else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
413 if (GET_CODE(operands[0]) == REG)
414 return \"sprd fp,%0\";
416 return \"addr 0(fp),%0\" ;
418 else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
420 if (GET_CODE(operands[0]) == REG)
421 return \"sprd sp,%0\";
423 return \"addr 0(sp),%0\" ;
427 else if (GET_CODE (operands[1]) == MEM)
428 return \"movd %1,%0\";
430 /* Check if this effective address can be
431 calculated faster by pulling it apart. */
432 if (REG_P (operands[0])
433 && GET_CODE (operands[1]) == MULT
434 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
435 && (INTVAL (XEXP (operands[1], 1)) == 2
436 || INTVAL (XEXP (operands[1], 1)) == 4))
439 xoperands[0] = operands[0];
440 xoperands[1] = XEXP (operands[1], 0);
441 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
442 return output_shift_insn (xoperands);
444 return \"addr %a1,%0\";
448 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<,*f,rm")
449 (match_operand:HI 1 "general_operand" "g,g,*f"))]
453 if (GET_CODE (operands[1]) == CONST_INT)
455 short i = INTVAL (operands[1]);
456 if (i <= 7 && i >= -8)
458 if (INTVAL (operands[1]) > 7)
459 operands[1] = GEN_INT (i);
460 return \"movqw %1,%0\";
462 return \"movw %1,%0\";
464 else if (FP_REG_P (operands[0]))
466 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
467 return \"movwf %1,tos\;movf tos,%0\";
469 return \"movwf %1,%0\";
471 else if (FP_REG_P (operands[1]))
473 if (REG_P (operands[0]))
474 return \"movf %1,tos\;movd tos,%0\";
475 return \"movf %1,%0\";
478 return \"movw %1,%0\";
481 (define_insn "movstricthi"
482 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
483 (match_operand:HI 1 "general_operand" "g"))]
487 if (GET_CODE (operands[1]) == CONST_INT
488 && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
489 return \"movqw %1,%0\";
490 return \"movw %1,%0\";
494 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<,*f,rm")
495 (match_operand:QI 1 "general_operand" "g,g,*f"))]
498 { if (GET_CODE (operands[1]) == CONST_INT)
500 char char_val = (char)INTVAL (operands[1]);
501 if (char_val <= 7 && char_val >= -8)
503 if (INTVAL (operands[1]) > 7)
504 operands[1] = GEN_INT (char_val);
505 return \"movqb %1,%0\";
507 return \"movb %1,%0\";
509 else if (FP_REG_P (operands[0]))
511 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
512 return \"movbf %1,tos\;movf tos,%0\";
514 return \"movbf %1,%0\";
516 else if (FP_REG_P (operands[1]))
518 if (REG_P (operands[0]))
519 return \"movf %1,tos\;movd tos,%0\";
520 return \"movf %1,%0\";
523 return \"movb %1,%0\";
526 (define_insn "movstrictqi"
527 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
528 (match_operand:QI 1 "general_operand" "g"))]
532 if (GET_CODE (operands[1]) == CONST_INT
533 && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
534 return \"movqb %1,%0\";
535 return \"movb %1,%0\";
539 ;; Argument 0 is the destination
540 ;; Argument 1 is the source
541 ;; Argument 2 is the length
542 ;; Argument 3 is the alignment
544 ;; Strategy: Use define_expand to
545 ;; either emit insns directly if it can be done simply or
546 ;; emit rtl to match movstrsi1 which has extra scratch registers
547 ;; which can be used to generate more complex code.
549 (define_expand "movstrsi"
550 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
551 (match_operand:BLK 1 "memory_operand" ""))
552 (use (match_operand:SI 2 "general_operand" ""))
553 (use (match_operand:SI 3 "const_int_operand" ""))])]
557 if (operands[0]) /* avoid unused code messages */
559 expand_block_move (operands);
564 ;; Special Registers:
571 (define_insn "movstrsi1"
572 [(set (mem:BLK (reg:SI 2))
573 (mem:BLK (reg:SI 1)))
575 (set (reg:SI 2) (plus:SI (reg:SI 2) (mult:SI (reg:SI 0) (match_operand:SI 0 "const_int_operand" ""))))
576 (set (reg:SI 1) (plus:SI (reg:SI 1) (mult:SI (reg:SI 0) (match_dup 0))))
577 (set (reg:SI 0) (const_int 0))]
581 int align = INTVAL(operands[0]);
588 (define_insn "movstrsi2"
589 [(set (mem:BLK (match_operand:SI 0 "address_operand" "p"))
590 (mem:BLK (match_operand:SI 1 "address_operand" "p")))
591 (use (match_operand 2 "immediate_operand" "i"))]
596 ;; Extension and truncation insns.
597 ;; Those for integer source operand
598 ;; are ordered widest source type first.
600 (define_insn "extendhisi2"
601 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
602 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
606 (define_insn "extendqihi2"
607 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
608 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
612 (define_insn "extendqisi2"
613 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
614 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
618 (define_insn "extendsfdf2"
619 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
620 (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
624 (define_insn "truncdfsf2"
625 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
626 (float_truncate:SF (match_operand:DF 1 "general_operand" "lmF")))]
630 (define_insn "zero_extendhisi2"
631 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
632 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
636 (define_insn "zero_extendqihi2"
637 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
638 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
642 (define_insn "zero_extendqisi2"
643 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
644 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
648 ;; Fix-to-float conversion insns.
649 ;; Note that the ones that start with SImode come first.
650 ;; That is so that an operand that is a CONST_INT
651 ;; (and therefore lacks a specific machine mode).
652 ;; will be recognized as SImode (which is always valid)
653 ;; rather than as QImode or HImode.
655 ;; Rumor has it that the National part does not correctly convert
656 ;; constant ints to floats. This conversion is therefore disabled.
657 ;; A register must be used to perform the conversion.
659 (define_insn "floatsisf2"
660 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
661 (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
665 (define_insn "floatsidf2"
666 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
667 (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
671 (define_insn "floathisf2"
672 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
673 (float:SF (match_operand:HI 1 "nonimmediate_operand" "rm")))]
677 (define_insn "floathidf2"
678 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
679 (float:DF (match_operand:HI 1 "nonimmediate_operand" "rm")))]
683 (define_insn "floatqisf2"
684 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
685 (float:SF (match_operand:QI 1 "nonimmediate_operand" "rm")))]
689 ; Some assemblers warn that this insn doesn't work.
690 ; Maybe they know something we don't.
691 ;(define_insn "floatqidf2"
692 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
693 ; (float:DF (match_operand:QI 1 "nonimmediate_operand" "rm")))]
697 ;; Float-to-fix conversion insns.
698 ;; The sequent compiler always generates "trunc" insns.
700 (define_insn "fixsfqi2"
701 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
702 (fix:QI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
706 (define_insn "fixsfhi2"
707 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
708 (fix:HI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
712 (define_insn "fixsfsi2"
713 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
714 (fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
718 (define_insn "fixdfqi2"
719 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
720 (fix:QI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
724 (define_insn "fixdfhi2"
725 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
726 (fix:HI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
730 (define_insn "fixdfsi2"
731 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
732 (fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
738 (define_insn "fixunssfqi2"
739 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
740 (unsigned_fix:QI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
744 (define_insn "fixunssfhi2"
745 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
746 (unsigned_fix:HI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
750 (define_insn "fixunssfsi2"
751 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
752 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "fm"))))]
756 (define_insn "fixunsdfqi2"
757 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
758 (unsigned_fix:QI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
762 (define_insn "fixunsdfhi2"
763 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
764 (unsigned_fix:HI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
768 (define_insn "fixunsdfsi2"
769 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
770 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "lm"))))]
774 ;;; These are not yet used by GCC
775 (define_insn "fix_truncsfqi2"
776 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
777 (fix:QI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
781 (define_insn "fix_truncsfhi2"
782 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
783 (fix:HI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
787 (define_insn "fix_truncsfsi2"
788 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
789 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "fm")))]
793 (define_insn "fix_truncdfqi2"
794 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
795 (fix:QI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
799 (define_insn "fix_truncdfhi2"
800 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
801 (fix:HI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
805 (define_insn "fix_truncdfsi2"
806 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
807 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "lm")))]
811 ;; Multiply-add instructions
812 (define_insn "*madddf"
813 [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
814 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
815 (match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
816 (match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
821 mull %2,%0\;addl %3,%0")
823 (define_insn "*maddsf"
824 [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
825 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
826 (match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
827 (match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
832 mulf %2,%0\;addf %3,%0")
835 ;; Multiply-sub instructions
836 (define_insn "*msubdf"
837 [(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
838 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
839 (match_operand:DF 2 "general_operand" "lmF,lmF"))
840 (match_operand:DF 3 "general_operand" "lmF,lmF")))]
843 negl %3,%0\;dotl %1,%2
844 mull %2,%0\;subl %3,%0")
846 (define_insn "*msubsf"
847 [(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
848 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
849 (match_operand:SF 2 "general_operand" "fmF,fmF"))
850 (match_operand:SF 3 "general_operand" "fmF,fmF")))]
853 negf %3,%0\;dotf %1,%2
854 mulf %2,%0\;subf %3,%0")
856 ;;- All kinds of add instructions.
858 (define_insn "adddf3"
859 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
860 (plus:DF (match_operand:DF 1 "general_operand" "%0")
861 (match_operand:DF 2 "general_operand" "lmF")))]
866 (define_insn "addsf3"
867 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
868 (plus:SF (match_operand:SF 1 "general_operand" "%0")
869 (match_operand:SF 2 "general_operand" "fmF")))]
873 (define_insn "*add_to_sp"
876 (match_operand:SI 0 "immediate_operand" "i")))]
877 "GET_CODE (operands[0]) == CONST_INT"
880 #ifndef SEQUENT_ADJUST_STACK
882 if (INTVAL (operands[0]) == 8)
883 return \"cmpd tos,tos\";
884 if (TARGET_32532 || TARGET_32332)
885 if (INTVAL (operands[0]) == 4)
886 return \"cmpqd %$0,tos\";
890 if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
891 return \"adjspb %n0\";
892 else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
893 return \"adjspw %n0\";
895 return \"adjspd %n0\";
898 (define_insn "adddi3"
899 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
900 (plus:DI (match_operand:DI 1 "general_operand" "%0")
901 (match_operand:DI 2 "general_operand" "ron")))]
905 rtx low[3], high[3], xops[4];
906 split_di (operands, 3, low, high);
912 if (GET_CODE (xops[2]) == CONST_INT)
914 int i = INTVAL (xops[2]);
916 if (i <= 7 && i >= -8)
920 i = INTVAL (xops[3]);
921 if (i <= 7 && i >= -8)
922 output_asm_insn (\"addqd %3,%1\", xops);
924 output_asm_insn (\"addd %3,%1\", xops);
928 output_asm_insn (\"addqd %2,%0\", xops);
929 output_asm_insn (\"addcd %3,%1\", xops);
934 output_asm_insn (\"addd %2,%0\", xops);
935 output_asm_insn (\"addcd %3,%1\", xops);
940 (define_insn "addsi3"
941 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
942 (plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
943 (match_operand:SI 2 "general_operand" "g,i,i")))]
947 if (which_alternative == 1)
949 if (GET_CODE (operands[2]) == CONST_INT)
951 int i = INTVAL (operands[2]);
952 if (NS32K_DISPLACEMENT_P (i))
953 return \"addr %c2(%1),%0\";
955 return \"movd %1,%0\;addd %2,%0\";
960 return \"addr %a2[%1:b],%0\";
962 return \"addr %c2(%1),%0\";
965 else if (which_alternative == 2)
967 if (GET_CODE (operands[2]) == CONST_INT &&
968 NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
969 return \"addr %c2(%1),%0\";
971 return \"sprd %1,%0\;addd %2,%0\";
973 else if (GET_CODE (operands[2]) == CONST_INT)
975 int i = INTVAL (operands[2]);
977 if (i <= 7 && i >= -8)
978 return \"addqd %2,%0\";
979 else if (! TARGET_32532 && GET_CODE (operands[0]) == REG
980 && NS32K_DISPLACEMENT_P (i))
981 return \"addr %c2(%0),%0\";
983 return \"addd %2,%0\";
986 (define_insn "addhi3"
987 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
988 (plus:HI (match_operand:HI 1 "general_operand" "%0")
989 (match_operand:HI 2 "general_operand" "g")))]
992 { if (GET_CODE (operands[2]) == CONST_INT)
994 int i = INTVAL (operands[2]);
995 if (i <= 7 && i >= -8)
996 return \"addqw %2,%0\";
998 return \"addw %2,%0\";
1001 (define_insn "*addhi_strict_low3"
1002 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1003 (plus:HI (match_operand:HI 1 "general_operand" "0")
1004 (match_operand:HI 2 "general_operand" "g")))]
1008 if (GET_CODE (operands[1]) == CONST_INT
1009 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
1010 return \"addqw %2,%0\";
1011 return \"addw %2,%0\";
1014 (define_insn "addqi3"
1015 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1016 (plus:QI (match_operand:QI 1 "general_operand" "%0")
1017 (match_operand:QI 2 "general_operand" "g")))]
1020 { if (GET_CODE (operands[2]) == CONST_INT)
1022 int i = INTVAL (operands[2]);
1023 if (i <= 7 && i >= -8)
1024 return \"addqb %2,%0\";
1026 return \"addb %2,%0\";
1029 (define_insn "*addqi_strict_low3"
1030 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
1031 (plus:QI (match_operand:QI 1 "general_operand" "0")
1032 (match_operand:QI 2 "general_operand" "g")))]
1036 if (GET_CODE (operands[1]) == CONST_INT
1037 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
1038 return \"addqb %2,%0\";
1039 return \"addb %2,%0\";
1042 ;;- All kinds of subtract instructions.
1044 (define_insn "subdf3"
1045 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
1046 (minus:DF (match_operand:DF 1 "general_operand" "0")
1047 (match_operand:DF 2 "general_operand" "lmF")))]
1051 (define_insn "subsf3"
1052 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
1053 (minus:SF (match_operand:SF 1 "general_operand" "0")
1054 (match_operand:SF 2 "general_operand" "fmF")))]
1058 (define_insn "*sub_from_sp"
1060 (minus:SI (reg:SI 25)
1061 (match_operand:SI 0 "immediate_operand" "i")))]
1062 "GET_CODE (operands[0]) == CONST_INT"
1065 if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT
1066 && INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
1067 return \"adjspb %0\";
1068 return \"adjspd %0\";
1071 (define_insn "subdi3"
1072 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
1073 (minus:DI (match_operand:DI 1 "general_operand" "0")
1074 (match_operand:DI 2 "general_operand" "ron")))]
1078 rtx low[3], high[3], xops[4];
1079 split_di (operands, 3, low, high);
1085 if (GET_CODE (xops[2]) == CONST_INT)
1087 int i = INTVAL (xops[2]);
1089 if (i <= 8 && i >= -7)
1093 i = INTVAL (xops[3]);
1094 if (i <= 8 && i >= -7)
1095 output_asm_insn (\"addqd %n3,%1\", xops);
1097 output_asm_insn (\"subd %3,%1\", xops);
1101 output_asm_insn (\"addqd %n2,%0\", xops);
1102 output_asm_insn (\"subcd %3,%1\", xops);
1107 output_asm_insn (\"subd %2,%0\", xops);
1108 output_asm_insn (\"subcd %3,%1\", xops);
1112 (define_insn "subsi3"
1113 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1114 (minus:SI (match_operand:SI 1 "general_operand" "0")
1115 (match_operand:SI 2 "general_operand" "g")))]
1118 { if (GET_CODE (operands[2]) == CONST_INT)
1120 int i = INTVAL (operands[2]);
1122 if (i <= 8 && i >= -7)
1123 return \"addqd %n2,%0\";
1125 return \"subd %2,%0\";
1128 (define_insn "subhi3"
1129 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1130 (minus:HI (match_operand:HI 1 "general_operand" "0")
1131 (match_operand:HI 2 "general_operand" "g")))]
1134 { if (GET_CODE (operands[2]) == CONST_INT)
1136 int i = INTVAL (operands[2]);
1138 if (i <= 8 && i >= -7)
1139 return \"addqw %n2,%0\";
1141 return \"subw %2,%0\";
1144 (define_insn "*subhi_strict_low3"
1145 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1146 (minus:HI (match_operand:HI 1 "general_operand" "0")
1147 (match_operand:HI 2 "general_operand" "g")))]
1151 if (GET_CODE (operands[1]) == CONST_INT
1152 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1153 return \"addqw %n2,%0\";
1154 return \"subw %2,%0\";
1157 (define_insn "subqi3"
1158 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1159 (minus:QI (match_operand:QI 1 "general_operand" "0")
1160 (match_operand:QI 2 "general_operand" "g")))]
1163 { if (GET_CODE (operands[2]) == CONST_INT)
1165 int i = INTVAL (operands[2]);
1167 if (i <= 8 && i >= -7)
1168 return \"addqb %n2,%0\";
1170 return \"subb %2,%0\";
1173 (define_insn "*subqi_strict_low3"
1174 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
1175 (minus:QI (match_operand:QI 1 "general_operand" "0")
1176 (match_operand:QI 2 "general_operand" "g")))]
1180 if (GET_CODE (operands[1]) == CONST_INT
1181 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1182 return \"addqb %n2,%0\";
1183 return \"subb %2,%0\";
1186 ;;- Multiply instructions.
1188 (define_insn "muldf3"
1189 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
1190 (mult:DF (match_operand:DF 1 "general_operand" "%0")
1191 (match_operand:DF 2 "general_operand" "lmF")))]
1195 (define_insn "mulsf3"
1196 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
1197 (mult:SF (match_operand:SF 1 "general_operand" "%0")
1198 (match_operand:SF 2 "general_operand" "fmF")))]
1203 (define_insn "mulsi3"
1204 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1205 (mult:SI (match_operand:SI 1 "general_operand" "%0")
1206 (match_operand:SI 2 "general_operand" "g")))]
1210 (define_insn "mulhi3"
1211 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1212 (mult:HI (match_operand:HI 1 "general_operand" "%0")
1213 (match_operand:HI 2 "general_operand" "g")))]
1217 (define_insn "mulqi3"
1218 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1219 (mult:QI (match_operand:QI 1 "general_operand" "%0")
1220 (match_operand:QI 2 "general_operand" "g")))]
1224 (define_insn "umulsidi3"
1225 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1226 (mult:DI (zero_extend:DI
1227 (match_operand:SI 1 "nonimmediate_operand" "0"))
1229 (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
1233 ;; divmod insns: We can only do the unsigned case.
1234 (define_expand "udivmodsi4"
1236 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1237 (udiv:SI (match_operand:SI 1 "general_operand" "")
1238 (match_operand:SI 2 "general_operand" "")))
1239 (set (match_operand:SI 3 "nonimmediate_operand" "")
1240 (umod:SI (match_dup 1) (match_dup 2)))])]
1244 rtx temp = gen_reg_rtx(DImode);
1245 rtx insn, first, last;
1246 first = emit_move_insn(gen_lowpart(SImode, temp), operands[1]);
1247 emit_move_insn(gen_highpart(SImode, temp), const0_rtx);
1248 emit_insn(gen_udivmoddisi4_internal(temp, temp, operands[2]));
1249 last = emit_move_insn(temp, temp);
1251 rtx divdi, moddi, divsi, modsi;
1252 divsi = gen_rtx (UDIV, SImode, operands[1], operands[2]);
1253 modsi = gen_rtx (UMOD, SImode, operands[1], operands[2]);
1254 divdi = gen_rtx (ZERO_EXTEND, DImode, divsi);
1255 moddi = gen_rtx (ZERO_EXTEND, DImode, modsi);
1256 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1258 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1259 gen_rtx (EXPR_LIST, REG_EQUAL,
1260 gen_rtx (IOR, DImode, moddi,
1261 gen_rtx (ASHIFT, DImode, divdi, GEN_INT(32))),
1265 insn = emit_move_insn(operands[0], gen_highpart(SImode, temp));
1266 insn = emit_move_insn(operands[3], gen_lowpart(SImode, temp));
1270 ;; If we try and describe what this does, we have to zero-expand an
1271 ;; operand, which prevents it being a constant (VOIDmode) (see udivmoddisi4
1272 ;; below. This udivmoddisi4_internal never matches anything and is only
1273 ;; ever used when explicitly emitted by a define_expand.
1274 (define_insn "udivmoddisi4_internal"
1275 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1276 (unspec:DI [(match_operand:DI 1 "nonimmediate_operand" "0")
1277 (match_operand:SI 2 "general_operand" "g")] 0))]
1281 ;; Retain this insn which *does* have a pattern indicating what it does,
1282 ;; just in case the compiler is smart enough to recognize a substitution.
1283 (define_insn "udivmoddisi4"
1284 [(set (subreg:SI (match_operand:DI 0 "nonimmediate_operand" "=rm") 4)
1285 (truncate:SI (udiv:DI (match_operand:DI 1 "nonimmediate_operand" "0")
1286 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))))
1287 (set (subreg:SI (match_operand:DI 3 "nonimmediate_operand" "=0") 0)
1288 (truncate:SI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1292 ;;;; Part word variants. These seem to never be used at the moment (gcc
1293 ;;;; 2.7.2.2). The code generation prefers to zero extend hi's and qi's
1294 ;;;; and use signed div and mod. Keep these insns incase that changes.
1295 ;;;; divmod should have an advantage when both div and mod are needed. However,
1296 ;;;; divmod uses two registers, so maybe the compiler knows best.
1298 ;;(define_expand "udivmodhi4"
1300 ;; [(set (match_operand:HI 0 "nonimmediate_operand" "")
1301 ;; (udiv:HI (match_operand:HI 1 "general_operand" "")
1302 ;; (match_operand:HI 2 "general_operand" "")))
1303 ;; (set (match_operand:HI 3 "nonimmediate_operand" "")
1304 ;; (umod:HI (match_dup 1) (match_dup 2)))])]
1308 ;; rtx temp = gen_reg_rtx(DImode);
1309 ;; rtx insn, first, last;
1310 ;; first = emit_move_insn(gen_lowpart(HImode, temp), operands[1]);
1311 ;; emit_move_insn(gen_highpart (HImode, temp), const0_rtx);
1312 ;; operands[2] = force_reg(HImode, operands[2]);
1313 ;; emit_insn(gen_udivmoddihi4_internal(temp, temp, operands[2]));
1314 ;; last = emit_move_insn(temp, temp);
1316 ;; rtx divdi, moddi, divhi, modhi;
1317 ;; divhi = gen_rtx (UDIV, HImode, operands[1], operands[2]);
1318 ;; modhi = gen_rtx (UMOD, HImode, operands[1], operands[2]);
1319 ;; divdi = gen_rtx (ZERO_EXTEND, DImode, divhi);
1320 ;; moddi = gen_rtx (ZERO_EXTEND, DImode, modhi);
1321 ;; REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1322 ;; REG_NOTES (first));
1323 ;; REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1324 ;; gen_rtx (EXPR_LIST, REG_EQUAL,
1325 ;; gen_rtx(IOR, DImode, moddi,
1326 ;; gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
1327 ;; REG_NOTES (last)));
1330 ;; insn = emit_move_insn(operands[0], gen_highpart(HImode, temp));
1331 ;; insn = emit_move_insn(operands[3], gen_lowpart(HImode, temp));
1335 ;;;; deiw wants two hi's in separate registers or else they can be adjacent
1336 ;;;; in memory. DI mode will ensure two registers are available, but if we
1337 ;;;; want to allow memory as an operand we would need SI mode. There is no
1338 ;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
1339 ;;(define_insn "udivmoddihi4_internal"
1340 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1341 ;; (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1342 ;; (match_operand:HI 2 "general_operand" "g")] 0))]
1346 ;;(define_insn "udivmoddihi4"
1347 ;; [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 2)
1348 ;; (truncate:HI (udiv:DI (match_operand:DI 1 "register_operand" "0")
1349 ;; (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "rm")))))
1350 ;; (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
1351 ;; (truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1355 ;;(define_expand "udivmodqi4"
1357 ;; [(set (match_operand:QI 0 "nonimmediate_operand" "")
1358 ;; (udiv:QI (match_operand:QI 1 "general_operand" "")
1359 ;; (match_operand:QI 2 "general_operand" "")))
1360 ;; (set (match_operand:QI 3 "nonimmediate_operand" "")
1361 ;; (umod:QI (match_dup 1) (match_dup 2)))])]
1365 ;; rtx temp = gen_reg_rtx(DImode);
1366 ;; rtx insn, first, last;
1367 ;; first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
1368 ;; emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
1369 ;; operands[2] = force_reg(QImode, operands[2]);
1370 ;; emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
1371 ;; last = emit_move_insn(temp, temp);
1373 ;; rtx divdi, moddi, divqi, modqi;
1374 ;; divqi = gen_rtx (UDIV, QImode, operands[1], operands[2]);
1375 ;; modqi = gen_rtx (UMOD, QImode, operands[1], operands[2]);
1376 ;; divdi = gen_rtx (ZERO_EXTEND, DImode, divqi);
1377 ;; moddi = gen_rtx (ZERO_EXTEND, DImode, modqi);
1378 ;; REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1379 ;; REG_NOTES (first));
1380 ;; REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1381 ;; gen_rtx (EXPR_LIST, REG_EQUAL,
1382 ;; gen_rtx(IOR, DImode, moddi,
1383 ;; gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
1384 ;; REG_NOTES (last)));
1387 ;; insn = emit_move_insn(operands[0], gen_highpart(QImode, temp));
1388 ;; insn = emit_move_insn(operands[3], gen_lowpart(QImode, temp));
1392 ;;;; deib wants two qi's in separate registers or else they can be adjacent
1393 ;;;; in memory. DI mode will ensure two registers are available, but if we
1394 ;;;; want to allow memory as an operand we would need HI mode. There is no
1395 ;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
1396 ;;(define_insn "udivmoddiqi4_internal"
1397 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1398 ;; (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1399 ;; (match_operand:QI 2 "general_operand" "g")] 0))]
1403 ;;(define_insn "udivmoddiqi4"
1404 ;; [(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
1405 ;; (truncate:QI (udiv:DI (match_operand:DI 1 "register_operand" "0")
1406 ;; (zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "rm")))))
1407 ;; (set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
1408 ;; (truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1412 ;;- Divide instructions.
1414 (define_insn "divdf3"
1415 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
1416 (div:DF (match_operand:DF 1 "general_operand" "0")
1417 (match_operand:DF 2 "general_operand" "lmF")))]
1421 (define_insn "divsf3"
1422 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
1423 (div:SF (match_operand:SF 1 "general_operand" "0")
1424 (match_operand:SF 2 "general_operand" "fmF")))]
1429 (define_insn "divsi3"
1430 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1431 (div:SI (match_operand:SI 1 "general_operand" "0")
1432 (match_operand:SI 2 "general_operand" "g")))]
1436 (define_insn "divhi3"
1437 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1438 (div:HI (match_operand:HI 1 "general_operand" "0")
1439 (match_operand:HI 2 "general_operand" "g")))]
1443 (define_insn "divqi3"
1444 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1445 (div:QI (match_operand:QI 1 "general_operand" "0")
1446 (match_operand:QI 2 "general_operand" "g")))]
1450 ;; Remainder instructions.
1453 (define_insn "modsi3"
1454 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1455 (mod:SI (match_operand:SI 1 "general_operand" "0")
1456 (match_operand:SI 2 "general_operand" "g")))]
1460 (define_insn "modhi3"
1461 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1462 (mod:HI (match_operand:HI 1 "general_operand" "0")
1463 (match_operand:HI 2 "general_operand" "g")))]
1467 (define_insn "modqi3"
1468 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1469 (mod:QI (match_operand:QI 1 "general_operand" "0")
1470 (match_operand:QI 2 "general_operand" "g")))]
1475 ;;- Logical Instructions: AND
1478 (define_insn "andsi3"
1479 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1480 (and:SI (match_operand:SI 1 "general_operand" "%0")
1481 (match_operand:SI 2 "general_operand" "g")))]
1485 if (GET_CODE (operands[2]) == CONST_INT)
1487 if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1489 if (INTVAL (operands[2]) == 0xffffff00)
1490 return \"movqb %$0,%0\";
1493 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1494 return \"andb %2,%0\";
1497 if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1499 if (INTVAL (operands[2]) == 0xffff0000)
1500 return \"movqw %$0,%0\";
1503 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
1504 return \"andw %2,%0\";
1508 return \"andd %2,%0\";
1511 (define_insn "andhi3"
1512 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1513 (and:HI (match_operand:HI 1 "general_operand" "%0")
1514 (match_operand:HI 2 "general_operand" "g")))]
1518 if (GET_CODE (operands[2]) == CONST_INT
1519 && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1521 if (INTVAL (operands[2]) == 0xffffff00)
1522 return \"movqb %$0,%0\";
1525 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1526 return \"andb %2,%0\";
1529 return \"andw %2,%0\";
1532 (define_insn "andqi3"
1533 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1534 (and:QI (match_operand:QI 1 "general_operand" "%0")
1535 (match_operand:QI 2 "general_operand" "g")))]
1540 (define_insn "*bicsi"
1541 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1542 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
1543 (match_operand:SI 2 "general_operand" "0")))]
1547 (define_insn "*bichi"
1548 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1549 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1550 (match_operand:HI 2 "general_operand" "0")))]
1554 (define_insn "*bicqi"
1555 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1556 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1557 (match_operand:QI 2 "general_operand" "0")))]
1561 ;;- Bit set instructions.
1564 (define_insn "iorsi3"
1565 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1566 (ior:SI (match_operand:SI 1 "general_operand" "%0")
1567 (match_operand:SI 2 "general_operand" "g")))]
1571 if (GET_CODE (operands[2]) == CONST_INT) {
1572 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1573 return \"orb %2,%0\";
1574 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1575 return \"orw %2,%0\";
1577 return \"ord %2,%0\";
1580 (define_insn "iorhi3"
1581 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1582 (ior:HI (match_operand:HI 1 "general_operand" "%0")
1583 (match_operand:HI 2 "general_operand" "g")))]
1587 if (GET_CODE(operands[2]) == CONST_INT &&
1588 (INTVAL(operands[2]) & 0xffffff00) == 0)
1589 return \"orb %2,%0\";
1590 return \"orw %2,%0\";
1593 (define_insn "iorqi3"
1594 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1595 (ior:QI (match_operand:QI 1 "general_operand" "%0")
1596 (match_operand:QI 2 "general_operand" "g")))]
1600 ;;- xor instructions.
1603 (define_insn "xorsi3"
1604 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1605 (xor:SI (match_operand:SI 1 "general_operand" "%0")
1606 (match_operand:SI 2 "general_operand" "g")))]
1610 if (GET_CODE (operands[2]) == CONST_INT) {
1611 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1612 return \"xorb %2,%0\";
1613 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1614 return \"xorw %2,%0\";
1616 return \"xord %2,%0\";
1619 (define_insn "xorhi3"
1620 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1621 (xor:HI (match_operand:HI 1 "general_operand" "%0")
1622 (match_operand:HI 2 "general_operand" "g")))]
1626 if (GET_CODE(operands[2]) == CONST_INT &&
1627 (INTVAL(operands[2]) & 0xffffff00) == 0)
1628 return \"xorb %2,%0\";
1629 return \"xorw %2,%0\";
1632 (define_insn "xorqi3"
1633 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1634 (xor:QI (match_operand:QI 1 "general_operand" "%0")
1635 (match_operand:QI 2 "general_operand" "g")))]
1639 (define_insn "negdf2"
1640 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
1641 (neg:DF (match_operand:DF 1 "general_operand" "lmF")))]
1645 (define_insn "negsf2"
1646 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
1647 (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1651 (define_insn "negdi2"
1652 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
1653 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "ro")))]
1657 rtx low[2], high[2], xops[4];
1658 split_di (operands, 2, low, high);
1664 if (rtx_equal_p (operands[0], operands[1]))
1666 output_asm_insn (\"negd %3,%1\", xops);
1667 output_asm_insn (\"negd %2,%0\", xops);
1668 output_asm_insn (\"subcd %$0,%1\", xops);
1672 output_asm_insn (\"negd %2,%0\", xops);
1673 output_asm_insn (\"movqd %$0,%1\", xops);
1674 output_asm_insn (\"subcd %3,%1\", xops);
1680 (define_insn "negsi2"
1681 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
1682 (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1686 (define_insn "neghi2"
1687 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
1688 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1692 (define_insn "negqi2"
1693 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
1694 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1699 (define_insn "one_cmplsi2"
1700 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
1701 (not:SI (match_operand:SI 1 "general_operand" "g")))]
1705 (define_insn "one_cmplhi2"
1706 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
1707 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1711 (define_insn "one_cmplqi2"
1712 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
1713 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1717 ;; arithmetic left and right shift operations
1718 ;; on the 32532 we will always use lshd for arithmetic left shifts,
1719 ;; because it is three times faster. Broken programs which
1720 ;; use negative shift counts are probably broken differently
1723 ;; alternative 0 never matches on the 32532
1725 (define_insn "ashlsi3"
1726 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
1727 (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1728 (match_operand:SI 2 "general_operand" "I,g")))]
1732 return \"lshd %2,%0\";
1734 return output_shift_insn (operands);
1737 (define_insn "ashlhi3"
1738 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1739 (ashift:HI (match_operand:HI 1 "general_operand" "0")
1740 (match_operand:SI 2 "general_operand" "g")))]
1743 { if (GET_CODE (operands[2]) == CONST_INT)
1745 if (INTVAL (operands[2]) == 1)
1746 return \"addw %0,%0\";
1747 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1748 return \"addw %0,%0\;addw %0,%0\";
1751 return \"lshw %2,%0\";
1753 return \"ashw %2,%0\";
1756 (define_insn "ashlqi3"
1757 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1758 (ashift:QI (match_operand:QI 1 "general_operand" "0")
1759 (match_operand:SI 2 "general_operand" "g")))]
1762 { if (GET_CODE (operands[2]) == CONST_INT)
1764 if (INTVAL (operands[2]) == 1)
1765 return \"addb %0,%0\";
1766 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1767 return \"addb %0,%0\;addb %0,%0\";
1770 return \"lshb %2,%0\";
1772 return \"ashb %2,%0\";
1775 ;; Arithmetic right shift on the 32k works by negating the shift count.
1776 (define_expand "ashrsi3"
1777 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1778 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1779 (match_operand:SI 2 "general_operand" "g")))]
1783 if (GET_CODE (operands[2]) != CONST_INT)
1784 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1787 (define_insn "*ashrisi3"
1788 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1789 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1790 (match_operand:SI 2 "immediate_operand" "i")))]
1794 (define_insn "*ashrsi3"
1795 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1796 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1797 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1801 (define_expand "ashrhi3"
1802 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1803 (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1804 (match_operand:SI 2 "general_operand" "g")))]
1808 if (GET_CODE (operands[2]) != CONST_INT)
1809 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1812 (define_insn "*ashrihi3"
1813 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1814 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1815 (match_operand:SI 2 "immediate_operand" "i")))]
1819 (define_insn "*ashrhi3"
1820 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1821 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1822 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1826 (define_expand "ashrqi3"
1827 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1828 (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1829 (match_operand:SI 2 "general_operand" "g")))]
1833 if (GET_CODE (operands[2]) != CONST_INT)
1834 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1837 (define_insn "*ashriqi3"
1838 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1839 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1840 (match_operand:SI 2 "immediate_operand" "i")))]
1844 (define_insn "*ashrqi3"
1845 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1846 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1847 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1851 ;; logical shift instructions
1853 ;; Logical right shift on the 32k works by negating the shift count.
1854 (define_expand "lshrsi3"
1855 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1856 (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1857 (match_operand:SI 2 "general_operand" "g")))]
1861 if (GET_CODE (operands[2]) != CONST_INT)
1862 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1865 (define_insn "*lshrisi3"
1866 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1867 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1868 (match_operand:SI 2 "immediate_operand" "i")))]
1872 (define_insn "*lshrsi3"
1873 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1874 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1875 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1879 (define_expand "lshrhi3"
1880 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1881 (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1882 (match_operand:SI 2 "general_operand" "g")))]
1886 if (GET_CODE (operands[2]) != CONST_INT)
1887 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1890 (define_insn "*lshrihi3"
1891 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1892 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1893 (match_operand:SI 2 "immediate_operand" "i")))]
1897 (define_insn "*lshrhi3"
1898 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1899 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1900 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1904 (define_expand "lshrqi3"
1905 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1906 (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1907 (match_operand:SI 2 "general_operand" "g")))]
1911 if (GET_CODE (operands[2]) != CONST_INT)
1912 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1915 (define_insn "*lshriqi3"
1916 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1917 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1918 (match_operand:SI 2 "immediate_operand" "i")))]
1922 (define_insn "*lshrqi3"
1923 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1924 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1925 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1929 ;; Rotate instructions
1932 (define_insn "rotlsi3"
1933 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1934 (rotate:SI (match_operand:SI 1 "general_operand" "0")
1935 (match_operand:SI 2 "general_operand" "g")))]
1939 (define_insn "rotlhi3"
1940 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1941 (rotate:HI (match_operand:HI 1 "general_operand" "0")
1942 (match_operand:SI 2 "general_operand" "g")))]
1946 (define_insn "rotlqi3"
1947 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
1948 (rotate:QI (match_operand:QI 1 "general_operand" "0")
1949 (match_operand:SI 2 "general_operand" "g")))]
1953 ;; Right rotate on the 32k works by negating the shift count.
1954 (define_expand "rotrsi3"
1955 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1956 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1957 (match_operand:SI 2 "general_operand" "g")))]
1961 if (GET_CODE (operands[2]) != CONST_INT)
1962 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1965 (define_insn "*rotrisi3"
1966 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1967 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1968 (match_operand:SI 2 "immediate_operand" "i")))]
1972 (define_insn "*rotrsi3"
1973 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
1974 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1975 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
1979 (define_expand "rotrhi3"
1980 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1981 (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1982 (match_operand:SI 2 "general_operand" "g")))]
1986 if (GET_CODE (operands[2]) != CONST_INT)
1987 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1990 (define_insn "*rotrihi3"
1991 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1992 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1993 (match_operand:SI 2 "immediate_operand" "i")))]
1997 (define_insn "*rotrhi3"
1998 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
1999 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
2000 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
2004 (define_expand "rotrqi3"
2005 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2006 (rotatert:QI (match_operand:QI 1 "general_operand" "g")
2007 (match_operand:SI 2 "general_operand" "g")))]
2011 if (GET_CODE (operands[2]) != CONST_INT)
2012 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
2015 (define_insn "*rotriqi3"
2016 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2017 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2018 (match_operand:SI 2 "immediate_operand" "i")))]
2022 (define_insn "*rotrqi3"
2023 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2024 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2025 (neg:SI (match_operand:SI 2 "register_operand" "r"))))]
2029 ;;- load or push effective address
2030 ;; These come after the move, add, and multiply patterns
2031 ;; because we don't want pushl $1 turned into pushad 1.
2033 (define_insn "*addrsi"
2034 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2035 (match_operand:QI 1 "address_operand" "p"))]
2039 if (REG_P (operands[0])
2040 && GET_CODE (operands[1]) == MULT
2041 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
2042 && (INTVAL (XEXP (operands[1], 1)) == 2
2043 || INTVAL (XEXP (operands[1], 1)) == 4))
2046 xoperands[0] = operands[0];
2047 xoperands[1] = XEXP (operands[1], 0);
2048 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
2049 return output_shift_insn (xoperands);
2051 return \"addr %a1,%0\";
2054 ;;; Index insns. These are about the same speed as multiply-add counterparts.
2055 ;;; but slower than using power-of-2 shifts if we can use them
2059 ; [(set (match_operand:SI 0 "register_operand" "=r")
2060 ; (plus:SI (match_operand:SI 1 "general_operand" "g")
2061 ; (mult:SI (match_operand:SI 2 "register_operand" "0")
2062 ; (plus:SI (match_operand:SI 3 "general_operand" "g") (const_int 1)))))]
2063 ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
2064 ; "indexd %0,%3,%1")
2067 ; [(set (match_operand:SI 0 "register_operand" "=r")
2068 ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2069 ; (plus:SI (match_operand:SI 2 "general_operand" "g") (const_int 1)))
2070 ; (match_operand:SI 3 "general_operand" "g")))]
2071 ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
2072 ; "indexd %0,%2,%3")
2074 ;; Set, Clear, and Invert bit
2077 (define_insn "*sbitsi"
2078 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
2080 (match_operand:SI 1 "general_operand" "g"))
2086 (define_insn "*cbitsi"
2087 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
2089 (match_operand:SI 1 "general_operand" "g"))
2095 (define_insn "*ibitsi"
2096 [(set (match_operand:SI 0 "nonimmediate_operand" "+rm")
2097 (xor:SI (ashift:SI (const_int 1)
2098 (match_operand:SI 1 "general_operand" "g"))
2104 (define_insn "*ibitqi"
2105 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
2107 (ashift:SI (const_int 1)
2108 (match_operand:QI 1 "general_operand" "g")) 0)
2113 ;; Recognize jbs and jbc instructions.
2115 (define_insn "*tbit"
2117 (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
2119 (match_operand:SI 1 "general_operand" "g")))]
2122 { cc_status.flags = CC_Z_IN_F;
2123 return \"tbitd %1,%0\";
2126 ;; extract(base, width, offset)
2127 ;; Signed bit-field extraction is not supported in hardware on the
2128 ;; NS 32032. It is therefore better to let GCC figure out a
2129 ;; good strategy for generating the proper instruction sequence
2130 ;; and represent it as rtl.
2132 ;; Optimize the case of extracting a byte or word from a register.
2133 ;; Otherwise we must load a register with the offset of the
2134 ;; chunk we want, and perform an extract insn (each of which
2135 ;; is very expensive). Since we use the stack to do our bit-twiddling
2136 ;; we cannot use it for a destination. Perhaps things are fast
2137 ;; enough on the 32532 that such hacks are not needed.
2139 (define_insn "*extract_bytes"
2140 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2141 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2142 (match_operand:SI 2 "const_int_operand" "i")
2143 (match_operand:SI 3 "const_int_operand" "i")))]
2144 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2145 && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
2148 output_asm_insn (\"movd %1,tos\", operands);
2149 if (INTVAL (operands[2]) == 16)
2151 if (INTVAL (operands[3]) == 8)
2152 output_asm_insn (\"movzwd 1(sp),%0\", operands);
2154 output_asm_insn (\"movzwd 2(sp),%0\", operands);
2158 if (INTVAL (operands[3]) == 8)
2159 output_asm_insn (\"movzbd 1(sp),%0\", operands);
2160 else if (INTVAL (operands[3]) == 16)
2161 output_asm_insn (\"movzbd 2(sp),%0\", operands);
2163 output_asm_insn (\"movzbd 3(sp),%0\", operands);
2165 if (TARGET_32532 || TARGET_32332)
2166 return \"cmpqd %$0,tos\";
2168 return \"adjspb %$-4\";
2171 ;; The exts/ext instructions have the problem that they always access
2172 ;; 32 bits even if the bit-field is smaller. For example the instruction
2173 ;; extsd 7(r1),r0,2,5
2174 ;; would read not only at address 7(r1) but also at 8(r1) to 10(r1).
2175 ;; If these addresses are in a different (unmapped) page a memory fault
2178 ;; Timing considerations:
2179 ;; movd 0(r1),r0 3 bytes
2182 ;; takes about 13 cycles on the 532 while
2183 ;; extsd 7(r1),r0,2,5 5 bytes
2184 ;; takes about 21 cycles.
2186 ;; The inss/ins instructions suffer from the same problem.
2188 ;; A machine specific option (-mbitfield/-mnobitfield) is used
2189 ;; to allow/disallow the use of these instructions.
2191 (define_insn "*bitfield_ext"
2192 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2193 (zero_extract:SI (match_operand:SI 1 "register_operand" "g")
2194 (match_operand:SI 2 "const_int_operand" "i")
2195 (match_operand:SI 3 "nonmemory_operand" "rK")))]
2198 { if (GET_CODE (operands[3]) == CONST_INT)
2199 return \"extsd %1,%0,%3,%2\";
2200 else return \"extd %3,%1,%0,%2\";
2203 (define_insn "extzv"
2204 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2205 (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
2206 (match_operand:SI 2 "const_int_operand" "i")
2207 (match_operand:SI 3 "nonmemory_operand" "rK")))]
2210 { if (GET_CODE (operands[3]) == CONST_INT)
2211 return \"extsd %1,%0,%3,%2\";
2212 else return \"extd %3,%1,%0,%2\";
2215 (define_insn "*bitfield_set"
2216 [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o,+r")
2217 (match_operand:SI 1 "const_int_operand" "i,i")
2218 (match_operand:SI 2 "nonmemory_operand" "rn,rK"))
2219 (match_operand:SI 3 "nonimmediate_operand" "rm,rm"))]
2222 { if (GET_CODE (operands[2]) == CONST_INT)
2224 if (which_alternative == 0 && INTVAL (operands[2]) >= 8)
2226 operands[0] = adjust_address (operands[0], QImode,
2227 INTVAL (operands[2]) / 8);
2228 operands[2] = GEN_INT (INTVAL (operands[2]) % 8);
2230 if (INTVAL (operands[1]) <= 8)
2231 return \"inssb %3,%0,%2,%1\";
2232 else if (INTVAL (operands[1]) <= 16)
2233 return \"inssw %3,%0,%2,%1\";
2235 return \"inssd %3,%0,%2,%1\";
2237 return \"insd %2,%3,%0,%1\";
2242 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+rm")
2243 (match_operand:SI 1 "const_int_operand" "i")
2244 (match_operand:SI 2 "nonmemory_operand" "rK"))
2245 (match_operand:SI 3 "nonimmediate_operand" "rm"))]
2248 { if (GET_CODE (operands[2]) == CONST_INT)
2250 if (INTVAL (operands[1]) <= 8)
2251 return \"inssb %3,%0,%2,%1\";
2252 else if (INTVAL (operands[1]) <= 16)
2253 return \"inssw %3,%0,%2,%1\";
2255 return \"inssd %3,%0,%2,%1\";
2257 return \"insd %2,%3,%0,%1\";
2263 (label_ref (match_operand 0 "" "")))]
2269 (if_then_else (eq (cc0)
2271 (label_ref (match_operand 0 "" ""))
2275 { if (cc_prev_status.flags & CC_Z_IN_F)
2277 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2279 else return \"beq %l0\";
2284 (if_then_else (ne (cc0)
2286 (label_ref (match_operand 0 "" ""))
2290 { if (cc_prev_status.flags & CC_Z_IN_F)
2292 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2294 else return \"bne %l0\";
2299 (if_then_else (gt (cc0)
2301 (label_ref (match_operand 0 "" ""))
2308 (if_then_else (gtu (cc0)
2310 (label_ref (match_operand 0 "" ""))
2317 (if_then_else (lt (cc0)
2319 (label_ref (match_operand 0 "" ""))
2324 if (cc_prev_status.flags & CC_UNORD)
2325 return \"bhi 0f\;blt %l0\;0:\";
2332 (if_then_else (ltu (cc0)
2334 (label_ref (match_operand 0 "" ""))
2341 (if_then_else (ge (cc0)
2343 (label_ref (match_operand 0 "" ""))
2350 (if_then_else (geu (cc0)
2352 (label_ref (match_operand 0 "" ""))
2359 (if_then_else (le (cc0)
2361 (label_ref (match_operand 0 "" ""))
2366 if (cc_prev_status.flags & CC_UNORD)
2367 return \"bhi 0f\;ble %l0\;0:\";
2374 (if_then_else (leu (cc0)
2376 (label_ref (match_operand 0 "" ""))
2381 ;; "Reversed" jump instructions. Are these ever generated?
2385 (if_then_else (eq (cc0)
2388 (label_ref (match_operand 0 "" ""))))]
2391 { if (cc_prev_status.flags & CC_Z_IN_F)
2393 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2395 else return \"bne %l0\";
2400 (if_then_else (ne (cc0)
2403 (label_ref (match_operand 0 "" ""))))]
2406 { if (cc_prev_status.flags & CC_Z_IN_F)
2408 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2410 else return \"beq %l0\";
2415 (if_then_else (gt (cc0)
2418 (label_ref (match_operand 0 "" ""))))]
2422 if (cc_prev_status.flags & CC_UNORD)
2423 return \"bhi 0f\;ble %l0\;0:\";
2428 (define_insn "*bleu"
2430 (if_then_else (gtu (cc0)
2433 (label_ref (match_operand 0 "" ""))))]
2439 (if_then_else (lt (cc0)
2442 (label_ref (match_operand 0 "" ""))))]
2446 (define_insn "*bgeu"
2448 (if_then_else (ltu (cc0)
2451 (label_ref (match_operand 0 "" ""))))]
2457 (if_then_else (ge (cc0)
2460 (label_ref (match_operand 0 "" ""))))]
2464 if (cc_prev_status.flags & CC_UNORD)
2465 return \"bhi 0f\;blt %l0\;0:\";
2470 (define_insn "*bltu"
2472 (if_then_else (geu (cc0)
2475 (label_ref (match_operand 0 "" ""))))]
2481 (if_then_else (le (cc0)
2484 (label_ref (match_operand 0 "" ""))))]
2488 (define_insn "*bgtu"
2490 (if_then_else (leu (cc0)
2493 (label_ref (match_operand 0 "" ""))))]
2497 ;; Subtract-and-jump and Add-and-jump insns.
2498 ;; These can actually be used for adding numbers in the range -8 to 7
2500 (define_insn "*sub_br"
2503 (ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
2504 (match_operand:SI 1 "const_int_operand" "i"))
2505 (label_ref (match_operand 2 "" ""))
2508 (minus:SI (match_dup 0)
2510 "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2513 (define_insn "*add_br"
2516 (ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
2517 (match_operand:SI 1 "const_int_operand" "i"))
2518 (label_ref (match_operand 2 "" ""))
2521 (plus:SI (match_dup 0)
2522 (match_operand:SI 3 "const_int_operand" "i")))]
2523 "INTVAL (operands[1]) == - INTVAL (operands[3])
2524 && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2528 [(call (match_operand:QI 0 "memory_operand" "m")
2529 (match_operand 1 "" ""))]
2530 ;; Operand 1 is not used
2535 if (GET_CODE (operands[0]) == MEM)
2537 rtx temp = XEXP (operands[0], 0);
2538 if (CONSTANT_ADDRESS_P (temp))
2541 return \"bsr %?%0\";
2543 #ifdef CALL_MEMREF_IMPLICIT
2550 return \"bsr %?%a0\";
2555 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2556 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2562 #endif /* not JSR_ALWAYS */
2566 (define_insn "call_value"
2567 [(set (match_operand 0 "" "=rf")
2568 (call (match_operand:QI 1 "memory_operand" "m")
2569 (match_operand 2 "" "")))]
2570 ;; Operand 2 is not used
2575 if (GET_CODE (operands[1]) == MEM)
2577 rtx temp = XEXP (operands[1], 0);
2578 if (CONSTANT_ADDRESS_P (temp))
2581 return \"bsr %?%1\";
2583 #ifdef CALL_MEMREF_IMPLICIT
2590 return \"bsr %?%a1\";
2595 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2596 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2602 #endif /* not JSR_ALWAYS */
2606 ;; Call subroutine returning any type.
2608 (define_expand "untyped_call"
2609 [(parallel [(call (match_operand 0 "" "")
2611 (match_operand 1 "" "")
2612 (match_operand 2 "" "")])]
2618 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
2620 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2622 rtx set = XVECEXP (operands[2], 0, i);
2623 emit_move_insn (SET_DEST (set), SET_SRC (set));
2626 /* The optimizer does not know that the call sets the function value
2627 registers we stored in the result block. We avoid problems by
2628 claiming that all hard registers are used and clobbered at this
2630 emit_insn (gen_blockage ());
2635 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2636 ;; all of memory. This blocks insns from being moved across this point.
2638 (define_insn "blockage"
2639 [(unspec_volatile [(const_int 0)] 0)]
2643 (define_insn "return"
2648 (define_insn "abssf2"
2649 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
2650 (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2654 (define_insn "absdf2"
2655 [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
2656 (abs:DF (match_operand:DF 1 "general_operand" "lmF")))]
2661 (define_insn "abssi2"
2662 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
2663 (abs:SI (match_operand:SI 1 "general_operand" "g")))]
2667 (define_insn "abshi2"
2668 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
2669 (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2673 (define_insn "absqi2"
2674 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
2675 (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2684 (define_insn "indirect_jump"
2685 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2689 (define_insn "tablejump"
2691 (plus:SI (pc) (match_operand:SI 0 "general_operand" "g")))
2692 (use (label_ref (match_operand 1 "" "")))]
2696 (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
2697 CODE_LABEL_NUMBER (operands[1]));
2698 return \"cased %0\";
2701 ;; Scondi instructions
2703 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2704 (eq:SI (cc0) (const_int 0)))]
2707 { if (cc_prev_status.flags & CC_Z_IN_F)
2709 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2711 else return \"seqd %0\";
2714 (define_insn "*seqhi"
2715 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2716 (eq:HI (cc0) (const_int 0)))]
2719 { if (cc_prev_status.flags & CC_Z_IN_F)
2721 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2723 else return \"seqw %0\";
2726 (define_insn "*seqqi"
2727 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2728 (eq:QI (cc0) (const_int 0)))]
2731 { if (cc_prev_status.flags & CC_Z_IN_F)
2733 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2735 else return \"seqb %0\";
2739 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2740 (ne:SI (cc0) (const_int 0)))]
2743 { if (cc_prev_status.flags & CC_Z_IN_F)
2745 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2747 else return \"sned %0\";
2750 (define_insn "*snehi"
2751 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2752 (ne:HI (cc0) (const_int 0)))]
2755 { if (cc_prev_status.flags & CC_Z_IN_F)
2757 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2759 else return \"snew %0\";
2762 (define_insn "*sneqi"
2763 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2764 (ne:QI (cc0) (const_int 0)))]
2767 { if (cc_prev_status.flags & CC_Z_IN_F)
2769 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2771 else return \"sneb %0\";
2775 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2776 (gt:SI (cc0) (const_int 0)))]
2780 (define_insn "*sgthi"
2781 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2782 (gt:HI (cc0) (const_int 0)))]
2786 (define_insn "*sgtqi"
2787 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2788 (gt:QI (cc0) (const_int 0)))]
2793 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2794 (gtu:SI (cc0) (const_int 0)))]
2798 (define_insn "*sgtuhi"
2799 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2800 (gtu:HI (cc0) (const_int 0)))]
2804 (define_insn "*sgtuqi"
2805 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2806 (gtu:QI (cc0) (const_int 0)))]
2811 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2812 (lt:SI (cc0) (const_int 0)))]
2816 (define_insn "*slthi"
2817 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2818 (lt:HI (cc0) (const_int 0)))]
2822 (define_insn "*sltqi"
2823 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2824 (lt:QI (cc0) (const_int 0)))]
2829 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2830 (ltu:SI (cc0) (const_int 0)))]
2834 (define_insn "*sltuhi"
2835 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2836 (ltu:HI (cc0) (const_int 0)))]
2840 (define_insn "*sltuqi"
2841 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2842 (ltu:QI (cc0) (const_int 0)))]
2847 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2848 (ge:SI (cc0) (const_int 0)))]
2852 (define_insn "*sgehi"
2853 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2854 (ge:HI (cc0) (const_int 0)))]
2858 (define_insn "*sgeqi"
2859 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2860 (ge:QI (cc0) (const_int 0)))]
2865 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2866 (geu:SI (cc0) (const_int 0)))]
2870 (define_insn "*sgeuhi"
2871 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2872 (geu:HI (cc0) (const_int 0)))]
2876 (define_insn "*sgeuqi"
2877 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2878 (geu:QI (cc0) (const_int 0)))]
2883 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2884 (le:SI (cc0) (const_int 0)))]
2888 (define_insn "*slehi"
2889 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2890 (le:HI (cc0) (const_int 0)))]
2894 (define_insn "*sleqi"
2895 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2896 (le:QI (cc0) (const_int 0)))]
2901 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
2902 (leu:SI (cc0) (const_int 0)))]
2906 (define_insn "*sleuhi"
2907 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
2908 (leu:HI (cc0) (const_int 0)))]
2912 (define_insn "*sleuqi"
2913 [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
2914 (leu:QI (cc0) (const_int 0)))]
2921 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2923 (plus:SI (ffs:SI (zero_extract:SI
2924 (match_operand:SI 1 "general_operand" "g")
2925 (minus:SI (const_int 32) (match_dup 0))
2930 "ffsd %1,%0; bfc 1f; addqd %$-1,%0; 1:")
2932 (define_expand "ffssi2"
2933 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (const_int 0))
2936 (plus:SI (ffs:SI (zero_extract:SI
2937 (match_operand:SI 1 "general_operand" "g")
2938 (minus:SI (const_int 32) (match_dup 0))
2943 (plus:SI (match_dup 0)
2946 "operands[1] = make_safe_from(operands[1], operands[0]);")
2948 ;; Speed up stack adjust followed by a HI fixedpoint push.
2951 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2952 (set (match_operand:HI 0 "push_operand" "=m")
2953 (match_operand:HI 1 "general_operand" "g"))]
2954 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2957 if (GET_CODE (operands[1]) == CONST_INT)
2958 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2961 output_asm_insn (\"movzwd %1,tos\", operands);
2965 ;; Speed up stack adjust followed by a zero_extend:HI(QI) fixedpoint push.
2968 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2969 (set (match_operand:HI 0 "push_operand" "=m")
2970 (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2971 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2974 if (GET_CODE (operands[1]) == CONST_INT)
2975 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2978 output_asm_insn (\"movzbd %1,tos\", operands);
2982 ;; Speed up stack adjust followed by a sign_extend:HI(QI) fixedpoint push.
2985 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2986 (set (match_operand:HI 0 "push_operand" "=m")
2987 (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2988 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2991 if (GET_CODE (operands[1]) == CONST_INT)
2992 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2995 output_asm_insn (\"movxbd %1,tos\", operands);
2999 ;; Speed up stack adjust followed by a QI fixedpoint push.
3002 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -3)))
3003 (set (match_operand:QI 0 "push_operand" "=m")
3004 (match_operand:QI 1 "general_operand" "g"))]
3005 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
3008 if (GET_CODE (operands[1]) == CONST_INT)
3009 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
3012 output_asm_insn (\"movzbd %1,tos\", operands);
3016 ;; Speed up stack adjust followed by a SI fixedpoint push.
3019 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 4)))
3020 (set (match_operand:SI 0 "push_operand" "=m")
3021 (match_operand:SI 1 "general_operand" "g"))]
3022 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
3025 if (GET_CODE (operands[1]) == CONST_INT)
3026 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,0(sp)\"),
3028 else if (GET_CODE (operands[1]) != REG
3029 && GET_CODE (operands[1]) != MEM
3030 && address_operand (operands[1], SImode))
3031 output_asm_insn (\"addr %a1,0(sp)\", operands);
3033 output_asm_insn (\"movd %1,0(sp)\", operands);
3037 ;; Speed up stack adjust followed by two fullword fixedpoint pushes.
3040 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 8)))
3041 (set (match_operand:SI 0 "push_operand" "=m")
3042 (match_operand:SI 1 "general_operand" "g"))
3043 (set (match_operand:SI 2 "push_operand" "=m")
3044 (match_operand:SI 3 "general_operand" "g"))]
3045 "! reg_mentioned_p (stack_pointer_rtx, operands[1])
3046 && ! reg_mentioned_p (stack_pointer_rtx, operands[3])"
3049 if (GET_CODE (operands[1]) == CONST_INT)
3050 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,4(sp)\"),
3052 else if (GET_CODE (operands[1]) != REG
3053 && GET_CODE (operands[1]) != MEM
3054 && address_operand (operands[1], SImode))
3055 output_asm_insn (\"addr %a1,4(sp)\", operands);
3057 output_asm_insn (\"movd %1,4(sp)\", operands);
3059 if (GET_CODE (operands[3]) == CONST_INT)
3060 output_asm_insn (output_move_dconst (INTVAL (operands[3]), \"%3,0(sp)\"),
3062 else if (GET_CODE (operands[3]) != REG
3063 && GET_CODE (operands[3]) != MEM
3064 && address_operand (operands[3], SImode))
3065 output_asm_insn (\"addr %a3,0(sp)\", operands);
3067 output_asm_insn (\"movd %3,0(sp)\", operands);