1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
33 #include "stringpool.h"
39 #include "diagnostic-core.h"
40 #include "insn-attr.h"
42 #include "fold-const.h"
43 #include "stor-layout.h"
51 #include "common/common-target.h"
52 #include "langhooks.h"
57 /* This file should be included last. */
58 #include "target-def.h"
60 /* Return nonzero if there is a bypass for the output of
61 OUT_INSN and the fp store IN_INSN. */
63 pa_fpstore_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
65 machine_mode store_mode
;
66 machine_mode other_mode
;
69 if (recog_memoized (in_insn
) < 0
70 || (get_attr_type (in_insn
) != TYPE_FPSTORE
71 && get_attr_type (in_insn
) != TYPE_FPSTORE_LOAD
)
72 || recog_memoized (out_insn
) < 0)
75 store_mode
= GET_MODE (SET_SRC (PATTERN (in_insn
)));
77 set
= single_set (out_insn
);
81 other_mode
= GET_MODE (SET_SRC (set
));
83 return (GET_MODE_SIZE (store_mode
) == GET_MODE_SIZE (other_mode
));
87 #ifndef DO_FRAME_NOTES
88 #ifdef INCOMING_RETURN_ADDR_RTX
89 #define DO_FRAME_NOTES 1
91 #define DO_FRAME_NOTES 0
95 static void pa_option_override (void);
96 static void copy_reg_pointer (rtx
, rtx
);
97 static void fix_range (const char *);
98 static int hppa_register_move_cost (machine_mode mode
, reg_class_t
,
100 static int hppa_address_cost (rtx
, machine_mode mode
, addr_space_t
, bool);
101 static bool hppa_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
102 static inline rtx
force_mode (machine_mode
, rtx
);
103 static void pa_reorg (void);
104 static void pa_combine_instructions (void);
105 static int pa_can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, int, rtx
,
107 static bool forward_branch_p (rtx_insn
*);
108 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT
, unsigned *);
109 static void compute_zdepdi_operands (unsigned HOST_WIDE_INT
, unsigned *);
110 static int compute_movmem_length (rtx_insn
*);
111 static int compute_clrmem_length (rtx_insn
*);
112 static bool pa_assemble_integer (rtx
, unsigned int, int);
113 static void remove_useless_addtr_insns (int);
114 static void store_reg (int, HOST_WIDE_INT
, int);
115 static void store_reg_modify (int, int, HOST_WIDE_INT
);
116 static void load_reg (int, HOST_WIDE_INT
, int);
117 static void set_reg_plus_d (int, int, HOST_WIDE_INT
, int);
118 static rtx
pa_function_value (const_tree
, const_tree
, bool);
119 static rtx
pa_libcall_value (machine_mode
, const_rtx
);
120 static bool pa_function_value_regno_p (const unsigned int);
121 static void pa_output_function_prologue (FILE *);
122 static void update_total_code_bytes (unsigned int);
123 static void pa_output_function_epilogue (FILE *);
124 static int pa_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
125 static int pa_issue_rate (void);
126 static int pa_reloc_rw_mask (void);
127 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED
;
128 static section
*pa_som_tm_clone_table_section (void) ATTRIBUTE_UNUSED
;
129 static section
*pa_select_section (tree
, int, unsigned HOST_WIDE_INT
)
131 static void pa_encode_section_info (tree
, rtx
, int);
132 static const char *pa_strip_name_encoding (const char *);
133 static bool pa_function_ok_for_sibcall (tree
, tree
);
134 static void pa_globalize_label (FILE *, const char *)
136 static void pa_asm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
137 HOST_WIDE_INT
, tree
);
138 #if !defined(USE_COLLECT2)
139 static void pa_asm_out_constructor (rtx
, int);
140 static void pa_asm_out_destructor (rtx
, int);
142 static void pa_init_builtins (void);
143 static rtx
pa_expand_builtin (tree
, rtx
, rtx
, machine_mode mode
, int);
144 static rtx
hppa_builtin_saveregs (void);
145 static void hppa_va_start (tree
, rtx
);
146 static tree
hppa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
147 static bool pa_scalar_mode_supported_p (scalar_mode
);
148 static bool pa_commutative_p (const_rtx x
, int outer_code
);
149 static void copy_fp_args (rtx_insn
*) ATTRIBUTE_UNUSED
;
150 static int length_fp_args (rtx_insn
*) ATTRIBUTE_UNUSED
;
151 static rtx
hppa_legitimize_address (rtx
, rtx
, machine_mode
);
152 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED
;
153 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED
;
154 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED
;
155 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED
;
156 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED
;
157 static void pa_som_file_start (void) ATTRIBUTE_UNUSED
;
158 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED
;
159 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED
;
160 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED
;
161 static void output_deferred_plabels (void);
162 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED
;
163 static void pa_file_end (void);
164 static void pa_init_libfuncs (void);
165 static rtx
pa_struct_value_rtx (tree
, int);
166 static bool pa_pass_by_reference (cumulative_args_t
, machine_mode
,
168 static int pa_arg_partial_bytes (cumulative_args_t
, machine_mode
,
170 static void pa_function_arg_advance (cumulative_args_t
, machine_mode
,
172 static rtx
pa_function_arg (cumulative_args_t
, machine_mode
,
174 static pad_direction
pa_function_arg_padding (machine_mode
, const_tree
);
175 static unsigned int pa_function_arg_boundary (machine_mode
, const_tree
);
176 static struct machine_function
* pa_init_machine_status (void);
177 static reg_class_t
pa_secondary_reload (bool, rtx
, reg_class_t
,
179 secondary_reload_info
*);
180 static bool pa_secondary_memory_needed (machine_mode
,
181 reg_class_t
, reg_class_t
);
182 static void pa_extra_live_on_entry (bitmap
);
183 static machine_mode
pa_promote_function_mode (const_tree
,
187 static void pa_asm_trampoline_template (FILE *);
188 static void pa_trampoline_init (rtx
, tree
, rtx
);
189 static rtx
pa_trampoline_adjust_address (rtx
);
190 static rtx
pa_delegitimize_address (rtx
);
191 static bool pa_print_operand_punct_valid_p (unsigned char);
192 static rtx
pa_internal_arg_pointer (void);
193 static bool pa_can_eliminate (const int, const int);
194 static void pa_conditional_register_usage (void);
195 static machine_mode
pa_c_mode_for_suffix (char);
196 static section
*pa_function_section (tree
, enum node_frequency
, bool, bool);
197 static bool pa_cannot_force_const_mem (machine_mode
, rtx
);
198 static bool pa_legitimate_constant_p (machine_mode
, rtx
);
199 static unsigned int pa_section_type_flags (tree
, const char *, int);
200 static bool pa_legitimate_address_p (machine_mode
, rtx
, bool);
201 static bool pa_callee_copies (cumulative_args_t
, machine_mode
,
203 static unsigned int pa_hard_regno_nregs (unsigned int, machine_mode
);
204 static bool pa_hard_regno_mode_ok (unsigned int, machine_mode
);
205 static bool pa_modes_tieable_p (machine_mode
, machine_mode
);
206 static bool pa_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t
);
207 static HOST_WIDE_INT
pa_starting_frame_offset (void);
209 /* The following extra sections are only used for SOM. */
210 static GTY(()) section
*som_readonly_data_section
;
211 static GTY(()) section
*som_one_only_readonly_data_section
;
212 static GTY(()) section
*som_one_only_data_section
;
213 static GTY(()) section
*som_tm_clone_table_section
;
215 /* Counts for the number of callee-saved general and floating point
216 registers which were saved by the current function's prologue. */
217 static int gr_saved
, fr_saved
;
219 /* Boolean indicating whether the return pointer was saved by the
220 current function's prologue. */
221 static bool rp_saved
;
223 static rtx
find_addr_reg (rtx
);
225 /* Keep track of the number of bytes we have output in the CODE subspace
226 during this compilation so we'll know when to emit inline long-calls. */
227 unsigned long total_code_bytes
;
229 /* The last address of the previous function plus the number of bytes in
230 associated thunks that have been output. This is used to determine if
231 a thunk can use an IA-relative branch to reach its target function. */
232 static unsigned int last_address
;
234 /* Variables to handle plabels that we discover are necessary at assembly
235 output time. They are output after the current function. */
236 struct GTY(()) deferred_plabel
241 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel
*
243 static size_t n_deferred_plabels
= 0;
245 /* Initialize the GCC target structure. */
247 #undef TARGET_OPTION_OVERRIDE
248 #define TARGET_OPTION_OVERRIDE pa_option_override
250 #undef TARGET_ASM_ALIGNED_HI_OP
251 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
252 #undef TARGET_ASM_ALIGNED_SI_OP
253 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
254 #undef TARGET_ASM_ALIGNED_DI_OP
255 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
256 #undef TARGET_ASM_UNALIGNED_HI_OP
257 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
258 #undef TARGET_ASM_UNALIGNED_SI_OP
259 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
260 #undef TARGET_ASM_UNALIGNED_DI_OP
261 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
262 #undef TARGET_ASM_INTEGER
263 #define TARGET_ASM_INTEGER pa_assemble_integer
265 #undef TARGET_ASM_FUNCTION_PROLOGUE
266 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
267 #undef TARGET_ASM_FUNCTION_EPILOGUE
268 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
270 #undef TARGET_FUNCTION_VALUE
271 #define TARGET_FUNCTION_VALUE pa_function_value
272 #undef TARGET_LIBCALL_VALUE
273 #define TARGET_LIBCALL_VALUE pa_libcall_value
274 #undef TARGET_FUNCTION_VALUE_REGNO_P
275 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
277 #undef TARGET_LEGITIMIZE_ADDRESS
278 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
280 #undef TARGET_SCHED_ADJUST_COST
281 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
282 #undef TARGET_SCHED_ISSUE_RATE
283 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
285 #undef TARGET_ENCODE_SECTION_INFO
286 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
287 #undef TARGET_STRIP_NAME_ENCODING
288 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
290 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
291 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
293 #undef TARGET_COMMUTATIVE_P
294 #define TARGET_COMMUTATIVE_P pa_commutative_p
296 #undef TARGET_ASM_OUTPUT_MI_THUNK
297 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
298 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
299 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
301 #undef TARGET_ASM_FILE_END
302 #define TARGET_ASM_FILE_END pa_file_end
304 #undef TARGET_ASM_RELOC_RW_MASK
305 #define TARGET_ASM_RELOC_RW_MASK pa_reloc_rw_mask
307 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
308 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
310 #if !defined(USE_COLLECT2)
311 #undef TARGET_ASM_CONSTRUCTOR
312 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
313 #undef TARGET_ASM_DESTRUCTOR
314 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
317 #undef TARGET_INIT_BUILTINS
318 #define TARGET_INIT_BUILTINS pa_init_builtins
320 #undef TARGET_EXPAND_BUILTIN
321 #define TARGET_EXPAND_BUILTIN pa_expand_builtin
323 #undef TARGET_REGISTER_MOVE_COST
324 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
325 #undef TARGET_RTX_COSTS
326 #define TARGET_RTX_COSTS hppa_rtx_costs
327 #undef TARGET_ADDRESS_COST
328 #define TARGET_ADDRESS_COST hppa_address_cost
330 #undef TARGET_MACHINE_DEPENDENT_REORG
331 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
333 #undef TARGET_INIT_LIBFUNCS
334 #define TARGET_INIT_LIBFUNCS pa_init_libfuncs
336 #undef TARGET_PROMOTE_FUNCTION_MODE
337 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
338 #undef TARGET_PROMOTE_PROTOTYPES
339 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
341 #undef TARGET_STRUCT_VALUE_RTX
342 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
343 #undef TARGET_RETURN_IN_MEMORY
344 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
345 #undef TARGET_MUST_PASS_IN_STACK
346 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
347 #undef TARGET_PASS_BY_REFERENCE
348 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
349 #undef TARGET_CALLEE_COPIES
350 #define TARGET_CALLEE_COPIES pa_callee_copies
351 #undef TARGET_ARG_PARTIAL_BYTES
352 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
353 #undef TARGET_FUNCTION_ARG
354 #define TARGET_FUNCTION_ARG pa_function_arg
355 #undef TARGET_FUNCTION_ARG_ADVANCE
356 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
357 #undef TARGET_FUNCTION_ARG_PADDING
358 #define TARGET_FUNCTION_ARG_PADDING pa_function_arg_padding
359 #undef TARGET_FUNCTION_ARG_BOUNDARY
360 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
362 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
363 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
364 #undef TARGET_EXPAND_BUILTIN_VA_START
365 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
366 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
367 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
369 #undef TARGET_SCALAR_MODE_SUPPORTED_P
370 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
372 #undef TARGET_CANNOT_FORCE_CONST_MEM
373 #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem
375 #undef TARGET_SECONDARY_RELOAD
376 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
377 #undef TARGET_SECONDARY_MEMORY_NEEDED
378 #define TARGET_SECONDARY_MEMORY_NEEDED pa_secondary_memory_needed
380 #undef TARGET_EXTRA_LIVE_ON_ENTRY
381 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
383 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
384 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
385 #undef TARGET_TRAMPOLINE_INIT
386 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
387 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
388 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
389 #undef TARGET_DELEGITIMIZE_ADDRESS
390 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
391 #undef TARGET_INTERNAL_ARG_POINTER
392 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
393 #undef TARGET_CAN_ELIMINATE
394 #define TARGET_CAN_ELIMINATE pa_can_eliminate
395 #undef TARGET_CONDITIONAL_REGISTER_USAGE
396 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
397 #undef TARGET_C_MODE_FOR_SUFFIX
398 #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix
399 #undef TARGET_ASM_FUNCTION_SECTION
400 #define TARGET_ASM_FUNCTION_SECTION pa_function_section
402 #undef TARGET_LEGITIMATE_CONSTANT_P
403 #define TARGET_LEGITIMATE_CONSTANT_P pa_legitimate_constant_p
404 #undef TARGET_SECTION_TYPE_FLAGS
405 #define TARGET_SECTION_TYPE_FLAGS pa_section_type_flags
406 #undef TARGET_LEGITIMATE_ADDRESS_P
407 #define TARGET_LEGITIMATE_ADDRESS_P pa_legitimate_address_p
410 #define TARGET_LRA_P hook_bool_void_false
412 #undef TARGET_HARD_REGNO_NREGS
413 #define TARGET_HARD_REGNO_NREGS pa_hard_regno_nregs
414 #undef TARGET_HARD_REGNO_MODE_OK
415 #define TARGET_HARD_REGNO_MODE_OK pa_hard_regno_mode_ok
416 #undef TARGET_MODES_TIEABLE_P
417 #define TARGET_MODES_TIEABLE_P pa_modes_tieable_p
419 #undef TARGET_CAN_CHANGE_MODE_CLASS
420 #define TARGET_CAN_CHANGE_MODE_CLASS pa_can_change_mode_class
422 #undef TARGET_CONSTANT_ALIGNMENT
423 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
425 #undef TARGET_STARTING_FRAME_OFFSET
426 #define TARGET_STARTING_FRAME_OFFSET pa_starting_frame_offset
428 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
429 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
431 struct gcc_target targetm
= TARGET_INITIALIZER
;
433 /* Parse the -mfixed-range= option string. */
436 fix_range (const char *const_str
)
439 char *str
, *dash
, *comma
;
441 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
442 REG2 are either register names or register numbers. The effect
443 of this option is to mark the registers in the range from REG1 to
444 REG2 as ``fixed'' so they won't be used by the compiler. This is
445 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
447 i
= strlen (const_str
);
448 str
= (char *) alloca (i
+ 1);
449 memcpy (str
, const_str
, i
+ 1);
453 dash
= strchr (str
, '-');
456 warning (0, "value of %<-mfixed-range%> must have form REG1-REG2");
461 comma
= strchr (dash
+ 1, ',');
465 first
= decode_reg_name (str
);
468 warning (0, "unknown register name: %s", str
);
472 last
= decode_reg_name (dash
+ 1);
475 warning (0, "unknown register name: %s", dash
+ 1);
483 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
487 for (i
= first
; i
<= last
; ++i
)
488 fixed_regs
[i
] = call_used_regs
[i
] = 1;
497 /* Check if all floating point registers have been fixed. */
498 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
503 target_flags
|= MASK_DISABLE_FPREGS
;
506 /* Implement the TARGET_OPTION_OVERRIDE hook. */
509 pa_option_override (void)
512 cl_deferred_option
*opt
;
513 vec
<cl_deferred_option
> *v
514 = (vec
<cl_deferred_option
> *) pa_deferred_options
;
517 FOR_EACH_VEC_ELT (*v
, i
, opt
)
519 switch (opt
->opt_index
)
521 case OPT_mfixed_range_
:
522 fix_range (opt
->arg
);
530 if (flag_pic
&& TARGET_PORTABLE_RUNTIME
)
532 warning (0, "PIC code generation is not supported in the portable runtime model");
535 if (flag_pic
&& TARGET_FAST_INDIRECT_CALLS
)
537 warning (0, "PIC code generation is not compatible with fast indirect calls");
540 if (! TARGET_GAS
&& write_symbols
!= NO_DEBUG
)
542 warning (0, "%<-g%> is only supported when using GAS on this processor,");
543 warning (0, "%<-g%> option disabled");
544 write_symbols
= NO_DEBUG
;
547 /* We only support the "big PIC" model now. And we always generate PIC
548 code when in 64bit mode. */
549 if (flag_pic
== 1 || TARGET_64BIT
)
552 /* Disable -freorder-blocks-and-partition as we don't support hot and
553 cold partitioning. */
554 if (flag_reorder_blocks_and_partition
)
556 inform (input_location
,
557 "%<-freorder-blocks-and-partition%> does not work "
558 "on this architecture");
559 flag_reorder_blocks_and_partition
= 0;
560 flag_reorder_blocks
= 1;
563 /* We can't guarantee that .dword is available for 32-bit targets. */
564 if (UNITS_PER_WORD
== 4)
565 targetm
.asm_out
.aligned_op
.di
= NULL
;
567 /* The unaligned ops are only available when using GAS. */
570 targetm
.asm_out
.unaligned_op
.hi
= NULL
;
571 targetm
.asm_out
.unaligned_op
.si
= NULL
;
572 targetm
.asm_out
.unaligned_op
.di
= NULL
;
575 init_machine_status
= pa_init_machine_status
;
580 PA_BUILTIN_COPYSIGNQ
,
583 PA_BUILTIN_HUGE_VALQ
,
587 static GTY(()) tree pa_builtins
[(int) PA_BUILTIN_max
];
590 pa_init_builtins (void)
592 #ifdef DONT_HAVE_FPUTC_UNLOCKED
594 tree decl
= builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED
);
595 set_builtin_decl (BUILT_IN_FPUTC_UNLOCKED
, decl
,
596 builtin_decl_implicit_p (BUILT_IN_PUTC_UNLOCKED
));
603 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITE
)) != NULL_TREE
)
604 set_user_assembler_name (decl
, "_Isfinite");
605 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEF
)) != NULL_TREE
)
606 set_user_assembler_name (decl
, "_Isfinitef");
610 if (HPUX_LONG_DOUBLE_LIBRARY
)
614 /* Under HPUX, the __float128 type is a synonym for "long double". */
615 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
618 /* TFmode support builtins. */
619 ftype
= build_function_type_list (long_double_type_node
,
620 long_double_type_node
,
622 decl
= add_builtin_function ("__builtin_fabsq", ftype
,
623 PA_BUILTIN_FABSQ
, BUILT_IN_MD
,
624 "_U_Qfabs", NULL_TREE
);
625 TREE_READONLY (decl
) = 1;
626 pa_builtins
[PA_BUILTIN_FABSQ
] = decl
;
628 ftype
= build_function_type_list (long_double_type_node
,
629 long_double_type_node
,
630 long_double_type_node
,
632 decl
= add_builtin_function ("__builtin_copysignq", ftype
,
633 PA_BUILTIN_COPYSIGNQ
, BUILT_IN_MD
,
634 "_U_Qfcopysign", NULL_TREE
);
635 TREE_READONLY (decl
) = 1;
636 pa_builtins
[PA_BUILTIN_COPYSIGNQ
] = decl
;
638 ftype
= build_function_type_list (long_double_type_node
, NULL_TREE
);
639 decl
= add_builtin_function ("__builtin_infq", ftype
,
640 PA_BUILTIN_INFQ
, BUILT_IN_MD
,
642 pa_builtins
[PA_BUILTIN_INFQ
] = decl
;
644 decl
= add_builtin_function ("__builtin_huge_valq", ftype
,
645 PA_BUILTIN_HUGE_VALQ
, BUILT_IN_MD
,
647 pa_builtins
[PA_BUILTIN_HUGE_VALQ
] = decl
;
652 pa_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
653 machine_mode mode ATTRIBUTE_UNUSED
,
654 int ignore ATTRIBUTE_UNUSED
)
656 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
657 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
661 case PA_BUILTIN_FABSQ
:
662 case PA_BUILTIN_COPYSIGNQ
:
663 return expand_call (exp
, target
, ignore
);
665 case PA_BUILTIN_INFQ
:
666 case PA_BUILTIN_HUGE_VALQ
:
668 machine_mode target_mode
= TYPE_MODE (TREE_TYPE (exp
));
673 tmp
= const_double_from_real_value (inf
, target_mode
);
675 tmp
= validize_mem (force_const_mem (target_mode
, tmp
));
678 target
= gen_reg_rtx (target_mode
);
680 emit_move_insn (target
, tmp
);
691 /* Function to init struct machine_function.
692 This will be called, via a pointer variable,
693 from push_function_context. */
695 static struct machine_function
*
696 pa_init_machine_status (void)
698 return ggc_cleared_alloc
<machine_function
> ();
701 /* If FROM is a probable pointer register, mark TO as a probable
702 pointer register with the same pointer alignment as FROM. */
705 copy_reg_pointer (rtx to
, rtx from
)
707 if (REG_POINTER (from
))
708 mark_reg_pointer (to
, REGNO_POINTER_ALIGN (REGNO (from
)));
711 /* Return 1 if X contains a symbolic expression. We know these
712 expressions will have one of a few well defined forms, so
713 we need only check those forms. */
715 pa_symbolic_expression_p (rtx x
)
718 /* Strip off any HIGH. */
719 if (GET_CODE (x
) == HIGH
)
722 return symbolic_operand (x
, VOIDmode
);
725 /* Accept any constant that can be moved in one instruction into a
728 pa_cint_ok_for_move (unsigned HOST_WIDE_INT ival
)
730 /* OK if ldo, ldil, or zdepi, can be used. */
731 return (VAL_14_BITS_P (ival
)
732 || pa_ldil_cint_p (ival
)
733 || pa_zdepi_cint_p (ival
));
736 /* True iff ldil can be used to load this CONST_INT. The least
737 significant 11 bits of the value must be zero and the value must
738 not change sign when extended from 32 to 64 bits. */
740 pa_ldil_cint_p (unsigned HOST_WIDE_INT ival
)
742 unsigned HOST_WIDE_INT x
;
744 x
= ival
& (((unsigned HOST_WIDE_INT
) -1 << 31) | 0x7ff);
745 return x
== 0 || x
== ((unsigned HOST_WIDE_INT
) -1 << 31);
748 /* True iff zdepi can be used to generate this CONST_INT.
749 zdepi first sign extends a 5-bit signed number to a given field
750 length, then places this field anywhere in a zero. */
752 pa_zdepi_cint_p (unsigned HOST_WIDE_INT x
)
754 unsigned HOST_WIDE_INT lsb_mask
, t
;
756 /* This might not be obvious, but it's at least fast.
757 This function is critical; we don't have the time loops would take. */
759 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
760 /* Return true iff t is a power of two. */
761 return ((t
& (t
- 1)) == 0);
764 /* True iff depi or extru can be used to compute (reg & mask).
765 Accept bit pattern like these:
770 pa_and_mask_p (unsigned HOST_WIDE_INT mask
)
773 mask
+= mask
& -mask
;
774 return (mask
& (mask
- 1)) == 0;
777 /* True iff depi can be used to compute (reg | MASK). */
779 pa_ior_mask_p (unsigned HOST_WIDE_INT mask
)
781 mask
+= mask
& -mask
;
782 return (mask
& (mask
- 1)) == 0;
785 /* Legitimize PIC addresses. If the address is already
786 position-independent, we return ORIG. Newly generated
787 position-independent addresses go to REG. If we need more
788 than one register, we lose. */
791 legitimize_pic_address (rtx orig
, machine_mode mode
, rtx reg
)
795 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig
));
797 /* Labels need special handling. */
798 if (pic_label_operand (orig
, mode
))
802 /* We do not want to go through the movXX expanders here since that
803 would create recursion.
805 Nor do we really want to call a generator for a named pattern
806 since that requires multiple patterns if we want to support
809 So instead we just emit the raw set, which avoids the movXX
810 expanders completely. */
811 mark_reg_pointer (reg
, BITS_PER_UNIT
);
812 insn
= emit_insn (gen_rtx_SET (reg
, orig
));
814 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
815 add_reg_note (insn
, REG_EQUAL
, orig
);
817 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
818 and update LABEL_NUSES because this is not done automatically. */
819 if (reload_in_progress
|| reload_completed
)
821 /* Extract LABEL_REF. */
822 if (GET_CODE (orig
) == CONST
)
823 orig
= XEXP (XEXP (orig
, 0), 0);
824 /* Extract CODE_LABEL. */
825 orig
= XEXP (orig
, 0);
826 add_reg_note (insn
, REG_LABEL_OPERAND
, orig
);
827 /* Make sure we have label and not a note. */
829 LABEL_NUSES (orig
)++;
831 crtl
->uses_pic_offset_table
= 1;
834 if (GET_CODE (orig
) == SYMBOL_REF
)
841 /* Before reload, allocate a temporary register for the intermediate
842 result. This allows the sequence to be deleted when the final
843 result is unused and the insns are trivially dead. */
844 tmp_reg
= ((reload_in_progress
|| reload_completed
)
845 ? reg
: gen_reg_rtx (Pmode
));
847 if (function_label_operand (orig
, VOIDmode
))
849 /* Force function label into memory in word mode. */
850 orig
= XEXP (force_const_mem (word_mode
, orig
), 0);
851 /* Load plabel address from DLT. */
852 emit_move_insn (tmp_reg
,
853 gen_rtx_PLUS (word_mode
, pic_offset_table_rtx
,
854 gen_rtx_HIGH (word_mode
, orig
)));
856 = gen_const_mem (Pmode
,
857 gen_rtx_LO_SUM (Pmode
, tmp_reg
,
858 gen_rtx_UNSPEC (Pmode
,
861 emit_move_insn (reg
, pic_ref
);
862 /* Now load address of function descriptor. */
863 pic_ref
= gen_rtx_MEM (Pmode
, reg
);
867 /* Load symbol reference from DLT. */
868 emit_move_insn (tmp_reg
,
869 gen_rtx_PLUS (word_mode
, pic_offset_table_rtx
,
870 gen_rtx_HIGH (word_mode
, orig
)));
872 = gen_const_mem (Pmode
,
873 gen_rtx_LO_SUM (Pmode
, tmp_reg
,
874 gen_rtx_UNSPEC (Pmode
,
879 crtl
->uses_pic_offset_table
= 1;
880 mark_reg_pointer (reg
, BITS_PER_UNIT
);
881 insn
= emit_move_insn (reg
, pic_ref
);
883 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
884 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
888 else if (GET_CODE (orig
) == CONST
)
892 if (GET_CODE (XEXP (orig
, 0)) == PLUS
893 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
897 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
899 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
900 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
901 base
== reg
? 0 : reg
);
903 if (GET_CODE (orig
) == CONST_INT
)
905 if (INT_14_BITS (orig
))
906 return plus_constant (Pmode
, base
, INTVAL (orig
));
907 orig
= force_reg (Pmode
, orig
);
909 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
910 /* Likewise, should we set special REG_NOTEs here? */
916 static GTY(()) rtx gen_tls_tga
;
919 gen_tls_get_addr (void)
922 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
927 hppa_tls_call (rtx arg
)
931 ret
= gen_reg_rtx (Pmode
);
932 emit_library_call_value (gen_tls_get_addr (), ret
,
933 LCT_CONST
, Pmode
, arg
, Pmode
);
939 legitimize_tls_address (rtx addr
)
941 rtx ret
, tmp
, t1
, t2
, tp
;
944 /* Currently, we can't handle anything but a SYMBOL_REF. */
945 if (GET_CODE (addr
) != SYMBOL_REF
)
948 switch (SYMBOL_REF_TLS_MODEL (addr
))
950 case TLS_MODEL_GLOBAL_DYNAMIC
:
951 tmp
= gen_reg_rtx (Pmode
);
953 emit_insn (gen_tgd_load_pic (tmp
, addr
));
955 emit_insn (gen_tgd_load (tmp
, addr
));
956 ret
= hppa_tls_call (tmp
);
959 case TLS_MODEL_LOCAL_DYNAMIC
:
960 ret
= gen_reg_rtx (Pmode
);
961 tmp
= gen_reg_rtx (Pmode
);
964 emit_insn (gen_tld_load_pic (tmp
, addr
));
966 emit_insn (gen_tld_load (tmp
, addr
));
967 t1
= hppa_tls_call (tmp
);
970 t2
= gen_reg_rtx (Pmode
);
971 emit_libcall_block (insn
, t2
, t1
,
972 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
974 emit_insn (gen_tld_offset_load (ret
, addr
, t2
));
977 case TLS_MODEL_INITIAL_EXEC
:
978 tp
= gen_reg_rtx (Pmode
);
979 tmp
= gen_reg_rtx (Pmode
);
980 ret
= gen_reg_rtx (Pmode
);
981 emit_insn (gen_tp_load (tp
));
983 emit_insn (gen_tie_load_pic (tmp
, addr
));
985 emit_insn (gen_tie_load (tmp
, addr
));
986 emit_move_insn (ret
, gen_rtx_PLUS (Pmode
, tp
, tmp
));
989 case TLS_MODEL_LOCAL_EXEC
:
990 tp
= gen_reg_rtx (Pmode
);
991 ret
= gen_reg_rtx (Pmode
);
992 emit_insn (gen_tp_load (tp
));
993 emit_insn (gen_tle_load (ret
, addr
, tp
));
1003 /* Helper for hppa_legitimize_address. Given X, return true if it
1004 is a left shift by 1, 2 or 3 positions or a multiply by 2, 4 or 8.
1006 This respectively represent canonical shift-add rtxs or scaled
1007 memory addresses. */
1009 mem_shadd_or_shadd_rtx_p (rtx x
)
1011 return ((GET_CODE (x
) == ASHIFT
1012 || GET_CODE (x
) == MULT
)
1013 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1014 && ((GET_CODE (x
) == ASHIFT
1015 && pa_shadd_constant_p (INTVAL (XEXP (x
, 1))))
1016 || (GET_CODE (x
) == MULT
1017 && pa_mem_shadd_constant_p (INTVAL (XEXP (x
, 1))))));
1020 /* Try machine-dependent ways of modifying an illegitimate address
1021 to be legitimate. If we find one, return the new, valid address.
1022 This macro is used in only one place: `memory_address' in explow.c.
1024 OLDX is the address as it was before break_out_memory_refs was called.
1025 In some cases it is useful to look at this to decide what needs to be done.
1027 It is always safe for this macro to do nothing. It exists to recognize
1028 opportunities to optimize the output.
1030 For the PA, transform:
1032 memory(X + <large int>)
1036 if (<large int> & mask) >= 16
1037 Y = (<large int> & ~mask) + mask + 1 Round up.
1039 Y = (<large int> & ~mask) Round down.
1041 memory (Z + (<large int> - Y));
1043 This is for CSE to find several similar references, and only use one Z.
1045 X can either be a SYMBOL_REF or REG, but because combine cannot
1046 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1047 D will not fit in 14 bits.
1049 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1052 MODE_INT references allow displacements which fit in 14 bits, so use
1055 This relies on the fact that most mode MODE_FLOAT references will use FP
1056 registers and most mode MODE_INT references will use integer registers.
1057 (In the rare case of an FP register used in an integer MODE, we depend
1058 on secondary reloads to clean things up.)
1061 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1062 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1063 addressing modes to be used).
1065 Note that the addresses passed into hppa_legitimize_address always
1066 come from a MEM, so we only have to match the MULT form on incoming
1067 addresses. But to be future proof we also match the ASHIFT form.
1069 However, this routine always places those shift-add sequences into
1070 registers, so we have to generate the ASHIFT form as our output.
1072 Put X and Z into registers. Then put the entire expression into
1076 hppa_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1081 /* We need to canonicalize the order of operands in unscaled indexed
1082 addresses since the code that checks if an address is valid doesn't
1083 always try both orders. */
1084 if (!TARGET_NO_SPACE_REGS
1085 && GET_CODE (x
) == PLUS
1086 && GET_MODE (x
) == Pmode
1087 && REG_P (XEXP (x
, 0))
1088 && REG_P (XEXP (x
, 1))
1089 && REG_POINTER (XEXP (x
, 0))
1090 && !REG_POINTER (XEXP (x
, 1)))
1091 return gen_rtx_PLUS (Pmode
, XEXP (x
, 1), XEXP (x
, 0));
1093 if (tls_referenced_p (x
))
1094 return legitimize_tls_address (x
);
1096 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
1098 /* Strip off CONST. */
1099 if (GET_CODE (x
) == CONST
)
1102 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1103 That should always be safe. */
1104 if (GET_CODE (x
) == PLUS
1105 && GET_CODE (XEXP (x
, 0)) == REG
1106 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
1108 rtx reg
= force_reg (Pmode
, XEXP (x
, 1));
1109 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg
, XEXP (x
, 0)));
1112 /* Note we must reject symbols which represent function addresses
1113 since the assembler/linker can't handle arithmetic on plabels. */
1114 if (GET_CODE (x
) == PLUS
1115 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1116 && ((GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1117 && !FUNCTION_NAME_P (XSTR (XEXP (x
, 0), 0)))
1118 || GET_CODE (XEXP (x
, 0)) == REG
))
1120 rtx int_part
, ptr_reg
;
1122 int offset
= INTVAL (XEXP (x
, 1));
1125 mask
= (GET_MODE_CLASS (mode
) == MODE_FLOAT
1126 && !INT14_OK_STRICT
? 0x1f : 0x3fff);
1128 /* Choose which way to round the offset. Round up if we
1129 are >= halfway to the next boundary. */
1130 if ((offset
& mask
) >= ((mask
+ 1) / 2))
1131 newoffset
= (offset
& ~ mask
) + mask
+ 1;
1133 newoffset
= (offset
& ~ mask
);
1135 /* If the newoffset will not fit in 14 bits (ldo), then
1136 handling this would take 4 or 5 instructions (2 to load
1137 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1138 add the new offset and the SYMBOL_REF.) Combine cannot
1139 handle 4->2 or 5->2 combinations, so do not create
1141 if (! VAL_14_BITS_P (newoffset
)
1142 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
1144 rtx const_part
= plus_constant (Pmode
, XEXP (x
, 0), newoffset
);
1147 gen_rtx_HIGH (Pmode
, const_part
));
1150 gen_rtx_LO_SUM (Pmode
,
1151 tmp_reg
, const_part
));
1155 if (! VAL_14_BITS_P (newoffset
))
1156 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
1158 int_part
= GEN_INT (newoffset
);
1160 ptr_reg
= force_reg (Pmode
,
1161 gen_rtx_PLUS (Pmode
,
1162 force_reg (Pmode
, XEXP (x
, 0)),
1165 return plus_constant (Pmode
, ptr_reg
, offset
- newoffset
);
1168 /* Handle (plus (mult (a) (mem_shadd_constant)) (b)). */
1170 if (GET_CODE (x
) == PLUS
1171 && mem_shadd_or_shadd_rtx_p (XEXP (x
, 0))
1172 && (OBJECT_P (XEXP (x
, 1))
1173 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1174 && GET_CODE (XEXP (x
, 1)) != CONST
)
1176 /* If we were given a MULT, we must fix the constant
1177 as we're going to create the ASHIFT form. */
1178 int shift_val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1179 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1180 shift_val
= exact_log2 (shift_val
);
1184 if (GET_CODE (reg1
) != REG
)
1185 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1187 reg2
= XEXP (XEXP (x
, 0), 0);
1188 if (GET_CODE (reg2
) != REG
)
1189 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1191 return force_reg (Pmode
,
1192 gen_rtx_PLUS (Pmode
,
1193 gen_rtx_ASHIFT (Pmode
, reg2
,
1194 GEN_INT (shift_val
)),
1198 /* Similarly for (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)).
1200 Only do so for floating point modes since this is more speculative
1201 and we lose if it's an integer store. */
1202 if (GET_CODE (x
) == PLUS
1203 && GET_CODE (XEXP (x
, 0)) == PLUS
1204 && mem_shadd_or_shadd_rtx_p (XEXP (XEXP (x
, 0), 0))
1205 && (mode
== SFmode
|| mode
== DFmode
))
1207 int shift_val
= INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1));
1209 /* If we were given a MULT, we must fix the constant
1210 as we're going to create the ASHIFT form. */
1211 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
1212 shift_val
= exact_log2 (shift_val
);
1214 /* Try and figure out what to use as a base register. */
1215 rtx reg1
, reg2
, base
, idx
;
1217 reg1
= XEXP (XEXP (x
, 0), 1);
1222 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1223 then pa_emit_move_sequence will turn on REG_POINTER so we'll know
1224 it's a base register below. */
1225 if (GET_CODE (reg1
) != REG
)
1226 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1228 if (GET_CODE (reg2
) != REG
)
1229 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1231 /* Figure out what the base and index are. */
1233 if (GET_CODE (reg1
) == REG
1234 && REG_POINTER (reg1
))
1237 idx
= gen_rtx_PLUS (Pmode
,
1238 gen_rtx_ASHIFT (Pmode
,
1239 XEXP (XEXP (XEXP (x
, 0), 0), 0),
1240 GEN_INT (shift_val
)),
1243 else if (GET_CODE (reg2
) == REG
1244 && REG_POINTER (reg2
))
1253 /* If the index adds a large constant, try to scale the
1254 constant so that it can be loaded with only one insn. */
1255 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
1256 && VAL_14_BITS_P (INTVAL (XEXP (idx
, 1))
1257 / INTVAL (XEXP (XEXP (idx
, 0), 1)))
1258 && INTVAL (XEXP (idx
, 1)) % INTVAL (XEXP (XEXP (idx
, 0), 1)) == 0)
1260 /* Divide the CONST_INT by the scale factor, then add it to A. */
1261 int val
= INTVAL (XEXP (idx
, 1));
1262 val
/= (1 << shift_val
);
1264 reg1
= XEXP (XEXP (idx
, 0), 0);
1265 if (GET_CODE (reg1
) != REG
)
1266 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1268 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg1
, GEN_INT (val
)));
1270 /* We can now generate a simple scaled indexed address. */
1273 (Pmode
, gen_rtx_PLUS (Pmode
,
1274 gen_rtx_ASHIFT (Pmode
, reg1
,
1275 GEN_INT (shift_val
)),
1279 /* If B + C is still a valid base register, then add them. */
1280 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
1281 && INTVAL (XEXP (idx
, 1)) <= 4096
1282 && INTVAL (XEXP (idx
, 1)) >= -4096)
1286 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, XEXP (idx
, 1)));
1288 reg2
= XEXP (XEXP (idx
, 0), 0);
1289 if (GET_CODE (reg2
) != CONST_INT
)
1290 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1292 return force_reg (Pmode
,
1293 gen_rtx_PLUS (Pmode
,
1294 gen_rtx_ASHIFT (Pmode
, reg2
,
1295 GEN_INT (shift_val
)),
1299 /* Get the index into a register, then add the base + index and
1300 return a register holding the result. */
1302 /* First get A into a register. */
1303 reg1
= XEXP (XEXP (idx
, 0), 0);
1304 if (GET_CODE (reg1
) != REG
)
1305 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1307 /* And get B into a register. */
1308 reg2
= XEXP (idx
, 1);
1309 if (GET_CODE (reg2
) != REG
)
1310 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1312 reg1
= force_reg (Pmode
,
1313 gen_rtx_PLUS (Pmode
,
1314 gen_rtx_ASHIFT (Pmode
, reg1
,
1315 GEN_INT (shift_val
)),
1318 /* Add the result to our base register and return. */
1319 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, reg1
));
1323 /* Uh-oh. We might have an address for x[n-100000]. This needs
1324 special handling to avoid creating an indexed memory address
1325 with x-100000 as the base.
1327 If the constant part is small enough, then it's still safe because
1328 there is a guard page at the beginning and end of the data segment.
1330 Scaled references are common enough that we want to try and rearrange the
1331 terms so that we can use indexing for these addresses too. Only
1332 do the optimization for floatint point modes. */
1334 if (GET_CODE (x
) == PLUS
1335 && pa_symbolic_expression_p (XEXP (x
, 1)))
1337 /* Ugly. We modify things here so that the address offset specified
1338 by the index expression is computed first, then added to x to form
1339 the entire address. */
1341 rtx regx1
, regx2
, regy1
, regy2
, y
;
1343 /* Strip off any CONST. */
1345 if (GET_CODE (y
) == CONST
)
1348 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1350 /* See if this looks like
1351 (plus (mult (reg) (mem_shadd_const))
1352 (const (plus (symbol_ref) (const_int))))
1354 Where const_int is small. In that case the const
1355 expression is a valid pointer for indexing.
1357 If const_int is big, but can be divided evenly by shadd_const
1358 and added to (reg). This allows more scaled indexed addresses. */
1359 if (GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1360 && mem_shadd_or_shadd_rtx_p (XEXP (x
, 0))
1361 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1362 && INTVAL (XEXP (y
, 1)) >= -4096
1363 && INTVAL (XEXP (y
, 1)) <= 4095)
1365 int shift_val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1367 /* If we were given a MULT, we must fix the constant
1368 as we're going to create the ASHIFT form. */
1369 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1370 shift_val
= exact_log2 (shift_val
);
1375 if (GET_CODE (reg1
) != REG
)
1376 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1378 reg2
= XEXP (XEXP (x
, 0), 0);
1379 if (GET_CODE (reg2
) != REG
)
1380 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1384 gen_rtx_PLUS (Pmode
,
1385 gen_rtx_ASHIFT (Pmode
,
1387 GEN_INT (shift_val
)),
1390 else if ((mode
== DFmode
|| mode
== SFmode
)
1391 && GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1392 && mem_shadd_or_shadd_rtx_p (XEXP (x
, 0))
1393 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1394 && INTVAL (XEXP (y
, 1)) % (1 << INTVAL (XEXP (XEXP (x
, 0), 1))) == 0)
1396 int shift_val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1398 /* If we were given a MULT, we must fix the constant
1399 as we're going to create the ASHIFT form. */
1400 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1401 shift_val
= exact_log2 (shift_val
);
1404 = force_reg (Pmode
, GEN_INT (INTVAL (XEXP (y
, 1))
1405 / INTVAL (XEXP (XEXP (x
, 0), 1))));
1406 regx2
= XEXP (XEXP (x
, 0), 0);
1407 if (GET_CODE (regx2
) != REG
)
1408 regx2
= force_reg (Pmode
, force_operand (regx2
, 0));
1409 regx2
= force_reg (Pmode
, gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1413 gen_rtx_PLUS (Pmode
,
1414 gen_rtx_ASHIFT (Pmode
, regx2
,
1415 GEN_INT (shift_val
)),
1416 force_reg (Pmode
, XEXP (y
, 0))));
1418 else if (GET_CODE (XEXP (y
, 1)) == CONST_INT
1419 && INTVAL (XEXP (y
, 1)) >= -4096
1420 && INTVAL (XEXP (y
, 1)) <= 4095)
1422 /* This is safe because of the guard page at the
1423 beginning and end of the data space. Just
1424 return the original address. */
1429 /* Doesn't look like one we can optimize. */
1430 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1431 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1432 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1433 regx1
= force_reg (Pmode
,
1434 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1436 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1444 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1446 Compute extra cost of moving data between one register class
1449 Make moves from SAR so expensive they should never happen. We used to
1450 have 0xffff here, but that generates overflow in rare cases.
1452 Copies involving a FP register and a non-FP register are relatively
1453 expensive because they must go through memory.
1455 Other copies are reasonably cheap. */
1458 hppa_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1459 reg_class_t from
, reg_class_t to
)
1461 if (from
== SHIFT_REGS
)
1463 else if (to
== SHIFT_REGS
&& FP_REG_CLASS_P (from
))
1465 else if ((FP_REG_CLASS_P (from
) && ! FP_REG_CLASS_P (to
))
1466 || (FP_REG_CLASS_P (to
) && ! FP_REG_CLASS_P (from
)))
1472 /* For the HPPA, REG and REG+CONST is cost 0
1473 and addresses involving symbolic constants are cost 2.
1475 PIC addresses are very expensive.
1477 It is no coincidence that this has the same structure
1478 as pa_legitimate_address_p. */
1481 hppa_address_cost (rtx X
, machine_mode mode ATTRIBUTE_UNUSED
,
1482 addr_space_t as ATTRIBUTE_UNUSED
,
1483 bool speed ATTRIBUTE_UNUSED
)
1485 switch (GET_CODE (X
))
1498 /* Compute a (partial) cost for rtx X. Return true if the complete
1499 cost has been computed, and false if subexpressions should be
1500 scanned. In either case, *TOTAL contains the cost result. */
1503 hppa_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
1504 int opno ATTRIBUTE_UNUSED
,
1505 int *total
, bool speed ATTRIBUTE_UNUSED
)
1508 int code
= GET_CODE (x
);
1513 if (INTVAL (x
) == 0)
1515 else if (INT_14_BITS (x
))
1532 if ((x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1533 && outer_code
!= SET
)
1540 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1542 *total
= COSTS_N_INSNS (3);
1546 /* A mode size N times larger than SImode needs O(N*N) more insns. */
1547 factor
= GET_MODE_SIZE (mode
) / 4;
1551 if (TARGET_PA_11
&& !TARGET_DISABLE_FPREGS
&& !TARGET_SOFT_FLOAT
)
1552 *total
= factor
* factor
* COSTS_N_INSNS (8);
1554 *total
= factor
* factor
* COSTS_N_INSNS (20);
1558 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1560 *total
= COSTS_N_INSNS (14);
1568 /* A mode size N times larger than SImode needs O(N*N) more insns. */
1569 factor
= GET_MODE_SIZE (mode
) / 4;
1573 *total
= factor
* factor
* COSTS_N_INSNS (60);
1576 case PLUS
: /* this includes shNadd insns */
1578 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1580 *total
= COSTS_N_INSNS (3);
1584 /* A size N times larger than UNITS_PER_WORD needs N times as
1585 many insns, taking N times as long. */
1586 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
1589 *total
= factor
* COSTS_N_INSNS (1);
1595 *total
= COSTS_N_INSNS (1);
1603 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1604 new rtx with the correct mode. */
1606 force_mode (machine_mode mode
, rtx orig
)
1608 if (mode
== GET_MODE (orig
))
1611 gcc_assert (REGNO (orig
) < FIRST_PSEUDO_REGISTER
);
1613 return gen_rtx_REG (mode
, REGNO (orig
));
1616 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1619 pa_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1621 return tls_referenced_p (x
);
1624 /* Emit insns to move operands[1] into operands[0].
1626 Return 1 if we have written out everything that needs to be done to
1627 do the move. Otherwise, return 0 and the caller will emit the move
1630 Note SCRATCH_REG may not be in the proper mode depending on how it
1631 will be used. This routine is responsible for creating a new copy
1632 of SCRATCH_REG in the proper mode. */
1635 pa_emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
1637 register rtx operand0
= operands
[0];
1638 register rtx operand1
= operands
[1];
1641 /* We can only handle indexed addresses in the destination operand
1642 of floating point stores. Thus, we need to break out indexed
1643 addresses from the destination operand. */
1644 if (GET_CODE (operand0
) == MEM
&& IS_INDEX_ADDR_P (XEXP (operand0
, 0)))
1646 gcc_assert (can_create_pseudo_p ());
1648 tem
= copy_to_mode_reg (Pmode
, XEXP (operand0
, 0));
1649 operand0
= replace_equiv_address (operand0
, tem
);
1652 /* On targets with non-equivalent space registers, break out unscaled
1653 indexed addresses from the source operand before the final CSE.
1654 We have to do this because the REG_POINTER flag is not correctly
1655 carried through various optimization passes and CSE may substitute
1656 a pseudo without the pointer set for one with the pointer set. As
1657 a result, we loose various opportunities to create insns with
1658 unscaled indexed addresses. */
1659 if (!TARGET_NO_SPACE_REGS
1660 && !cse_not_expected
1661 && GET_CODE (operand1
) == MEM
1662 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1663 && REG_P (XEXP (XEXP (operand1
, 0), 0))
1664 && REG_P (XEXP (XEXP (operand1
, 0), 1)))
1666 = replace_equiv_address (operand1
,
1667 copy_to_mode_reg (Pmode
, XEXP (operand1
, 0)));
1670 && reload_in_progress
&& GET_CODE (operand0
) == REG
1671 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1672 operand0
= reg_equiv_mem (REGNO (operand0
));
1673 else if (scratch_reg
1674 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
1675 && GET_CODE (SUBREG_REG (operand0
)) == REG
1676 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
1678 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1679 the code which tracks sets/uses for delete_output_reload. */
1680 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
1681 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
1682 SUBREG_BYTE (operand0
));
1683 operand0
= alter_subreg (&temp
, true);
1687 && reload_in_progress
&& GET_CODE (operand1
) == REG
1688 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
1689 operand1
= reg_equiv_mem (REGNO (operand1
));
1690 else if (scratch_reg
1691 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
1692 && GET_CODE (SUBREG_REG (operand1
)) == REG
1693 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
1695 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1696 the code which tracks sets/uses for delete_output_reload. */
1697 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
1698 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
1699 SUBREG_BYTE (operand1
));
1700 operand1
= alter_subreg (&temp
, true);
1703 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
1704 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
1705 != XEXP (operand0
, 0)))
1706 operand0
= replace_equiv_address (operand0
, tem
);
1708 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
1709 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
1710 != XEXP (operand1
, 0)))
1711 operand1
= replace_equiv_address (operand1
, tem
);
1713 /* Handle secondary reloads for loads/stores of FP registers from
1714 REG+D addresses where D does not fit in 5 or 14 bits, including
1715 (subreg (mem (addr))) cases, and reloads for other unsupported
1718 && FP_REG_P (operand0
)
1719 && (MEM_P (operand1
)
1720 || (GET_CODE (operand1
) == SUBREG
1721 && MEM_P (XEXP (operand1
, 0)))))
1725 if (GET_CODE (op1
) == SUBREG
)
1726 op1
= XEXP (op1
, 0);
1728 if (reg_plus_base_memory_operand (op1
, GET_MODE (op1
)))
1732 && INT_14_BITS (XEXP (XEXP (op1
, 0), 1)))
1733 && !INT_5_BITS (XEXP (XEXP (op1
, 0), 1)))
1735 /* SCRATCH_REG will hold an address and maybe the actual data.
1736 We want it in WORD_MODE regardless of what mode it was
1737 originally given to us. */
1738 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1740 /* D might not fit in 14 bits either; for such cases load D
1741 into scratch reg. */
1742 if (!INT_14_BITS (XEXP (XEXP (op1
, 0), 1)))
1744 emit_move_insn (scratch_reg
, XEXP (XEXP (op1
, 0), 1));
1745 emit_move_insn (scratch_reg
,
1746 gen_rtx_fmt_ee (GET_CODE (XEXP (op1
, 0)),
1748 XEXP (XEXP (op1
, 0), 0),
1752 emit_move_insn (scratch_reg
, XEXP (op1
, 0));
1753 op1
= replace_equiv_address (op1
, scratch_reg
);
1756 else if ((!INT14_OK_STRICT
&& symbolic_memory_operand (op1
, VOIDmode
))
1757 || IS_LO_SUM_DLT_ADDR_P (XEXP (op1
, 0))
1758 || IS_INDEX_ADDR_P (XEXP (op1
, 0)))
1760 /* Load memory address into SCRATCH_REG. */
1761 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1762 emit_move_insn (scratch_reg
, XEXP (op1
, 0));
1763 op1
= replace_equiv_address (op1
, scratch_reg
);
1765 emit_insn (gen_rtx_SET (operand0
, op1
));
1768 else if (scratch_reg
1769 && FP_REG_P (operand1
)
1770 && (MEM_P (operand0
)
1771 || (GET_CODE (operand0
) == SUBREG
1772 && MEM_P (XEXP (operand0
, 0)))))
1776 if (GET_CODE (op0
) == SUBREG
)
1777 op0
= XEXP (op0
, 0);
1779 if (reg_plus_base_memory_operand (op0
, GET_MODE (op0
)))
1783 && INT_14_BITS (XEXP (XEXP (op0
, 0), 1)))
1784 && !INT_5_BITS (XEXP (XEXP (op0
, 0), 1)))
1786 /* SCRATCH_REG will hold an address and maybe the actual data.
1787 We want it in WORD_MODE regardless of what mode it was
1788 originally given to us. */
1789 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1791 /* D might not fit in 14 bits either; for such cases load D
1792 into scratch reg. */
1793 if (!INT_14_BITS (XEXP (XEXP (op0
, 0), 1)))
1795 emit_move_insn (scratch_reg
, XEXP (XEXP (op0
, 0), 1));
1796 emit_move_insn (scratch_reg
,
1797 gen_rtx_fmt_ee (GET_CODE (XEXP (op0
, 0)),
1799 XEXP (XEXP (op0
, 0), 0),
1803 emit_move_insn (scratch_reg
, XEXP (op0
, 0));
1804 op0
= replace_equiv_address (op0
, scratch_reg
);
1807 else if ((!INT14_OK_STRICT
&& symbolic_memory_operand (op0
, VOIDmode
))
1808 || IS_LO_SUM_DLT_ADDR_P (XEXP (op0
, 0))
1809 || IS_INDEX_ADDR_P (XEXP (op0
, 0)))
1811 /* Load memory address into SCRATCH_REG. */
1812 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1813 emit_move_insn (scratch_reg
, XEXP (op0
, 0));
1814 op0
= replace_equiv_address (op0
, scratch_reg
);
1816 emit_insn (gen_rtx_SET (op0
, operand1
));
1819 /* Handle secondary reloads for loads of FP registers from constant
1820 expressions by forcing the constant into memory. For the most part,
1821 this is only necessary for SImode and DImode.
1823 Use scratch_reg to hold the address of the memory location. */
1824 else if (scratch_reg
1825 && CONSTANT_P (operand1
)
1826 && FP_REG_P (operand0
))
1828 rtx const_mem
, xoperands
[2];
1830 if (operand1
== CONST0_RTX (mode
))
1832 emit_insn (gen_rtx_SET (operand0
, operand1
));
1836 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1837 it in WORD_MODE regardless of what mode it was originally given
1839 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1841 /* Force the constant into memory and put the address of the
1842 memory location into scratch_reg. */
1843 const_mem
= force_const_mem (mode
, operand1
);
1844 xoperands
[0] = scratch_reg
;
1845 xoperands
[1] = XEXP (const_mem
, 0);
1846 pa_emit_move_sequence (xoperands
, Pmode
, 0);
1848 /* Now load the destination register. */
1849 emit_insn (gen_rtx_SET (operand0
,
1850 replace_equiv_address (const_mem
, scratch_reg
)));
1853 /* Handle secondary reloads for SAR. These occur when trying to load
1854 the SAR from memory or a constant. */
1855 else if (scratch_reg
1856 && GET_CODE (operand0
) == REG
1857 && REGNO (operand0
) < FIRST_PSEUDO_REGISTER
1858 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
1859 && (GET_CODE (operand1
) == MEM
|| GET_CODE (operand1
) == CONST_INT
))
1861 /* D might not fit in 14 bits either; for such cases load D into
1863 if (GET_CODE (operand1
) == MEM
1864 && !memory_address_p (GET_MODE (operand0
), XEXP (operand1
, 0)))
1866 /* We are reloading the address into the scratch register, so we
1867 want to make sure the scratch register is a full register. */
1868 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1870 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1871 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
,
1874 XEXP (XEXP (operand1
, 0),
1878 /* Now we are going to load the scratch register from memory,
1879 we want to load it in the same width as the original MEM,
1880 which must be the same as the width of the ultimate destination,
1882 scratch_reg
= force_mode (GET_MODE (operand0
), scratch_reg
);
1884 emit_move_insn (scratch_reg
,
1885 replace_equiv_address (operand1
, scratch_reg
));
1889 /* We want to load the scratch register using the same mode as
1890 the ultimate destination. */
1891 scratch_reg
= force_mode (GET_MODE (operand0
), scratch_reg
);
1893 emit_move_insn (scratch_reg
, operand1
);
1896 /* And emit the insn to set the ultimate destination. We know that
1897 the scratch register has the same mode as the destination at this
1899 emit_move_insn (operand0
, scratch_reg
);
1903 /* Handle the most common case: storing into a register. */
1904 if (register_operand (operand0
, mode
))
1906 /* Legitimize TLS symbol references. This happens for references
1907 that aren't a legitimate constant. */
1908 if (PA_SYMBOL_REF_TLS_P (operand1
))
1909 operand1
= legitimize_tls_address (operand1
);
1911 if (register_operand (operand1
, mode
)
1912 || (GET_CODE (operand1
) == CONST_INT
1913 && pa_cint_ok_for_move (UINTVAL (operand1
)))
1914 || (operand1
== CONST0_RTX (mode
))
1915 || (GET_CODE (operand1
) == HIGH
1916 && !symbolic_operand (XEXP (operand1
, 0), VOIDmode
))
1917 /* Only `general_operands' can come here, so MEM is ok. */
1918 || GET_CODE (operand1
) == MEM
)
1920 /* Various sets are created during RTL generation which don't
1921 have the REG_POINTER flag correctly set. After the CSE pass,
1922 instruction recognition can fail if we don't consistently
1923 set this flag when performing register copies. This should
1924 also improve the opportunities for creating insns that use
1925 unscaled indexing. */
1926 if (REG_P (operand0
) && REG_P (operand1
))
1928 if (REG_POINTER (operand1
)
1929 && !REG_POINTER (operand0
)
1930 && !HARD_REGISTER_P (operand0
))
1931 copy_reg_pointer (operand0
, operand1
);
1934 /* When MEMs are broken out, the REG_POINTER flag doesn't
1935 get set. In some cases, we can set the REG_POINTER flag
1936 from the declaration for the MEM. */
1937 if (REG_P (operand0
)
1938 && GET_CODE (operand1
) == MEM
1939 && !REG_POINTER (operand0
))
1941 tree decl
= MEM_EXPR (operand1
);
1943 /* Set the register pointer flag and register alignment
1944 if the declaration for this memory reference is a
1950 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1952 if (TREE_CODE (decl
) == COMPONENT_REF
)
1953 decl
= TREE_OPERAND (decl
, 1);
1955 type
= TREE_TYPE (decl
);
1956 type
= strip_array_types (type
);
1958 if (POINTER_TYPE_P (type
))
1959 mark_reg_pointer (operand0
, BITS_PER_UNIT
);
1963 emit_insn (gen_rtx_SET (operand0
, operand1
));
1967 else if (GET_CODE (operand0
) == MEM
)
1969 if (mode
== DFmode
&& operand1
== CONST0_RTX (mode
)
1970 && !(reload_in_progress
|| reload_completed
))
1972 rtx temp
= gen_reg_rtx (DFmode
);
1974 emit_insn (gen_rtx_SET (temp
, operand1
));
1975 emit_insn (gen_rtx_SET (operand0
, temp
));
1978 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
1980 /* Run this case quickly. */
1981 emit_insn (gen_rtx_SET (operand0
, operand1
));
1984 if (! (reload_in_progress
|| reload_completed
))
1986 operands
[0] = validize_mem (operand0
);
1987 operands
[1] = operand1
= force_reg (mode
, operand1
);
1991 /* Simplify the source if we need to.
1992 Note we do have to handle function labels here, even though we do
1993 not consider them legitimate constants. Loop optimizations can
1994 call the emit_move_xxx with one as a source. */
1995 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1996 || (GET_CODE (operand1
) == HIGH
1997 && symbolic_operand (XEXP (operand1
, 0), mode
))
1998 || function_label_operand (operand1
, VOIDmode
)
1999 || tls_referenced_p (operand1
))
2003 if (GET_CODE (operand1
) == HIGH
)
2006 operand1
= XEXP (operand1
, 0);
2008 if (symbolic_operand (operand1
, mode
))
2010 /* Argh. The assembler and linker can't handle arithmetic
2013 So we force the plabel into memory, load operand0 from
2014 the memory location, then add in the constant part. */
2015 if ((GET_CODE (operand1
) == CONST
2016 && GET_CODE (XEXP (operand1
, 0)) == PLUS
2017 && function_label_operand (XEXP (XEXP (operand1
, 0), 0),
2019 || function_label_operand (operand1
, VOIDmode
))
2021 rtx temp
, const_part
;
2023 /* Figure out what (if any) scratch register to use. */
2024 if (reload_in_progress
|| reload_completed
)
2026 scratch_reg
= scratch_reg
? scratch_reg
: operand0
;
2027 /* SCRATCH_REG will hold an address and maybe the actual
2028 data. We want it in WORD_MODE regardless of what mode it
2029 was originally given to us. */
2030 scratch_reg
= force_mode (word_mode
, scratch_reg
);
2033 scratch_reg
= gen_reg_rtx (Pmode
);
2035 if (GET_CODE (operand1
) == CONST
)
2037 /* Save away the constant part of the expression. */
2038 const_part
= XEXP (XEXP (operand1
, 0), 1);
2039 gcc_assert (GET_CODE (const_part
) == CONST_INT
);
2041 /* Force the function label into memory. */
2042 temp
= force_const_mem (mode
, XEXP (XEXP (operand1
, 0), 0));
2046 /* No constant part. */
2047 const_part
= NULL_RTX
;
2049 /* Force the function label into memory. */
2050 temp
= force_const_mem (mode
, operand1
);
2054 /* Get the address of the memory location. PIC-ify it if
2056 temp
= XEXP (temp
, 0);
2058 temp
= legitimize_pic_address (temp
, mode
, scratch_reg
);
2060 /* Put the address of the memory location into our destination
2063 pa_emit_move_sequence (operands
, mode
, scratch_reg
);
2065 /* Now load from the memory location into our destination
2067 operands
[1] = gen_rtx_MEM (Pmode
, operands
[0]);
2068 pa_emit_move_sequence (operands
, mode
, scratch_reg
);
2070 /* And add back in the constant part. */
2071 if (const_part
!= NULL_RTX
)
2072 expand_inc (operand0
, const_part
);
2082 if (reload_in_progress
|| reload_completed
)
2084 temp
= scratch_reg
? scratch_reg
: operand0
;
2085 /* TEMP will hold an address and maybe the actual
2086 data. We want it in WORD_MODE regardless of what mode it
2087 was originally given to us. */
2088 temp
= force_mode (word_mode
, temp
);
2091 temp
= gen_reg_rtx (Pmode
);
2093 /* Force (const (plus (symbol) (const_int))) to memory
2094 if the const_int will not fit in 14 bits. Although
2095 this requires a relocation, the instruction sequence
2096 needed to load the value is shorter. */
2097 if (GET_CODE (operand1
) == CONST
2098 && GET_CODE (XEXP (operand1
, 0)) == PLUS
2099 && GET_CODE (XEXP (XEXP (operand1
, 0), 1)) == CONST_INT
2100 && !INT_14_BITS (XEXP (XEXP (operand1
, 0), 1)))
2102 rtx x
, m
= force_const_mem (mode
, operand1
);
2104 x
= legitimize_pic_address (XEXP (m
, 0), mode
, temp
);
2105 x
= replace_equiv_address (m
, x
);
2106 insn
= emit_move_insn (operand0
, x
);
2110 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
2111 if (REG_P (operand0
) && REG_P (operands
[1]))
2112 copy_reg_pointer (operand0
, operands
[1]);
2113 insn
= emit_move_insn (operand0
, operands
[1]);
2116 /* Put a REG_EQUAL note on this insn. */
2117 set_unique_reg_note (insn
, REG_EQUAL
, operand1
);
2119 /* On the HPPA, references to data space are supposed to use dp,
2120 register 27, but showing it in the RTL inhibits various cse
2121 and loop optimizations. */
2126 if (reload_in_progress
|| reload_completed
)
2128 temp
= scratch_reg
? scratch_reg
: operand0
;
2129 /* TEMP will hold an address and maybe the actual
2130 data. We want it in WORD_MODE regardless of what mode it
2131 was originally given to us. */
2132 temp
= force_mode (word_mode
, temp
);
2135 temp
= gen_reg_rtx (mode
);
2137 /* Loading a SYMBOL_REF into a register makes that register
2138 safe to be used as the base in an indexed address.
2140 Don't mark hard registers though. That loses. */
2141 if (GET_CODE (operand0
) == REG
2142 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2143 mark_reg_pointer (operand0
, BITS_PER_UNIT
);
2144 if (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
)
2145 mark_reg_pointer (temp
, BITS_PER_UNIT
);
2148 set
= gen_rtx_SET (operand0
, temp
);
2150 set
= gen_rtx_SET (operand0
,
2151 gen_rtx_LO_SUM (mode
, temp
, operand1
));
2153 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, operand1
)));
2159 else if (tls_referenced_p (operand1
))
2164 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
2166 addend
= XEXP (XEXP (tmp
, 0), 1);
2167 tmp
= XEXP (XEXP (tmp
, 0), 0);
2170 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
2171 tmp
= legitimize_tls_address (tmp
);
2174 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
2175 tmp
= force_operand (tmp
, operands
[0]);
2179 else if (GET_CODE (operand1
) != CONST_INT
2180 || !pa_cint_ok_for_move (UINTVAL (operand1
)))
2185 HOST_WIDE_INT value
= 0;
2186 HOST_WIDE_INT insv
= 0;
2189 if (GET_CODE (operand1
) == CONST_INT
)
2190 value
= INTVAL (operand1
);
2193 && GET_CODE (operand1
) == CONST_INT
2194 && HOST_BITS_PER_WIDE_INT
> 32
2195 && GET_MODE_BITSIZE (GET_MODE (operand0
)) > 32)
2199 /* Extract the low order 32 bits of the value and sign extend.
2200 If the new value is the same as the original value, we can
2201 can use the original value as-is. If the new value is
2202 different, we use it and insert the most-significant 32-bits
2203 of the original value into the final result. */
2204 nval
= ((value
& (((HOST_WIDE_INT
) 2 << 31) - 1))
2205 ^ ((HOST_WIDE_INT
) 1 << 31)) - ((HOST_WIDE_INT
) 1 << 31);
2208 #if HOST_BITS_PER_WIDE_INT > 32
2209 insv
= value
>= 0 ? value
>> 32 : ~(~value
>> 32);
2213 operand1
= GEN_INT (nval
);
2217 if (reload_in_progress
|| reload_completed
)
2218 temp
= scratch_reg
? scratch_reg
: operand0
;
2220 temp
= gen_reg_rtx (mode
);
2222 /* We don't directly split DImode constants on 32-bit targets
2223 because PLUS uses an 11-bit immediate and the insn sequence
2224 generated is not as efficient as the one using HIGH/LO_SUM. */
2225 if (GET_CODE (operand1
) == CONST_INT
2226 && GET_MODE_BITSIZE (mode
) <= BITS_PER_WORD
2227 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2230 /* Directly break constant into high and low parts. This
2231 provides better optimization opportunities because various
2232 passes recognize constants split with PLUS but not LO_SUM.
2233 We use a 14-bit signed low part except when the addition
2234 of 0x4000 to the high part might change the sign of the
2236 HOST_WIDE_INT low
= value
& 0x3fff;
2237 HOST_WIDE_INT high
= value
& ~ 0x3fff;
2241 if (high
== 0x7fffc000 || (mode
== HImode
&& high
== 0x4000))
2249 emit_insn (gen_rtx_SET (temp
, GEN_INT (high
)));
2250 operands
[1] = gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2254 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, operand1
)));
2255 operands
[1] = gen_rtx_LO_SUM (mode
, temp
, operand1
);
2258 insn
= emit_move_insn (operands
[0], operands
[1]);
2260 /* Now insert the most significant 32 bits of the value
2261 into the register. When we don't have a second register
2262 available, it could take up to nine instructions to load
2263 a 64-bit integer constant. Prior to reload, we force
2264 constants that would take more than three instructions
2265 to load to the constant pool. During and after reload,
2266 we have to handle all possible values. */
2269 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2270 register and the value to be inserted is outside the
2271 range that can be loaded with three depdi instructions. */
2272 if (temp
!= operand0
&& (insv
>= 16384 || insv
< -16384))
2274 operand1
= GEN_INT (insv
);
2276 emit_insn (gen_rtx_SET (temp
,
2277 gen_rtx_HIGH (mode
, operand1
)));
2278 emit_move_insn (temp
, gen_rtx_LO_SUM (mode
, temp
, operand1
));
2280 insn
= emit_insn (gen_insvdi (operand0
, GEN_INT (32),
2283 insn
= emit_insn (gen_insvsi (operand0
, GEN_INT (32),
2288 int len
= 5, pos
= 27;
2290 /* Insert the bits using the depdi instruction. */
2293 HOST_WIDE_INT v5
= ((insv
& 31) ^ 16) - 16;
2294 HOST_WIDE_INT sign
= v5
< 0;
2296 /* Left extend the insertion. */
2297 insv
= (insv
>= 0 ? insv
>> len
: ~(~insv
>> len
));
2298 while (pos
> 0 && (insv
& 1) == sign
)
2300 insv
= (insv
>= 0 ? insv
>> 1 : ~(~insv
>> 1));
2306 insn
= emit_insn (gen_insvdi (operand0
,
2311 insn
= emit_insn (gen_insvsi (operand0
,
2316 len
= pos
> 0 && pos
< 5 ? pos
: 5;
2322 set_unique_reg_note (insn
, REG_EQUAL
, op1
);
2327 /* Now have insn-emit do whatever it normally does. */
2331 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2332 it will need a link/runtime reloc). */
2335 pa_reloc_needed (tree exp
)
2339 switch (TREE_CODE (exp
))
2344 case POINTER_PLUS_EXPR
:
2347 reloc
= pa_reloc_needed (TREE_OPERAND (exp
, 0));
2348 reloc
|= pa_reloc_needed (TREE_OPERAND (exp
, 1));
2352 case NON_LVALUE_EXPR
:
2353 reloc
= pa_reloc_needed (TREE_OPERAND (exp
, 0));
2359 unsigned HOST_WIDE_INT ix
;
2361 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp
), ix
, value
)
2363 reloc
|= pa_reloc_needed (value
);
2377 /* Return the best assembler insn template
2378 for moving operands[1] into operands[0] as a fullword. */
2380 pa_singlemove_string (rtx
*operands
)
2382 HOST_WIDE_INT intval
;
2384 if (GET_CODE (operands
[0]) == MEM
)
2385 return "stw %r1,%0";
2386 if (GET_CODE (operands
[1]) == MEM
)
2388 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2392 gcc_assert (GET_MODE (operands
[1]) == SFmode
);
2394 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2396 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands
[1]), i
);
2398 operands
[1] = GEN_INT (i
);
2399 /* Fall through to CONST_INT case. */
2401 if (GET_CODE (operands
[1]) == CONST_INT
)
2403 intval
= INTVAL (operands
[1]);
2405 if (VAL_14_BITS_P (intval
))
2407 else if ((intval
& 0x7ff) == 0)
2408 return "ldil L'%1,%0";
2409 else if (pa_zdepi_cint_p (intval
))
2410 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2412 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2414 return "copy %1,%0";
2418 /* Compute position (in OP[1]) and width (in OP[2])
2419 useful for copying IMM to a register using the zdepi
2420 instructions. Store the immediate value to insert in OP[0]. */
2422 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm
, unsigned *op
)
2426 /* Find the least significant set bit in IMM. */
2427 for (lsb
= 0; lsb
< 32; lsb
++)
2434 /* Choose variants based on *sign* of the 5-bit field. */
2435 if ((imm
& 0x10) == 0)
2436 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
2439 /* Find the width of the bitstring in IMM. */
2440 for (len
= 5; len
< 32 - lsb
; len
++)
2442 if ((imm
& ((unsigned HOST_WIDE_INT
) 1 << len
)) == 0)
2446 /* Sign extend IMM as a 5-bit value. */
2447 imm
= (imm
& 0xf) - 0x10;
2455 /* Compute position (in OP[1]) and width (in OP[2])
2456 useful for copying IMM to a register using the depdi,z
2457 instructions. Store the immediate value to insert in OP[0]. */
2460 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm
, unsigned *op
)
2462 int lsb
, len
, maxlen
;
2464 maxlen
= MIN (HOST_BITS_PER_WIDE_INT
, 64);
2466 /* Find the least significant set bit in IMM. */
2467 for (lsb
= 0; lsb
< maxlen
; lsb
++)
2474 /* Choose variants based on *sign* of the 5-bit field. */
2475 if ((imm
& 0x10) == 0)
2476 len
= (lsb
<= maxlen
- 4) ? 4 : maxlen
- lsb
;
2479 /* Find the width of the bitstring in IMM. */
2480 for (len
= 5; len
< maxlen
- lsb
; len
++)
2482 if ((imm
& ((unsigned HOST_WIDE_INT
) 1 << len
)) == 0)
2486 /* Extend length if host is narrow and IMM is negative. */
2487 if (HOST_BITS_PER_WIDE_INT
== 32 && len
== maxlen
- lsb
)
2490 /* Sign extend IMM as a 5-bit value. */
2491 imm
= (imm
& 0xf) - 0x10;
2499 /* Output assembler code to perform a doubleword move insn
2500 with operands OPERANDS. */
2503 pa_output_move_double (rtx
*operands
)
2505 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
2507 rtx addreg0
= 0, addreg1
= 0;
2510 /* First classify both operands. */
2512 if (REG_P (operands
[0]))
2514 else if (offsettable_memref_p (operands
[0]))
2516 else if (GET_CODE (operands
[0]) == MEM
)
2521 if (REG_P (operands
[1]))
2523 else if (CONSTANT_P (operands
[1]))
2525 else if (offsettable_memref_p (operands
[1]))
2527 else if (GET_CODE (operands
[1]) == MEM
)
2532 /* Check for the cases that the operand constraints are not
2533 supposed to allow to happen. */
2534 gcc_assert (optype0
== REGOP
|| optype1
== REGOP
);
2536 /* Handle copies between general and floating registers. */
2538 if (optype0
== REGOP
&& optype1
== REGOP
2539 && FP_REG_P (operands
[0]) ^ FP_REG_P (operands
[1]))
2541 if (FP_REG_P (operands
[0]))
2543 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands
);
2544 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands
);
2545 return "{fldds|fldd} -16(%%sp),%0";
2549 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands
);
2550 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands
);
2551 return "{ldws|ldw} -12(%%sp),%R0";
2555 /* Handle auto decrementing and incrementing loads and stores
2556 specifically, since the structure of the function doesn't work
2557 for them without major modification. Do it better when we learn
2558 this port about the general inc/dec addressing of PA.
2559 (This was written by tege. Chide him if it doesn't work.) */
2561 if (optype0
== MEMOP
)
2563 /* We have to output the address syntax ourselves, since print_operand
2564 doesn't deal with the addresses we want to use. Fix this later. */
2566 rtx addr
= XEXP (operands
[0], 0);
2567 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
2569 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
2571 operands
[0] = XEXP (addr
, 0);
2572 gcc_assert (GET_CODE (operands
[1]) == REG
2573 && GET_CODE (operands
[0]) == REG
);
2575 gcc_assert (!reg_overlap_mentioned_p (high_reg
, addr
));
2577 /* No overlap between high target register and address
2578 register. (We do this in a non-obvious way to
2579 save a register file writeback) */
2580 if (GET_CODE (addr
) == POST_INC
)
2581 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2582 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2584 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
2586 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
2588 operands
[0] = XEXP (addr
, 0);
2589 gcc_assert (GET_CODE (operands
[1]) == REG
2590 && GET_CODE (operands
[0]) == REG
);
2592 gcc_assert (!reg_overlap_mentioned_p (high_reg
, addr
));
2593 /* No overlap between high target register and address
2594 register. (We do this in a non-obvious way to save a
2595 register file writeback) */
2596 if (GET_CODE (addr
) == PRE_INC
)
2597 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2598 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2601 if (optype1
== MEMOP
)
2603 /* We have to output the address syntax ourselves, since print_operand
2604 doesn't deal with the addresses we want to use. Fix this later. */
2606 rtx addr
= XEXP (operands
[1], 0);
2607 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
2609 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
2611 operands
[1] = XEXP (addr
, 0);
2612 gcc_assert (GET_CODE (operands
[0]) == REG
2613 && GET_CODE (operands
[1]) == REG
);
2615 if (!reg_overlap_mentioned_p (high_reg
, addr
))
2617 /* No overlap between high target register and address
2618 register. (We do this in a non-obvious way to
2619 save a register file writeback) */
2620 if (GET_CODE (addr
) == POST_INC
)
2621 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2622 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2626 /* This is an undefined situation. We should load into the
2627 address register *and* update that register. Probably
2628 we don't need to handle this at all. */
2629 if (GET_CODE (addr
) == POST_INC
)
2630 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2631 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2634 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
2636 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
2638 operands
[1] = XEXP (addr
, 0);
2639 gcc_assert (GET_CODE (operands
[0]) == REG
2640 && GET_CODE (operands
[1]) == REG
);
2642 if (!reg_overlap_mentioned_p (high_reg
, addr
))
2644 /* No overlap between high target register and address
2645 register. (We do this in a non-obvious way to
2646 save a register file writeback) */
2647 if (GET_CODE (addr
) == PRE_INC
)
2648 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2649 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2653 /* This is an undefined situation. We should load into the
2654 address register *and* update that register. Probably
2655 we don't need to handle this at all. */
2656 if (GET_CODE (addr
) == PRE_INC
)
2657 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2658 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2661 else if (GET_CODE (addr
) == PLUS
2662 && GET_CODE (XEXP (addr
, 0)) == MULT
)
2666 /* Load address into left half of destination register. */
2667 xoperands
[0] = gen_rtx_SUBREG (SImode
, operands
[0], 0);
2668 xoperands
[1] = XEXP (addr
, 1);
2669 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
2670 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
2671 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2673 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2675 else if (GET_CODE (addr
) == PLUS
2676 && REG_P (XEXP (addr
, 0))
2677 && REG_P (XEXP (addr
, 1)))
2681 /* Load address into left half of destination register. */
2682 xoperands
[0] = gen_rtx_SUBREG (SImode
, operands
[0], 0);
2683 xoperands
[1] = XEXP (addr
, 0);
2684 xoperands
[2] = XEXP (addr
, 1);
2685 output_asm_insn ("{addl|add,l} %1,%2,%0",
2687 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2691 /* If an operand is an unoffsettable memory ref, find a register
2692 we can increment temporarily to make it refer to the second word. */
2694 if (optype0
== MEMOP
)
2695 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2697 if (optype1
== MEMOP
)
2698 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2700 /* Ok, we can do one word at a time.
2701 Normally we do the low-numbered word first.
2703 In either case, set up in LATEHALF the operands to use
2704 for the high-numbered word and in some cases alter the
2705 operands in OPERANDS to be suitable for the low-numbered word. */
2707 if (optype0
== REGOP
)
2708 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2709 else if (optype0
== OFFSOP
)
2710 latehalf
[0] = adjust_address_nv (operands
[0], SImode
, 4);
2712 latehalf
[0] = operands
[0];
2714 if (optype1
== REGOP
)
2715 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2716 else if (optype1
== OFFSOP
)
2717 latehalf
[1] = adjust_address_nv (operands
[1], SImode
, 4);
2718 else if (optype1
== CNSTOP
)
2720 if (GET_CODE (operands
[1]) == HIGH
)
2722 operands
[1] = XEXP (operands
[1], 0);
2725 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2728 latehalf
[1] = operands
[1];
2730 /* If the first move would clobber the source of the second one,
2731 do them in the other order.
2733 This can happen in two cases:
2735 mem -> register where the first half of the destination register
2736 is the same register used in the memory's address. Reload
2737 can create such insns.
2739 mem in this case will be either register indirect or register
2740 indirect plus a valid offset.
2742 register -> register move where REGNO(dst) == REGNO(src + 1)
2743 someone (Tim/Tege?) claimed this can happen for parameter loads.
2745 Handle mem -> register case first. */
2746 if (optype0
== REGOP
2747 && (optype1
== MEMOP
|| optype1
== OFFSOP
)
2748 && refers_to_regno_p (REGNO (operands
[0]), operands
[1]))
2750 /* Do the late half first. */
2752 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2753 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2757 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2758 return pa_singlemove_string (operands
);
2761 /* Now handle register -> register case. */
2762 if (optype0
== REGOP
&& optype1
== REGOP
2763 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
2765 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2766 return pa_singlemove_string (operands
);
2769 /* Normal case: do the two words, low-numbered first. */
2771 output_asm_insn (pa_singlemove_string (operands
), operands
);
2773 /* Make any unoffsettable addresses point at high-numbered word. */
2775 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
2777 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2779 /* Do high-numbered word. */
2781 output_asm_insn ("ldil L'%1,%0", latehalf
);
2783 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2785 /* Undo the adds we just did. */
2787 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
2789 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2795 pa_output_fp_move_double (rtx
*operands
)
2797 if (FP_REG_P (operands
[0]))
2799 if (FP_REG_P (operands
[1])
2800 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
2801 output_asm_insn ("fcpy,dbl %f1,%0", operands
);
2803 output_asm_insn ("fldd%F1 %1,%0", operands
);
2805 else if (FP_REG_P (operands
[1]))
2807 output_asm_insn ("fstd%F0 %1,%0", operands
);
2813 gcc_assert (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])));
2815 /* This is a pain. You have to be prepared to deal with an
2816 arbitrary address here including pre/post increment/decrement.
2818 so avoid this in the MD. */
2819 gcc_assert (GET_CODE (operands
[0]) == REG
);
2821 xoperands
[1] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2822 xoperands
[0] = operands
[0];
2823 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
2828 /* Return a REG that occurs in ADDR with coefficient 1.
2829 ADDR can be effectively incremented by incrementing REG. */
2832 find_addr_reg (rtx addr
)
2834 while (GET_CODE (addr
) == PLUS
)
2836 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2837 addr
= XEXP (addr
, 0);
2838 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2839 addr
= XEXP (addr
, 1);
2840 else if (CONSTANT_P (XEXP (addr
, 0)))
2841 addr
= XEXP (addr
, 1);
2842 else if (CONSTANT_P (XEXP (addr
, 1)))
2843 addr
= XEXP (addr
, 0);
2847 gcc_assert (GET_CODE (addr
) == REG
);
2851 /* Emit code to perform a block move.
2853 OPERANDS[0] is the destination pointer as a REG, clobbered.
2854 OPERANDS[1] is the source pointer as a REG, clobbered.
2855 OPERANDS[2] is a register for temporary storage.
2856 OPERANDS[3] is a register for temporary storage.
2857 OPERANDS[4] is the size as a CONST_INT
2858 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2859 OPERANDS[6] is another temporary register. */
2862 pa_output_block_move (rtx
*operands
, int size_is_constant ATTRIBUTE_UNUSED
)
2864 int align
= INTVAL (operands
[5]);
2865 unsigned long n_bytes
= INTVAL (operands
[4]);
2867 /* We can't move more than a word at a time because the PA
2868 has no longer integer move insns. (Could use fp mem ops?) */
2869 if (align
> (TARGET_64BIT
? 8 : 4))
2870 align
= (TARGET_64BIT
? 8 : 4);
2872 /* Note that we know each loop below will execute at least twice
2873 (else we would have open-coded the copy). */
2877 /* Pre-adjust the loop counter. */
2878 operands
[4] = GEN_INT (n_bytes
- 16);
2879 output_asm_insn ("ldi %4,%2", operands
);
2882 output_asm_insn ("ldd,ma 8(%1),%3", operands
);
2883 output_asm_insn ("ldd,ma 8(%1),%6", operands
);
2884 output_asm_insn ("std,ma %3,8(%0)", operands
);
2885 output_asm_insn ("addib,>= -16,%2,.-12", operands
);
2886 output_asm_insn ("std,ma %6,8(%0)", operands
);
2888 /* Handle the residual. There could be up to 7 bytes of
2889 residual to copy! */
2890 if (n_bytes
% 16 != 0)
2892 operands
[4] = GEN_INT (n_bytes
% 8);
2893 if (n_bytes
% 16 >= 8)
2894 output_asm_insn ("ldd,ma 8(%1),%3", operands
);
2895 if (n_bytes
% 8 != 0)
2896 output_asm_insn ("ldd 0(%1),%6", operands
);
2897 if (n_bytes
% 16 >= 8)
2898 output_asm_insn ("std,ma %3,8(%0)", operands
);
2899 if (n_bytes
% 8 != 0)
2900 output_asm_insn ("stdby,e %6,%4(%0)", operands
);
2905 /* Pre-adjust the loop counter. */
2906 operands
[4] = GEN_INT (n_bytes
- 8);
2907 output_asm_insn ("ldi %4,%2", operands
);
2910 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2911 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands
);
2912 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2913 output_asm_insn ("addib,>= -8,%2,.-12", operands
);
2914 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands
);
2916 /* Handle the residual. There could be up to 7 bytes of
2917 residual to copy! */
2918 if (n_bytes
% 8 != 0)
2920 operands
[4] = GEN_INT (n_bytes
% 4);
2921 if (n_bytes
% 8 >= 4)
2922 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2923 if (n_bytes
% 4 != 0)
2924 output_asm_insn ("ldw 0(%1),%6", operands
);
2925 if (n_bytes
% 8 >= 4)
2926 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2927 if (n_bytes
% 4 != 0)
2928 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands
);
2933 /* Pre-adjust the loop counter. */
2934 operands
[4] = GEN_INT (n_bytes
- 4);
2935 output_asm_insn ("ldi %4,%2", operands
);
2938 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2939 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands
);
2940 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2941 output_asm_insn ("addib,>= -4,%2,.-12", operands
);
2942 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands
);
2944 /* Handle the residual. */
2945 if (n_bytes
% 4 != 0)
2947 if (n_bytes
% 4 >= 2)
2948 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2949 if (n_bytes
% 2 != 0)
2950 output_asm_insn ("ldb 0(%1),%6", operands
);
2951 if (n_bytes
% 4 >= 2)
2952 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2953 if (n_bytes
% 2 != 0)
2954 output_asm_insn ("stb %6,0(%0)", operands
);
2959 /* Pre-adjust the loop counter. */
2960 operands
[4] = GEN_INT (n_bytes
- 2);
2961 output_asm_insn ("ldi %4,%2", operands
);
2964 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands
);
2965 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands
);
2966 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands
);
2967 output_asm_insn ("addib,>= -2,%2,.-12", operands
);
2968 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands
);
2970 /* Handle the residual. */
2971 if (n_bytes
% 2 != 0)
2973 output_asm_insn ("ldb 0(%1),%3", operands
);
2974 output_asm_insn ("stb %3,0(%0)", operands
);
2983 /* Count the number of insns necessary to handle this block move.
2985 Basic structure is the same as emit_block_move, except that we
2986 count insns rather than emit them. */
2989 compute_movmem_length (rtx_insn
*insn
)
2991 rtx pat
= PATTERN (insn
);
2992 unsigned int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 7), 0));
2993 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
2994 unsigned int n_insns
= 0;
2996 /* We can't move more than four bytes at a time because the PA
2997 has no longer integer move insns. (Could use fp mem ops?) */
2998 if (align
> (TARGET_64BIT
? 8 : 4))
2999 align
= (TARGET_64BIT
? 8 : 4);
3001 /* The basic copying loop. */
3005 if (n_bytes
% (2 * align
) != 0)
3007 if ((n_bytes
% (2 * align
)) >= align
)
3010 if ((n_bytes
% align
) != 0)
3014 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3018 /* Emit code to perform a block clear.
3020 OPERANDS[0] is the destination pointer as a REG, clobbered.
3021 OPERANDS[1] is a register for temporary storage.
3022 OPERANDS[2] is the size as a CONST_INT
3023 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
3026 pa_output_block_clear (rtx
*operands
, int size_is_constant ATTRIBUTE_UNUSED
)
3028 int align
= INTVAL (operands
[3]);
3029 unsigned long n_bytes
= INTVAL (operands
[2]);
3031 /* We can't clear more than a word at a time because the PA
3032 has no longer integer move insns. */
3033 if (align
> (TARGET_64BIT
? 8 : 4))
3034 align
= (TARGET_64BIT
? 8 : 4);
3036 /* Note that we know each loop below will execute at least twice
3037 (else we would have open-coded the copy). */
3041 /* Pre-adjust the loop counter. */
3042 operands
[2] = GEN_INT (n_bytes
- 16);
3043 output_asm_insn ("ldi %2,%1", operands
);
3046 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
3047 output_asm_insn ("addib,>= -16,%1,.-4", operands
);
3048 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
3050 /* Handle the residual. There could be up to 7 bytes of
3051 residual to copy! */
3052 if (n_bytes
% 16 != 0)
3054 operands
[2] = GEN_INT (n_bytes
% 8);
3055 if (n_bytes
% 16 >= 8)
3056 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
3057 if (n_bytes
% 8 != 0)
3058 output_asm_insn ("stdby,e %%r0,%2(%0)", operands
);
3063 /* Pre-adjust the loop counter. */
3064 operands
[2] = GEN_INT (n_bytes
- 8);
3065 output_asm_insn ("ldi %2,%1", operands
);
3068 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
3069 output_asm_insn ("addib,>= -8,%1,.-4", operands
);
3070 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
3072 /* Handle the residual. There could be up to 7 bytes of
3073 residual to copy! */
3074 if (n_bytes
% 8 != 0)
3076 operands
[2] = GEN_INT (n_bytes
% 4);
3077 if (n_bytes
% 8 >= 4)
3078 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
3079 if (n_bytes
% 4 != 0)
3080 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands
);
3085 /* Pre-adjust the loop counter. */
3086 operands
[2] = GEN_INT (n_bytes
- 4);
3087 output_asm_insn ("ldi %2,%1", operands
);
3090 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3091 output_asm_insn ("addib,>= -4,%1,.-4", operands
);
3092 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3094 /* Handle the residual. */
3095 if (n_bytes
% 4 != 0)
3097 if (n_bytes
% 4 >= 2)
3098 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3099 if (n_bytes
% 2 != 0)
3100 output_asm_insn ("stb %%r0,0(%0)", operands
);
3105 /* Pre-adjust the loop counter. */
3106 operands
[2] = GEN_INT (n_bytes
- 2);
3107 output_asm_insn ("ldi %2,%1", operands
);
3110 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands
);
3111 output_asm_insn ("addib,>= -2,%1,.-4", operands
);
3112 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands
);
3114 /* Handle the residual. */
3115 if (n_bytes
% 2 != 0)
3116 output_asm_insn ("stb %%r0,0(%0)", operands
);
3125 /* Count the number of insns necessary to handle this block move.
3127 Basic structure is the same as emit_block_move, except that we
3128 count insns rather than emit them. */
3131 compute_clrmem_length (rtx_insn
*insn
)
3133 rtx pat
= PATTERN (insn
);
3134 unsigned int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 4), 0));
3135 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 3), 0));
3136 unsigned int n_insns
= 0;
3138 /* We can't clear more than a word at a time because the PA
3139 has no longer integer move insns. */
3140 if (align
> (TARGET_64BIT
? 8 : 4))
3141 align
= (TARGET_64BIT
? 8 : 4);
3143 /* The basic loop. */
3147 if (n_bytes
% (2 * align
) != 0)
3149 if ((n_bytes
% (2 * align
)) >= align
)
3152 if ((n_bytes
% align
) != 0)
3156 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3162 pa_output_and (rtx
*operands
)
3164 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
3166 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3167 int ls0
, ls1
, ms0
, p
, len
;
3169 for (ls0
= 0; ls0
< 32; ls0
++)
3170 if ((mask
& (1 << ls0
)) == 0)
3173 for (ls1
= ls0
; ls1
< 32; ls1
++)
3174 if ((mask
& (1 << ls1
)) != 0)
3177 for (ms0
= ls1
; ms0
< 32; ms0
++)
3178 if ((mask
& (1 << ms0
)) == 0)
3181 gcc_assert (ms0
== 32);
3189 operands
[2] = GEN_INT (len
);
3190 return "{extru|extrw,u} %1,31,%2,%0";
3194 /* We could use this `depi' for the case above as well, but `depi'
3195 requires one more register file access than an `extru'. */
3200 operands
[2] = GEN_INT (p
);
3201 operands
[3] = GEN_INT (len
);
3202 return "{depi|depwi} 0,%2,%3,%0";
3206 return "and %1,%2,%0";
3209 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3210 storing the result in operands[0]. */
3212 pa_output_64bit_and (rtx
*operands
)
3214 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
3216 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3217 int ls0
, ls1
, ms0
, p
, len
;
3219 for (ls0
= 0; ls0
< HOST_BITS_PER_WIDE_INT
; ls0
++)
3220 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls0
)) == 0)
3223 for (ls1
= ls0
; ls1
< HOST_BITS_PER_WIDE_INT
; ls1
++)
3224 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls1
)) != 0)
3227 for (ms0
= ls1
; ms0
< HOST_BITS_PER_WIDE_INT
; ms0
++)
3228 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ms0
)) == 0)
3231 gcc_assert (ms0
== HOST_BITS_PER_WIDE_INT
);
3233 if (ls1
== HOST_BITS_PER_WIDE_INT
)
3239 operands
[2] = GEN_INT (len
);
3240 return "extrd,u %1,63,%2,%0";
3244 /* We could use this `depi' for the case above as well, but `depi'
3245 requires one more register file access than an `extru'. */
3250 operands
[2] = GEN_INT (p
);
3251 operands
[3] = GEN_INT (len
);
3252 return "depdi 0,%2,%3,%0";
3256 return "and %1,%2,%0";
3260 pa_output_ior (rtx
*operands
)
3262 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3263 int bs0
, bs1
, p
, len
;
3265 if (INTVAL (operands
[2]) == 0)
3266 return "copy %1,%0";
3268 for (bs0
= 0; bs0
< 32; bs0
++)
3269 if ((mask
& (1 << bs0
)) != 0)
3272 for (bs1
= bs0
; bs1
< 32; bs1
++)
3273 if ((mask
& (1 << bs1
)) == 0)
3276 gcc_assert (bs1
== 32 || ((unsigned HOST_WIDE_INT
) 1 << bs1
) > mask
);
3281 operands
[2] = GEN_INT (p
);
3282 operands
[3] = GEN_INT (len
);
3283 return "{depi|depwi} -1,%2,%3,%0";
3286 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3287 storing the result in operands[0]. */
3289 pa_output_64bit_ior (rtx
*operands
)
3291 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3292 int bs0
, bs1
, p
, len
;
3294 if (INTVAL (operands
[2]) == 0)
3295 return "copy %1,%0";
3297 for (bs0
= 0; bs0
< HOST_BITS_PER_WIDE_INT
; bs0
++)
3298 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs0
)) != 0)
3301 for (bs1
= bs0
; bs1
< HOST_BITS_PER_WIDE_INT
; bs1
++)
3302 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs1
)) == 0)
3305 gcc_assert (bs1
== HOST_BITS_PER_WIDE_INT
3306 || ((unsigned HOST_WIDE_INT
) 1 << bs1
) > mask
);
3311 operands
[2] = GEN_INT (p
);
3312 operands
[3] = GEN_INT (len
);
3313 return "depdi -1,%2,%3,%0";
3316 /* Target hook for assembling integer objects. This code handles
3317 aligned SI and DI integers specially since function references
3318 must be preceded by P%. */
3321 pa_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3326 /* When we have a SYMBOL_REF with a SYMBOL_REF_DECL, we need to call
3327 call assemble_external and set the SYMBOL_REF_DECL to NULL before
3328 calling output_addr_const. Otherwise, it may call assemble_external
3329 in the midst of outputing the assembler code for the SYMBOL_REF.
3330 We restore the SYMBOL_REF_DECL after the output is done. */
3331 if (GET_CODE (x
) == SYMBOL_REF
)
3333 decl
= SYMBOL_REF_DECL (x
);
3336 assemble_external (decl
);
3337 SET_SYMBOL_REF_DECL (x
, NULL
);
3341 if (size
== UNITS_PER_WORD
3343 && function_label_operand (x
, VOIDmode
))
3345 fputs (size
== 8? "\t.dword\t" : "\t.word\t", asm_out_file
);
3347 /* We don't want an OPD when generating fast indirect calls. */
3348 if (!TARGET_FAST_INDIRECT_CALLS
)
3349 fputs ("P%", asm_out_file
);
3351 output_addr_const (asm_out_file
, x
);
3352 fputc ('\n', asm_out_file
);
3356 result
= default_assemble_integer (x
, size
, aligned_p
);
3359 SET_SYMBOL_REF_DECL (x
, decl
);
3364 /* Output an ascii string. */
3366 pa_output_ascii (FILE *file
, const char *p
, int size
)
3370 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
3372 /* The HP assembler can only take strings of 256 characters at one
3373 time. This is a limitation on input line length, *not* the
3374 length of the string. Sigh. Even worse, it seems that the
3375 restriction is in number of input characters (see \xnn &
3376 \whatever). So we have to do this very carefully. */
3378 fputs ("\t.STRING \"", file
);
3381 for (i
= 0; i
< size
; i
+= 4)
3385 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
3387 register unsigned int c
= (unsigned char) p
[i
+ io
];
3389 if (c
== '\"' || c
== '\\')
3390 partial_output
[co
++] = '\\';
3391 if (c
>= ' ' && c
< 0177)
3392 partial_output
[co
++] = c
;
3396 partial_output
[co
++] = '\\';
3397 partial_output
[co
++] = 'x';
3398 hexd
= c
/ 16 - 0 + '0';
3400 hexd
-= '9' - 'a' + 1;
3401 partial_output
[co
++] = hexd
;
3402 hexd
= c
% 16 - 0 + '0';
3404 hexd
-= '9' - 'a' + 1;
3405 partial_output
[co
++] = hexd
;
3408 if (chars_output
+ co
> 243)
3410 fputs ("\"\n\t.STRING \"", file
);
3413 fwrite (partial_output
, 1, (size_t) co
, file
);
3417 fputs ("\"\n", file
);
3420 /* Try to rewrite floating point comparisons & branches to avoid
3421 useless add,tr insns.
3423 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3424 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3425 first attempt to remove useless add,tr insns. It is zero
3426 for the second pass as reorg sometimes leaves bogus REG_DEAD
3429 When CHECK_NOTES is zero we can only eliminate add,tr insns
3430 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3433 remove_useless_addtr_insns (int check_notes
)
3436 static int pass
= 0;
3438 /* This is fairly cheap, so always run it when optimizing. */
3442 int fbranch_count
= 0;
3444 /* Walk all the insns in this function looking for fcmp & fbranch
3445 instructions. Keep track of how many of each we find. */
3446 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3450 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3451 if (! NONJUMP_INSN_P (insn
) && ! JUMP_P (insn
))
3454 tmp
= PATTERN (insn
);
3456 /* It must be a set. */
3457 if (GET_CODE (tmp
) != SET
)
3460 /* If the destination is CCFP, then we've found an fcmp insn. */
3461 tmp
= SET_DEST (tmp
);
3462 if (GET_CODE (tmp
) == REG
&& REGNO (tmp
) == 0)
3468 tmp
= PATTERN (insn
);
3469 /* If this is an fbranch instruction, bump the fbranch counter. */
3470 if (GET_CODE (tmp
) == SET
3471 && SET_DEST (tmp
) == pc_rtx
3472 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3473 && GET_CODE (XEXP (SET_SRC (tmp
), 0)) == NE
3474 && GET_CODE (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == REG
3475 && REGNO (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == 0)
3483 /* Find all floating point compare + branch insns. If possible,
3484 reverse the comparison & the branch to avoid add,tr insns. */
3485 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3490 /* Ignore anything that isn't an INSN. */
3491 if (! NONJUMP_INSN_P (insn
))
3494 tmp
= PATTERN (insn
);
3496 /* It must be a set. */
3497 if (GET_CODE (tmp
) != SET
)
3500 /* The destination must be CCFP, which is register zero. */
3501 tmp
= SET_DEST (tmp
);
3502 if (GET_CODE (tmp
) != REG
|| REGNO (tmp
) != 0)
3505 /* INSN should be a set of CCFP.
3507 See if the result of this insn is used in a reversed FP
3508 conditional branch. If so, reverse our condition and
3509 the branch. Doing so avoids useless add,tr insns. */
3510 next
= next_insn (insn
);
3513 /* Jumps, calls and labels stop our search. */
3514 if (JUMP_P (next
) || CALL_P (next
) || LABEL_P (next
))
3517 /* As does another fcmp insn. */
3518 if (NONJUMP_INSN_P (next
)
3519 && GET_CODE (PATTERN (next
)) == SET
3520 && GET_CODE (SET_DEST (PATTERN (next
))) == REG
3521 && REGNO (SET_DEST (PATTERN (next
))) == 0)
3524 next
= next_insn (next
);
3527 /* Is NEXT_INSN a branch? */
3528 if (next
&& JUMP_P (next
))
3530 rtx pattern
= PATTERN (next
);
3532 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3533 and CCFP dies, then reverse our conditional and the branch
3534 to avoid the add,tr. */
3535 if (GET_CODE (pattern
) == SET
3536 && SET_DEST (pattern
) == pc_rtx
3537 && GET_CODE (SET_SRC (pattern
)) == IF_THEN_ELSE
3538 && GET_CODE (XEXP (SET_SRC (pattern
), 0)) == NE
3539 && GET_CODE (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == REG
3540 && REGNO (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == 0
3541 && GET_CODE (XEXP (SET_SRC (pattern
), 1)) == PC
3542 && (fcmp_count
== fbranch_count
3544 && find_regno_note (next
, REG_DEAD
, 0))))
3546 /* Reverse the branch. */
3547 tmp
= XEXP (SET_SRC (pattern
), 1);
3548 XEXP (SET_SRC (pattern
), 1) = XEXP (SET_SRC (pattern
), 2);
3549 XEXP (SET_SRC (pattern
), 2) = tmp
;
3550 INSN_CODE (next
) = -1;
3552 /* Reverse our condition. */
3553 tmp
= PATTERN (insn
);
3554 PUT_CODE (XEXP (tmp
, 1),
3555 (reverse_condition_maybe_unordered
3556 (GET_CODE (XEXP (tmp
, 1)))));
3566 /* You may have trouble believing this, but this is the 32 bit HP-PA
3571 Variable arguments (optional; any number may be allocated)
3573 SP-(4*(N+9)) arg word N
3578 Fixed arguments (must be allocated; may remain unused)
3587 SP-32 External Data Pointer (DP)
3589 SP-24 External/stub RP (RP')
3593 SP-8 Calling Stub RP (RP'')
3598 SP-0 Stack Pointer (points to next available address)
3602 /* This function saves registers as follows. Registers marked with ' are
3603 this function's registers (as opposed to the previous function's).
3604 If a frame_pointer isn't needed, r4 is saved as a general register;
3605 the space for the frame pointer is still allocated, though, to keep
3611 SP (FP') Previous FP
3612 SP + 4 Alignment filler (sigh)
3613 SP + 8 Space for locals reserved here.
3617 SP + n All call saved register used.
3621 SP + o All call saved fp registers used.
3625 SP + p (SP') points to next available address.
3629 /* Global variables set by output_function_prologue(). */
3630 /* Size of frame. Need to know this to emit return insns from
3632 static HOST_WIDE_INT actual_fsize
, local_fsize
;
3633 static int save_fregs
;
3635 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3636 Handle case where DISP > 8k by using the add_high_const patterns.
3638 Note in DISP > 8k case, we will leave the high part of the address
3639 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3642 store_reg (int reg
, HOST_WIDE_INT disp
, int base
)
3644 rtx dest
, src
, basereg
;
3647 src
= gen_rtx_REG (word_mode
, reg
);
3648 basereg
= gen_rtx_REG (Pmode
, base
);
3649 if (VAL_14_BITS_P (disp
))
3651 dest
= gen_rtx_MEM (word_mode
, plus_constant (Pmode
, basereg
, disp
));
3652 insn
= emit_move_insn (dest
, src
);
3654 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
3656 rtx delta
= GEN_INT (disp
);
3657 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3659 emit_move_insn (tmpreg
, delta
);
3660 insn
= emit_move_insn (tmpreg
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
3663 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3664 gen_rtx_SET (tmpreg
,
3665 gen_rtx_PLUS (Pmode
, basereg
, delta
)));
3666 RTX_FRAME_RELATED_P (insn
) = 1;
3668 dest
= gen_rtx_MEM (word_mode
, tmpreg
);
3669 insn
= emit_move_insn (dest
, src
);
3673 rtx delta
= GEN_INT (disp
);
3674 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
3675 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3677 emit_move_insn (tmpreg
, high
);
3678 dest
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
3679 insn
= emit_move_insn (dest
, src
);
3681 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3682 gen_rtx_SET (gen_rtx_MEM (word_mode
,
3683 gen_rtx_PLUS (word_mode
,
3690 RTX_FRAME_RELATED_P (insn
) = 1;
3693 /* Emit RTL to store REG at the memory location specified by BASE and then
3694 add MOD to BASE. MOD must be <= 8k. */
3697 store_reg_modify (int base
, int reg
, HOST_WIDE_INT mod
)
3699 rtx basereg
, srcreg
, delta
;
3702 gcc_assert (VAL_14_BITS_P (mod
));
3704 basereg
= gen_rtx_REG (Pmode
, base
);
3705 srcreg
= gen_rtx_REG (word_mode
, reg
);
3706 delta
= GEN_INT (mod
);
3708 insn
= emit_insn (gen_post_store (basereg
, srcreg
, delta
));
3711 RTX_FRAME_RELATED_P (insn
) = 1;
3713 /* RTX_FRAME_RELATED_P must be set on each frame related set
3714 in a parallel with more than one element. */
3715 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, 0)) = 1;
3716 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, 1)) = 1;
3720 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3721 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3722 whether to add a frame note or not.
3724 In the DISP > 8k case, we leave the high part of the address in %r1.
3725 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3728 set_reg_plus_d (int reg
, int base
, HOST_WIDE_INT disp
, int note
)
3732 if (VAL_14_BITS_P (disp
))
3734 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3735 plus_constant (Pmode
,
3736 gen_rtx_REG (Pmode
, base
), disp
));
3738 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
3740 rtx basereg
= gen_rtx_REG (Pmode
, base
);
3741 rtx delta
= GEN_INT (disp
);
3742 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3744 emit_move_insn (tmpreg
, delta
);
3745 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3746 gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
3748 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3749 gen_rtx_SET (tmpreg
,
3750 gen_rtx_PLUS (Pmode
, basereg
, delta
)));
3754 rtx basereg
= gen_rtx_REG (Pmode
, base
);
3755 rtx delta
= GEN_INT (disp
);
3756 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3758 emit_move_insn (tmpreg
,
3759 gen_rtx_PLUS (Pmode
, basereg
,
3760 gen_rtx_HIGH (Pmode
, delta
)));
3761 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3762 gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
3765 if (DO_FRAME_NOTES
&& note
)
3766 RTX_FRAME_RELATED_P (insn
) = 1;
3770 pa_compute_frame_size (poly_int64 size
, int *fregs_live
)
3775 /* The code in pa_expand_prologue and pa_expand_epilogue must
3776 be consistent with the rounding and size calculation done here.
3777 Change them at the same time. */
3779 /* We do our own stack alignment. First, round the size of the
3780 stack locals up to a word boundary. */
3781 size
= (size
+ UNITS_PER_WORD
- 1) & ~(UNITS_PER_WORD
- 1);
3783 /* Space for previous frame pointer + filler. If any frame is
3784 allocated, we need to add in the TARGET_STARTING_FRAME_OFFSET. We
3785 waste some space here for the sake of HP compatibility. The
3786 first slot is only used when the frame pointer is needed. */
3787 if (size
|| frame_pointer_needed
)
3788 size
+= pa_starting_frame_offset ();
3790 /* If the current function calls __builtin_eh_return, then we need
3791 to allocate stack space for registers that will hold data for
3792 the exception handler. */
3793 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
3797 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
3799 size
+= i
* UNITS_PER_WORD
;
3802 /* Account for space used by the callee general register saves. */
3803 for (i
= 18, j
= frame_pointer_needed
? 4 : 3; i
>= j
; i
--)
3804 if (df_regs_ever_live_p (i
))
3805 size
+= UNITS_PER_WORD
;
3807 /* Account for space used by the callee floating point register saves. */
3808 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
3809 if (df_regs_ever_live_p (i
)
3810 || (!TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
3814 /* We always save both halves of the FP register, so always
3815 increment the frame size by 8 bytes. */
3819 /* If any of the floating registers are saved, account for the
3820 alignment needed for the floating point register save block. */
3823 size
= (size
+ 7) & ~7;
3828 /* The various ABIs include space for the outgoing parameters in the
3829 size of the current function's stack frame. We don't need to align
3830 for the outgoing arguments as their alignment is set by the final
3831 rounding for the frame as a whole. */
3832 size
+= crtl
->outgoing_args_size
;
3834 /* Allocate space for the fixed frame marker. This space must be
3835 allocated for any function that makes calls or allocates
3837 if (!crtl
->is_leaf
|| size
)
3838 size
+= TARGET_64BIT
? 48 : 32;
3840 /* Finally, round to the preferred stack boundary. */
3841 return ((size
+ PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
3842 & ~(PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
3845 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3846 of memory. If any fpu reg is used in the function, we allocate
3847 such a block here, at the bottom of the frame, just in case it's needed.
3849 If this function is a leaf procedure, then we may choose not
3850 to do a "save" insn. The decision about whether or not
3851 to do this is made in regclass.c. */
3854 pa_output_function_prologue (FILE *file
)
3856 /* The function's label and associated .PROC must never be
3857 separated and must be output *after* any profiling declarations
3858 to avoid changing spaces/subspaces within a procedure. */
3859 ASM_OUTPUT_LABEL (file
, XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0));
3860 fputs ("\t.PROC\n", file
);
3862 /* pa_expand_prologue does the dirty work now. We just need
3863 to output the assembler directives which denote the start
3865 fprintf (file
, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC
, actual_fsize
);
3867 fputs (",NO_CALLS", file
);
3869 fputs (",CALLS", file
);
3871 fputs (",SAVE_RP", file
);
3873 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3874 at the beginning of the frame and that it is used as the frame
3875 pointer for the frame. We do this because our current frame
3876 layout doesn't conform to that specified in the HP runtime
3877 documentation and we need a way to indicate to programs such as
3878 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3879 isn't used by HP compilers but is supported by the assembler.
3880 However, SAVE_SP is supposed to indicate that the previous stack
3881 pointer has been saved in the frame marker. */
3882 if (frame_pointer_needed
)
3883 fputs (",SAVE_SP", file
);
3885 /* Pass on information about the number of callee register saves
3886 performed in the prologue.
3888 The compiler is supposed to pass the highest register number
3889 saved, the assembler then has to adjust that number before
3890 entering it into the unwind descriptor (to account for any
3891 caller saved registers with lower register numbers than the
3892 first callee saved register). */
3894 fprintf (file
, ",ENTRY_GR=%d", gr_saved
+ 2);
3897 fprintf (file
, ",ENTRY_FR=%d", fr_saved
+ 11);
3899 fputs ("\n\t.ENTRY\n", file
);
3901 remove_useless_addtr_insns (0);
3905 pa_expand_prologue (void)
3907 int merge_sp_adjust_with_store
= 0;
3908 HOST_WIDE_INT size
= get_frame_size ();
3909 HOST_WIDE_INT offset
;
3918 /* Compute total size for frame pointer, filler, locals and rounding to
3919 the next word boundary. Similar code appears in pa_compute_frame_size
3920 and must be changed in tandem with this code. */
3921 local_fsize
= (size
+ UNITS_PER_WORD
- 1) & ~(UNITS_PER_WORD
- 1);
3922 if (local_fsize
|| frame_pointer_needed
)
3923 local_fsize
+= pa_starting_frame_offset ();
3925 actual_fsize
= pa_compute_frame_size (size
, &save_fregs
);
3926 if (flag_stack_usage_info
)
3927 current_function_static_stack_size
= actual_fsize
;
3929 /* Compute a few things we will use often. */
3930 tmpreg
= gen_rtx_REG (word_mode
, 1);
3932 /* Save RP first. The calling conventions manual states RP will
3933 always be stored into the caller's frame at sp - 20 or sp - 16
3934 depending on which ABI is in use. */
3935 if (df_regs_ever_live_p (2) || crtl
->calls_eh_return
)
3937 store_reg (2, TARGET_64BIT
? -16 : -20, STACK_POINTER_REGNUM
);
3943 /* Allocate the local frame and set up the frame pointer if needed. */
3944 if (actual_fsize
!= 0)
3946 if (frame_pointer_needed
)
3948 /* Copy the old frame pointer temporarily into %r1. Set up the
3949 new stack pointer, then store away the saved old frame pointer
3950 into the stack at sp and at the same time update the stack
3951 pointer by actual_fsize bytes. Two versions, first
3952 handles small (<8k) frames. The second handles large (>=8k)
3954 insn
= emit_move_insn (tmpreg
, hard_frame_pointer_rtx
);
3956 RTX_FRAME_RELATED_P (insn
) = 1;
3958 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3960 RTX_FRAME_RELATED_P (insn
) = 1;
3962 if (VAL_14_BITS_P (actual_fsize
))
3963 store_reg_modify (STACK_POINTER_REGNUM
, 1, actual_fsize
);
3966 /* It is incorrect to store the saved frame pointer at *sp,
3967 then increment sp (writes beyond the current stack boundary).
3969 So instead use stwm to store at *sp and post-increment the
3970 stack pointer as an atomic operation. Then increment sp to
3971 finish allocating the new frame. */
3972 HOST_WIDE_INT adjust1
= 8192 - 64;
3973 HOST_WIDE_INT adjust2
= actual_fsize
- adjust1
;
3975 store_reg_modify (STACK_POINTER_REGNUM
, 1, adjust1
);
3976 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
3980 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3981 we need to store the previous stack pointer (frame pointer)
3982 into the frame marker on targets that use the HP unwind
3983 library. This allows the HP unwind library to be used to
3984 unwind GCC frames. However, we are not fully compatible
3985 with the HP library because our frame layout differs from
3986 that specified in the HP runtime specification.
3988 We don't want a frame note on this instruction as the frame
3989 marker moves during dynamic stack allocation.
3991 This instruction also serves as a blockage to prevent
3992 register spills from being scheduled before the stack
3993 pointer is raised. This is necessary as we store
3994 registers using the frame pointer as a base register,
3995 and the frame pointer is set before sp is raised. */
3996 if (TARGET_HPUX_UNWIND_LIBRARY
)
3998 rtx addr
= gen_rtx_PLUS (word_mode
, stack_pointer_rtx
,
3999 GEN_INT (TARGET_64BIT
? -8 : -4));
4001 emit_move_insn (gen_rtx_MEM (word_mode
, addr
),
4002 hard_frame_pointer_rtx
);
4005 emit_insn (gen_blockage ());
4007 /* no frame pointer needed. */
4010 /* In some cases we can perform the first callee register save
4011 and allocating the stack frame at the same time. If so, just
4012 make a note of it and defer allocating the frame until saving
4013 the callee registers. */
4014 if (VAL_14_BITS_P (actual_fsize
) && local_fsize
== 0)
4015 merge_sp_adjust_with_store
= 1;
4016 /* Cannot optimize. Adjust the stack frame by actual_fsize
4019 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4024 /* Normal register save.
4026 Do not save the frame pointer in the frame_pointer_needed case. It
4027 was done earlier. */
4028 if (frame_pointer_needed
)
4030 offset
= local_fsize
;
4032 /* Saving the EH return data registers in the frame is the simplest
4033 way to get the frame unwind information emitted. We put them
4034 just before the general registers. */
4035 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4037 unsigned int i
, regno
;
4041 regno
= EH_RETURN_DATA_REGNO (i
);
4042 if (regno
== INVALID_REGNUM
)
4045 store_reg (regno
, offset
, HARD_FRAME_POINTER_REGNUM
);
4046 offset
+= UNITS_PER_WORD
;
4050 for (i
= 18; i
>= 4; i
--)
4051 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
4053 store_reg (i
, offset
, HARD_FRAME_POINTER_REGNUM
);
4054 offset
+= UNITS_PER_WORD
;
4057 /* Account for %r3 which is saved in a special place. */
4060 /* No frame pointer needed. */
4063 offset
= local_fsize
- actual_fsize
;
4065 /* Saving the EH return data registers in the frame is the simplest
4066 way to get the frame unwind information emitted. */
4067 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4069 unsigned int i
, regno
;
4073 regno
= EH_RETURN_DATA_REGNO (i
);
4074 if (regno
== INVALID_REGNUM
)
4077 /* If merge_sp_adjust_with_store is nonzero, then we can
4078 optimize the first save. */
4079 if (merge_sp_adjust_with_store
)
4081 store_reg_modify (STACK_POINTER_REGNUM
, regno
, -offset
);
4082 merge_sp_adjust_with_store
= 0;
4085 store_reg (regno
, offset
, STACK_POINTER_REGNUM
);
4086 offset
+= UNITS_PER_WORD
;
4090 for (i
= 18; i
>= 3; i
--)
4091 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
4093 /* If merge_sp_adjust_with_store is nonzero, then we can
4094 optimize the first GR save. */
4095 if (merge_sp_adjust_with_store
)
4097 store_reg_modify (STACK_POINTER_REGNUM
, i
, -offset
);
4098 merge_sp_adjust_with_store
= 0;
4101 store_reg (i
, offset
, STACK_POINTER_REGNUM
);
4102 offset
+= UNITS_PER_WORD
;
4106 /* If we wanted to merge the SP adjustment with a GR save, but we never
4107 did any GR saves, then just emit the adjustment here. */
4108 if (merge_sp_adjust_with_store
)
4109 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4113 /* The hppa calling conventions say that %r19, the pic offset
4114 register, is saved at sp - 32 (in this function's frame)
4115 when generating PIC code. FIXME: What is the correct thing
4116 to do for functions which make no calls and allocate no
4117 frame? Do we need to allocate a frame, or can we just omit
4118 the save? For now we'll just omit the save.
4120 We don't want a note on this insn as the frame marker can
4121 move if there is a dynamic stack allocation. */
4122 if (flag_pic
&& actual_fsize
!= 0 && !TARGET_64BIT
)
4124 rtx addr
= gen_rtx_PLUS (word_mode
, stack_pointer_rtx
, GEN_INT (-32));
4126 emit_move_insn (gen_rtx_MEM (word_mode
, addr
), pic_offset_table_rtx
);
4130 /* Align pointer properly (doubleword boundary). */
4131 offset
= (offset
+ 7) & ~7;
4133 /* Floating point register store. */
4138 /* First get the frame or stack pointer to the start of the FP register
4140 if (frame_pointer_needed
)
4142 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM
, offset
, 0);
4143 base
= hard_frame_pointer_rtx
;
4147 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
, 0);
4148 base
= stack_pointer_rtx
;
4151 /* Now actually save the FP registers. */
4152 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
4154 if (df_regs_ever_live_p (i
)
4155 || (! TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
4159 addr
= gen_rtx_MEM (DFmode
,
4160 gen_rtx_POST_INC (word_mode
, tmpreg
));
4161 reg
= gen_rtx_REG (DFmode
, i
);
4162 insn
= emit_move_insn (addr
, reg
);
4165 RTX_FRAME_RELATED_P (insn
) = 1;
4168 rtx mem
= gen_rtx_MEM (DFmode
,
4169 plus_constant (Pmode
, base
,
4171 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4172 gen_rtx_SET (mem
, reg
));
4176 rtx meml
= gen_rtx_MEM (SFmode
,
4177 plus_constant (Pmode
, base
,
4179 rtx memr
= gen_rtx_MEM (SFmode
,
4180 plus_constant (Pmode
, base
,
4182 rtx regl
= gen_rtx_REG (SFmode
, i
);
4183 rtx regr
= gen_rtx_REG (SFmode
, i
+ 1);
4184 rtx setl
= gen_rtx_SET (meml
, regl
);
4185 rtx setr
= gen_rtx_SET (memr
, regr
);
4188 RTX_FRAME_RELATED_P (setl
) = 1;
4189 RTX_FRAME_RELATED_P (setr
) = 1;
4190 vec
= gen_rtvec (2, setl
, setr
);
4191 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4192 gen_rtx_SEQUENCE (VOIDmode
, vec
));
4195 offset
+= GET_MODE_SIZE (DFmode
);
4202 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4203 Handle case where DISP > 8k by using the add_high_const patterns. */
4206 load_reg (int reg
, HOST_WIDE_INT disp
, int base
)
4208 rtx dest
= gen_rtx_REG (word_mode
, reg
);
4209 rtx basereg
= gen_rtx_REG (Pmode
, base
);
4212 if (VAL_14_BITS_P (disp
))
4213 src
= gen_rtx_MEM (word_mode
, plus_constant (Pmode
, basereg
, disp
));
4214 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
4216 rtx delta
= GEN_INT (disp
);
4217 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
4219 emit_move_insn (tmpreg
, delta
);
4220 if (TARGET_DISABLE_INDEXING
)
4222 emit_move_insn (tmpreg
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
4223 src
= gen_rtx_MEM (word_mode
, tmpreg
);
4226 src
= gen_rtx_MEM (word_mode
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
4230 rtx delta
= GEN_INT (disp
);
4231 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
4232 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
4234 emit_move_insn (tmpreg
, high
);
4235 src
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
4238 emit_move_insn (dest
, src
);
4241 /* Update the total code bytes output to the text section. */
4244 update_total_code_bytes (unsigned int nbytes
)
4246 if ((TARGET_PORTABLE_RUNTIME
|| !TARGET_GAS
|| !TARGET_SOM
)
4247 && !IN_NAMED_SECTION_P (cfun
->decl
))
4249 unsigned int old_total
= total_code_bytes
;
4251 total_code_bytes
+= nbytes
;
4253 /* Be prepared to handle overflows. */
4254 if (old_total
> total_code_bytes
)
4255 total_code_bytes
= UINT_MAX
;
4259 /* This function generates the assembly code for function exit.
4260 Args are as for output_function_prologue ().
4262 The function epilogue should not depend on the current stack
4263 pointer! It should use the frame pointer only. This is mandatory
4264 because of alloca; we also take advantage of it to omit stack
4265 adjustments before returning. */
4268 pa_output_function_epilogue (FILE *file
)
4270 rtx_insn
*insn
= get_last_insn ();
4273 /* pa_expand_epilogue does the dirty work now. We just need
4274 to output the assembler directives which denote the end
4277 To make debuggers happy, emit a nop if the epilogue was completely
4278 eliminated due to a volatile call as the last insn in the
4279 current function. That way the return address (in %r2) will
4280 always point to a valid instruction in the current function. */
4282 /* Get the last real insn. */
4284 insn
= prev_real_insn (insn
);
4286 /* If it is a sequence, then look inside. */
4287 if (insn
&& NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4288 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))-> insn (0);
4290 /* If insn is a CALL_INSN, then it must be a call to a volatile
4291 function (otherwise there would be epilogue insns). */
4292 if (insn
&& CALL_P (insn
))
4294 fputs ("\tnop\n", file
);
4300 fputs ("\t.EXIT\n\t.PROCEND\n", file
);
4302 if (TARGET_SOM
&& TARGET_GAS
)
4304 /* We are done with this subspace except possibly for some additional
4305 debug information. Forget that we are in this subspace to ensure
4306 that the next function is output in its own subspace. */
4308 cfun
->machine
->in_nsubspa
= 2;
4311 /* Thunks do their own insn accounting. */
4315 if (INSN_ADDRESSES_SET_P ())
4317 last_address
= extra_nop
? 4 : 0;
4318 insn
= get_last_nonnote_insn ();
4321 last_address
+= INSN_ADDRESSES (INSN_UID (insn
));
4323 last_address
+= insn_default_length (insn
);
4325 last_address
= ((last_address
+ FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1)
4326 & ~(FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1));
4329 last_address
= UINT_MAX
;
4331 /* Finally, update the total number of code bytes output so far. */
4332 update_total_code_bytes (last_address
);
4336 pa_expand_epilogue (void)
4339 HOST_WIDE_INT offset
;
4340 HOST_WIDE_INT ret_off
= 0;
4342 int merge_sp_adjust_with_load
= 0;
4344 /* We will use this often. */
4345 tmpreg
= gen_rtx_REG (word_mode
, 1);
4347 /* Try to restore RP early to avoid load/use interlocks when
4348 RP gets used in the return (bv) instruction. This appears to still
4349 be necessary even when we schedule the prologue and epilogue. */
4352 ret_off
= TARGET_64BIT
? -16 : -20;
4353 if (frame_pointer_needed
)
4355 load_reg (2, ret_off
, HARD_FRAME_POINTER_REGNUM
);
4360 /* No frame pointer, and stack is smaller than 8k. */
4361 if (VAL_14_BITS_P (ret_off
- actual_fsize
))
4363 load_reg (2, ret_off
- actual_fsize
, STACK_POINTER_REGNUM
);
4369 /* General register restores. */
4370 if (frame_pointer_needed
)
4372 offset
= local_fsize
;
4374 /* If the current function calls __builtin_eh_return, then we need
4375 to restore the saved EH data registers. */
4376 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4378 unsigned int i
, regno
;
4382 regno
= EH_RETURN_DATA_REGNO (i
);
4383 if (regno
== INVALID_REGNUM
)
4386 load_reg (regno
, offset
, HARD_FRAME_POINTER_REGNUM
);
4387 offset
+= UNITS_PER_WORD
;
4391 for (i
= 18; i
>= 4; i
--)
4392 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
4394 load_reg (i
, offset
, HARD_FRAME_POINTER_REGNUM
);
4395 offset
+= UNITS_PER_WORD
;
4400 offset
= local_fsize
- actual_fsize
;
4402 /* If the current function calls __builtin_eh_return, then we need
4403 to restore the saved EH data registers. */
4404 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4406 unsigned int i
, regno
;
4410 regno
= EH_RETURN_DATA_REGNO (i
);
4411 if (regno
== INVALID_REGNUM
)
4414 /* Only for the first load.
4415 merge_sp_adjust_with_load holds the register load
4416 with which we will merge the sp adjustment. */
4417 if (merge_sp_adjust_with_load
== 0
4419 && VAL_14_BITS_P (-actual_fsize
))
4420 merge_sp_adjust_with_load
= regno
;
4422 load_reg (regno
, offset
, STACK_POINTER_REGNUM
);
4423 offset
+= UNITS_PER_WORD
;
4427 for (i
= 18; i
>= 3; i
--)
4429 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
4431 /* Only for the first load.
4432 merge_sp_adjust_with_load holds the register load
4433 with which we will merge the sp adjustment. */
4434 if (merge_sp_adjust_with_load
== 0
4436 && VAL_14_BITS_P (-actual_fsize
))
4437 merge_sp_adjust_with_load
= i
;
4439 load_reg (i
, offset
, STACK_POINTER_REGNUM
);
4440 offset
+= UNITS_PER_WORD
;
4445 /* Align pointer properly (doubleword boundary). */
4446 offset
= (offset
+ 7) & ~7;
4448 /* FP register restores. */
4451 /* Adjust the register to index off of. */
4452 if (frame_pointer_needed
)
4453 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM
, offset
, 0);
4455 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
, 0);
4457 /* Actually do the restores now. */
4458 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
4459 if (df_regs_ever_live_p (i
)
4460 || (! TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
4462 rtx src
= gen_rtx_MEM (DFmode
,
4463 gen_rtx_POST_INC (word_mode
, tmpreg
));
4464 rtx dest
= gen_rtx_REG (DFmode
, i
);
4465 emit_move_insn (dest
, src
);
4469 /* Emit a blockage insn here to keep these insns from being moved to
4470 an earlier spot in the epilogue, or into the main instruction stream.
4472 This is necessary as we must not cut the stack back before all the
4473 restores are finished. */
4474 emit_insn (gen_blockage ());
4476 /* Reset stack pointer (and possibly frame pointer). The stack
4477 pointer is initially set to fp + 64 to avoid a race condition. */
4478 if (frame_pointer_needed
)
4480 rtx delta
= GEN_INT (-64);
4482 set_reg_plus_d (STACK_POINTER_REGNUM
, HARD_FRAME_POINTER_REGNUM
, 64, 0);
4483 emit_insn (gen_pre_load (hard_frame_pointer_rtx
,
4484 stack_pointer_rtx
, delta
));
4486 /* If we were deferring a callee register restore, do it now. */
4487 else if (merge_sp_adjust_with_load
)
4489 rtx delta
= GEN_INT (-actual_fsize
);
4490 rtx dest
= gen_rtx_REG (word_mode
, merge_sp_adjust_with_load
);
4492 emit_insn (gen_pre_load (dest
, stack_pointer_rtx
, delta
));
4494 else if (actual_fsize
!= 0)
4495 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4498 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4499 frame greater than 8k), do so now. */
4501 load_reg (2, ret_off
, STACK_POINTER_REGNUM
);
4503 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4505 rtx sa
= EH_RETURN_STACKADJ_RTX
;
4507 emit_insn (gen_blockage ());
4508 emit_insn (TARGET_64BIT
4509 ? gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
, sa
)
4510 : gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, sa
));
4515 pa_can_use_return_insn (void)
4517 if (!reload_completed
)
4520 if (frame_pointer_needed
)
4523 if (df_regs_ever_live_p (2))
4529 return pa_compute_frame_size (get_frame_size (), 0) == 0;
4533 hppa_pic_save_rtx (void)
4535 return get_hard_reg_initial_val (word_mode
, PIC_OFFSET_TABLE_REGNUM
);
4538 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4539 #define NO_DEFERRED_PROFILE_COUNTERS 0
4543 /* Vector of funcdef numbers. */
4544 static vec
<int> funcdef_nos
;
4546 /* Output deferred profile counters. */
4548 output_deferred_profile_counters (void)
4553 if (funcdef_nos
.is_empty ())
4556 switch_to_section (data_section
);
4557 align
= MIN (BIGGEST_ALIGNMENT
, LONG_TYPE_SIZE
);
4558 ASM_OUTPUT_ALIGN (asm_out_file
, floor_log2 (align
/ BITS_PER_UNIT
));
4560 for (i
= 0; funcdef_nos
.iterate (i
, &n
); i
++)
4562 targetm
.asm_out
.internal_label (asm_out_file
, "LP", n
);
4563 assemble_integer (const0_rtx
, LONG_TYPE_SIZE
/ BITS_PER_UNIT
, align
, 1);
4566 funcdef_nos
.release ();
4570 hppa_profile_hook (int label_no
)
4572 /* We use SImode for the address of the function in both 32 and
4573 64-bit code to avoid having to provide DImode versions of the
4574 lcla2 and load_offset_label_address insn patterns. */
4575 rtx reg
= gen_reg_rtx (SImode
);
4576 rtx_code_label
*label_rtx
= gen_label_rtx ();
4577 int reg_parm_stack_space
= REG_PARM_STACK_SPACE (NULL_TREE
);
4578 rtx arg_bytes
, begin_label_rtx
, mcount
, sym
;
4579 rtx_insn
*call_insn
;
4580 char begin_label_name
[16];
4581 bool use_mcount_pcrel_call
;
4583 /* Set up call destination. */
4584 sym
= gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
4585 pa_encode_label (sym
);
4586 mcount
= gen_rtx_MEM (Pmode
, sym
);
4588 /* If we can reach _mcount with a pc-relative call, we can optimize
4589 loading the address of the current function. This requires linker
4590 long branch stub support. */
4591 if (!TARGET_PORTABLE_RUNTIME
4592 && !TARGET_LONG_CALLS
4593 && (TARGET_SOM
|| flag_function_sections
))
4594 use_mcount_pcrel_call
= TRUE
;
4596 use_mcount_pcrel_call
= FALSE
;
4598 ASM_GENERATE_INTERNAL_LABEL (begin_label_name
, FUNC_BEGIN_PROLOG_LABEL
,
4600 begin_label_rtx
= gen_rtx_SYMBOL_REF (SImode
, ggc_strdup (begin_label_name
));
4602 emit_move_insn (gen_rtx_REG (word_mode
, 26), gen_rtx_REG (word_mode
, 2));
4604 if (!use_mcount_pcrel_call
)
4606 /* The address of the function is loaded into %r25 with an instruction-
4607 relative sequence that avoids the use of relocations. The sequence
4608 is split so that the load_offset_label_address instruction can
4609 occupy the delay slot of the call to _mcount. */
4611 emit_insn (gen_lcla2 (reg
, label_rtx
));
4613 emit_insn (gen_lcla1 (reg
, label_rtx
));
4615 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode
, 25),
4621 if (!NO_DEFERRED_PROFILE_COUNTERS
)
4623 rtx count_label_rtx
, addr
, r24
;
4624 char count_label_name
[16];
4626 funcdef_nos
.safe_push (label_no
);
4627 ASM_GENERATE_INTERNAL_LABEL (count_label_name
, "LP", label_no
);
4628 count_label_rtx
= gen_rtx_SYMBOL_REF (Pmode
,
4629 ggc_strdup (count_label_name
));
4631 addr
= force_reg (Pmode
, count_label_rtx
);
4632 r24
= gen_rtx_REG (Pmode
, 24);
4633 emit_move_insn (r24
, addr
);
4635 arg_bytes
= GEN_INT (TARGET_64BIT
? 24 : 12);
4636 if (use_mcount_pcrel_call
)
4637 call_insn
= emit_call_insn (gen_call_mcount (mcount
, arg_bytes
,
4640 call_insn
= emit_call_insn (gen_call (mcount
, arg_bytes
));
4642 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), r24
);
4646 arg_bytes
= GEN_INT (TARGET_64BIT
? 16 : 8);
4647 if (use_mcount_pcrel_call
)
4648 call_insn
= emit_call_insn (gen_call_mcount (mcount
, arg_bytes
,
4651 call_insn
= emit_call_insn (gen_call (mcount
, arg_bytes
));
4654 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), gen_rtx_REG (SImode
, 25));
4655 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), gen_rtx_REG (SImode
, 26));
4657 /* Indicate the _mcount call cannot throw, nor will it execute a
4659 make_reg_eh_region_note_nothrow_nononlocal (call_insn
);
4661 /* Allocate space for fixed arguments. */
4662 if (reg_parm_stack_space
> crtl
->outgoing_args_size
)
4663 crtl
->outgoing_args_size
= reg_parm_stack_space
;
4666 /* Fetch the return address for the frame COUNT steps up from
4667 the current frame, after the prologue. FRAMEADDR is the
4668 frame pointer of the COUNT frame.
4670 We want to ignore any export stub remnants here. To handle this,
4671 we examine the code at the return address, and if it is an export
4672 stub, we return a memory rtx for the stub return address stored
4675 The value returned is used in two different ways:
4677 1. To find a function's caller.
4679 2. To change the return address for a function.
4681 This function handles most instances of case 1; however, it will
4682 fail if there are two levels of stubs to execute on the return
4683 path. The only way I believe that can happen is if the return value
4684 needs a parameter relocation, which never happens for C code.
4686 This function handles most instances of case 2; however, it will
4687 fail if we did not originally have stub code on the return path
4688 but will need stub code on the new return path. This can happen if
4689 the caller & callee are both in the main program, but the new
4690 return location is in a shared library. */
4693 pa_return_addr_rtx (int count
, rtx frameaddr
)
4700 /* The instruction stream at the return address of a PA1.X export stub is:
4702 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4703 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4704 0x00011820 | stub+16: mtsp r1,sr0
4705 0xe0400002 | stub+20: be,n 0(sr0,rp)
4707 0xe0400002 must be specified as -532676606 so that it won't be
4708 rejected as an invalid immediate operand on 64-bit hosts.
4710 The instruction stream at the return address of a PA2.0 export stub is:
4712 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4713 0xe840d002 | stub+12: bve,n (rp)
4716 HOST_WIDE_INT insns
[4];
4722 rp
= get_hard_reg_initial_val (Pmode
, 2);
4724 if (TARGET_64BIT
|| TARGET_NO_SPACE_REGS
)
4727 /* If there is no export stub then just use the value saved from
4728 the return pointer register. */
4730 saved_rp
= gen_reg_rtx (Pmode
);
4731 emit_move_insn (saved_rp
, rp
);
4733 /* Get pointer to the instruction stream. We have to mask out the
4734 privilege level from the two low order bits of the return address
4735 pointer here so that ins will point to the start of the first
4736 instruction that would have been executed if we returned. */
4737 ins
= copy_to_reg (gen_rtx_AND (Pmode
, rp
, MASK_RETURN_ADDR
));
4738 label
= gen_label_rtx ();
4742 insns
[0] = 0x4bc23fd1;
4743 insns
[1] = -398405630;
4748 insns
[0] = 0x4bc23fd1;
4749 insns
[1] = 0x004010a1;
4750 insns
[2] = 0x00011820;
4751 insns
[3] = -532676606;
4755 /* Check the instruction stream at the normal return address for the
4756 export stub. If it is an export stub, than our return address is
4757 really in -24[frameaddr]. */
4759 for (i
= 0; i
< len
; i
++)
4761 rtx op0
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, ins
, i
* 4));
4762 rtx op1
= GEN_INT (insns
[i
]);
4763 emit_cmp_and_jump_insns (op0
, op1
, NE
, NULL
, SImode
, 0, label
);
4766 /* Here we know that our return address points to an export
4767 stub. We don't want to return the address of the export stub,
4768 but rather the return address of the export stub. That return
4769 address is stored at -24[frameaddr]. */
4771 emit_move_insn (saved_rp
,
4773 memory_address (Pmode
,
4774 plus_constant (Pmode
, frameaddr
,
4783 pa_emit_bcond_fp (rtx operands
[])
4785 enum rtx_code code
= GET_CODE (operands
[0]);
4786 rtx operand0
= operands
[1];
4787 rtx operand1
= operands
[2];
4788 rtx label
= operands
[3];
4790 emit_insn (gen_rtx_SET (gen_rtx_REG (CCFPmode
, 0),
4791 gen_rtx_fmt_ee (code
, CCFPmode
, operand0
, operand1
)));
4793 emit_jump_insn (gen_rtx_SET (pc_rtx
,
4794 gen_rtx_IF_THEN_ELSE (VOIDmode
,
4797 gen_rtx_REG (CCFPmode
, 0),
4799 gen_rtx_LABEL_REF (VOIDmode
, label
),
4804 /* Adjust the cost of a scheduling dependency. Return the new cost of
4805 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4808 pa_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
4811 enum attr_type attr_type
;
4813 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4814 true dependencies as they are described with bypasses now. */
4815 if (pa_cpu
>= PROCESSOR_8000
|| dep_type
== 0)
4818 if (! recog_memoized (insn
))
4821 attr_type
= get_attr_type (insn
);
4826 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4829 if (attr_type
== TYPE_FPLOAD
)
4831 rtx pat
= PATTERN (insn
);
4832 rtx dep_pat
= PATTERN (dep_insn
);
4833 if (GET_CODE (pat
) == PARALLEL
)
4835 /* This happens for the fldXs,mb patterns. */
4836 pat
= XVECEXP (pat
, 0, 0);
4838 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4839 /* If this happens, we have to extend this to schedule
4840 optimally. Return 0 for now. */
4843 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
4845 if (! recog_memoized (dep_insn
))
4847 switch (get_attr_type (dep_insn
))
4854 case TYPE_FPSQRTSGL
:
4855 case TYPE_FPSQRTDBL
:
4856 /* A fpload can't be issued until one cycle before a
4857 preceding arithmetic operation has finished if
4858 the target of the fpload is any of the sources
4859 (or destination) of the arithmetic operation. */
4860 return insn_default_latency (dep_insn
) - 1;
4867 else if (attr_type
== TYPE_FPALU
)
4869 rtx pat
= PATTERN (insn
);
4870 rtx dep_pat
= PATTERN (dep_insn
);
4871 if (GET_CODE (pat
) == PARALLEL
)
4873 /* This happens for the fldXs,mb patterns. */
4874 pat
= XVECEXP (pat
, 0, 0);
4876 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4877 /* If this happens, we have to extend this to schedule
4878 optimally. Return 0 for now. */
4881 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
4883 if (! recog_memoized (dep_insn
))
4885 switch (get_attr_type (dep_insn
))
4889 case TYPE_FPSQRTSGL
:
4890 case TYPE_FPSQRTDBL
:
4891 /* An ALU flop can't be issued until two cycles before a
4892 preceding divide or sqrt operation has finished if
4893 the target of the ALU flop is any of the sources
4894 (or destination) of the divide or sqrt operation. */
4895 return insn_default_latency (dep_insn
) - 2;
4903 /* For other anti dependencies, the cost is 0. */
4906 case REG_DEP_OUTPUT
:
4907 /* Output dependency; DEP_INSN writes a register that INSN writes some
4909 if (attr_type
== TYPE_FPLOAD
)
4911 rtx pat
= PATTERN (insn
);
4912 rtx dep_pat
= PATTERN (dep_insn
);
4913 if (GET_CODE (pat
) == PARALLEL
)
4915 /* This happens for the fldXs,mb patterns. */
4916 pat
= XVECEXP (pat
, 0, 0);
4918 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4919 /* If this happens, we have to extend this to schedule
4920 optimally. Return 0 for now. */
4923 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
4925 if (! recog_memoized (dep_insn
))
4927 switch (get_attr_type (dep_insn
))
4934 case TYPE_FPSQRTSGL
:
4935 case TYPE_FPSQRTDBL
:
4936 /* A fpload can't be issued until one cycle before a
4937 preceding arithmetic operation has finished if
4938 the target of the fpload is the destination of the
4939 arithmetic operation.
4941 Exception: For PA7100LC, PA7200 and PA7300, the cost
4942 is 3 cycles, unless they bundle together. We also
4943 pay the penalty if the second insn is a fpload. */
4944 return insn_default_latency (dep_insn
) - 1;
4951 else if (attr_type
== TYPE_FPALU
)
4953 rtx pat
= PATTERN (insn
);
4954 rtx dep_pat
= PATTERN (dep_insn
);
4955 if (GET_CODE (pat
) == PARALLEL
)
4957 /* This happens for the fldXs,mb patterns. */
4958 pat
= XVECEXP (pat
, 0, 0);
4960 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4961 /* If this happens, we have to extend this to schedule
4962 optimally. Return 0 for now. */
4965 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
4967 if (! recog_memoized (dep_insn
))
4969 switch (get_attr_type (dep_insn
))
4973 case TYPE_FPSQRTSGL
:
4974 case TYPE_FPSQRTDBL
:
4975 /* An ALU flop can't be issued until two cycles before a
4976 preceding divide or sqrt operation has finished if
4977 the target of the ALU flop is also the target of
4978 the divide or sqrt operation. */
4979 return insn_default_latency (dep_insn
) - 2;
4987 /* For other output dependencies, the cost is 0. */
4995 /* The 700 can only issue a single insn at a time.
4996 The 7XXX processors can issue two insns at a time.
4997 The 8000 can issue 4 insns at a time. */
4999 pa_issue_rate (void)
5003 case PROCESSOR_700
: return 1;
5004 case PROCESSOR_7100
: return 2;
5005 case PROCESSOR_7100LC
: return 2;
5006 case PROCESSOR_7200
: return 2;
5007 case PROCESSOR_7300
: return 2;
5008 case PROCESSOR_8000
: return 4;
5017 /* Return any length plus adjustment needed by INSN which already has
5018 its length computed as LENGTH. Return LENGTH if no adjustment is
5021 Also compute the length of an inline block move here as it is too
5022 complicated to express as a length attribute in pa.md. */
5024 pa_adjust_insn_length (rtx_insn
*insn
, int length
)
5026 rtx pat
= PATTERN (insn
);
5028 /* If length is negative or undefined, provide initial length. */
5029 if ((unsigned int) length
>= INT_MAX
)
5031 if (GET_CODE (pat
) == SEQUENCE
)
5032 insn
= as_a
<rtx_insn
*> (XVECEXP (pat
, 0, 0));
5034 switch (get_attr_type (insn
))
5037 length
= pa_attr_length_millicode_call (insn
);
5040 length
= pa_attr_length_call (insn
, 0);
5043 length
= pa_attr_length_call (insn
, 1);
5046 length
= pa_attr_length_indirect_call (insn
);
5048 case TYPE_SH_FUNC_ADRS
:
5049 length
= pa_attr_length_millicode_call (insn
) + 20;
5056 /* Block move pattern. */
5057 if (NONJUMP_INSN_P (insn
)
5058 && GET_CODE (pat
) == PARALLEL
5059 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
5060 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
5061 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
5062 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
5063 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
5064 length
+= compute_movmem_length (insn
) - 4;
5065 /* Block clear pattern. */
5066 else if (NONJUMP_INSN_P (insn
)
5067 && GET_CODE (pat
) == PARALLEL
5068 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
5069 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
5070 && XEXP (XVECEXP (pat
, 0, 0), 1) == const0_rtx
5071 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
)
5072 length
+= compute_clrmem_length (insn
) - 4;
5073 /* Conditional branch with an unfilled delay slot. */
5074 else if (JUMP_P (insn
) && ! simplejump_p (insn
))
5076 /* Adjust a short backwards conditional with an unfilled delay slot. */
5077 if (GET_CODE (pat
) == SET
5079 && JUMP_LABEL (insn
) != NULL_RTX
5080 && ! forward_branch_p (insn
))
5082 else if (GET_CODE (pat
) == PARALLEL
5083 && get_attr_type (insn
) == TYPE_PARALLEL_BRANCH
5086 /* Adjust dbra insn with short backwards conditional branch with
5087 unfilled delay slot -- only for case where counter is in a
5088 general register register. */
5089 else if (GET_CODE (pat
) == PARALLEL
5090 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
5091 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
5092 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
5094 && ! forward_branch_p (insn
))
5100 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
5103 pa_print_operand_punct_valid_p (unsigned char code
)
5114 /* Print operand X (an rtx) in assembler syntax to file FILE.
5115 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5116 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5119 pa_print_operand (FILE *file
, rtx x
, int code
)
5124 /* Output a 'nop' if there's nothing for the delay slot. */
5125 if (dbr_sequence_length () == 0)
5126 fputs ("\n\tnop", file
);
5129 /* Output a nullification completer if there's nothing for the */
5130 /* delay slot or nullification is requested. */
5131 if (dbr_sequence_length () == 0 ||
5133 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
5137 /* Print out the second register name of a register pair.
5138 I.e., R (6) => 7. */
5139 fputs (reg_names
[REGNO (x
) + 1], file
);
5142 /* A register or zero. */
5144 || (x
== CONST0_RTX (DFmode
))
5145 || (x
== CONST0_RTX (SFmode
)))
5147 fputs ("%r0", file
);
5153 /* A register or zero (floating point). */
5155 || (x
== CONST0_RTX (DFmode
))
5156 || (x
== CONST0_RTX (SFmode
)))
5158 fputs ("%fr0", file
);
5167 xoperands
[0] = XEXP (XEXP (x
, 0), 0);
5168 xoperands
[1] = XVECEXP (XEXP (XEXP (x
, 0), 1), 0, 0);
5169 pa_output_global_address (file
, xoperands
[1], 0);
5170 fprintf (file
, "(%s)", reg_names
[REGNO (xoperands
[0])]);
5174 case 'C': /* Plain (C)ondition */
5176 switch (GET_CODE (x
))
5179 fputs ("=", file
); break;
5181 fputs ("<>", file
); break;
5183 fputs (">", file
); break;
5185 fputs (">=", file
); break;
5187 fputs (">>=", file
); break;
5189 fputs (">>", file
); break;
5191 fputs ("<", file
); break;
5193 fputs ("<=", file
); break;
5195 fputs ("<<=", file
); break;
5197 fputs ("<<", file
); break;
5202 case 'N': /* Condition, (N)egated */
5203 switch (GET_CODE (x
))
5206 fputs ("<>", file
); break;
5208 fputs ("=", file
); break;
5210 fputs ("<=", file
); break;
5212 fputs ("<", file
); break;
5214 fputs ("<<", file
); break;
5216 fputs ("<<=", file
); break;
5218 fputs (">=", file
); break;
5220 fputs (">", file
); break;
5222 fputs (">>", file
); break;
5224 fputs (">>=", file
); break;
5229 /* For floating point comparisons. Note that the output
5230 predicates are the complement of the desired mode. The
5231 conditions for GT, GE, LT, LE and LTGT cause an invalid
5232 operation exception if the result is unordered and this
5233 exception is enabled in the floating-point status register. */
5235 switch (GET_CODE (x
))
5238 fputs ("!=", file
); break;
5240 fputs ("=", file
); break;
5242 fputs ("!>", file
); break;
5244 fputs ("!>=", file
); break;
5246 fputs ("!<", file
); break;
5248 fputs ("!<=", file
); break;
5250 fputs ("!<>", file
); break;
5252 fputs ("!?<=", file
); break;
5254 fputs ("!?<", file
); break;
5256 fputs ("!?>=", file
); break;
5258 fputs ("!?>", file
); break;
5260 fputs ("!?=", file
); break;
5262 fputs ("!?", file
); break;
5264 fputs ("?", file
); break;
5269 case 'S': /* Condition, operands are (S)wapped. */
5270 switch (GET_CODE (x
))
5273 fputs ("=", file
); break;
5275 fputs ("<>", file
); break;
5277 fputs ("<", file
); break;
5279 fputs ("<=", file
); break;
5281 fputs ("<<=", file
); break;
5283 fputs ("<<", file
); break;
5285 fputs (">", file
); break;
5287 fputs (">=", file
); break;
5289 fputs (">>=", file
); break;
5291 fputs (">>", file
); break;
5296 case 'B': /* Condition, (B)oth swapped and negate. */
5297 switch (GET_CODE (x
))
5300 fputs ("<>", file
); break;
5302 fputs ("=", file
); break;
5304 fputs (">=", file
); break;
5306 fputs (">", file
); break;
5308 fputs (">>", file
); break;
5310 fputs (">>=", file
); break;
5312 fputs ("<=", file
); break;
5314 fputs ("<", file
); break;
5316 fputs ("<<", file
); break;
5318 fputs ("<<=", file
); break;
5324 gcc_assert (GET_CODE (x
) == CONST_INT
);
5325 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~INTVAL (x
));
5328 gcc_assert (GET_CODE (x
) == CONST_INT
);
5329 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - (INTVAL (x
) & 63));
5332 gcc_assert (GET_CODE (x
) == CONST_INT
);
5333 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - (INTVAL (x
) & 31));
5336 gcc_assert (GET_CODE (x
) == CONST_INT
5337 && (INTVAL (x
) == 1 || INTVAL (x
) == 2 || INTVAL (x
) == 3));
5338 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5341 gcc_assert (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0);
5342 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
5345 gcc_assert (GET_CODE (x
) == CONST_INT
);
5346 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 63 - (INTVAL (x
) & 63));
5349 gcc_assert (GET_CODE (x
) == CONST_INT
);
5350 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 31 - (INTVAL (x
) & 31));
5353 if (GET_CODE (x
) == CONST_INT
)
5358 switch (GET_CODE (XEXP (x
, 0)))
5362 if (ASSEMBLER_DIALECT
== 0)
5363 fputs ("s,mb", file
);
5365 fputs (",mb", file
);
5369 if (ASSEMBLER_DIALECT
== 0)
5370 fputs ("s,ma", file
);
5372 fputs (",ma", file
);
5375 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
5376 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
)
5378 if (ASSEMBLER_DIALECT
== 0)
5381 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
5382 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
5384 if (ASSEMBLER_DIALECT
== 0)
5385 fputs ("x,s", file
);
5389 else if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
5393 if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
5399 pa_output_global_address (file
, x
, 0);
5402 pa_output_global_address (file
, x
, 1);
5404 case 0: /* Don't do anything special */
5409 compute_zdepwi_operands (INTVAL (x
), op
);
5410 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
5416 compute_zdepdi_operands (INTVAL (x
), op
);
5417 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
5421 /* We can get here from a .vtable_inherit due to our
5422 CONSTANT_ADDRESS_P rejecting perfectly good constant
5428 if (GET_CODE (x
) == REG
)
5430 fputs (reg_names
[REGNO (x
)], file
);
5431 if (TARGET_64BIT
&& FP_REG_P (x
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4)
5437 && GET_MODE_SIZE (GET_MODE (x
)) <= 4
5438 && (REGNO (x
) & 1) == 0)
5441 else if (GET_CODE (x
) == MEM
)
5443 int size
= GET_MODE_SIZE (GET_MODE (x
));
5444 rtx base
= NULL_RTX
;
5445 switch (GET_CODE (XEXP (x
, 0)))
5449 base
= XEXP (XEXP (x
, 0), 0);
5450 fprintf (file
, "-%d(%s)", size
, reg_names
[REGNO (base
)]);
5454 base
= XEXP (XEXP (x
, 0), 0);
5455 fprintf (file
, "%d(%s)", size
, reg_names
[REGNO (base
)]);
5458 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
5459 fprintf (file
, "%s(%s)",
5460 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 0), 0))],
5461 reg_names
[REGNO (XEXP (XEXP (x
, 0), 1))]);
5462 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
5463 fprintf (file
, "%s(%s)",
5464 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 1), 0))],
5465 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
5466 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
5467 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
)
5469 /* Because the REG_POINTER flag can get lost during reload,
5470 pa_legitimate_address_p canonicalizes the order of the
5471 index and base registers in the combined move patterns. */
5472 rtx base
= XEXP (XEXP (x
, 0), 1);
5473 rtx index
= XEXP (XEXP (x
, 0), 0);
5475 fprintf (file
, "%s(%s)",
5476 reg_names
[REGNO (index
)], reg_names
[REGNO (base
)]);
5479 output_address (GET_MODE (x
), XEXP (x
, 0));
5482 output_address (GET_MODE (x
), XEXP (x
, 0));
5487 output_addr_const (file
, x
);
5490 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5493 pa_output_global_address (FILE *file
, rtx x
, int round_constant
)
5496 /* Imagine (high (const (plus ...))). */
5497 if (GET_CODE (x
) == HIGH
)
5500 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
, VOIDmode
))
5501 output_addr_const (file
, x
);
5502 else if (GET_CODE (x
) == SYMBOL_REF
&& !flag_pic
)
5504 output_addr_const (file
, x
);
5505 fputs ("-$global$", file
);
5507 else if (GET_CODE (x
) == CONST
)
5509 const char *sep
= "";
5510 int offset
= 0; /* assembler wants -$global$ at end */
5511 rtx base
= NULL_RTX
;
5513 switch (GET_CODE (XEXP (XEXP (x
, 0), 0)))
5517 base
= XEXP (XEXP (x
, 0), 0);
5518 output_addr_const (file
, base
);
5521 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
5527 switch (GET_CODE (XEXP (XEXP (x
, 0), 1)))
5531 base
= XEXP (XEXP (x
, 0), 1);
5532 output_addr_const (file
, base
);
5535 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
5541 /* How bogus. The compiler is apparently responsible for
5542 rounding the constant if it uses an LR field selector.
5544 The linker and/or assembler seem a better place since
5545 they have to do this kind of thing already.
5547 If we fail to do this, HP's optimizing linker may eliminate
5548 an addil, but not update the ldw/stw/ldo instruction that
5549 uses the result of the addil. */
5551 offset
= ((offset
+ 0x1000) & ~0x1fff);
5553 switch (GET_CODE (XEXP (x
, 0)))
5566 gcc_assert (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
);
5574 if (!read_only_operand (base
, VOIDmode
) && !flag_pic
)
5575 fputs ("-$global$", file
);
5577 fprintf (file
, "%s%d", sep
, offset
);
5580 output_addr_const (file
, x
);
5583 /* Output boilerplate text to appear at the beginning of the file.
5584 There are several possible versions. */
5585 #define aputs(x) fputs(x, asm_out_file)
5587 pa_file_start_level (void)
5590 aputs ("\t.LEVEL 2.0w\n");
5591 else if (TARGET_PA_20
)
5592 aputs ("\t.LEVEL 2.0\n");
5593 else if (TARGET_PA_11
)
5594 aputs ("\t.LEVEL 1.1\n");
5596 aputs ("\t.LEVEL 1.0\n");
5600 pa_file_start_space (int sortspace
)
5602 aputs ("\t.SPACE $PRIVATE$");
5605 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31");
5607 aputs ("\n\t.SUBSPA $TM_CLONE_TABLE$,QUAD=1,ALIGN=8,ACCESS=31");
5608 aputs ("\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5609 "\n\t.SPACE $TEXT$");
5612 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5613 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5617 pa_file_start_file (int want_version
)
5619 if (write_symbols
!= NO_DEBUG
)
5621 output_file_directive (asm_out_file
, main_input_filename
);
5623 aputs ("\t.version\t\"01.01\"\n");
5628 pa_file_start_mcount (const char *aswhat
)
5631 fprintf (asm_out_file
, "\t.IMPORT _mcount,%s\n", aswhat
);
5635 pa_elf_file_start (void)
5637 pa_file_start_level ();
5638 pa_file_start_mcount ("ENTRY");
5639 pa_file_start_file (0);
5643 pa_som_file_start (void)
5645 pa_file_start_level ();
5646 pa_file_start_space (0);
5647 aputs ("\t.IMPORT $global$,DATA\n"
5648 "\t.IMPORT $$dyncall,MILLICODE\n");
5649 pa_file_start_mcount ("CODE");
5650 pa_file_start_file (0);
5654 pa_linux_file_start (void)
5656 pa_file_start_file (1);
5657 pa_file_start_level ();
5658 pa_file_start_mcount ("CODE");
5662 pa_hpux64_gas_file_start (void)
5664 pa_file_start_level ();
5665 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5667 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, "_mcount", "function");
5669 pa_file_start_file (1);
5673 pa_hpux64_hpas_file_start (void)
5675 pa_file_start_level ();
5676 pa_file_start_space (1);
5677 pa_file_start_mcount ("CODE");
5678 pa_file_start_file (0);
5682 /* Search the deferred plabel list for SYMBOL and return its internal
5683 label. If an entry for SYMBOL is not found, a new entry is created. */
5686 pa_get_deferred_plabel (rtx symbol
)
5688 const char *fname
= XSTR (symbol
, 0);
5691 /* See if we have already put this function on the list of deferred
5692 plabels. This list is generally small, so a liner search is not
5693 too ugly. If it proves too slow replace it with something faster. */
5694 for (i
= 0; i
< n_deferred_plabels
; i
++)
5695 if (strcmp (fname
, XSTR (deferred_plabels
[i
].symbol
, 0)) == 0)
5698 /* If the deferred plabel list is empty, or this entry was not found
5699 on the list, create a new entry on the list. */
5700 if (deferred_plabels
== NULL
|| i
== n_deferred_plabels
)
5704 if (deferred_plabels
== 0)
5705 deferred_plabels
= ggc_alloc
<deferred_plabel
> ();
5707 deferred_plabels
= GGC_RESIZEVEC (struct deferred_plabel
,
5709 n_deferred_plabels
+ 1);
5711 i
= n_deferred_plabels
++;
5712 deferred_plabels
[i
].internal_label
= gen_label_rtx ();
5713 deferred_plabels
[i
].symbol
= symbol
;
5715 /* Gross. We have just implicitly taken the address of this
5716 function. Mark it in the same manner as assemble_name. */
5717 id
= maybe_get_identifier (targetm
.strip_name_encoding (fname
));
5719 mark_referenced (id
);
5722 return deferred_plabels
[i
].internal_label
;
5726 output_deferred_plabels (void)
5730 /* If we have some deferred plabels, then we need to switch into the
5731 data or readonly data section, and align it to a 4 byte boundary
5732 before outputting the deferred plabels. */
5733 if (n_deferred_plabels
)
5735 switch_to_section (flag_pic
? data_section
: readonly_data_section
);
5736 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
5739 /* Now output the deferred plabels. */
5740 for (i
= 0; i
< n_deferred_plabels
; i
++)
5742 targetm
.asm_out
.internal_label (asm_out_file
, "L",
5743 CODE_LABEL_NUMBER (deferred_plabels
[i
].internal_label
));
5744 assemble_integer (deferred_plabels
[i
].symbol
,
5745 TARGET_64BIT
? 8 : 4, TARGET_64BIT
? 64 : 32, 1);
5749 /* Initialize optabs to point to emulation routines. */
5752 pa_init_libfuncs (void)
5754 if (HPUX_LONG_DOUBLE_LIBRARY
)
5756 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
5757 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
5758 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
5759 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
5760 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qmin");
5761 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
5762 set_optab_libfunc (sqrt_optab
, TFmode
, "_U_Qfsqrt");
5763 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
5764 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
5766 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
5767 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
5768 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
5769 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
5770 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
5771 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
5772 set_optab_libfunc (unord_optab
, TFmode
, "_U_Qfunord");
5774 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
5775 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
5776 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
5777 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
5779 set_conv_libfunc (sfix_optab
, SImode
, TFmode
,
5780 TARGET_64BIT
? "__U_Qfcnvfxt_quad_to_sgl"
5781 : "_U_Qfcnvfxt_quad_to_sgl");
5782 set_conv_libfunc (sfix_optab
, DImode
, TFmode
,
5783 "_U_Qfcnvfxt_quad_to_dbl");
5784 set_conv_libfunc (ufix_optab
, SImode
, TFmode
,
5785 "_U_Qfcnvfxt_quad_to_usgl");
5786 set_conv_libfunc (ufix_optab
, DImode
, TFmode
,
5787 "_U_Qfcnvfxt_quad_to_udbl");
5789 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
,
5790 "_U_Qfcnvxf_sgl_to_quad");
5791 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
,
5792 "_U_Qfcnvxf_dbl_to_quad");
5793 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
,
5794 "_U_Qfcnvxf_usgl_to_quad");
5795 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
,
5796 "_U_Qfcnvxf_udbl_to_quad");
5799 if (TARGET_SYNC_LIBCALL
)
5800 init_sync_libfuncs (8);
5803 /* HP's millicode routines mean something special to the assembler.
5804 Keep track of which ones we have used. */
5806 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, end1000
};
5807 static void import_milli (enum millicodes
);
5808 static char imported
[(int) end1000
];
5809 static const char * const milli_names
[] = {"remI", "remU", "divI", "divU", "mulI"};
5810 static const char import_string
[] = ".IMPORT $$....,MILLICODE";
5811 #define MILLI_START 10
5814 import_milli (enum millicodes code
)
5816 char str
[sizeof (import_string
)];
5818 if (!imported
[(int) code
])
5820 imported
[(int) code
] = 1;
5821 strcpy (str
, import_string
);
5822 strncpy (str
+ MILLI_START
, milli_names
[(int) code
], 4);
5823 output_asm_insn (str
, 0);
5827 /* The register constraints have put the operands and return value in
5828 the proper registers. */
5831 pa_output_mul_insn (int unsignedp ATTRIBUTE_UNUSED
, rtx_insn
*insn
)
5833 import_milli (mulI
);
5834 return pa_output_millicode_call (insn
, gen_rtx_SYMBOL_REF (Pmode
, "$$mulI"));
5837 /* Emit the rtl for doing a division by a constant. */
5839 /* Do magic division millicodes exist for this value? */
5840 const int pa_magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5842 /* We'll use an array to keep track of the magic millicodes and
5843 whether or not we've used them already. [n][0] is signed, [n][1] is
5846 static int div_milli
[16][2];
5849 pa_emit_hpdiv_const (rtx
*operands
, int unsignedp
)
5851 if (GET_CODE (operands
[2]) == CONST_INT
5852 && INTVAL (operands
[2]) > 0
5853 && INTVAL (operands
[2]) < 16
5854 && pa_magic_milli
[INTVAL (operands
[2])])
5856 rtx ret
= gen_rtx_REG (SImode
, TARGET_64BIT
? 2 : 31);
5858 emit_move_insn (gen_rtx_REG (SImode
, 26), operands
[1]);
5862 gen_rtvec (6, gen_rtx_SET (gen_rtx_REG (SImode
, 29),
5863 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
5865 gen_rtx_REG (SImode
, 26),
5867 gen_rtx_CLOBBER (VOIDmode
, operands
[4]),
5868 gen_rtx_CLOBBER (VOIDmode
, operands
[3]),
5869 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 26)),
5870 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 25)),
5871 gen_rtx_CLOBBER (VOIDmode
, ret
))));
5872 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 29));
5879 pa_output_div_insn (rtx
*operands
, int unsignedp
, rtx_insn
*insn
)
5883 /* If the divisor is a constant, try to use one of the special
5885 if (GET_CODE (operands
[0]) == CONST_INT
)
5887 static char buf
[100];
5888 divisor
= INTVAL (operands
[0]);
5889 if (!div_milli
[divisor
][unsignedp
])
5891 div_milli
[divisor
][unsignedp
] = 1;
5893 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
5895 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
5899 sprintf (buf
, "$$divU_" HOST_WIDE_INT_PRINT_DEC
,
5900 INTVAL (operands
[0]));
5901 return pa_output_millicode_call (insn
,
5902 gen_rtx_SYMBOL_REF (SImode
, buf
));
5906 sprintf (buf
, "$$divI_" HOST_WIDE_INT_PRINT_DEC
,
5907 INTVAL (operands
[0]));
5908 return pa_output_millicode_call (insn
,
5909 gen_rtx_SYMBOL_REF (SImode
, buf
));
5912 /* Divisor isn't a special constant. */
5917 import_milli (divU
);
5918 return pa_output_millicode_call (insn
,
5919 gen_rtx_SYMBOL_REF (SImode
, "$$divU"));
5923 import_milli (divI
);
5924 return pa_output_millicode_call (insn
,
5925 gen_rtx_SYMBOL_REF (SImode
, "$$divI"));
5930 /* Output a $$rem millicode to do mod. */
5933 pa_output_mod_insn (int unsignedp
, rtx_insn
*insn
)
5937 import_milli (remU
);
5938 return pa_output_millicode_call (insn
,
5939 gen_rtx_SYMBOL_REF (SImode
, "$$remU"));
5943 import_milli (remI
);
5944 return pa_output_millicode_call (insn
,
5945 gen_rtx_SYMBOL_REF (SImode
, "$$remI"));
5950 pa_output_arg_descriptor (rtx_insn
*call_insn
)
5952 const char *arg_regs
[4];
5953 machine_mode arg_mode
;
5955 int i
, output_flag
= 0;
5958 /* We neither need nor want argument location descriptors for the
5959 64bit runtime environment or the ELF32 environment. */
5960 if (TARGET_64BIT
|| TARGET_ELF32
)
5963 for (i
= 0; i
< 4; i
++)
5966 /* Specify explicitly that no argument relocations should take place
5967 if using the portable runtime calling conventions. */
5968 if (TARGET_PORTABLE_RUNTIME
)
5970 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5975 gcc_assert (CALL_P (call_insn
));
5976 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
);
5977 link
; link
= XEXP (link
, 1))
5979 rtx use
= XEXP (link
, 0);
5981 if (! (GET_CODE (use
) == USE
5982 && GET_CODE (XEXP (use
, 0)) == REG
5983 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
5986 arg_mode
= GET_MODE (XEXP (use
, 0));
5987 regno
= REGNO (XEXP (use
, 0));
5988 if (regno
>= 23 && regno
<= 26)
5990 arg_regs
[26 - regno
] = "GR";
5991 if (arg_mode
== DImode
)
5992 arg_regs
[25 - regno
] = "GR";
5994 else if (regno
>= 32 && regno
<= 39)
5996 if (arg_mode
== SFmode
)
5997 arg_regs
[(regno
- 32) / 2] = "FR";
6000 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
6001 arg_regs
[(regno
- 34) / 2] = "FR";
6002 arg_regs
[(regno
- 34) / 2 + 1] = "FU";
6004 arg_regs
[(regno
- 34) / 2] = "FU";
6005 arg_regs
[(regno
- 34) / 2 + 1] = "FR";
6010 fputs ("\t.CALL ", asm_out_file
);
6011 for (i
= 0; i
< 4; i
++)
6016 fputc (',', asm_out_file
);
6017 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
6020 fputc ('\n', asm_out_file
);
6023 /* Inform reload about cases where moving X with a mode MODE to or from
6024 a register in RCLASS requires an extra scratch or immediate register.
6025 Return the class needed for the immediate register. */
6028 pa_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
6029 machine_mode mode
, secondary_reload_info
*sri
)
6032 enum reg_class rclass
= (enum reg_class
) rclass_i
;
6034 /* Handle the easy stuff first. */
6035 if (rclass
== R1_REGS
)
6041 if (rclass
== BASE_REG_CLASS
&& regno
< FIRST_PSEUDO_REGISTER
)
6047 /* If we have something like (mem (mem (...)), we can safely assume the
6048 inner MEM will end up in a general register after reloading, so there's
6049 no need for a secondary reload. */
6050 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == MEM
)
6053 /* Trying to load a constant into a FP register during PIC code
6054 generation requires %r1 as a scratch register. For float modes,
6055 the only legitimate constant is CONST0_RTX. However, there are
6056 a few patterns that accept constant double operands. */
6058 && FP_REG_CLASS_P (rclass
)
6059 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
6064 sri
->icode
= CODE_FOR_reload_insi_r1
;
6068 sri
->icode
= CODE_FOR_reload_indi_r1
;
6072 sri
->icode
= CODE_FOR_reload_insf_r1
;
6076 sri
->icode
= CODE_FOR_reload_indf_r1
;
6085 /* Secondary reloads of symbolic expressions require %r1 as a scratch
6086 register when we're generating PIC code or when the operand isn't
6088 if (pa_symbolic_expression_p (x
))
6090 if (GET_CODE (x
) == HIGH
)
6093 if (flag_pic
|| !read_only_operand (x
, VOIDmode
))
6098 sri
->icode
= CODE_FOR_reload_insi_r1
;
6102 sri
->icode
= CODE_FOR_reload_indi_r1
;
6112 /* Profiling showed the PA port spends about 1.3% of its compilation
6113 time in true_regnum from calls inside pa_secondary_reload_class. */
6114 if (regno
>= FIRST_PSEUDO_REGISTER
|| GET_CODE (x
) == SUBREG
)
6115 regno
= true_regnum (x
);
6117 /* Handle reloads for floating point loads and stores. */
6118 if ((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
6119 && FP_REG_CLASS_P (rclass
))
6125 /* We don't need a secondary reload for indexed memory addresses.
6127 When INT14_OK_STRICT is true, it might appear that we could
6128 directly allow register indirect memory addresses. However,
6129 this doesn't work because we don't support SUBREGs in
6130 floating-point register copies and reload doesn't tell us
6131 when it's going to use a SUBREG. */
6132 if (IS_INDEX_ADDR_P (x
))
6136 /* Request a secondary reload with a general scratch register
6137 for everything else. ??? Could symbolic operands be handled
6138 directly when generating non-pic PA 2.0 code? */
6140 ? direct_optab_handler (reload_in_optab
, mode
)
6141 : direct_optab_handler (reload_out_optab
, mode
));
6145 /* A SAR<->FP register copy requires an intermediate general register
6146 and secondary memory. We need a secondary reload with a general
6147 scratch register for spills. */
6148 if (rclass
== SHIFT_REGS
)
6151 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
< 0)
6154 ? direct_optab_handler (reload_in_optab
, mode
)
6155 : direct_optab_handler (reload_out_optab
, mode
));
6159 /* Handle FP copy. */
6160 if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno
)))
6161 return GENERAL_REGS
;
6164 if (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
6165 && REGNO_REG_CLASS (regno
) == SHIFT_REGS
6166 && FP_REG_CLASS_P (rclass
))
6167 return GENERAL_REGS
;
6172 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. */
6175 pa_secondary_memory_needed (machine_mode mode ATTRIBUTE_UNUSED
,
6176 reg_class_t class1 ATTRIBUTE_UNUSED
,
6177 reg_class_t class2 ATTRIBUTE_UNUSED
)
6179 #ifdef PA_SECONDARY_MEMORY_NEEDED
6180 return PA_SECONDARY_MEMORY_NEEDED (mode
, class1
, class2
);
6186 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
6187 is only marked as live on entry by df-scan when it is a fixed
6188 register. It isn't a fixed register in the 64-bit runtime,
6189 so we need to mark it here. */
6192 pa_extra_live_on_entry (bitmap regs
)
6195 bitmap_set_bit (regs
, ARG_POINTER_REGNUM
);
6198 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
6199 to prevent it from being deleted. */
6202 pa_eh_return_handler_rtx (void)
6206 tmp
= gen_rtx_PLUS (word_mode
, hard_frame_pointer_rtx
,
6207 TARGET_64BIT
? GEN_INT (-16) : GEN_INT (-20));
6208 tmp
= gen_rtx_MEM (word_mode
, tmp
);
6213 /* In the 32-bit runtime, arguments larger than eight bytes are passed
6214 by invisible reference. As a GCC extension, we also pass anything
6215 with a zero or variable size by reference.
6217 The 64-bit runtime does not describe passing any types by invisible
6218 reference. The internals of GCC can't currently handle passing
6219 empty structures, and zero or variable length arrays when they are
6220 not passed entirely on the stack or by reference. Thus, as a GCC
6221 extension, we pass these types by reference. The HP compiler doesn't
6222 support these types, so hopefully there shouldn't be any compatibility
6223 issues. This may have to be revisited when HP releases a C99 compiler
6224 or updates the ABI. */
6227 pa_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
6228 machine_mode mode
, const_tree type
,
6229 bool named ATTRIBUTE_UNUSED
)
6234 size
= int_size_in_bytes (type
);
6236 size
= GET_MODE_SIZE (mode
);
6241 return size
<= 0 || size
> 8;
6244 /* Implement TARGET_FUNCTION_ARG_PADDING. */
6246 static pad_direction
6247 pa_function_arg_padding (machine_mode mode
, const_tree type
)
6252 && (AGGREGATE_TYPE_P (type
)
6253 || TREE_CODE (type
) == COMPLEX_TYPE
6254 || TREE_CODE (type
) == VECTOR_TYPE
)))
6256 /* Return PAD_NONE if justification is not required. */
6258 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
6259 && (int_size_in_bytes (type
) * BITS_PER_UNIT
) % PARM_BOUNDARY
== 0)
6262 /* The directions set here are ignored when a BLKmode argument larger
6263 than a word is placed in a register. Different code is used for
6264 the stack and registers. This makes it difficult to have a
6265 consistent data representation for both the stack and registers.
6266 For both runtimes, the justification and padding for arguments on
6267 the stack and in registers should be identical. */
6269 /* The 64-bit runtime specifies left justification for aggregates. */
6272 /* The 32-bit runtime architecture specifies right justification.
6273 When the argument is passed on the stack, the argument is padded
6274 with garbage on the left. The HP compiler pads with zeros. */
6275 return PAD_DOWNWARD
;
6278 if (GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
6279 return PAD_DOWNWARD
;
6285 /* Do what is necessary for `va_start'. We look at the current function
6286 to determine if stdargs or varargs is used and fill in an initial
6287 va_list. A pointer to this constructor is returned. */
6290 hppa_builtin_saveregs (void)
6293 tree fntype
= TREE_TYPE (current_function_decl
);
6294 int argadj
= ((!stdarg_p (fntype
))
6295 ? UNITS_PER_WORD
: 0);
6298 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, argadj
);
6300 offset
= crtl
->args
.arg_offset_rtx
;
6306 /* Adjust for varargs/stdarg differences. */
6308 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, -argadj
);
6310 offset
= crtl
->args
.arg_offset_rtx
;
6312 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6313 from the incoming arg pointer and growing to larger addresses. */
6314 for (i
= 26, off
= -64; i
>= 19; i
--, off
+= 8)
6315 emit_move_insn (gen_rtx_MEM (word_mode
,
6316 plus_constant (Pmode
,
6317 arg_pointer_rtx
, off
)),
6318 gen_rtx_REG (word_mode
, i
));
6320 /* The incoming args pointer points just beyond the flushback area;
6321 normally this is not a serious concern. However, when we are doing
6322 varargs/stdargs we want to make the arg pointer point to the start
6323 of the incoming argument area. */
6324 emit_move_insn (virtual_incoming_args_rtx
,
6325 plus_constant (Pmode
, arg_pointer_rtx
, -64));
6327 /* Now return a pointer to the first anonymous argument. */
6328 return copy_to_reg (expand_binop (Pmode
, add_optab
,
6329 virtual_incoming_args_rtx
,
6330 offset
, 0, 0, OPTAB_LIB_WIDEN
));
6333 /* Store general registers on the stack. */
6334 dest
= gen_rtx_MEM (BLKmode
,
6335 plus_constant (Pmode
, crtl
->args
.internal_arg_pointer
,
6337 set_mem_alias_set (dest
, get_varargs_alias_set ());
6338 set_mem_align (dest
, BITS_PER_WORD
);
6339 move_block_from_reg (23, dest
, 4);
6341 /* move_block_from_reg will emit code to store the argument registers
6342 individually as scalar stores.
6344 However, other insns may later load from the same addresses for
6345 a structure load (passing a struct to a varargs routine).
6347 The alias code assumes that such aliasing can never happen, so we
6348 have to keep memory referencing insns from moving up beyond the
6349 last argument register store. So we emit a blockage insn here. */
6350 emit_insn (gen_blockage ());
6352 return copy_to_reg (expand_binop (Pmode
, add_optab
,
6353 crtl
->args
.internal_arg_pointer
,
6354 offset
, 0, 0, OPTAB_LIB_WIDEN
));
6358 hppa_va_start (tree valist
, rtx nextarg
)
6360 nextarg
= expand_builtin_saveregs ();
6361 std_expand_builtin_va_start (valist
, nextarg
);
6365 hppa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6370 /* Args grow upward. We can use the generic routines. */
6371 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6373 else /* !TARGET_64BIT */
6375 tree ptr
= build_pointer_type (type
);
6378 unsigned int size
, ofs
;
6381 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6385 ptr
= build_pointer_type (type
);
6387 size
= int_size_in_bytes (type
);
6388 valist_type
= TREE_TYPE (valist
);
6390 /* Args grow down. Not handled by generic routines. */
6392 u
= fold_convert (sizetype
, size_in_bytes (type
));
6393 u
= fold_build1 (NEGATE_EXPR
, sizetype
, u
);
6394 t
= fold_build_pointer_plus (valist
, u
);
6396 /* Align to 4 or 8 byte boundary depending on argument size. */
6398 u
= build_int_cst (TREE_TYPE (t
), (HOST_WIDE_INT
)(size
> 4 ? -8 : -4));
6399 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6400 t
= fold_convert (valist_type
, t
);
6402 t
= build2 (MODIFY_EXPR
, valist_type
, valist
, t
);
6404 ofs
= (8 - size
) % 4;
6406 t
= fold_build_pointer_plus_hwi (t
, ofs
);
6408 t
= fold_convert (ptr
, t
);
6409 t
= build_va_arg_indirect_ref (t
);
6412 t
= build_va_arg_indirect_ref (t
);
6418 /* True if MODE is valid for the target. By "valid", we mean able to
6419 be manipulated in non-trivial ways. In particular, this means all
6420 the arithmetic is supported.
6422 Currently, TImode is not valid as the HP 64-bit runtime documentation
6423 doesn't document the alignment and calling conventions for this type.
6424 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6425 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6428 pa_scalar_mode_supported_p (scalar_mode mode
)
6430 int precision
= GET_MODE_PRECISION (mode
);
6432 switch (GET_MODE_CLASS (mode
))
6434 case MODE_PARTIAL_INT
:
6436 if (precision
== CHAR_TYPE_SIZE
)
6438 if (precision
== SHORT_TYPE_SIZE
)
6440 if (precision
== INT_TYPE_SIZE
)
6442 if (precision
== LONG_TYPE_SIZE
)
6444 if (precision
== LONG_LONG_TYPE_SIZE
)
6449 if (precision
== FLOAT_TYPE_SIZE
)
6451 if (precision
== DOUBLE_TYPE_SIZE
)
6453 if (precision
== LONG_DOUBLE_TYPE_SIZE
)
6457 case MODE_DECIMAL_FLOAT
:
6465 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6466 it branches into the delay slot. Otherwise, return FALSE. */
6469 branch_to_delay_slot_p (rtx_insn
*insn
)
6471 rtx_insn
*jump_insn
;
6473 if (dbr_sequence_length ())
6476 jump_insn
= next_active_insn (JUMP_LABEL_AS_INSN (insn
));
6479 insn
= next_active_insn (insn
);
6480 if (jump_insn
== insn
)
6483 /* We can't rely on the length of asms. So, we return FALSE when
6484 the branch is followed by an asm. */
6486 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
6487 || asm_noperands (PATTERN (insn
)) >= 0
6488 || get_attr_length (insn
) > 0)
6495 /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
6497 This occurs when INSN has an unfilled delay slot and is followed
6498 by an asm. Disaster can occur if the asm is empty and the jump
6499 branches into the delay slot. So, we add a nop in the delay slot
6500 when this occurs. */
6503 branch_needs_nop_p (rtx_insn
*insn
)
6505 rtx_insn
*jump_insn
;
6507 if (dbr_sequence_length ())
6510 jump_insn
= next_active_insn (JUMP_LABEL_AS_INSN (insn
));
6513 insn
= next_active_insn (insn
);
6514 if (!insn
|| jump_insn
== insn
)
6517 if (!(GET_CODE (PATTERN (insn
)) == ASM_INPUT
6518 || asm_noperands (PATTERN (insn
)) >= 0)
6519 && get_attr_length (insn
) > 0)
6526 /* Return TRUE if INSN, a forward jump insn, can use nullification
6527 to skip the following instruction. This avoids an extra cycle due
6528 to a mis-predicted branch when we fall through. */
6531 use_skip_p (rtx_insn
*insn
)
6533 rtx_insn
*jump_insn
= next_active_insn (JUMP_LABEL_AS_INSN (insn
));
6537 insn
= next_active_insn (insn
);
6539 /* We can't rely on the length of asms, so we can't skip asms. */
6541 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
6542 || asm_noperands (PATTERN (insn
)) >= 0)
6544 if (get_attr_length (insn
) == 4
6545 && jump_insn
== next_active_insn (insn
))
6547 if (get_attr_length (insn
) > 0)
6554 /* This routine handles all the normal conditional branch sequences we
6555 might need to generate. It handles compare immediate vs compare
6556 register, nullification of delay slots, varying length branches,
6557 negated branches, and all combinations of the above. It returns the
6558 output appropriate to emit the branch corresponding to all given
6562 pa_output_cbranch (rtx
*operands
, int negated
, rtx_insn
*insn
)
6564 static char buf
[100];
6566 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
6567 int length
= get_attr_length (insn
);
6570 /* A conditional branch to the following instruction (e.g. the delay slot)
6571 is asking for a disaster. This can happen when not optimizing and
6572 when jump optimization fails.
6574 While it is usually safe to emit nothing, this can fail if the
6575 preceding instruction is a nullified branch with an empty delay
6576 slot and the same branch target as this branch. We could check
6577 for this but jump optimization should eliminate nop jumps. It
6578 is always safe to emit a nop. */
6579 if (branch_to_delay_slot_p (insn
))
6582 /* The doubleword form of the cmpib instruction doesn't have the LEU
6583 and GTU conditions while the cmpb instruction does. Since we accept
6584 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6585 if (GET_MODE (operands
[1]) == DImode
&& operands
[2] == const0_rtx
)
6586 operands
[2] = gen_rtx_REG (DImode
, 0);
6587 if (GET_MODE (operands
[2]) == DImode
&& operands
[1] == const0_rtx
)
6588 operands
[1] = gen_rtx_REG (DImode
, 0);
6590 /* If this is a long branch with its delay slot unfilled, set `nullify'
6591 as it can nullify the delay slot and save a nop. */
6592 if (length
== 8 && dbr_sequence_length () == 0)
6595 /* If this is a short forward conditional branch which did not get
6596 its delay slot filled, the delay slot can still be nullified. */
6597 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
6598 nullify
= forward_branch_p (insn
);
6600 /* A forward branch over a single nullified insn can be done with a
6601 comclr instruction. This avoids a single cycle penalty due to
6602 mis-predicted branch if we fall through (branch not taken). */
6603 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
6607 /* All short conditional branches except backwards with an unfilled
6611 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
6613 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6614 if (GET_MODE (operands
[1]) == DImode
)
6617 strcat (buf
, "%B3");
6619 strcat (buf
, "%S3");
6621 strcat (buf
, " %2,%r1,%%r0");
6624 if (branch_needs_nop_p (insn
))
6625 strcat (buf
, ",n %2,%r1,%0%#");
6627 strcat (buf
, ",n %2,%r1,%0");
6630 strcat (buf
, " %2,%r1,%0");
6633 /* All long conditionals. Note a short backward branch with an
6634 unfilled delay slot is treated just like a long backward branch
6635 with an unfilled delay slot. */
6637 /* Handle weird backwards branch with a filled delay slot
6638 which is nullified. */
6639 if (dbr_sequence_length () != 0
6640 && ! forward_branch_p (insn
)
6643 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6644 if (GET_MODE (operands
[1]) == DImode
)
6647 strcat (buf
, "%S3");
6649 strcat (buf
, "%B3");
6650 strcat (buf
, ",n %2,%r1,.+12\n\tb %0");
6652 /* Handle short backwards branch with an unfilled delay slot.
6653 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6654 taken and untaken branches. */
6655 else if (dbr_sequence_length () == 0
6656 && ! forward_branch_p (insn
)
6657 && INSN_ADDRESSES_SET_P ()
6658 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
6659 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
6661 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6662 if (GET_MODE (operands
[1]) == DImode
)
6665 strcat (buf
, "%B3 %2,%r1,%0%#");
6667 strcat (buf
, "%S3 %2,%r1,%0%#");
6671 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
6672 if (GET_MODE (operands
[1]) == DImode
)
6675 strcat (buf
, "%S3");
6677 strcat (buf
, "%B3");
6679 strcat (buf
, " %2,%r1,%%r0\n\tb,n %0");
6681 strcat (buf
, " %2,%r1,%%r0\n\tb %0");
6686 /* The reversed conditional branch must branch over one additional
6687 instruction if the delay slot is filled and needs to be extracted
6688 by pa_output_lbranch. If the delay slot is empty or this is a
6689 nullified forward branch, the instruction after the reversed
6690 condition branch must be nullified. */
6691 if (dbr_sequence_length () == 0
6692 || (nullify
&& forward_branch_p (insn
)))
6696 operands
[4] = GEN_INT (length
);
6701 operands
[4] = GEN_INT (length
+ 4);
6704 /* Create a reversed conditional branch which branches around
6705 the following insns. */
6706 if (GET_MODE (operands
[1]) != DImode
)
6712 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6715 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6721 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6724 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6733 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6736 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6742 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6745 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6749 output_asm_insn (buf
, operands
);
6750 return pa_output_lbranch (operands
[0], insn
, xdelay
);
6755 /* Output a PIC pc-relative instruction sequence to load the address of
6756 OPERANDS[0] to register OPERANDS[2]. OPERANDS[0] is a symbol ref
6757 or a code label. OPERANDS[1] specifies the register to use to load
6758 the program counter. OPERANDS[3] may be used for label generation
6759 The sequence is always three instructions in length. The program
6760 counter recorded for PA 1.X is eight bytes more than that for PA 2.0.
6761 Register %r1 is clobbered. */
6764 pa_output_pic_pcrel_sequence (rtx
*operands
)
6766 gcc_assert (SYMBOL_REF_P (operands
[0]) || LABEL_P (operands
[0]));
6769 /* We can use mfia to determine the current program counter. */
6770 if (TARGET_SOM
|| !TARGET_GAS
)
6772 operands
[3] = gen_label_rtx ();
6773 targetm
.asm_out
.internal_label (asm_out_file
, "L",
6774 CODE_LABEL_NUMBER (operands
[3]));
6775 output_asm_insn ("mfia %1", operands
);
6776 output_asm_insn ("addil L'%0-%l3,%1", operands
);
6777 output_asm_insn ("ldo R'%0-%l3(%%r1),%2", operands
);
6781 output_asm_insn ("mfia %1", operands
);
6782 output_asm_insn ("addil L'%0-$PIC_pcrel$0+12,%1", operands
);
6783 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+16(%%r1),%2", operands
);
6788 /* We need to use a branch to determine the current program counter. */
6789 output_asm_insn ("{bl|b,l} .+8,%1", operands
);
6790 if (TARGET_SOM
|| !TARGET_GAS
)
6792 operands
[3] = gen_label_rtx ();
6793 output_asm_insn ("addil L'%0-%l3,%1", operands
);
6794 targetm
.asm_out
.internal_label (asm_out_file
, "L",
6795 CODE_LABEL_NUMBER (operands
[3]));
6796 output_asm_insn ("ldo R'%0-%l3(%%r1),%2", operands
);
6800 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%1", operands
);
6801 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%2", operands
);
6806 /* This routine handles output of long unconditional branches that
6807 exceed the maximum range of a simple branch instruction. Since
6808 we don't have a register available for the branch, we save register
6809 %r1 in the frame marker, load the branch destination DEST into %r1,
6810 execute the branch, and restore %r1 in the delay slot of the branch.
6812 Since long branches may have an insn in the delay slot and the
6813 delay slot is used to restore %r1, we in general need to extract
6814 this insn and execute it before the branch. However, to facilitate
6815 use of this function by conditional branches, we also provide an
6816 option to not extract the delay insn so that it will be emitted
6817 after the long branch. So, if there is an insn in the delay slot,
6818 it is extracted if XDELAY is nonzero.
6820 The lengths of the various long-branch sequences are 20, 16 and 24
6821 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6824 pa_output_lbranch (rtx dest
, rtx_insn
*insn
, int xdelay
)
6828 xoperands
[0] = dest
;
6830 /* First, free up the delay slot. */
6831 if (xdelay
&& dbr_sequence_length () != 0)
6833 /* We can't handle a jump in the delay slot. */
6834 gcc_assert (! JUMP_P (NEXT_INSN (insn
)));
6836 final_scan_insn (NEXT_INSN (insn
), asm_out_file
,
6839 /* Now delete the delay insn. */
6840 SET_INSN_DELETED (NEXT_INSN (insn
));
6843 /* Output an insn to save %r1. The runtime documentation doesn't
6844 specify whether the "Clean Up" slot in the callers frame can
6845 be clobbered by the callee. It isn't copied by HP's builtin
6846 alloca, so this suggests that it can be clobbered if necessary.
6847 The "Static Link" location is copied by HP builtin alloca, so
6848 we avoid using it. Using the cleanup slot might be a problem
6849 if we have to interoperate with languages that pass cleanup
6850 information. However, it should be possible to handle these
6851 situations with GCC's asm feature.
6853 The "Current RP" slot is reserved for the called procedure, so
6854 we try to use it when we don't have a frame of our own. It's
6855 rather unlikely that we won't have a frame when we need to emit
6858 Really the way to go long term is a register scavenger; goto
6859 the target of the jump and find a register which we can use
6860 as a scratch to hold the value in %r1. Then, we wouldn't have
6861 to free up the delay slot or clobber a slot that may be needed
6862 for other purposes. */
6865 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6866 /* Use the return pointer slot in the frame marker. */
6867 output_asm_insn ("std %%r1,-16(%%r30)", xoperands
);
6869 /* Use the slot at -40 in the frame marker since HP builtin
6870 alloca doesn't copy it. */
6871 output_asm_insn ("std %%r1,-40(%%r30)", xoperands
);
6875 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6876 /* Use the return pointer slot in the frame marker. */
6877 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands
);
6879 /* Use the "Clean Up" slot in the frame marker. In GCC,
6880 the only other use of this location is for copying a
6881 floating point double argument from a floating-point
6882 register to two general registers. The copy is done
6883 as an "atomic" operation when outputting a call, so it
6884 won't interfere with our using the location here. */
6885 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands
);
6888 if (TARGET_PORTABLE_RUNTIME
)
6890 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
6891 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands
);
6892 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
6896 xoperands
[1] = gen_rtx_REG (Pmode
, 1);
6897 xoperands
[2] = xoperands
[1];
6898 pa_output_pic_pcrel_sequence (xoperands
);
6899 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
6902 /* Now output a very long branch to the original target. */
6903 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands
);
6905 /* Now restore the value of %r1 in the delay slot. */
6908 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6909 return "ldd -16(%%r30),%%r1";
6911 return "ldd -40(%%r30),%%r1";
6915 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6916 return "ldw -20(%%r30),%%r1";
6918 return "ldw -12(%%r30),%%r1";
6922 /* This routine handles all the branch-on-bit conditional branch sequences we
6923 might need to generate. It handles nullification of delay slots,
6924 varying length branches, negated branches and all combinations of the
6925 above. it returns the appropriate output template to emit the branch. */
6928 pa_output_bb (rtx
*operands ATTRIBUTE_UNUSED
, int negated
, rtx_insn
*insn
, int which
)
6930 static char buf
[100];
6932 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
6933 int length
= get_attr_length (insn
);
6936 /* A conditional branch to the following instruction (e.g. the delay slot) is
6937 asking for a disaster. I do not think this can happen as this pattern
6938 is only used when optimizing; jump optimization should eliminate the
6939 jump. But be prepared just in case. */
6941 if (branch_to_delay_slot_p (insn
))
6944 /* If this is a long branch with its delay slot unfilled, set `nullify'
6945 as it can nullify the delay slot and save a nop. */
6946 if (length
== 8 && dbr_sequence_length () == 0)
6949 /* If this is a short forward conditional branch which did not get
6950 its delay slot filled, the delay slot can still be nullified. */
6951 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
6952 nullify
= forward_branch_p (insn
);
6954 /* A forward branch over a single nullified insn can be done with a
6955 extrs instruction. This avoids a single cycle penalty due to
6956 mis-predicted branch if we fall through (branch not taken). */
6957 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
6962 /* All short conditional branches except backwards with an unfilled
6966 strcpy (buf
, "{extrs,|extrw,s,}");
6968 strcpy (buf
, "bb,");
6969 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
6970 strcpy (buf
, "extrd,s,*");
6971 else if (GET_MODE (operands
[0]) == DImode
)
6972 strcpy (buf
, "bb,*");
6973 if ((which
== 0 && negated
)
6974 || (which
== 1 && ! negated
))
6979 strcat (buf
, " %0,%1,1,%%r0");
6980 else if (nullify
&& negated
)
6982 if (branch_needs_nop_p (insn
))
6983 strcat (buf
, ",n %0,%1,%3%#");
6985 strcat (buf
, ",n %0,%1,%3");
6987 else if (nullify
&& ! negated
)
6989 if (branch_needs_nop_p (insn
))
6990 strcat (buf
, ",n %0,%1,%2%#");
6992 strcat (buf
, ",n %0,%1,%2");
6994 else if (! nullify
&& negated
)
6995 strcat (buf
, " %0,%1,%3");
6996 else if (! nullify
&& ! negated
)
6997 strcat (buf
, " %0,%1,%2");
7000 /* All long conditionals. Note a short backward branch with an
7001 unfilled delay slot is treated just like a long backward branch
7002 with an unfilled delay slot. */
7004 /* Handle weird backwards branch with a filled delay slot
7005 which is nullified. */
7006 if (dbr_sequence_length () != 0
7007 && ! forward_branch_p (insn
)
7010 strcpy (buf
, "bb,");
7011 if (GET_MODE (operands
[0]) == DImode
)
7013 if ((which
== 0 && negated
)
7014 || (which
== 1 && ! negated
))
7019 strcat (buf
, ",n %0,%1,.+12\n\tb %3");
7021 strcat (buf
, ",n %0,%1,.+12\n\tb %2");
7023 /* Handle short backwards branch with an unfilled delay slot.
7024 Using a bb;nop rather than extrs;bl saves 1 cycle for both
7025 taken and untaken branches. */
7026 else if (dbr_sequence_length () == 0
7027 && ! forward_branch_p (insn
)
7028 && INSN_ADDRESSES_SET_P ()
7029 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7030 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7032 strcpy (buf
, "bb,");
7033 if (GET_MODE (operands
[0]) == DImode
)
7035 if ((which
== 0 && negated
)
7036 || (which
== 1 && ! negated
))
7041 strcat (buf
, " %0,%1,%3%#");
7043 strcat (buf
, " %0,%1,%2%#");
7047 if (GET_MODE (operands
[0]) == DImode
)
7048 strcpy (buf
, "extrd,s,*");
7050 strcpy (buf
, "{extrs,|extrw,s,}");
7051 if ((which
== 0 && negated
)
7052 || (which
== 1 && ! negated
))
7056 if (nullify
&& negated
)
7057 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %3");
7058 else if (nullify
&& ! negated
)
7059 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %2");
7061 strcat (buf
, " %0,%1,1,%%r0\n\tb %3");
7063 strcat (buf
, " %0,%1,1,%%r0\n\tb %2");
7068 /* The reversed conditional branch must branch over one additional
7069 instruction if the delay slot is filled and needs to be extracted
7070 by pa_output_lbranch. If the delay slot is empty or this is a
7071 nullified forward branch, the instruction after the reversed
7072 condition branch must be nullified. */
7073 if (dbr_sequence_length () == 0
7074 || (nullify
&& forward_branch_p (insn
)))
7078 operands
[4] = GEN_INT (length
);
7083 operands
[4] = GEN_INT (length
+ 4);
7086 if (GET_MODE (operands
[0]) == DImode
)
7087 strcpy (buf
, "bb,*");
7089 strcpy (buf
, "bb,");
7090 if ((which
== 0 && negated
)
7091 || (which
== 1 && !negated
))
7096 strcat (buf
, ",n %0,%1,.+%4");
7098 strcat (buf
, " %0,%1,.+%4");
7099 output_asm_insn (buf
, operands
);
7100 return pa_output_lbranch (negated
? operands
[3] : operands
[2],
7106 /* This routine handles all the branch-on-variable-bit conditional branch
7107 sequences we might need to generate. It handles nullification of delay
7108 slots, varying length branches, negated branches and all combinations
7109 of the above. it returns the appropriate output template to emit the
7113 pa_output_bvb (rtx
*operands ATTRIBUTE_UNUSED
, int negated
, rtx_insn
*insn
,
7116 static char buf
[100];
7118 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7119 int length
= get_attr_length (insn
);
7122 /* A conditional branch to the following instruction (e.g. the delay slot) is
7123 asking for a disaster. I do not think this can happen as this pattern
7124 is only used when optimizing; jump optimization should eliminate the
7125 jump. But be prepared just in case. */
7127 if (branch_to_delay_slot_p (insn
))
7130 /* If this is a long branch with its delay slot unfilled, set `nullify'
7131 as it can nullify the delay slot and save a nop. */
7132 if (length
== 8 && dbr_sequence_length () == 0)
7135 /* If this is a short forward conditional branch which did not get
7136 its delay slot filled, the delay slot can still be nullified. */
7137 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7138 nullify
= forward_branch_p (insn
);
7140 /* A forward branch over a single nullified insn can be done with a
7141 extrs instruction. This avoids a single cycle penalty due to
7142 mis-predicted branch if we fall through (branch not taken). */
7143 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
7148 /* All short conditional branches except backwards with an unfilled
7152 strcpy (buf
, "{vextrs,|extrw,s,}");
7154 strcpy (buf
, "{bvb,|bb,}");
7155 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
7156 strcpy (buf
, "extrd,s,*");
7157 else if (GET_MODE (operands
[0]) == DImode
)
7158 strcpy (buf
, "bb,*");
7159 if ((which
== 0 && negated
)
7160 || (which
== 1 && ! negated
))
7165 strcat (buf
, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
7166 else if (nullify
&& negated
)
7168 if (branch_needs_nop_p (insn
))
7169 strcat (buf
, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
7171 strcat (buf
, "{,n %0,%3|,n %0,%%sar,%3}");
7173 else if (nullify
&& ! negated
)
7175 if (branch_needs_nop_p (insn
))
7176 strcat (buf
, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
7178 strcat (buf
, "{,n %0,%2|,n %0,%%sar,%2}");
7180 else if (! nullify
&& negated
)
7181 strcat (buf
, "{ %0,%3| %0,%%sar,%3}");
7182 else if (! nullify
&& ! negated
)
7183 strcat (buf
, "{ %0,%2| %0,%%sar,%2}");
7186 /* All long conditionals. Note a short backward branch with an
7187 unfilled delay slot is treated just like a long backward branch
7188 with an unfilled delay slot. */
7190 /* Handle weird backwards branch with a filled delay slot
7191 which is nullified. */
7192 if (dbr_sequence_length () != 0
7193 && ! forward_branch_p (insn
)
7196 strcpy (buf
, "{bvb,|bb,}");
7197 if (GET_MODE (operands
[0]) == DImode
)
7199 if ((which
== 0 && negated
)
7200 || (which
== 1 && ! negated
))
7205 strcat (buf
, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
7207 strcat (buf
, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
7209 /* Handle short backwards branch with an unfilled delay slot.
7210 Using a bb;nop rather than extrs;bl saves 1 cycle for both
7211 taken and untaken branches. */
7212 else if (dbr_sequence_length () == 0
7213 && ! forward_branch_p (insn
)
7214 && INSN_ADDRESSES_SET_P ()
7215 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7216 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7218 strcpy (buf
, "{bvb,|bb,}");
7219 if (GET_MODE (operands
[0]) == DImode
)
7221 if ((which
== 0 && negated
)
7222 || (which
== 1 && ! negated
))
7227 strcat (buf
, "{ %0,%3%#| %0,%%sar,%3%#}");
7229 strcat (buf
, "{ %0,%2%#| %0,%%sar,%2%#}");
7233 strcpy (buf
, "{vextrs,|extrw,s,}");
7234 if (GET_MODE (operands
[0]) == DImode
)
7235 strcpy (buf
, "extrd,s,*");
7236 if ((which
== 0 && negated
)
7237 || (which
== 1 && ! negated
))
7241 if (nullify
&& negated
)
7242 strcat (buf
, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
7243 else if (nullify
&& ! negated
)
7244 strcat (buf
, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
7246 strcat (buf
, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
7248 strcat (buf
, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
7253 /* The reversed conditional branch must branch over one additional
7254 instruction if the delay slot is filled and needs to be extracted
7255 by pa_output_lbranch. If the delay slot is empty or this is a
7256 nullified forward branch, the instruction after the reversed
7257 condition branch must be nullified. */
7258 if (dbr_sequence_length () == 0
7259 || (nullify
&& forward_branch_p (insn
)))
7263 operands
[4] = GEN_INT (length
);
7268 operands
[4] = GEN_INT (length
+ 4);
7271 if (GET_MODE (operands
[0]) == DImode
)
7272 strcpy (buf
, "bb,*");
7274 strcpy (buf
, "{bvb,|bb,}");
7275 if ((which
== 0 && negated
)
7276 || (which
== 1 && !negated
))
7281 strcat (buf
, ",n {%0,.+%4|%0,%%sar,.+%4}");
7283 strcat (buf
, " {%0,.+%4|%0,%%sar,.+%4}");
7284 output_asm_insn (buf
, operands
);
7285 return pa_output_lbranch (negated
? operands
[3] : operands
[2],
7291 /* Return the output template for emitting a dbra type insn.
7293 Note it may perform some output operations on its own before
7294 returning the final output string. */
7296 pa_output_dbra (rtx
*operands
, rtx_insn
*insn
, int which_alternative
)
7298 int length
= get_attr_length (insn
);
7300 /* A conditional branch to the following instruction (e.g. the delay slot) is
7301 asking for a disaster. Be prepared! */
7303 if (branch_to_delay_slot_p (insn
))
7305 if (which_alternative
== 0)
7306 return "ldo %1(%0),%0";
7307 else if (which_alternative
== 1)
7309 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands
);
7310 output_asm_insn ("ldw -16(%%r30),%4", operands
);
7311 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
7312 return "{fldws|fldw} -16(%%r30),%0";
7316 output_asm_insn ("ldw %0,%4", operands
);
7317 return "ldo %1(%4),%4\n\tstw %4,%0";
7321 if (which_alternative
== 0)
7323 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7326 /* If this is a long branch with its delay slot unfilled, set `nullify'
7327 as it can nullify the delay slot and save a nop. */
7328 if (length
== 8 && dbr_sequence_length () == 0)
7331 /* If this is a short forward conditional branch which did not get
7332 its delay slot filled, the delay slot can still be nullified. */
7333 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7334 nullify
= forward_branch_p (insn
);
7341 if (branch_needs_nop_p (insn
))
7342 return "addib,%C2,n %1,%0,%3%#";
7344 return "addib,%C2,n %1,%0,%3";
7347 return "addib,%C2 %1,%0,%3";
7350 /* Handle weird backwards branch with a fulled delay slot
7351 which is nullified. */
7352 if (dbr_sequence_length () != 0
7353 && ! forward_branch_p (insn
)
7355 return "addib,%N2,n %1,%0,.+12\n\tb %3";
7356 /* Handle short backwards branch with an unfilled delay slot.
7357 Using a addb;nop rather than addi;bl saves 1 cycle for both
7358 taken and untaken branches. */
7359 else if (dbr_sequence_length () == 0
7360 && ! forward_branch_p (insn
)
7361 && INSN_ADDRESSES_SET_P ()
7362 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7363 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7364 return "addib,%C2 %1,%0,%3%#";
7366 /* Handle normal cases. */
7368 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7370 return "addi,%N2 %1,%0,%0\n\tb %3";
7373 /* The reversed conditional branch must branch over one additional
7374 instruction if the delay slot is filled and needs to be extracted
7375 by pa_output_lbranch. If the delay slot is empty or this is a
7376 nullified forward branch, the instruction after the reversed
7377 condition branch must be nullified. */
7378 if (dbr_sequence_length () == 0
7379 || (nullify
&& forward_branch_p (insn
)))
7383 operands
[4] = GEN_INT (length
);
7388 operands
[4] = GEN_INT (length
+ 4);
7392 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands
);
7394 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands
);
7396 return pa_output_lbranch (operands
[3], insn
, xdelay
);
7400 /* Deal with gross reload from FP register case. */
7401 else if (which_alternative
== 1)
7403 /* Move loop counter from FP register to MEM then into a GR,
7404 increment the GR, store the GR into MEM, and finally reload
7405 the FP register from MEM from within the branch's delay slot. */
7406 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7408 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
7410 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7411 else if (length
== 28)
7412 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7415 operands
[5] = GEN_INT (length
- 16);
7416 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands
);
7417 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands
);
7418 return pa_output_lbranch (operands
[3], insn
, 0);
7421 /* Deal with gross reload from memory case. */
7424 /* Reload loop counter from memory, the store back to memory
7425 happens in the branch's delay slot. */
7426 output_asm_insn ("ldw %0,%4", operands
);
7428 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7429 else if (length
== 16)
7430 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7433 operands
[5] = GEN_INT (length
- 4);
7434 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands
);
7435 return pa_output_lbranch (operands
[3], insn
, 0);
7440 /* Return the output template for emitting a movb type insn.
7442 Note it may perform some output operations on its own before
7443 returning the final output string. */
7445 pa_output_movb (rtx
*operands
, rtx_insn
*insn
, int which_alternative
,
7446 int reverse_comparison
)
7448 int length
= get_attr_length (insn
);
7450 /* A conditional branch to the following instruction (e.g. the delay slot) is
7451 asking for a disaster. Be prepared! */
7453 if (branch_to_delay_slot_p (insn
))
7455 if (which_alternative
== 0)
7456 return "copy %1,%0";
7457 else if (which_alternative
== 1)
7459 output_asm_insn ("stw %1,-16(%%r30)", operands
);
7460 return "{fldws|fldw} -16(%%r30),%0";
7462 else if (which_alternative
== 2)
7468 /* Support the second variant. */
7469 if (reverse_comparison
)
7470 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
7472 if (which_alternative
== 0)
7474 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7477 /* If this is a long branch with its delay slot unfilled, set `nullify'
7478 as it can nullify the delay slot and save a nop. */
7479 if (length
== 8 && dbr_sequence_length () == 0)
7482 /* If this is a short forward conditional branch which did not get
7483 its delay slot filled, the delay slot can still be nullified. */
7484 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7485 nullify
= forward_branch_p (insn
);
7492 if (branch_needs_nop_p (insn
))
7493 return "movb,%C2,n %1,%0,%3%#";
7495 return "movb,%C2,n %1,%0,%3";
7498 return "movb,%C2 %1,%0,%3";
7501 /* Handle weird backwards branch with a filled delay slot
7502 which is nullified. */
7503 if (dbr_sequence_length () != 0
7504 && ! forward_branch_p (insn
)
7506 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7508 /* Handle short backwards branch with an unfilled delay slot.
7509 Using a movb;nop rather than or;bl saves 1 cycle for both
7510 taken and untaken branches. */
7511 else if (dbr_sequence_length () == 0
7512 && ! forward_branch_p (insn
)
7513 && INSN_ADDRESSES_SET_P ()
7514 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7515 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7516 return "movb,%C2 %1,%0,%3%#";
7517 /* Handle normal cases. */
7519 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7521 return "or,%N2 %1,%%r0,%0\n\tb %3";
7524 /* The reversed conditional branch must branch over one additional
7525 instruction if the delay slot is filled and needs to be extracted
7526 by pa_output_lbranch. If the delay slot is empty or this is a
7527 nullified forward branch, the instruction after the reversed
7528 condition branch must be nullified. */
7529 if (dbr_sequence_length () == 0
7530 || (nullify
&& forward_branch_p (insn
)))
7534 operands
[4] = GEN_INT (length
);
7539 operands
[4] = GEN_INT (length
+ 4);
7543 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands
);
7545 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands
);
7547 return pa_output_lbranch (operands
[3], insn
, xdelay
);
7550 /* Deal with gross reload for FP destination register case. */
7551 else if (which_alternative
== 1)
7553 /* Move source register to MEM, perform the branch test, then
7554 finally load the FP register from MEM from within the branch's
7556 output_asm_insn ("stw %1,-16(%%r30)", operands
);
7558 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7559 else if (length
== 16)
7560 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7563 operands
[4] = GEN_INT (length
- 4);
7564 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands
);
7565 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands
);
7566 return pa_output_lbranch (operands
[3], insn
, 0);
7569 /* Deal with gross reload from memory case. */
7570 else if (which_alternative
== 2)
7572 /* Reload loop counter from memory, the store back to memory
7573 happens in the branch's delay slot. */
7575 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7576 else if (length
== 12)
7577 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7580 operands
[4] = GEN_INT (length
);
7581 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7583 return pa_output_lbranch (operands
[3], insn
, 0);
7586 /* Handle SAR as a destination. */
7590 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7591 else if (length
== 12)
7592 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7595 operands
[4] = GEN_INT (length
);
7596 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7598 return pa_output_lbranch (operands
[3], insn
, 0);
7603 /* Copy any FP arguments in INSN into integer registers. */
7605 copy_fp_args (rtx_insn
*insn
)
7610 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
7612 int arg_mode
, regno
;
7613 rtx use
= XEXP (link
, 0);
7615 if (! (GET_CODE (use
) == USE
7616 && GET_CODE (XEXP (use
, 0)) == REG
7617 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
7620 arg_mode
= GET_MODE (XEXP (use
, 0));
7621 regno
= REGNO (XEXP (use
, 0));
7623 /* Is it a floating point register? */
7624 if (regno
>= 32 && regno
<= 39)
7626 /* Copy the FP register into an integer register via memory. */
7627 if (arg_mode
== SFmode
)
7629 xoperands
[0] = XEXP (use
, 0);
7630 xoperands
[1] = gen_rtx_REG (SImode
, 26 - (regno
- 32) / 2);
7631 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands
);
7632 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
7636 xoperands
[0] = XEXP (use
, 0);
7637 xoperands
[1] = gen_rtx_REG (DImode
, 25 - (regno
- 34) / 2);
7638 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands
);
7639 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands
);
7640 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
7646 /* Compute length of the FP argument copy sequence for INSN. */
7648 length_fp_args (rtx_insn
*insn
)
7653 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
7655 int arg_mode
, regno
;
7656 rtx use
= XEXP (link
, 0);
7658 if (! (GET_CODE (use
) == USE
7659 && GET_CODE (XEXP (use
, 0)) == REG
7660 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
7663 arg_mode
= GET_MODE (XEXP (use
, 0));
7664 regno
= REGNO (XEXP (use
, 0));
7666 /* Is it a floating point register? */
7667 if (regno
>= 32 && regno
<= 39)
7669 if (arg_mode
== SFmode
)
7679 /* Return the attribute length for the millicode call instruction INSN.
7680 The length must match the code generated by pa_output_millicode_call.
7681 We include the delay slot in the returned length as it is better to
7682 over estimate the length than to under estimate it. */
7685 pa_attr_length_millicode_call (rtx_insn
*insn
)
7687 unsigned long distance
= -1;
7688 unsigned long total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
7690 if (INSN_ADDRESSES_SET_P ())
7692 distance
= (total
+ insn_current_reference_address (insn
));
7693 if (distance
< total
)
7699 if (!TARGET_LONG_CALLS
&& distance
< 7600000)
7704 else if (TARGET_PORTABLE_RUNTIME
)
7708 if (!TARGET_LONG_CALLS
&& distance
< MAX_PCREL17F_OFFSET
)
7718 /* INSN is a function call.
7720 CALL_DEST is the routine we are calling. */
7723 pa_output_millicode_call (rtx_insn
*insn
, rtx call_dest
)
7725 int attr_length
= get_attr_length (insn
);
7726 int seq_length
= dbr_sequence_length ();
7729 xoperands
[0] = call_dest
;
7731 /* Handle the common case where we are sure that the branch will
7732 reach the beginning of the $CODE$ subspace. The within reach
7733 form of the $$sh_func_adrs call has a length of 28. Because it
7734 has an attribute type of sh_func_adrs, it never has a nonzero
7735 sequence length (i.e., the delay slot is never filled). */
7736 if (!TARGET_LONG_CALLS
7737 && (attr_length
== 8
7738 || (attr_length
== 28
7739 && get_attr_type (insn
) == TYPE_SH_FUNC_ADRS
)))
7741 xoperands
[1] = gen_rtx_REG (Pmode
, TARGET_64BIT
? 2 : 31);
7742 output_asm_insn ("{bl|b,l} %0,%1", xoperands
);
7748 /* It might seem that one insn could be saved by accessing
7749 the millicode function using the linkage table. However,
7750 this doesn't work in shared libraries and other dynamically
7751 loaded objects. Using a pc-relative sequence also avoids
7752 problems related to the implicit use of the gp register. */
7753 xoperands
[1] = gen_rtx_REG (Pmode
, 1);
7754 xoperands
[2] = xoperands
[1];
7755 pa_output_pic_pcrel_sequence (xoperands
);
7756 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
7758 else if (TARGET_PORTABLE_RUNTIME
)
7760 /* Pure portable runtime doesn't allow be/ble; we also don't
7761 have PIC support in the assembler/linker, so this sequence
7764 /* Get the address of our target into %r1. */
7765 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7766 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands
);
7768 /* Get our return address into %r31. */
7769 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands
);
7770 output_asm_insn ("addi 8,%%r31,%%r31", xoperands
);
7772 /* Jump to our target address in %r1. */
7773 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
7777 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7779 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands
);
7781 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands
);
7785 xoperands
[1] = gen_rtx_REG (Pmode
, 31);
7786 xoperands
[2] = gen_rtx_REG (Pmode
, 1);
7787 pa_output_pic_pcrel_sequence (xoperands
);
7789 /* Adjust return address. */
7790 output_asm_insn ("ldo {16|24}(%%r31),%%r31", xoperands
);
7792 /* Jump to our target address in %r1. */
7793 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
7797 if (seq_length
== 0)
7798 output_asm_insn ("nop", xoperands
);
7803 /* Return the attribute length of the call instruction INSN. The SIBCALL
7804 flag indicates whether INSN is a regular call or a sibling call. The
7805 length returned must be longer than the code actually generated by
7806 pa_output_call. Since branch shortening is done before delay branch
7807 sequencing, there is no way to determine whether or not the delay
7808 slot will be filled during branch shortening. Even when the delay
7809 slot is filled, we may have to add a nop if the delay slot contains
7810 a branch that can't reach its target. Thus, we always have to include
7811 the delay slot in the length estimate. This used to be done in
7812 pa_adjust_insn_length but we do it here now as some sequences always
7813 fill the delay slot and we can save four bytes in the estimate for
7817 pa_attr_length_call (rtx_insn
*insn
, int sibcall
)
7820 rtx call
, call_dest
;
7823 rtx pat
= PATTERN (insn
);
7824 unsigned long distance
= -1;
7826 gcc_assert (CALL_P (insn
));
7828 if (INSN_ADDRESSES_SET_P ())
7830 unsigned long total
;
7832 total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
7833 distance
= (total
+ insn_current_reference_address (insn
));
7834 if (distance
< total
)
7838 gcc_assert (GET_CODE (pat
) == PARALLEL
);
7840 /* Get the call rtx. */
7841 call
= XVECEXP (pat
, 0, 0);
7842 if (GET_CODE (call
) == SET
)
7843 call
= SET_SRC (call
);
7845 gcc_assert (GET_CODE (call
) == CALL
);
7847 /* Determine if this is a local call. */
7848 call_dest
= XEXP (XEXP (call
, 0), 0);
7849 call_decl
= SYMBOL_REF_DECL (call_dest
);
7850 local_call
= call_decl
&& targetm
.binds_local_p (call_decl
);
7852 /* pc-relative branch. */
7853 if (!TARGET_LONG_CALLS
7854 && ((TARGET_PA_20
&& !sibcall
&& distance
< 7600000)
7855 || distance
< MAX_PCREL17F_OFFSET
))
7858 /* 64-bit plabel sequence. */
7859 else if (TARGET_64BIT
&& !local_call
)
7860 length
+= sibcall
? 28 : 24;
7862 /* non-pic long absolute branch sequence. */
7863 else if ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7866 /* long pc-relative branch sequence. */
7867 else if (TARGET_LONG_PIC_SDIFF_CALL
7868 || (TARGET_GAS
&& !TARGET_SOM
&& local_call
))
7872 if (!TARGET_PA_20
&& !TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
7876 /* 32-bit plabel sequence. */
7882 length
+= length_fp_args (insn
);
7892 if (!TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
7900 /* INSN is a function call.
7902 CALL_DEST is the routine we are calling. */
7905 pa_output_call (rtx_insn
*insn
, rtx call_dest
, int sibcall
)
7907 int seq_length
= dbr_sequence_length ();
7908 tree call_decl
= SYMBOL_REF_DECL (call_dest
);
7909 int local_call
= call_decl
&& targetm
.binds_local_p (call_decl
);
7912 xoperands
[0] = call_dest
;
7914 /* Handle the common case where we're sure that the branch will reach
7915 the beginning of the "$CODE$" subspace. This is the beginning of
7916 the current function if we are in a named section. */
7917 if (!TARGET_LONG_CALLS
&& pa_attr_length_call (insn
, sibcall
) == 8)
7919 xoperands
[1] = gen_rtx_REG (word_mode
, sibcall
? 0 : 2);
7920 output_asm_insn ("{bl|b,l} %0,%1", xoperands
);
7924 if (TARGET_64BIT
&& !local_call
)
7926 /* ??? As far as I can tell, the HP linker doesn't support the
7927 long pc-relative sequence described in the 64-bit runtime
7928 architecture. So, we use a slightly longer indirect call. */
7929 xoperands
[0] = pa_get_deferred_plabel (call_dest
);
7930 xoperands
[1] = gen_label_rtx ();
7932 /* If this isn't a sibcall, we put the load of %r27 into the
7933 delay slot. We can't do this in a sibcall as we don't
7934 have a second call-clobbered scratch register available.
7935 We don't need to do anything when generating fast indirect
7937 if (seq_length
!= 0 && !sibcall
)
7939 final_scan_insn (NEXT_INSN (insn
), asm_out_file
,
7942 /* Now delete the delay insn. */
7943 SET_INSN_DELETED (NEXT_INSN (insn
));
7947 output_asm_insn ("addil LT'%0,%%r27", xoperands
);
7948 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands
);
7949 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands
);
7953 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands
);
7954 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands
);
7955 output_asm_insn ("bve (%%r1)", xoperands
);
7959 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands
);
7960 output_asm_insn ("bve,l (%%r2),%%r2", xoperands
);
7961 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands
);
7967 int indirect_call
= 0;
7969 /* Emit a long call. There are several different sequences
7970 of increasing length and complexity. In most cases,
7971 they don't allow an instruction in the delay slot. */
7972 if (!((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7973 && !TARGET_LONG_PIC_SDIFF_CALL
7974 && !(TARGET_GAS
&& !TARGET_SOM
&& local_call
)
7982 || ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)))
7984 /* A non-jump insn in the delay slot. By definition we can
7985 emit this insn before the call (and in fact before argument
7987 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0,
7990 /* Now delete the delay insn. */
7991 SET_INSN_DELETED (NEXT_INSN (insn
));
7995 if ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7997 /* This is the best sequence for making long calls in
7998 non-pic code. Unfortunately, GNU ld doesn't provide
7999 the stub needed for external calls, and GAS's support
8000 for this with the SOM linker is buggy. It is safe
8001 to use this for local calls. */
8002 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
8004 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands
);
8008 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
8011 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands
);
8013 output_asm_insn ("copy %%r31,%%r2", xoperands
);
8019 /* The HP assembler and linker can handle relocations for
8020 the difference of two symbols. The HP assembler
8021 recognizes the sequence as a pc-relative call and
8022 the linker provides stubs when needed. */
8024 /* GAS currently can't generate the relocations that
8025 are needed for the SOM linker under HP-UX using this
8026 sequence. The GNU linker doesn't generate the stubs
8027 that are needed for external calls on TARGET_ELF32
8028 with this sequence. For now, we have to use a longer
8029 plabel sequence when using GAS for non local calls. */
8030 if (TARGET_LONG_PIC_SDIFF_CALL
8031 || (TARGET_GAS
&& !TARGET_SOM
&& local_call
))
8033 xoperands
[1] = gen_rtx_REG (Pmode
, 1);
8034 xoperands
[2] = xoperands
[1];
8035 pa_output_pic_pcrel_sequence (xoperands
);
8039 /* Emit a long plabel-based call sequence. This is
8040 essentially an inline implementation of $$dyncall.
8041 We don't actually try to call $$dyncall as this is
8042 as difficult as calling the function itself. */
8043 xoperands
[0] = pa_get_deferred_plabel (call_dest
);
8044 xoperands
[1] = gen_label_rtx ();
8046 /* Since the call is indirect, FP arguments in registers
8047 need to be copied to the general registers. Then, the
8048 argument relocation stub will copy them back. */
8050 copy_fp_args (insn
);
8054 output_asm_insn ("addil LT'%0,%%r19", xoperands
);
8055 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands
);
8056 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands
);
8060 output_asm_insn ("addil LR'%0-$global$,%%r27",
8062 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
8066 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands
);
8067 output_asm_insn ("depi 0,31,2,%%r1", xoperands
);
8068 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands
);
8069 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands
);
8071 if (!sibcall
&& !TARGET_PA_20
)
8073 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands
);
8074 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8075 output_asm_insn ("addi 8,%%r2,%%r2", xoperands
);
8077 output_asm_insn ("addi 16,%%r2,%%r2", xoperands
);
8084 output_asm_insn ("bve (%%r1)", xoperands
);
8089 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
8090 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands
);
8094 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
8099 if (!TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
8100 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
8105 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8106 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands
);
8108 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands
);
8112 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8113 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands
);
8115 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands
);
8118 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands
);
8120 output_asm_insn ("copy %%r31,%%r2", xoperands
);
8128 if (seq_length
== 0)
8129 output_asm_insn ("nop", xoperands
);
8134 /* Return the attribute length of the indirect call instruction INSN.
8135 The length must match the code generated by output_indirect call.
8136 The returned length includes the delay slot. Currently, the delay
8137 slot of an indirect call sequence is not exposed and it is used by
8138 the sequence itself. */
8141 pa_attr_length_indirect_call (rtx_insn
*insn
)
8143 unsigned long distance
= -1;
8144 unsigned long total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
8146 if (INSN_ADDRESSES_SET_P ())
8148 distance
= (total
+ insn_current_reference_address (insn
));
8149 if (distance
< total
)
8156 if (TARGET_FAST_INDIRECT_CALLS
)
8159 if (TARGET_PORTABLE_RUNTIME
)
8162 /* Inline version of $$dyncall. */
8163 if ((TARGET_NO_SPACE_REGS
|| TARGET_PA_20
) && !optimize_size
)
8166 if (!TARGET_LONG_CALLS
8167 && ((TARGET_PA_20
&& !TARGET_SOM
&& distance
< 7600000)
8168 || distance
< MAX_PCREL17F_OFFSET
))
8171 /* Out of reach, can use ble. */
8175 /* Inline version of $$dyncall. */
8176 if (TARGET_NO_SPACE_REGS
|| TARGET_PA_20
)
8182 /* Long PIC pc-relative call. */
8187 pa_output_indirect_call (rtx_insn
*insn
, rtx call_dest
)
8194 xoperands
[0] = call_dest
;
8195 output_asm_insn ("ldd 16(%0),%%r2\n\t"
8196 "bve,l (%%r2),%%r2\n\t"
8197 "ldd 24(%0),%%r27", xoperands
);
8201 /* First the special case for kernels, level 0 systems, etc. */
8202 if (TARGET_FAST_INDIRECT_CALLS
)
8204 pa_output_arg_descriptor (insn
);
8206 return "bve,l,n (%%r22),%%r2\n\tnop";
8207 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8210 if (TARGET_PORTABLE_RUNTIME
)
8212 output_asm_insn ("ldil L'$$dyncall,%%r31\n\t"
8213 "ldo R'$$dyncall(%%r31),%%r31", xoperands
);
8214 pa_output_arg_descriptor (insn
);
8215 return "blr %%r0,%%r2\n\tbv,n %%r0(%%r31)";
8218 /* Maybe emit a fast inline version of $$dyncall. */
8219 if ((TARGET_NO_SPACE_REGS
|| TARGET_PA_20
) && !optimize_size
)
8221 output_asm_insn ("bb,>=,n %%r22,30,.+12\n\t"
8222 "ldw 2(%%r22),%%r19\n\t"
8223 "ldw -2(%%r22),%%r22", xoperands
);
8224 pa_output_arg_descriptor (insn
);
8225 if (TARGET_NO_SPACE_REGS
)
8228 return "bve,l,n (%%r22),%%r2\n\tnop";
8229 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8231 return "bve,l (%%r22),%%r2\n\tstw %%r2,-24(%%sp)";
8234 /* Now the normal case -- we can reach $$dyncall directly or
8235 we're sure that we can get there via a long-branch stub.
8237 No need to check target flags as the length uniquely identifies
8238 the remaining cases. */
8239 length
= pa_attr_length_indirect_call (insn
);
8242 pa_output_arg_descriptor (insn
);
8244 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
8245 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
8246 variant of the B,L instruction can't be used on the SOM target. */
8247 if (TARGET_PA_20
&& !TARGET_SOM
)
8248 return "b,l,n $$dyncall,%%r2\n\tnop";
8250 return "bl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
8253 /* Long millicode call, but we are not generating PIC or portable runtime
8257 output_asm_insn ("ldil L'$$dyncall,%%r2", xoperands
);
8258 pa_output_arg_descriptor (insn
);
8259 return "ble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
8262 /* Maybe emit a fast inline version of $$dyncall. The long PIC
8263 pc-relative call sequence is five instructions. The inline PA 2.0
8264 version of $$dyncall is also five instructions. The PA 1.X versions
8265 are longer but still an overall win. */
8266 if (TARGET_NO_SPACE_REGS
|| TARGET_PA_20
|| !optimize_size
)
8268 output_asm_insn ("bb,>=,n %%r22,30,.+12\n\t"
8269 "ldw 2(%%r22),%%r19\n\t"
8270 "ldw -2(%%r22),%%r22", xoperands
);
8271 if (TARGET_NO_SPACE_REGS
)
8273 pa_output_arg_descriptor (insn
);
8275 return "bve,l,n (%%r22),%%r2\n\tnop";
8276 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8280 pa_output_arg_descriptor (insn
);
8281 return "bve,l (%%r22),%%r2\n\tstw %%r2,-24(%%sp)";
8283 output_asm_insn ("bl .+8,%%r2\n\t"
8284 "ldo 16(%%r2),%%r2\n\t"
8285 "ldsid (%%r22),%%r1\n\t"
8286 "mtsp %%r1,%%sr0", xoperands
);
8287 pa_output_arg_descriptor (insn
);
8288 return "be 0(%%sr0,%%r22)\n\tstw %%r2,-24(%%sp)";
8291 /* We need a long PIC call to $$dyncall. */
8292 xoperands
[0] = gen_rtx_SYMBOL_REF (Pmode
, "$$dyncall");
8293 xoperands
[1] = gen_rtx_REG (Pmode
, 2);
8294 xoperands
[2] = gen_rtx_REG (Pmode
, 1);
8295 pa_output_pic_pcrel_sequence (xoperands
);
8296 pa_output_arg_descriptor (insn
);
8297 return "bv %%r0(%%r1)\n\tldo {12|20}(%%r2),%%r2";
8300 /* In HPUX 8.0's shared library scheme, special relocations are needed
8301 for function labels if they might be passed to a function
8302 in a shared library (because shared libraries don't live in code
8303 space), and special magic is needed to construct their address. */
8306 pa_encode_label (rtx sym
)
8308 const char *str
= XSTR (sym
, 0);
8309 int len
= strlen (str
) + 1;
8312 p
= newstr
= XALLOCAVEC (char, len
+ 1);
8316 XSTR (sym
, 0) = ggc_alloc_string (newstr
, len
);
8320 pa_encode_section_info (tree decl
, rtx rtl
, int first
)
8322 int old_referenced
= 0;
8324 if (!first
&& MEM_P (rtl
) && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
)
8326 = SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) & SYMBOL_FLAG_REFERENCED
;
8328 default_encode_section_info (decl
, rtl
, first
);
8330 if (first
&& TEXT_SPACE_P (decl
))
8332 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
8333 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8334 pa_encode_label (XEXP (rtl
, 0));
8336 else if (old_referenced
)
8337 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= old_referenced
;
8340 /* This is sort of inverse to pa_encode_section_info. */
8343 pa_strip_name_encoding (const char *str
)
8345 str
+= (*str
== '@');
8346 str
+= (*str
== '*');
8350 /* Returns 1 if OP is a function label involved in a simple addition
8351 with a constant. Used to keep certain patterns from matching
8352 during instruction combination. */
8354 pa_is_function_label_plus_const (rtx op
)
8356 /* Strip off any CONST. */
8357 if (GET_CODE (op
) == CONST
)
8360 return (GET_CODE (op
) == PLUS
8361 && function_label_operand (XEXP (op
, 0), VOIDmode
)
8362 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
8365 /* Output assembly code for a thunk to FUNCTION. */
8368 pa_asm_output_mi_thunk (FILE *file
, tree thunk_fndecl
, HOST_WIDE_INT delta
,
8369 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
8372 static unsigned int current_thunk_number
;
8373 int val_14
= VAL_14_BITS_P (delta
);
8374 unsigned int old_last_address
= last_address
, nbytes
= 0;
8378 xoperands
[0] = XEXP (DECL_RTL (function
), 0);
8379 xoperands
[1] = XEXP (DECL_RTL (thunk_fndecl
), 0);
8380 xoperands
[2] = GEN_INT (delta
);
8382 final_start_function (emit_barrier (), file
, 1);
8384 /* Output the thunk. We know that the function is in the same
8385 translation unit (i.e., the same space) as the thunk, and that
8386 thunks are output after their method. Thus, we don't need an
8387 external branch to reach the function. With SOM and GAS,
8388 functions and thunks are effectively in different sections.
8389 Thus, we can always use a IA-relative branch and the linker
8390 will add a long branch stub if necessary.
8392 However, we have to be careful when generating PIC code on the
8393 SOM port to ensure that the sequence does not transfer to an
8394 import stub for the target function as this could clobber the
8395 return value saved at SP-24. This would also apply to the
8396 32-bit linux port if the multi-space model is implemented. */
8397 if ((!TARGET_LONG_CALLS
&& TARGET_SOM
&& !TARGET_PORTABLE_RUNTIME
8398 && !(flag_pic
&& TREE_PUBLIC (function
))
8399 && (TARGET_GAS
|| last_address
< 262132))
8400 || (!TARGET_LONG_CALLS
&& !TARGET_SOM
&& !TARGET_PORTABLE_RUNTIME
8401 && ((targetm_common
.have_named_sections
8402 && DECL_SECTION_NAME (thunk_fndecl
) != NULL
8403 /* The GNU 64-bit linker has rather poor stub management.
8404 So, we use a long branch from thunks that aren't in
8405 the same section as the target function. */
8407 && (DECL_SECTION_NAME (thunk_fndecl
)
8408 != DECL_SECTION_NAME (function
)))
8409 || ((DECL_SECTION_NAME (thunk_fndecl
)
8410 == DECL_SECTION_NAME (function
))
8411 && last_address
< 262132)))
8412 /* In this case, we need to be able to reach the start of
8413 the stub table even though the function is likely closer
8414 and can be jumped to directly. */
8415 || (targetm_common
.have_named_sections
8416 && DECL_SECTION_NAME (thunk_fndecl
) == NULL
8417 && DECL_SECTION_NAME (function
) == NULL
8418 && total_code_bytes
< MAX_PCREL17F_OFFSET
)
8420 || (!targetm_common
.have_named_sections
8421 && total_code_bytes
< MAX_PCREL17F_OFFSET
))))
8424 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8426 output_asm_insn ("b %0", xoperands
);
8430 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8435 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8439 else if (TARGET_64BIT
)
8443 /* We only have one call-clobbered scratch register, so we can't
8444 make use of the delay slot if delta doesn't fit in 14 bits. */
8447 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8448 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8451 /* Load function address into %r1. */
8452 xop
[0] = xoperands
[0];
8453 xop
[1] = gen_rtx_REG (Pmode
, 1);
8455 pa_output_pic_pcrel_sequence (xop
);
8459 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
8460 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8465 output_asm_insn ("bv,n %%r0(%%r1)", xoperands
);
8469 else if (TARGET_PORTABLE_RUNTIME
)
8471 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
8472 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands
);
8475 output_asm_insn ("ldil L'%2,%%r26", xoperands
);
8477 output_asm_insn ("bv %%r0(%%r22)", xoperands
);
8481 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8486 output_asm_insn ("ldo R'%2(%%r26),%%r26", xoperands
);
8490 else if (TARGET_SOM
&& flag_pic
&& TREE_PUBLIC (function
))
8492 /* The function is accessible from outside this module. The only
8493 way to avoid an import stub between the thunk and function is to
8494 call the function directly with an indirect sequence similar to
8495 that used by $$dyncall. This is possible because $$dyncall acts
8496 as the import stub in an indirect call. */
8497 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHN", current_thunk_number
);
8498 xoperands
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
8499 output_asm_insn ("addil LT'%3,%%r19", xoperands
);
8500 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands
);
8501 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands
);
8502 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands
);
8503 output_asm_insn ("depi 0,31,2,%%r22", xoperands
);
8504 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands
);
8505 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands
);
8509 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8515 output_asm_insn ("bve (%%r22)", xoperands
);
8518 else if (TARGET_NO_SPACE_REGS
)
8520 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands
);
8525 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands
);
8526 output_asm_insn ("mtsp %%r21,%%sr0", xoperands
);
8527 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands
);
8532 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8534 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8540 /* Load function address into %r22. */
8541 xop
[0] = xoperands
[0];
8542 xop
[1] = gen_rtx_REG (Pmode
, 1);
8543 xop
[2] = gen_rtx_REG (Pmode
, 22);
8544 pa_output_pic_pcrel_sequence (xop
);
8547 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8549 output_asm_insn ("bv %%r0(%%r22)", xoperands
);
8553 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8558 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8565 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8567 output_asm_insn ("ldil L'%0,%%r22", xoperands
);
8568 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands
);
8572 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8577 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8582 final_end_function ();
8584 if (TARGET_SOM
&& flag_pic
&& TREE_PUBLIC (function
))
8586 switch_to_section (data_section
);
8587 output_asm_insn (".align 4", xoperands
);
8588 ASM_OUTPUT_LABEL (file
, label
);
8589 output_asm_insn (".word P'%0", xoperands
);
8592 current_thunk_number
++;
8593 nbytes
= ((nbytes
+ FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1)
8594 & ~(FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1));
8595 last_address
+= nbytes
;
8596 if (old_last_address
> last_address
)
8597 last_address
= UINT_MAX
;
8598 update_total_code_bytes (nbytes
);
8601 /* Only direct calls to static functions are allowed to be sibling (tail)
8604 This restriction is necessary because some linker generated stubs will
8605 store return pointers into rp' in some cases which might clobber a
8606 live value already in rp'.
8608 In a sibcall the current function and the target function share stack
8609 space. Thus if the path to the current function and the path to the
8610 target function save a value in rp', they save the value into the
8611 same stack slot, which has undesirable consequences.
8613 Because of the deferred binding nature of shared libraries any function
8614 with external scope could be in a different load module and thus require
8615 rp' to be saved when calling that function. So sibcall optimizations
8616 can only be safe for static function.
8618 Note that GCC never needs return value relocations, so we don't have to
8619 worry about static calls with return value relocations (which require
8622 It is safe to perform a sibcall optimization when the target function
8623 will never return. */
8625 pa_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
8627 /* Sibcalls are not ok because the arg pointer register is not a fixed
8628 register. This prevents the sibcall optimization from occurring. In
8629 addition, there are problems with stub placement using GNU ld. This
8630 is because a normal sibcall branch uses a 17-bit relocation while
8631 a regular call branch uses a 22-bit relocation. As a result, more
8632 care needs to be taken in the placement of long-branch stubs. */
8636 if (TARGET_PORTABLE_RUNTIME
)
8639 /* Sibcalls are only ok within a translation unit. */
8640 return decl
&& targetm
.binds_local_p (decl
);
8643 /* ??? Addition is not commutative on the PA due to the weird implicit
8644 space register selection rules for memory addresses. Therefore, we
8645 don't consider a + b == b + a, as this might be inside a MEM. */
8647 pa_commutative_p (const_rtx x
, int outer_code
)
8649 return (COMMUTATIVE_P (x
)
8650 && (TARGET_NO_SPACE_REGS
8651 || (outer_code
!= UNKNOWN
&& outer_code
!= MEM
)
8652 || GET_CODE (x
) != PLUS
));
8655 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8656 use in fmpyadd instructions. */
8658 pa_fmpyaddoperands (rtx
*operands
)
8660 machine_mode mode
= GET_MODE (operands
[0]);
8662 /* Must be a floating point mode. */
8663 if (mode
!= SFmode
&& mode
!= DFmode
)
8666 /* All modes must be the same. */
8667 if (! (mode
== GET_MODE (operands
[1])
8668 && mode
== GET_MODE (operands
[2])
8669 && mode
== GET_MODE (operands
[3])
8670 && mode
== GET_MODE (operands
[4])
8671 && mode
== GET_MODE (operands
[5])))
8674 /* All operands must be registers. */
8675 if (! (GET_CODE (operands
[1]) == REG
8676 && GET_CODE (operands
[2]) == REG
8677 && GET_CODE (operands
[3]) == REG
8678 && GET_CODE (operands
[4]) == REG
8679 && GET_CODE (operands
[5]) == REG
))
8682 /* Only 2 real operands to the addition. One of the input operands must
8683 be the same as the output operand. */
8684 if (! rtx_equal_p (operands
[3], operands
[4])
8685 && ! rtx_equal_p (operands
[3], operands
[5]))
8688 /* Inout operand of add cannot conflict with any operands from multiply. */
8689 if (rtx_equal_p (operands
[3], operands
[0])
8690 || rtx_equal_p (operands
[3], operands
[1])
8691 || rtx_equal_p (operands
[3], operands
[2]))
8694 /* multiply cannot feed into addition operands. */
8695 if (rtx_equal_p (operands
[4], operands
[0])
8696 || rtx_equal_p (operands
[5], operands
[0]))
8699 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8701 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
8702 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
8703 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
8704 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
8705 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
8706 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
8709 /* Passed. Operands are suitable for fmpyadd. */
8713 #if !defined(USE_COLLECT2)
8715 pa_asm_out_constructor (rtx symbol
, int priority
)
8717 if (!function_label_operand (symbol
, VOIDmode
))
8718 pa_encode_label (symbol
);
8720 #ifdef CTORS_SECTION_ASM_OP
8721 default_ctor_section_asm_out_constructor (symbol
, priority
);
8723 # ifdef TARGET_ASM_NAMED_SECTION
8724 default_named_section_asm_out_constructor (symbol
, priority
);
8726 default_stabs_asm_out_constructor (symbol
, priority
);
8732 pa_asm_out_destructor (rtx symbol
, int priority
)
8734 if (!function_label_operand (symbol
, VOIDmode
))
8735 pa_encode_label (symbol
);
8737 #ifdef DTORS_SECTION_ASM_OP
8738 default_dtor_section_asm_out_destructor (symbol
, priority
);
8740 # ifdef TARGET_ASM_NAMED_SECTION
8741 default_named_section_asm_out_destructor (symbol
, priority
);
8743 default_stabs_asm_out_destructor (symbol
, priority
);
8749 /* This function places uninitialized global data in the bss section.
8750 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8751 function on the SOM port to prevent uninitialized global data from
8752 being placed in the data section. */
8755 pa_asm_output_aligned_bss (FILE *stream
,
8757 unsigned HOST_WIDE_INT size
,
8760 switch_to_section (bss_section
);
8761 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8763 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8764 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8767 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8768 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8771 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8772 ASM_OUTPUT_LABEL (stream
, name
);
8773 fprintf (stream
, "\t.block " HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8776 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8777 that doesn't allow the alignment of global common storage to be directly
8778 specified. The SOM linker aligns common storage based on the rounded
8779 value of the NUM_BYTES parameter in the .comm directive. It's not
8780 possible to use the .align directive as it doesn't affect the alignment
8781 of the label associated with a .comm directive. */
8784 pa_asm_output_aligned_common (FILE *stream
,
8786 unsigned HOST_WIDE_INT size
,
8789 unsigned int max_common_align
;
8791 max_common_align
= TARGET_64BIT
? 128 : (size
>= 4096 ? 256 : 64);
8792 if (align
> max_common_align
)
8794 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8795 "for global common data. Using %u",
8796 align
/ BITS_PER_UNIT
, name
, max_common_align
/ BITS_PER_UNIT
);
8797 align
= max_common_align
;
8800 switch_to_section (bss_section
);
8802 assemble_name (stream
, name
);
8803 fprintf (stream
, "\t.comm " HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8804 MAX (size
, align
/ BITS_PER_UNIT
));
8807 /* We can't use .comm for local common storage as the SOM linker effectively
8808 treats the symbol as universal and uses the same storage for local symbols
8809 with the same name in different object files. The .block directive
8810 reserves an uninitialized block of storage. However, it's not common
8811 storage. Fortunately, GCC never requests common storage with the same
8812 name in any given translation unit. */
8815 pa_asm_output_aligned_local (FILE *stream
,
8817 unsigned HOST_WIDE_INT size
,
8820 switch_to_section (bss_section
);
8821 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8824 fprintf (stream
, "%s", LOCAL_ASM_OP
);
8825 assemble_name (stream
, name
);
8826 fprintf (stream
, "\n");
8829 ASM_OUTPUT_LABEL (stream
, name
);
8830 fprintf (stream
, "\t.block " HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8833 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8834 use in fmpysub instructions. */
8836 pa_fmpysuboperands (rtx
*operands
)
8838 machine_mode mode
= GET_MODE (operands
[0]);
8840 /* Must be a floating point mode. */
8841 if (mode
!= SFmode
&& mode
!= DFmode
)
8844 /* All modes must be the same. */
8845 if (! (mode
== GET_MODE (operands
[1])
8846 && mode
== GET_MODE (operands
[2])
8847 && mode
== GET_MODE (operands
[3])
8848 && mode
== GET_MODE (operands
[4])
8849 && mode
== GET_MODE (operands
[5])))
8852 /* All operands must be registers. */
8853 if (! (GET_CODE (operands
[1]) == REG
8854 && GET_CODE (operands
[2]) == REG
8855 && GET_CODE (operands
[3]) == REG
8856 && GET_CODE (operands
[4]) == REG
8857 && GET_CODE (operands
[5]) == REG
))
8860 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8861 operation, so operands[4] must be the same as operand[3]. */
8862 if (! rtx_equal_p (operands
[3], operands
[4]))
8865 /* multiply cannot feed into subtraction. */
8866 if (rtx_equal_p (operands
[5], operands
[0]))
8869 /* Inout operand of sub cannot conflict with any operands from multiply. */
8870 if (rtx_equal_p (operands
[3], operands
[0])
8871 || rtx_equal_p (operands
[3], operands
[1])
8872 || rtx_equal_p (operands
[3], operands
[2]))
8875 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8877 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
8878 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
8879 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
8880 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
8881 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
8882 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
8885 /* Passed. Operands are suitable for fmpysub. */
8889 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8890 constants for a MULT embedded inside a memory address. */
8892 pa_mem_shadd_constant_p (int val
)
8894 if (val
== 2 || val
== 4 || val
== 8)
8900 /* Return 1 if the given constant is 1, 2, or 3. These are the valid
8901 constants for shadd instructions. */
8903 pa_shadd_constant_p (int val
)
8905 if (val
== 1 || val
== 2 || val
== 3)
8911 /* Return TRUE if INSN branches forward. */
8914 forward_branch_p (rtx_insn
*insn
)
8916 rtx lab
= JUMP_LABEL (insn
);
8918 /* The INSN must have a jump label. */
8919 gcc_assert (lab
!= NULL_RTX
);
8921 if (INSN_ADDRESSES_SET_P ())
8922 return INSN_ADDRESSES (INSN_UID (lab
)) > INSN_ADDRESSES (INSN_UID (insn
));
8929 insn
= NEXT_INSN (insn
);
8935 /* Output an unconditional move and branch insn. */
8938 pa_output_parallel_movb (rtx
*operands
, rtx_insn
*insn
)
8940 int length
= get_attr_length (insn
);
8942 /* These are the cases in which we win. */
8944 return "mov%I1b,tr %1,%0,%2";
8946 /* None of the following cases win, but they don't lose either. */
8949 if (dbr_sequence_length () == 0)
8951 /* Nothing in the delay slot, fake it by putting the combined
8952 insn (the copy or add) in the delay slot of a bl. */
8953 if (GET_CODE (operands
[1]) == CONST_INT
)
8954 return "b %2\n\tldi %1,%0";
8956 return "b %2\n\tcopy %1,%0";
8960 /* Something in the delay slot, but we've got a long branch. */
8961 if (GET_CODE (operands
[1]) == CONST_INT
)
8962 return "ldi %1,%0\n\tb %2";
8964 return "copy %1,%0\n\tb %2";
8968 if (GET_CODE (operands
[1]) == CONST_INT
)
8969 output_asm_insn ("ldi %1,%0", operands
);
8971 output_asm_insn ("copy %1,%0", operands
);
8972 return pa_output_lbranch (operands
[2], insn
, 1);
8975 /* Output an unconditional add and branch insn. */
8978 pa_output_parallel_addb (rtx
*operands
, rtx_insn
*insn
)
8980 int length
= get_attr_length (insn
);
8982 /* To make life easy we want operand0 to be the shared input/output
8983 operand and operand1 to be the readonly operand. */
8984 if (operands
[0] == operands
[1])
8985 operands
[1] = operands
[2];
8987 /* These are the cases in which we win. */
8989 return "add%I1b,tr %1,%0,%3";
8991 /* None of the following cases win, but they don't lose either. */
8994 if (dbr_sequence_length () == 0)
8995 /* Nothing in the delay slot, fake it by putting the combined
8996 insn (the copy or add) in the delay slot of a bl. */
8997 return "b %3\n\tadd%I1 %1,%0,%0";
8999 /* Something in the delay slot, but we've got a long branch. */
9000 return "add%I1 %1,%0,%0\n\tb %3";
9003 output_asm_insn ("add%I1 %1,%0,%0", operands
);
9004 return pa_output_lbranch (operands
[3], insn
, 1);
9007 /* We use this hook to perform a PA specific optimization which is difficult
9008 to do in earlier passes. */
9013 remove_useless_addtr_insns (1);
9015 if (pa_cpu
< PROCESSOR_8000
)
9016 pa_combine_instructions ();
9019 /* The PA has a number of odd instructions which can perform multiple
9020 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
9021 it may be profitable to combine two instructions into one instruction
9022 with two outputs. It's not profitable PA2.0 machines because the
9023 two outputs would take two slots in the reorder buffers.
9025 This routine finds instructions which can be combined and combines
9026 them. We only support some of the potential combinations, and we
9027 only try common ways to find suitable instructions.
9029 * addb can add two registers or a register and a small integer
9030 and jump to a nearby (+-8k) location. Normally the jump to the
9031 nearby location is conditional on the result of the add, but by
9032 using the "true" condition we can make the jump unconditional.
9033 Thus addb can perform two independent operations in one insn.
9035 * movb is similar to addb in that it can perform a reg->reg
9036 or small immediate->reg copy and jump to a nearby (+-8k location).
9038 * fmpyadd and fmpysub can perform a FP multiply and either an
9039 FP add or FP sub if the operands of the multiply and add/sub are
9040 independent (there are other minor restrictions). Note both
9041 the fmpy and fadd/fsub can in theory move to better spots according
9042 to data dependencies, but for now we require the fmpy stay at a
9045 * Many of the memory operations can perform pre & post updates
9046 of index registers. GCC's pre/post increment/decrement addressing
9047 is far too simple to take advantage of all the possibilities. This
9048 pass may not be suitable since those insns may not be independent.
9050 * comclr can compare two ints or an int and a register, nullify
9051 the following instruction and zero some other register. This
9052 is more difficult to use as it's harder to find an insn which
9053 will generate a comclr than finding something like an unconditional
9054 branch. (conditional moves & long branches create comclr insns).
9056 * Most arithmetic operations can conditionally skip the next
9057 instruction. They can be viewed as "perform this operation
9058 and conditionally jump to this nearby location" (where nearby
9059 is an insns away). These are difficult to use due to the
9060 branch length restrictions. */
9063 pa_combine_instructions (void)
9067 /* This can get expensive since the basic algorithm is on the
9068 order of O(n^2) (or worse). Only do it for -O2 or higher
9069 levels of optimization. */
9073 /* Walk down the list of insns looking for "anchor" insns which
9074 may be combined with "floating" insns. As the name implies,
9075 "anchor" instructions don't move, while "floating" insns may
9077 rtx par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, NULL_RTX
, NULL_RTX
));
9078 rtx_insn
*new_rtx
= make_insn_raw (par
);
9080 for (anchor
= get_insns (); anchor
; anchor
= NEXT_INSN (anchor
))
9082 enum attr_pa_combine_type anchor_attr
;
9083 enum attr_pa_combine_type floater_attr
;
9085 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9086 Also ignore any special USE insns. */
9087 if ((! NONJUMP_INSN_P (anchor
) && ! JUMP_P (anchor
) && ! CALL_P (anchor
))
9088 || GET_CODE (PATTERN (anchor
)) == USE
9089 || GET_CODE (PATTERN (anchor
)) == CLOBBER
)
9092 anchor_attr
= get_attr_pa_combine_type (anchor
);
9093 /* See if anchor is an insn suitable for combination. */
9094 if (anchor_attr
== PA_COMBINE_TYPE_FMPY
9095 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9096 || (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
9097 && ! forward_branch_p (anchor
)))
9101 for (floater
= PREV_INSN (anchor
);
9103 floater
= PREV_INSN (floater
))
9105 if (NOTE_P (floater
)
9106 || (NONJUMP_INSN_P (floater
)
9107 && (GET_CODE (PATTERN (floater
)) == USE
9108 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
9111 /* Anything except a regular INSN will stop our search. */
9112 if (! NONJUMP_INSN_P (floater
))
9118 /* See if FLOATER is suitable for combination with the
9120 floater_attr
= get_attr_pa_combine_type (floater
);
9121 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
9122 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
9123 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9124 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
9126 /* If ANCHOR and FLOATER can be combined, then we're
9127 done with this pass. */
9128 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9129 SET_DEST (PATTERN (floater
)),
9130 XEXP (SET_SRC (PATTERN (floater
)), 0),
9131 XEXP (SET_SRC (PATTERN (floater
)), 1)))
9135 else if (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
9136 && floater_attr
== PA_COMBINE_TYPE_ADDMOVE
)
9138 if (GET_CODE (SET_SRC (PATTERN (floater
))) == PLUS
)
9140 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9141 SET_DEST (PATTERN (floater
)),
9142 XEXP (SET_SRC (PATTERN (floater
)), 0),
9143 XEXP (SET_SRC (PATTERN (floater
)), 1)))
9148 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9149 SET_DEST (PATTERN (floater
)),
9150 SET_SRC (PATTERN (floater
)),
9151 SET_SRC (PATTERN (floater
))))
9157 /* If we didn't find anything on the backwards scan try forwards. */
9159 && (anchor_attr
== PA_COMBINE_TYPE_FMPY
9160 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
))
9162 for (floater
= anchor
; floater
; floater
= NEXT_INSN (floater
))
9164 if (NOTE_P (floater
)
9165 || (NONJUMP_INSN_P (floater
)
9166 && (GET_CODE (PATTERN (floater
)) == USE
9167 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
9171 /* Anything except a regular INSN will stop our search. */
9172 if (! NONJUMP_INSN_P (floater
))
9178 /* See if FLOATER is suitable for combination with the
9180 floater_attr
= get_attr_pa_combine_type (floater
);
9181 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
9182 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
9183 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9184 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
9186 /* If ANCHOR and FLOATER can be combined, then we're
9187 done with this pass. */
9188 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 1,
9189 SET_DEST (PATTERN (floater
)),
9190 XEXP (SET_SRC (PATTERN (floater
)),
9192 XEXP (SET_SRC (PATTERN (floater
)),
9199 /* FLOATER will be nonzero if we found a suitable floating
9200 insn for combination with ANCHOR. */
9202 && (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9203 || anchor_attr
== PA_COMBINE_TYPE_FMPY
))
9205 /* Emit the new instruction and delete the old anchor. */
9206 rtvec vtemp
= gen_rtvec (2, copy_rtx (PATTERN (anchor
)),
9207 copy_rtx (PATTERN (floater
)));
9208 rtx temp
= gen_rtx_PARALLEL (VOIDmode
, vtemp
);
9209 emit_insn_before (temp
, anchor
);
9211 SET_INSN_DELETED (anchor
);
9213 /* Emit a special USE insn for FLOATER, then delete
9214 the floating insn. */
9215 temp
= copy_rtx (PATTERN (floater
));
9216 emit_insn_before (gen_rtx_USE (VOIDmode
, temp
), floater
);
9217 delete_insn (floater
);
9222 && anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
)
9224 /* Emit the new_jump instruction and delete the old anchor. */
9225 rtvec vtemp
= gen_rtvec (2, copy_rtx (PATTERN (anchor
)),
9226 copy_rtx (PATTERN (floater
)));
9227 rtx temp
= gen_rtx_PARALLEL (VOIDmode
, vtemp
);
9228 temp
= emit_jump_insn_before (temp
, anchor
);
9230 JUMP_LABEL (temp
) = JUMP_LABEL (anchor
);
9231 SET_INSN_DELETED (anchor
);
9233 /* Emit a special USE insn for FLOATER, then delete
9234 the floating insn. */
9235 temp
= copy_rtx (PATTERN (floater
));
9236 emit_insn_before (gen_rtx_USE (VOIDmode
, temp
), floater
);
9237 delete_insn (floater
);
9245 pa_can_combine_p (rtx_insn
*new_rtx
, rtx_insn
*anchor
, rtx_insn
*floater
,
9246 int reversed
, rtx dest
,
9249 int insn_code_number
;
9250 rtx_insn
*start
, *end
;
9252 /* Create a PARALLEL with the patterns of ANCHOR and
9253 FLOATER, try to recognize it, then test constraints
9254 for the resulting pattern.
9256 If the pattern doesn't match or the constraints
9257 aren't met keep searching for a suitable floater
9259 XVECEXP (PATTERN (new_rtx
), 0, 0) = PATTERN (anchor
);
9260 XVECEXP (PATTERN (new_rtx
), 0, 1) = PATTERN (floater
);
9261 INSN_CODE (new_rtx
) = -1;
9262 insn_code_number
= recog_memoized (new_rtx
);
9263 basic_block bb
= BLOCK_FOR_INSN (anchor
);
9264 if (insn_code_number
< 0
9265 || (extract_insn (new_rtx
),
9266 !constrain_operands (1, get_preferred_alternatives (new_rtx
, bb
))))
9280 /* There's up to three operands to consider. One
9281 output and two inputs.
9283 The output must not be used between FLOATER & ANCHOR
9284 exclusive. The inputs must not be set between
9285 FLOATER and ANCHOR exclusive. */
9287 if (reg_used_between_p (dest
, start
, end
))
9290 if (reg_set_between_p (src1
, start
, end
))
9293 if (reg_set_between_p (src2
, start
, end
))
9296 /* If we get here, then everything is good. */
9300 /* Return nonzero if references for INSN are delayed.
9302 Millicode insns are actually function calls with some special
9303 constraints on arguments and register usage.
9305 Millicode calls always expect their arguments in the integer argument
9306 registers, and always return their result in %r29 (ret1). They
9307 are expected to clobber their arguments, %r1, %r29, and the return
9308 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9310 This function tells reorg that the references to arguments and
9311 millicode calls do not appear to happen until after the millicode call.
9312 This allows reorg to put insns which set the argument registers into the
9313 delay slot of the millicode call -- thus they act more like traditional
9316 Note we cannot consider side effects of the insn to be delayed because
9317 the branch and link insn will clobber the return pointer. If we happened
9318 to use the return pointer in the delay slot of the call, then we lose.
9320 get_attr_type will try to recognize the given insn, so make sure to
9321 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9324 pa_insn_refs_are_delayed (rtx_insn
*insn
)
9326 return ((NONJUMP_INSN_P (insn
)
9327 && GET_CODE (PATTERN (insn
)) != SEQUENCE
9328 && GET_CODE (PATTERN (insn
)) != USE
9329 && GET_CODE (PATTERN (insn
)) != CLOBBER
9330 && get_attr_type (insn
) == TYPE_MILLI
));
9333 /* Promote the return value, but not the arguments. */
9336 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
9338 int *punsignedp ATTRIBUTE_UNUSED
,
9339 const_tree fntype ATTRIBUTE_UNUSED
,
9342 if (for_return
== 0)
9344 return promote_mode (type
, mode
, punsignedp
);
9347 /* On the HP-PA the value is found in register(s) 28(-29), unless
9348 the mode is SF or DF. Then the value is returned in fr4 (32).
9350 This must perform the same promotions as PROMOTE_MODE, else promoting
9351 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9353 Small structures must be returned in a PARALLEL on PA64 in order
9354 to match the HP Compiler ABI. */
9357 pa_function_value (const_tree valtype
,
9358 const_tree func ATTRIBUTE_UNUSED
,
9359 bool outgoing ATTRIBUTE_UNUSED
)
9361 machine_mode valmode
;
9363 if (AGGREGATE_TYPE_P (valtype
)
9364 || TREE_CODE (valtype
) == COMPLEX_TYPE
9365 || TREE_CODE (valtype
) == VECTOR_TYPE
)
9367 HOST_WIDE_INT valsize
= int_size_in_bytes (valtype
);
9369 /* Handle aggregates that fit exactly in a word or double word. */
9370 if ((valsize
& (UNITS_PER_WORD
- 1)) == 0)
9371 return gen_rtx_REG (TYPE_MODE (valtype
), 28);
9375 /* Aggregates with a size less than or equal to 128 bits are
9376 returned in GR 28(-29). They are left justified. The pad
9377 bits are undefined. Larger aggregates are returned in
9381 int ub
= valsize
<= UNITS_PER_WORD
? 1 : 2;
9383 for (i
= 0; i
< ub
; i
++)
9385 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
9386 gen_rtx_REG (DImode
, 28 + i
),
9391 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (ub
, loc
));
9393 else if (valsize
> UNITS_PER_WORD
)
9395 /* Aggregates 5 to 8 bytes in size are returned in general
9396 registers r28-r29 in the same manner as other non
9397 floating-point objects. The data is right-justified and
9398 zero-extended to 64 bits. This is opposite to the normal
9399 justification used on big endian targets and requires
9400 special treatment. */
9401 rtx loc
= gen_rtx_EXPR_LIST (VOIDmode
,
9402 gen_rtx_REG (DImode
, 28), const0_rtx
);
9403 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec (1, loc
));
9407 if ((INTEGRAL_TYPE_P (valtype
)
9408 && GET_MODE_BITSIZE (TYPE_MODE (valtype
)) < BITS_PER_WORD
)
9409 || POINTER_TYPE_P (valtype
))
9410 valmode
= word_mode
;
9412 valmode
= TYPE_MODE (valtype
);
9414 if (TREE_CODE (valtype
) == REAL_TYPE
9415 && !AGGREGATE_TYPE_P (valtype
)
9416 && TYPE_MODE (valtype
) != TFmode
9417 && !TARGET_SOFT_FLOAT
)
9418 return gen_rtx_REG (valmode
, 32);
9420 return gen_rtx_REG (valmode
, 28);
9423 /* Implement the TARGET_LIBCALL_VALUE hook. */
9426 pa_libcall_value (machine_mode mode
,
9427 const_rtx fun ATTRIBUTE_UNUSED
)
9429 if (! TARGET_SOFT_FLOAT
9430 && (mode
== SFmode
|| mode
== DFmode
))
9431 return gen_rtx_REG (mode
, 32);
9433 return gen_rtx_REG (mode
, 28);
9436 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9439 pa_function_value_regno_p (const unsigned int regno
)
9442 || (! TARGET_SOFT_FLOAT
&& regno
== 32))
9448 /* Update the data in CUM to advance over an argument
9449 of mode MODE and data type TYPE.
9450 (TYPE is null for libcalls where that information may not be available.) */
9453 pa_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
9454 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9456 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9457 int arg_size
= pa_function_arg_size (mode
, type
);
9459 cum
->nargs_prototype
--;
9460 cum
->words
+= (arg_size
9461 + ((cum
->words
& 01)
9462 && type
!= NULL_TREE
9466 /* Return the location of a parameter that is passed in a register or NULL
9467 if the parameter has any component that is passed in memory.
9469 This is new code and will be pushed to into the net sources after
9472 ??? We might want to restructure this so that it looks more like other
9475 pa_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
9476 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9478 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9479 int max_arg_words
= (TARGET_64BIT
? 8 : 4);
9486 if (mode
== VOIDmode
)
9489 arg_size
= pa_function_arg_size (mode
, type
);
9491 /* If this arg would be passed partially or totally on the stack, then
9492 this routine should return zero. pa_arg_partial_bytes will
9493 handle arguments which are split between regs and stack slots if
9494 the ABI mandates split arguments. */
9497 /* The 32-bit ABI does not split arguments. */
9498 if (cum
->words
+ arg_size
> max_arg_words
)
9504 alignment
= cum
->words
& 1;
9505 if (cum
->words
+ alignment
>= max_arg_words
)
9509 /* The 32bit ABIs and the 64bit ABIs are rather different,
9510 particularly in their handling of FP registers. We might
9511 be able to cleverly share code between them, but I'm not
9512 going to bother in the hope that splitting them up results
9513 in code that is more easily understood. */
9517 /* Advance the base registers to their current locations.
9519 Remember, gprs grow towards smaller register numbers while
9520 fprs grow to higher register numbers. Also remember that
9521 although FP regs are 32-bit addressable, we pretend that
9522 the registers are 64-bits wide. */
9523 gpr_reg_base
= 26 - cum
->words
;
9524 fpr_reg_base
= 32 + cum
->words
;
9526 /* Arguments wider than one word and small aggregates need special
9530 || (type
&& (AGGREGATE_TYPE_P (type
)
9531 || TREE_CODE (type
) == COMPLEX_TYPE
9532 || TREE_CODE (type
) == VECTOR_TYPE
)))
9534 /* Double-extended precision (80-bit), quad-precision (128-bit)
9535 and aggregates including complex numbers are aligned on
9536 128-bit boundaries. The first eight 64-bit argument slots
9537 are associated one-to-one, with general registers r26
9538 through r19, and also with floating-point registers fr4
9539 through fr11. Arguments larger than one word are always
9540 passed in general registers.
9542 Using a PARALLEL with a word mode register results in left
9543 justified data on a big-endian target. */
9546 int i
, offset
= 0, ub
= arg_size
;
9548 /* Align the base register. */
9549 gpr_reg_base
-= alignment
;
9551 ub
= MIN (ub
, max_arg_words
- cum
->words
- alignment
);
9552 for (i
= 0; i
< ub
; i
++)
9554 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
9555 gen_rtx_REG (DImode
, gpr_reg_base
),
9561 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (ub
, loc
));
9566 /* If the argument is larger than a word, then we know precisely
9567 which registers we must use. */
9581 /* Structures 5 to 8 bytes in size are passed in the general
9582 registers in the same manner as other non floating-point
9583 objects. The data is right-justified and zero-extended
9584 to 64 bits. This is opposite to the normal justification
9585 used on big endian targets and requires special treatment.
9586 We now define BLOCK_REG_PADDING to pad these objects.
9587 Aggregates, complex and vector types are passed in the same
9588 manner as structures. */
9590 || (type
&& (AGGREGATE_TYPE_P (type
)
9591 || TREE_CODE (type
) == COMPLEX_TYPE
9592 || TREE_CODE (type
) == VECTOR_TYPE
)))
9594 rtx loc
= gen_rtx_EXPR_LIST (VOIDmode
,
9595 gen_rtx_REG (DImode
, gpr_reg_base
),
9597 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec (1, loc
));
9602 /* We have a single word (32 bits). A simple computation
9603 will get us the register #s we need. */
9604 gpr_reg_base
= 26 - cum
->words
;
9605 fpr_reg_base
= 32 + 2 * cum
->words
;
9609 /* Determine if the argument needs to be passed in both general and
9610 floating point registers. */
9611 if (((TARGET_PORTABLE_RUNTIME
|| TARGET_64BIT
|| TARGET_ELF32
)
9612 /* If we are doing soft-float with portable runtime, then there
9613 is no need to worry about FP regs. */
9614 && !TARGET_SOFT_FLOAT
9615 /* The parameter must be some kind of scalar float, else we just
9616 pass it in integer registers. */
9617 && GET_MODE_CLASS (mode
) == MODE_FLOAT
9618 /* The target function must not have a prototype. */
9619 && cum
->nargs_prototype
<= 0
9620 /* libcalls do not need to pass items in both FP and general
9622 && type
!= NULL_TREE
9623 /* All this hair applies to "outgoing" args only. This includes
9624 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9626 /* Also pass outgoing floating arguments in both registers in indirect
9627 calls with the 32 bit ABI and the HP assembler since there is no
9628 way to the specify argument locations in static functions. */
9633 && GET_MODE_CLASS (mode
) == MODE_FLOAT
))
9639 gen_rtx_EXPR_LIST (VOIDmode
,
9640 gen_rtx_REG (mode
, fpr_reg_base
),
9642 gen_rtx_EXPR_LIST (VOIDmode
,
9643 gen_rtx_REG (mode
, gpr_reg_base
),
9648 /* See if we should pass this parameter in a general register. */
9649 if (TARGET_SOFT_FLOAT
9650 /* Indirect calls in the normal 32bit ABI require all arguments
9651 to be passed in general registers. */
9652 || (!TARGET_PORTABLE_RUNTIME
9656 /* If the parameter is not a scalar floating-point parameter,
9657 then it belongs in GPRs. */
9658 || GET_MODE_CLASS (mode
) != MODE_FLOAT
9659 /* Structure with single SFmode field belongs in GPR. */
9660 || (type
&& AGGREGATE_TYPE_P (type
)))
9661 retval
= gen_rtx_REG (mode
, gpr_reg_base
);
9663 retval
= gen_rtx_REG (mode
, fpr_reg_base
);
9668 /* Arguments larger than one word are double word aligned. */
9671 pa_function_arg_boundary (machine_mode mode
, const_tree type
)
9673 bool singleword
= (type
9674 ? (integer_zerop (TYPE_SIZE (type
))
9675 || !TREE_CONSTANT (TYPE_SIZE (type
))
9676 || int_size_in_bytes (type
) <= UNITS_PER_WORD
)
9677 : GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
);
9679 return singleword
? PARM_BOUNDARY
: MAX_PARM_BOUNDARY
;
9682 /* If this arg would be passed totally in registers or totally on the stack,
9683 then this routine should return zero. */
9686 pa_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
9687 tree type
, bool named ATTRIBUTE_UNUSED
)
9689 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9690 unsigned int max_arg_words
= 8;
9691 unsigned int offset
= 0;
9696 if (pa_function_arg_size (mode
, type
) > 1 && (cum
->words
& 1))
9699 if (cum
->words
+ offset
+ pa_function_arg_size (mode
, type
) <= max_arg_words
)
9700 /* Arg fits fully into registers. */
9702 else if (cum
->words
+ offset
>= max_arg_words
)
9703 /* Arg fully on the stack. */
9707 return (max_arg_words
- cum
->words
- offset
) * UNITS_PER_WORD
;
9711 /* A get_unnamed_section callback for switching to the text section.
9713 This function is only used with SOM. Because we don't support
9714 named subspaces, we can only create a new subspace or switch back
9715 to the default text subspace. */
9718 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
9720 gcc_assert (TARGET_SOM
);
9723 if (cfun
&& cfun
->machine
&& !cfun
->machine
->in_nsubspa
)
9725 /* We only want to emit a .nsubspa directive once at the
9726 start of the function. */
9727 cfun
->machine
->in_nsubspa
= 1;
9729 /* Create a new subspace for the text. This provides
9730 better stub placement and one-only functions. */
9732 && DECL_ONE_ONLY (cfun
->decl
)
9733 && !DECL_WEAK (cfun
->decl
))
9735 output_section_asm_op ("\t.SPACE $TEXT$\n"
9736 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9737 "ACCESS=44,SORT=24,COMDAT");
9743 /* There isn't a current function or the body of the current
9744 function has been completed. So, we are changing to the
9745 text section to output debugging information. Thus, we
9746 need to forget that we are in the text section so that
9747 varasm.c will call us when text_section is selected again. */
9748 gcc_assert (!cfun
|| !cfun
->machine
9749 || cfun
->machine
->in_nsubspa
== 2);
9752 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9755 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9758 /* A get_unnamed_section callback for switching to comdat data
9759 sections. This function is only used with SOM. */
9762 som_output_comdat_data_section_asm_op (const void *data
)
9765 output_section_asm_op (data
);
9768 /* Implement TARGET_ASM_INIT_SECTIONS. */
9771 pa_som_asm_init_sections (void)
9774 = get_unnamed_section (0, som_output_text_section_asm_op
, NULL
);
9776 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9777 is not being generated. */
9778 som_readonly_data_section
9779 = get_unnamed_section (0, output_section_asm_op
,
9780 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9782 /* When secondary definitions are not supported, SOM makes readonly
9783 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9785 som_one_only_readonly_data_section
9786 = get_unnamed_section (0, som_output_comdat_data_section_asm_op
,
9788 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9789 "ACCESS=0x2c,SORT=16,COMDAT");
9792 /* When secondary definitions are not supported, SOM makes data one-only
9793 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9794 som_one_only_data_section
9795 = get_unnamed_section (SECTION_WRITE
,
9796 som_output_comdat_data_section_asm_op
,
9797 "\t.SPACE $PRIVATE$\n"
9798 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9799 "ACCESS=31,SORT=24,COMDAT");
9802 som_tm_clone_table_section
9803 = get_unnamed_section (0, output_section_asm_op
,
9804 "\t.SPACE $PRIVATE$\n\t.SUBSPA $TM_CLONE_TABLE$");
9806 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9807 which reference data within the $TEXT$ space (for example constant
9808 strings in the $LIT$ subspace).
9810 The assemblers (GAS and HP as) both have problems with handling
9811 the difference of two symbols which is the other correct way to
9812 reference constant data during PIC code generation.
9814 So, there's no way to reference constant data which is in the
9815 $TEXT$ space during PIC generation. Instead place all constant
9816 data into the $PRIVATE$ subspace (this reduces sharing, but it
9817 works correctly). */
9818 readonly_data_section
= flag_pic
? data_section
: som_readonly_data_section
;
9820 /* We must not have a reference to an external symbol defined in a
9821 shared library in a readonly section, else the SOM linker will
9824 So, we force exception information into the data section. */
9825 exception_section
= data_section
;
9828 /* Implement TARGET_ASM_TM_CLONE_TABLE_SECTION. */
9831 pa_som_tm_clone_table_section (void)
9833 return som_tm_clone_table_section
;
9836 /* On hpux10, the linker will give an error if we have a reference
9837 in the read-only data section to a symbol defined in a shared
9838 library. Therefore, expressions that might require a reloc
9839 cannot be placed in the read-only data section. */
9842 pa_select_section (tree exp
, int reloc
,
9843 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
9845 if (TREE_CODE (exp
) == VAR_DECL
9846 && TREE_READONLY (exp
)
9847 && !TREE_THIS_VOLATILE (exp
)
9848 && DECL_INITIAL (exp
)
9849 && (DECL_INITIAL (exp
) == error_mark_node
9850 || TREE_CONSTANT (DECL_INITIAL (exp
)))
9854 && DECL_ONE_ONLY (exp
)
9855 && !DECL_WEAK (exp
))
9856 return som_one_only_readonly_data_section
;
9858 return readonly_data_section
;
9860 else if (CONSTANT_CLASS_P (exp
) && !reloc
)
9861 return readonly_data_section
;
9863 && TREE_CODE (exp
) == VAR_DECL
9864 && DECL_ONE_ONLY (exp
)
9865 && !DECL_WEAK (exp
))
9866 return som_one_only_data_section
;
9868 return data_section
;
9871 /* Implement pa_reloc_rw_mask. */
9874 pa_reloc_rw_mask (void)
9876 /* We force (const (plus (symbol) (const_int))) to memory when the
9877 const_int doesn't fit in a 14-bit integer. The SOM linker can't
9878 handle this construct in read-only memory and we want to avoid
9879 this for ELF. So, we always force an RTX needing relocation to
9880 the data section. */
9885 pa_globalize_label (FILE *stream
, const char *name
)
9887 /* We only handle DATA objects here, functions are globalized in
9888 ASM_DECLARE_FUNCTION_NAME. */
9889 if (! FUNCTION_NAME_P (name
))
9891 fputs ("\t.EXPORT ", stream
);
9892 assemble_name (stream
, name
);
9893 fputs (",DATA\n", stream
);
9897 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9900 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9901 int incoming ATTRIBUTE_UNUSED
)
9903 return gen_rtx_REG (Pmode
, PA_STRUCT_VALUE_REGNUM
);
9906 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9909 pa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
9911 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9912 PA64 ABI says that objects larger than 128 bits are returned in memory.
9913 Note, int_size_in_bytes can return -1 if the size of the object is
9914 variable or larger than the maximum value that can be expressed as
9915 a HOST_WIDE_INT. It can also return zero for an empty type. The
9916 simplest way to handle variable and empty types is to pass them in
9917 memory. This avoids problems in defining the boundaries of argument
9918 slots, allocating registers, etc. */
9919 return (int_size_in_bytes (type
) > (TARGET_64BIT
? 16 : 8)
9920 || int_size_in_bytes (type
) <= 0);
9923 /* Structure to hold declaration and name of external symbols that are
9924 emitted by GCC. We generate a vector of these symbols and output them
9925 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9926 This avoids putting out names that are never really used. */
9928 typedef struct GTY(()) extern_symbol
9934 /* Define gc'd vector type for extern_symbol. */
9936 /* Vector of extern_symbol pointers. */
9937 static GTY(()) vec
<extern_symbol
, va_gc
> *extern_symbols
;
9939 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9940 /* Mark DECL (name NAME) as an external reference (assembler output
9941 file FILE). This saves the names to output at the end of the file
9942 if actually referenced. */
9945 pa_hpux_asm_output_external (FILE *file
, tree decl
, const char *name
)
9947 gcc_assert (file
== asm_out_file
);
9948 extern_symbol p
= {decl
, name
};
9949 vec_safe_push (extern_symbols
, p
);
9953 /* Output text required at the end of an assembler file.
9954 This includes deferred plabels and .import directives for
9955 all external symbols that were actually referenced. */
9960 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9964 if (!NO_DEFERRED_PROFILE_COUNTERS
)
9965 output_deferred_profile_counters ();
9968 output_deferred_plabels ();
9970 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9971 for (i
= 0; vec_safe_iterate (extern_symbols
, i
, &p
); i
++)
9973 tree decl
= p
->decl
;
9975 if (!TREE_ASM_WRITTEN (decl
)
9976 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl
), 0)))
9977 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file
, decl
, p
->name
);
9980 vec_free (extern_symbols
);
9983 if (NEED_INDICATE_EXEC_STACK
)
9984 file_end_indicate_exec_stack ();
9987 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
9990 pa_can_change_mode_class (machine_mode from
, machine_mode to
,
9996 if (GET_MODE_SIZE (from
) == GET_MODE_SIZE (to
))
9999 /* Reject changes to/from modes with zero size. */
10000 if (!GET_MODE_SIZE (from
) || !GET_MODE_SIZE (to
))
10003 /* Reject changes to/from complex and vector modes. */
10004 if (COMPLEX_MODE_P (from
) || VECTOR_MODE_P (from
)
10005 || COMPLEX_MODE_P (to
) || VECTOR_MODE_P (to
))
10008 /* There is no way to load QImode or HImode values directly from memory
10009 to a FP register. SImode loads to the FP registers are not zero
10010 extended. On the 64-bit target, this conflicts with the definition
10011 of LOAD_EXTEND_OP. Thus, we can't allow changing between modes with
10012 different sizes in the floating-point registers. */
10013 if (MAYBE_FP_REG_CLASS_P (rclass
))
10016 /* TARGET_HARD_REGNO_MODE_OK places modes with sizes larger than a word
10017 in specific sets of registers. Thus, we cannot allow changing
10018 to a larger mode when it's larger than a word. */
10019 if (GET_MODE_SIZE (to
) > UNITS_PER_WORD
10020 && GET_MODE_SIZE (to
) > GET_MODE_SIZE (from
))
10026 /* Implement TARGET_MODES_TIEABLE_P.
10028 We should return FALSE for QImode and HImode because these modes
10029 are not ok in the floating-point registers. However, this prevents
10030 tieing these modes to SImode and DImode in the general registers.
10031 So, this isn't a good idea. We rely on TARGET_HARD_REGNO_MODE_OK and
10032 TARGET_CAN_CHANGE_MODE_CLASS to prevent these modes from being used
10033 in the floating-point registers. */
10036 pa_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
10038 /* Don't tie modes in different classes. */
10039 if (GET_MODE_CLASS (mode1
) != GET_MODE_CLASS (mode2
))
10046 /* Length in units of the trampoline instruction code. */
10048 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
10051 /* Output assembler code for a block containing the constant parts
10052 of a trampoline, leaving space for the variable parts.\
10054 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
10055 and then branches to the specified routine.
10057 This code template is copied from text segment to stack location
10058 and then patched with pa_trampoline_init to contain valid values,
10059 and then entered as a subroutine.
10061 It is best to keep this as small as possible to avoid having to
10062 flush multiple lines in the cache. */
10065 pa_asm_trampoline_template (FILE *f
)
10069 fputs ("\tldw 36(%r22),%r21\n", f
);
10070 fputs ("\tbb,>=,n %r21,30,.+16\n", f
);
10071 if (ASSEMBLER_DIALECT
== 0)
10072 fputs ("\tdepi 0,31,2,%r21\n", f
);
10074 fputs ("\tdepwi 0,31,2,%r21\n", f
);
10075 fputs ("\tldw 4(%r21),%r19\n", f
);
10076 fputs ("\tldw 0(%r21),%r21\n", f
);
10079 fputs ("\tbve (%r21)\n", f
);
10080 fputs ("\tldw 40(%r22),%r29\n", f
);
10081 fputs ("\t.word 0\n", f
);
10082 fputs ("\t.word 0\n", f
);
10086 fputs ("\tldsid (%r21),%r1\n", f
);
10087 fputs ("\tmtsp %r1,%sr0\n", f
);
10088 fputs ("\tbe 0(%sr0,%r21)\n", f
);
10089 fputs ("\tldw 40(%r22),%r29\n", f
);
10091 fputs ("\t.word 0\n", f
);
10092 fputs ("\t.word 0\n", f
);
10093 fputs ("\t.word 0\n", f
);
10094 fputs ("\t.word 0\n", f
);
10098 fputs ("\t.dword 0\n", f
);
10099 fputs ("\t.dword 0\n", f
);
10100 fputs ("\t.dword 0\n", f
);
10101 fputs ("\t.dword 0\n", f
);
10102 fputs ("\tmfia %r31\n", f
);
10103 fputs ("\tldd 24(%r31),%r1\n", f
);
10104 fputs ("\tldd 24(%r1),%r27\n", f
);
10105 fputs ("\tldd 16(%r1),%r1\n", f
);
10106 fputs ("\tbve (%r1)\n", f
);
10107 fputs ("\tldd 32(%r31),%r31\n", f
);
10108 fputs ("\t.dword 0 ; fptr\n", f
);
10109 fputs ("\t.dword 0 ; static link\n", f
);
10113 /* Emit RTL insns to initialize the variable parts of a trampoline.
10114 FNADDR is an RTX for the address of the function's pure code.
10115 CXT is an RTX for the static chain value for the function.
10117 Move the function address to the trampoline template at offset 36.
10118 Move the static chain value to trampoline template at offset 40.
10119 Move the trampoline address to trampoline template at offset 44.
10120 Move r19 to trampoline template at offset 48. The latter two
10121 words create a plabel for the indirect call to the trampoline.
10123 A similar sequence is used for the 64-bit port but the plabel is
10124 at the beginning of the trampoline.
10126 Finally, the cache entries for the trampoline code are flushed.
10127 This is necessary to ensure that the trampoline instruction sequence
10128 is written to memory prior to any attempts at prefetching the code
10132 pa_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
10134 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
10135 rtx start_addr
= gen_reg_rtx (Pmode
);
10136 rtx end_addr
= gen_reg_rtx (Pmode
);
10137 rtx line_length
= gen_reg_rtx (Pmode
);
10140 emit_block_move (m_tramp
, assemble_trampoline_template (),
10141 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
10142 r_tramp
= force_reg (Pmode
, XEXP (m_tramp
, 0));
10146 tmp
= adjust_address (m_tramp
, Pmode
, 36);
10147 emit_move_insn (tmp
, fnaddr
);
10148 tmp
= adjust_address (m_tramp
, Pmode
, 40);
10149 emit_move_insn (tmp
, chain_value
);
10151 /* Create a fat pointer for the trampoline. */
10152 tmp
= adjust_address (m_tramp
, Pmode
, 44);
10153 emit_move_insn (tmp
, r_tramp
);
10154 tmp
= adjust_address (m_tramp
, Pmode
, 48);
10155 emit_move_insn (tmp
, gen_rtx_REG (Pmode
, 19));
10157 /* fdc and fic only use registers for the address to flush,
10158 they do not accept integer displacements. We align the
10159 start and end addresses to the beginning of their respective
10160 cache lines to minimize the number of lines flushed. */
10161 emit_insn (gen_andsi3 (start_addr
, r_tramp
,
10162 GEN_INT (-MIN_CACHELINE_SIZE
)));
10163 tmp
= force_reg (Pmode
, plus_constant (Pmode
, r_tramp
,
10164 TRAMPOLINE_CODE_SIZE
-1));
10165 emit_insn (gen_andsi3 (end_addr
, tmp
,
10166 GEN_INT (-MIN_CACHELINE_SIZE
)));
10167 emit_move_insn (line_length
, GEN_INT (MIN_CACHELINE_SIZE
));
10168 emit_insn (gen_dcacheflushsi (start_addr
, end_addr
, line_length
));
10169 emit_insn (gen_icacheflushsi (start_addr
, end_addr
, line_length
,
10170 gen_reg_rtx (Pmode
),
10171 gen_reg_rtx (Pmode
)));
10175 tmp
= adjust_address (m_tramp
, Pmode
, 56);
10176 emit_move_insn (tmp
, fnaddr
);
10177 tmp
= adjust_address (m_tramp
, Pmode
, 64);
10178 emit_move_insn (tmp
, chain_value
);
10180 /* Create a fat pointer for the trampoline. */
10181 tmp
= adjust_address (m_tramp
, Pmode
, 16);
10182 emit_move_insn (tmp
, force_reg (Pmode
, plus_constant (Pmode
,
10184 tmp
= adjust_address (m_tramp
, Pmode
, 24);
10185 emit_move_insn (tmp
, gen_rtx_REG (Pmode
, 27));
10187 /* fdc and fic only use registers for the address to flush,
10188 they do not accept integer displacements. We align the
10189 start and end addresses to the beginning of their respective
10190 cache lines to minimize the number of lines flushed. */
10191 tmp
= force_reg (Pmode
, plus_constant (Pmode
, r_tramp
, 32));
10192 emit_insn (gen_anddi3 (start_addr
, tmp
,
10193 GEN_INT (-MIN_CACHELINE_SIZE
)));
10194 tmp
= force_reg (Pmode
, plus_constant (Pmode
, tmp
,
10195 TRAMPOLINE_CODE_SIZE
- 1));
10196 emit_insn (gen_anddi3 (end_addr
, tmp
,
10197 GEN_INT (-MIN_CACHELINE_SIZE
)));
10198 emit_move_insn (line_length
, GEN_INT (MIN_CACHELINE_SIZE
));
10199 emit_insn (gen_dcacheflushdi (start_addr
, end_addr
, line_length
));
10200 emit_insn (gen_icacheflushdi (start_addr
, end_addr
, line_length
,
10201 gen_reg_rtx (Pmode
),
10202 gen_reg_rtx (Pmode
)));
10205 #ifdef HAVE_ENABLE_EXECUTE_STACK
10206 Â
emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
10207 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
10211 /* Perform any machine-specific adjustment in the address of the trampoline.
10212 ADDR contains the address that was passed to pa_trampoline_init.
10213 Adjust the trampoline address to point to the plabel at offset 44. */
10216 pa_trampoline_adjust_address (rtx addr
)
10219 addr
= memory_address (Pmode
, plus_constant (Pmode
, addr
, 46));
10224 pa_delegitimize_address (rtx orig_x
)
10226 rtx x
= delegitimize_mem_from_attrs (orig_x
);
10228 if (GET_CODE (x
) == LO_SUM
10229 && GET_CODE (XEXP (x
, 1)) == UNSPEC
10230 && XINT (XEXP (x
, 1), 1) == UNSPEC_DLTIND14R
)
10231 return gen_const_mem (Pmode
, XVECEXP (XEXP (x
, 1), 0, 0));
10236 pa_internal_arg_pointer (void)
10238 /* The argument pointer and the hard frame pointer are the same in
10239 the 32-bit runtime, so we don't need a copy. */
10241 return copy_to_reg (virtual_incoming_args_rtx
);
10243 return virtual_incoming_args_rtx
;
10246 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10247 Frame pointer elimination is automatically handled. */
10250 pa_can_eliminate (const int from
, const int to
)
10252 /* The argument cannot be eliminated in the 64-bit runtime. */
10253 if (TARGET_64BIT
&& from
== ARG_POINTER_REGNUM
)
10256 return (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
10257 ? ! frame_pointer_needed
10261 /* Define the offset between two registers, FROM to be eliminated and its
10262 replacement TO, at the start of a routine. */
10264 pa_initial_elimination_offset (int from
, int to
)
10266 HOST_WIDE_INT offset
;
10268 if ((from
== HARD_FRAME_POINTER_REGNUM
|| from
== FRAME_POINTER_REGNUM
)
10269 && to
== STACK_POINTER_REGNUM
)
10270 offset
= -pa_compute_frame_size (get_frame_size (), 0);
10271 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
10274 gcc_unreachable ();
10280 pa_conditional_register_usage (void)
10284 if (!TARGET_64BIT
&& !TARGET_PA_11
)
10286 for (i
= 56; i
<= FP_REG_LAST
; i
++)
10287 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10288 for (i
= 33; i
< 56; i
+= 2)
10289 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10291 if (TARGET_DISABLE_FPREGS
|| TARGET_SOFT_FLOAT
)
10293 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
10294 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10297 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10300 /* Target hook for c_mode_for_suffix. */
10302 static machine_mode
10303 pa_c_mode_for_suffix (char suffix
)
10305 if (HPUX_LONG_DOUBLE_LIBRARY
)
10314 /* Target hook for function_section. */
10317 pa_function_section (tree decl
, enum node_frequency freq
,
10318 bool startup
, bool exit
)
10320 /* Put functions in text section if target doesn't have named sections. */
10321 if (!targetm_common
.have_named_sections
)
10322 return text_section
;
10324 /* Force nested functions into the same section as the containing
10327 && DECL_SECTION_NAME (decl
) == NULL
10328 && DECL_CONTEXT (decl
) != NULL_TREE
10329 && TREE_CODE (DECL_CONTEXT (decl
)) == FUNCTION_DECL
10330 && DECL_SECTION_NAME (DECL_CONTEXT (decl
)) == NULL
)
10331 return function_section (DECL_CONTEXT (decl
));
10333 /* Otherwise, use the default function section. */
10334 return default_function_section (decl
, freq
, startup
, exit
);
10337 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
10339 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
10340 that need more than three instructions to load prior to reload. This
10341 limit is somewhat arbitrary. It takes three instructions to load a
10342 CONST_INT from memory but two are memory accesses. It may be better
10343 to increase the allowed range for CONST_INTS. We may also be able
10344 to handle CONST_DOUBLES. */
10347 pa_legitimate_constant_p (machine_mode mode
, rtx x
)
10349 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& x
!= CONST0_RTX (mode
))
10352 if (!NEW_HP_ASSEMBLER
&& !TARGET_GAS
&& GET_CODE (x
) == LABEL_REF
)
10355 /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not
10356 legitimate constants. The other variants can't be handled by
10357 the move patterns after reload starts. */
10358 if (tls_referenced_p (x
))
10361 if (TARGET_64BIT
&& GET_CODE (x
) == CONST_DOUBLE
)
10365 && HOST_BITS_PER_WIDE_INT
> 32
10366 && GET_CODE (x
) == CONST_INT
10367 && !reload_in_progress
10368 && !reload_completed
10369 && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x
))
10370 && !pa_cint_ok_for_move (UINTVAL (x
)))
10373 if (function_label_operand (x
, mode
))
10379 /* Implement TARGET_SECTION_TYPE_FLAGS. */
10381 static unsigned int
10382 pa_section_type_flags (tree decl
, const char *name
, int reloc
)
10384 unsigned int flags
;
10386 flags
= default_section_type_flags (decl
, name
, reloc
);
10388 /* Function labels are placed in the constant pool. This can
10389 cause a section conflict if decls are put in ".data.rel.ro"
10390 or ".data.rel.ro.local" using the __attribute__ construct. */
10391 if (strcmp (name
, ".data.rel.ro") == 0
10392 || strcmp (name
, ".data.rel.ro.local") == 0)
10393 flags
|= SECTION_WRITE
| SECTION_RELRO
;
10398 /* pa_legitimate_address_p recognizes an RTL expression that is a
10399 valid memory address for an instruction. The MODE argument is the
10400 machine mode for the MEM expression that wants to use this address.
10402 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
10403 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
10404 available with floating point loads and stores, and integer loads.
10405 We get better code by allowing indexed addresses in the initial
10408 The acceptance of indexed addresses as legitimate implies that we
10409 must provide patterns for doing indexed integer stores, or the move
10410 expanders must force the address of an indexed store to a register.
10411 We have adopted the latter approach.
10413 Another function of pa_legitimate_address_p is to ensure that
10414 the base register is a valid pointer for indexed instructions.
10415 On targets that have non-equivalent space registers, we have to
10416 know at the time of assembler output which register in a REG+REG
10417 pair is the base register. The REG_POINTER flag is sometimes lost
10418 in reload and the following passes, so it can't be relied on during
10419 code generation. Thus, we either have to canonicalize the order
10420 of the registers in REG+REG indexed addresses, or treat REG+REG
10421 addresses separately and provide patterns for both permutations.
10423 The latter approach requires several hundred additional lines of
10424 code in pa.md. The downside to canonicalizing is that a PLUS
10425 in the wrong order can't combine to form to make a scaled indexed
10426 memory operand. As we won't need to canonicalize the operands if
10427 the REG_POINTER lossage can be fixed, it seems better canonicalize.
10429 We initially break out scaled indexed addresses in canonical order
10430 in pa_emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
10431 scaled indexed addresses during RTL generation. However, fold_rtx
10432 has its own opinion on how the operands of a PLUS should be ordered.
10433 If one of the operands is equivalent to a constant, it will make
10434 that operand the second operand. As the base register is likely to
10435 be equivalent to a SYMBOL_REF, we have made it the second operand.
10437 pa_legitimate_address_p accepts REG+REG as legitimate when the
10438 operands are in the order INDEX+BASE on targets with non-equivalent
10439 space registers, and in any order on targets with equivalent space
10440 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
10442 We treat a SYMBOL_REF as legitimate if it is part of the current
10443 function's constant-pool, because such addresses can actually be
10444 output as REG+SMALLINT. */
10447 pa_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
10450 && (strict
? STRICT_REG_OK_FOR_BASE_P (x
)
10451 : REG_OK_FOR_BASE_P (x
)))
10452 || ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_DEC
10453 || GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_INC
)
10454 && REG_P (XEXP (x
, 0))
10455 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 0))
10456 : REG_OK_FOR_BASE_P (XEXP (x
, 0)))))
10459 if (GET_CODE (x
) == PLUS
)
10463 /* For REG+REG, the base register should be in XEXP (x, 1),
10464 so check it first. */
10465 if (REG_P (XEXP (x
, 1))
10466 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 1))
10467 : REG_OK_FOR_BASE_P (XEXP (x
, 1))))
10468 base
= XEXP (x
, 1), index
= XEXP (x
, 0);
10469 else if (REG_P (XEXP (x
, 0))
10470 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 0))
10471 : REG_OK_FOR_BASE_P (XEXP (x
, 0))))
10472 base
= XEXP (x
, 0), index
= XEXP (x
, 1);
10476 if (GET_CODE (index
) == CONST_INT
)
10478 if (INT_5_BITS (index
))
10481 /* When INT14_OK_STRICT is false, a secondary reload is needed
10482 to adjust the displacement of SImode and DImode floating point
10483 instructions but this may fail when the register also needs
10484 reloading. So, we return false when STRICT is true. We
10485 also reject long displacements for float mode addresses since
10486 the majority of accesses will use floating point instructions
10487 that don't support 14-bit offsets. */
10488 if (!INT14_OK_STRICT
10489 && (strict
|| !(reload_in_progress
|| reload_completed
))
10494 return base14_operand (index
, mode
);
10497 if (!TARGET_DISABLE_INDEXING
10498 /* Only accept the "canonical" INDEX+BASE operand order
10499 on targets with non-equivalent space registers. */
10500 && (TARGET_NO_SPACE_REGS
10502 : (base
== XEXP (x
, 1) && REG_P (index
)
10503 && (reload_completed
10504 || (reload_in_progress
&& HARD_REGISTER_P (base
))
10505 || REG_POINTER (base
))
10506 && (reload_completed
10507 || (reload_in_progress
&& HARD_REGISTER_P (index
))
10508 || !REG_POINTER (index
))))
10509 && MODE_OK_FOR_UNSCALED_INDEXING_P (mode
)
10510 && (strict
? STRICT_REG_OK_FOR_INDEX_P (index
)
10511 : REG_OK_FOR_INDEX_P (index
))
10512 && borx_reg_operand (base
, Pmode
)
10513 && borx_reg_operand (index
, Pmode
))
10516 if (!TARGET_DISABLE_INDEXING
10517 && GET_CODE (index
) == MULT
10518 /* Only accept base operands with the REG_POINTER flag prior to
10519 reload on targets with non-equivalent space registers. */
10520 && (TARGET_NO_SPACE_REGS
10521 || (base
== XEXP (x
, 1)
10522 && (reload_completed
10523 || (reload_in_progress
&& HARD_REGISTER_P (base
))
10524 || REG_POINTER (base
))))
10525 && REG_P (XEXP (index
, 0))
10526 && GET_MODE (XEXP (index
, 0)) == Pmode
10527 && MODE_OK_FOR_SCALED_INDEXING_P (mode
)
10528 && (strict
? STRICT_REG_OK_FOR_INDEX_P (XEXP (index
, 0))
10529 : REG_OK_FOR_INDEX_P (XEXP (index
, 0)))
10530 && GET_CODE (XEXP (index
, 1)) == CONST_INT
10531 && INTVAL (XEXP (index
, 1))
10532 == (HOST_WIDE_INT
) GET_MODE_SIZE (mode
)
10533 && borx_reg_operand (base
, Pmode
))
10539 if (GET_CODE (x
) == LO_SUM
)
10541 rtx y
= XEXP (x
, 0);
10543 if (GET_CODE (y
) == SUBREG
)
10544 y
= SUBREG_REG (y
);
10547 && (strict
? STRICT_REG_OK_FOR_BASE_P (y
)
10548 : REG_OK_FOR_BASE_P (y
)))
10550 /* Needed for -fPIC */
10552 && GET_CODE (XEXP (x
, 1)) == UNSPEC
)
10555 if (!INT14_OK_STRICT
10556 && (strict
|| !(reload_in_progress
|| reload_completed
))
10561 if (CONSTANT_P (XEXP (x
, 1)))
10567 if (GET_CODE (x
) == CONST_INT
&& INT_5_BITS (x
))
10573 /* Look for machine dependent ways to make the invalid address AD a
10576 For the PA, transform:
10578 memory(X + <large int>)
10582 if (<large int> & mask) >= 16
10583 Y = (<large int> & ~mask) + mask + 1 Round up.
10585 Y = (<large int> & ~mask) Round down.
10587 memory (Z + (<large int> - Y));
10589 This makes reload inheritance and reload_cse work better since Z
10592 There may be more opportunities to improve code with this hook. */
10595 pa_legitimize_reload_address (rtx ad
, machine_mode mode
,
10596 int opnum
, int type
,
10597 int ind_levels ATTRIBUTE_UNUSED
)
10599 long offset
, newoffset
, mask
;
10600 rtx new_rtx
, temp
= NULL_RTX
;
10602 mask
= (GET_MODE_CLASS (mode
) == MODE_FLOAT
10603 && !INT14_OK_STRICT
? 0x1f : 0x3fff);
10605 if (optimize
&& GET_CODE (ad
) == PLUS
)
10606 temp
= simplify_binary_operation (PLUS
, Pmode
,
10607 XEXP (ad
, 0), XEXP (ad
, 1));
10609 new_rtx
= temp
? temp
: ad
;
10612 && GET_CODE (new_rtx
) == PLUS
10613 && GET_CODE (XEXP (new_rtx
, 0)) == REG
10614 && GET_CODE (XEXP (new_rtx
, 1)) == CONST_INT
)
10616 offset
= INTVAL (XEXP ((new_rtx
), 1));
10618 /* Choose rounding direction. Round up if we are >= halfway. */
10619 if ((offset
& mask
) >= ((mask
+ 1) / 2))
10620 newoffset
= (offset
& ~mask
) + mask
+ 1;
10622 newoffset
= offset
& ~mask
;
10624 /* Ensure that long displacements are aligned. */
10626 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
10627 || (TARGET_64BIT
&& (mode
) == DImode
)))
10628 newoffset
&= ~(GET_MODE_SIZE (mode
) - 1);
10630 if (newoffset
!= 0 && VAL_14_BITS_P (newoffset
))
10632 temp
= gen_rtx_PLUS (Pmode
, XEXP (new_rtx
, 0),
10633 GEN_INT (newoffset
));
10634 ad
= gen_rtx_PLUS (Pmode
, temp
, GEN_INT (offset
- newoffset
));
10635 push_reload (XEXP (ad
, 0), 0, &XEXP (ad
, 0), 0,
10636 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
10637 opnum
, (enum reload_type
) type
);
10645 /* Output address vector. */
10648 pa_output_addr_vec (rtx lab
, rtx body
)
10650 int idx
, vlen
= XVECLEN (body
, 0);
10653 fputs ("\t.align 4\n", asm_out_file
);
10654 targetm
.asm_out
.internal_label (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10656 fputs ("\t.begin_brtab\n", asm_out_file
);
10657 for (idx
= 0; idx
< vlen
; idx
++)
10659 ASM_OUTPUT_ADDR_VEC_ELT
10660 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10663 fputs ("\t.end_brtab\n", asm_out_file
);
10666 /* Output address difference vector. */
10669 pa_output_addr_diff_vec (rtx lab
, rtx body
)
10671 rtx base
= XEXP (XEXP (body
, 0), 0);
10672 int idx
, vlen
= XVECLEN (body
, 1);
10674 targetm
.asm_out
.internal_label (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10676 fputs ("\t.begin_brtab\n", asm_out_file
);
10677 for (idx
= 0; idx
< vlen
; idx
++)
10679 ASM_OUTPUT_ADDR_DIFF_ELT
10682 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10683 CODE_LABEL_NUMBER (base
));
10686 fputs ("\t.end_brtab\n", asm_out_file
);
10689 /* This is a helper function for the other atomic operations. This function
10690 emits a loop that contains SEQ that iterates until a compare-and-swap
10691 operation at the end succeeds. MEM is the memory to be modified. SEQ is
10692 a set of instructions that takes a value from OLD_REG as an input and
10693 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
10694 set to the current contents of MEM. After SEQ, a compare-and-swap will
10695 attempt to update MEM with NEW_REG. The function returns true when the
10696 loop was generated successfully. */
10699 pa_expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
10701 machine_mode mode
= GET_MODE (mem
);
10702 rtx_code_label
*label
;
10703 rtx cmp_reg
, success
, oldval
;
10705 /* The loop we want to generate looks like
10711 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
10715 Note that we only do the plain load from memory once. Subsequent
10716 iterations use the value loaded by the compare-and-swap pattern. */
10718 label
= gen_label_rtx ();
10719 cmp_reg
= gen_reg_rtx (mode
);
10721 emit_move_insn (cmp_reg
, mem
);
10722 emit_label (label
);
10723 emit_move_insn (old_reg
, cmp_reg
);
10727 success
= NULL_RTX
;
10729 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
10730 new_reg
, false, MEMMODEL_SYNC_SEQ_CST
,
10734 if (oldval
!= cmp_reg
)
10735 emit_move_insn (cmp_reg
, oldval
);
10737 /* Mark this jump predicted not taken. */
10738 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
10739 GET_MODE (success
), 1, label
,
10740 profile_probability::guessed_never ());
10744 /* This function tries to implement an atomic exchange operation using a
10745 compare_and_swap loop. VAL is written to *MEM. The previous contents of
10746 *MEM are returned, using TARGET if possible. No memory model is required
10747 since a compare_and_swap loop is seq-cst. */
10750 pa_maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
10752 machine_mode mode
= GET_MODE (mem
);
10754 if (can_compare_and_swap_p (mode
, true))
10756 if (!target
|| !register_operand (target
, mode
))
10757 target
= gen_reg_rtx (mode
);
10758 if (pa_expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
10765 /* Implement TARGET_CALLEE_COPIES. The callee is responsible for copying
10766 arguments passed by hidden reference in the 32-bit HP runtime. Users
10767 can override this behavior for better compatibility with openmp at the
10768 risk of library incompatibilities. Arguments are always passed by value
10769 in the 64-bit HP runtime. */
10772 pa_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10773 machine_mode mode ATTRIBUTE_UNUSED
,
10774 const_tree type ATTRIBUTE_UNUSED
,
10775 bool named ATTRIBUTE_UNUSED
)
10777 return !TARGET_CALLER_COPIES
;
10780 /* Implement TARGET_HARD_REGNO_NREGS. */
10782 static unsigned int
10783 pa_hard_regno_nregs (unsigned int regno ATTRIBUTE_UNUSED
, machine_mode mode
)
10785 return PA_HARD_REGNO_NREGS (regno
, mode
);
10788 /* Implement TARGET_HARD_REGNO_MODE_OK. */
10791 pa_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
10793 return PA_HARD_REGNO_MODE_OK (regno
, mode
);
10796 /* Implement TARGET_STARTING_FRAME_OFFSET.
10798 On the 32-bit ports, we reserve one slot for the previous frame
10799 pointer and one fill slot. The fill slot is for compatibility
10800 with HP compiled programs. On the 64-bit ports, we reserve one
10801 slot for the previous frame pointer. */
10803 static HOST_WIDE_INT
10804 pa_starting_frame_offset (void)
10809 /* Figure out the size in words of the function argument. The size
10810 returned by this function should always be greater than zero because
10811 we pass variable and zero sized objects by reference. */
10814 pa_function_arg_size (machine_mode mode
, const_tree type
)
10816 HOST_WIDE_INT size
;
10818 size
= mode
!= BLKmode
? GET_MODE_SIZE (mode
) : int_size_in_bytes (type
);
10819 return CEIL (size
, UNITS_PER_WORD
);