1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 ;; Boston, MA 02110-1301, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
32 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
33 (UNSPEC_GOTO 1) ; indirect_goto
34 (UNSPEC_DLTIND14R 2) ;
47 [(UNSPECV_BLOCKAGE 0) ; blockage
48 (UNSPECV_DCACHE 1) ; dcacheflush
49 (UNSPECV_ICACHE 2) ; icacheflush
50 (UNSPECV_OPC 3) ; outline_prologue_call
51 (UNSPECV_OEC 4) ; outline_epilogue_call
52 (UNSPECV_LONGJMP 5) ; builtin_longjmp
55 ;; Maximum pc-relative branch offsets.
57 ;; These numbers are a bit smaller than the maximum allowable offsets
58 ;; so that a few instructions may be inserted before the actual branch.
61 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
62 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
65 ;; Insn type. Used to default other attribute values.
67 ;; type "unary" insns have one input operand (1) and one output operand (0)
68 ;; type "binary" insns have two input operands (1,2) and one output (0)
71 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
72 (const_string "binary"))
74 (define_attr "pa_combine_type"
75 "fmpy,faddsub,uncond_branch,addmove,none"
76 (const_string "none"))
78 ;; Processor type (for scheduling, not code generation) -- this attribute
79 ;; must exactly match the processor_type enumeration in pa.h.
81 ;; FIXME: Add 800 scheduling for completeness?
83 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
85 ;; Length (in # of bytes).
86 (define_attr "length" ""
87 (cond [(eq_attr "type" "load,fpload")
88 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
89 (const_int 8) (const_int 4))
91 (eq_attr "type" "store,fpstore")
92 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
93 (const_int 8) (const_int 4))
95 (eq_attr "type" "binary,shift,nullshift")
96 (if_then_else (match_operand 2 "arith_operand" "")
97 (const_int 4) (const_int 12))
99 (eq_attr "type" "move,unary,shift,nullshift")
100 (if_then_else (match_operand 1 "arith_operand" "")
101 (const_int 4) (const_int 8))]
105 (define_asm_attributes
106 [(set_attr "length" "4")
107 (set_attr "type" "multi")])
109 ;; Attributes for instruction and branch scheduling
111 ;; For conditional branches.
112 (define_attr "in_branch_delay" "false,true"
113 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
114 (eq_attr "length" "4"))
115 (const_string "true")
116 (const_string "false")))
118 ;; Disallow instructions which use the FPU since they will tie up the FPU
119 ;; even if the instruction is nullified.
120 (define_attr "in_nullified_branch_delay" "false,true"
121 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
122 (eq_attr "length" "4"))
123 (const_string "true")
124 (const_string "false")))
126 ;; For calls and millicode calls. Allow unconditional branches in the
128 (define_attr "in_call_delay" "false,true"
129 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
130 (eq_attr "length" "4"))
131 (const_string "true")
132 (eq_attr "type" "uncond_branch")
133 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
135 (const_string "true")
136 (const_string "false"))]
137 (const_string "false")))
140 ;; Call delay slot description.
141 (define_delay (eq_attr "type" "call")
142 [(eq_attr "in_call_delay" "true") (nil) (nil)])
144 ;; Millicode call delay slot description.
145 (define_delay (eq_attr "type" "milli")
146 [(eq_attr "in_call_delay" "true") (nil) (nil)])
148 ;; Return and other similar instructions.
149 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
150 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
152 ;; Floating point conditional branch delay slot description.
153 (define_delay (eq_attr "type" "fbranch")
154 [(eq_attr "in_branch_delay" "true")
155 (eq_attr "in_nullified_branch_delay" "true")
158 ;; Integer conditional branch delay slot description.
159 ;; Nullification of conditional branches on the PA is dependent on the
160 ;; direction of the branch. Forward branches nullify true and
161 ;; backward branches nullify false. If the direction is unknown
162 ;; then nullification is not allowed.
163 (define_delay (eq_attr "type" "cbranch")
164 [(eq_attr "in_branch_delay" "true")
165 (and (eq_attr "in_nullified_branch_delay" "true")
166 (attr_flag "forward"))
167 (and (eq_attr "in_nullified_branch_delay" "true")
168 (attr_flag "backward"))])
170 (define_delay (and (eq_attr "type" "uncond_branch")
171 (eq (symbol_ref "following_call (insn)")
173 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
175 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
176 ;; load: 2, fpload: 3
177 ;; store, fpstore: 3, no D-cache operations should be scheduled.
179 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
181 ;; Instruction Time Unit Minimum Distance (unit contention)
188 ;; fmpyadd 3 ALU,MPY 2
189 ;; fmpysub 3 ALU,MPY 2
190 ;; fmpycfxt 3 ALU,MPY 2
193 ;; fdiv,sgl 10 MPY 10
194 ;; fdiv,dbl 12 MPY 12
195 ;; fsqrt,sgl 14 MPY 14
196 ;; fsqrt,dbl 18 MPY 18
198 ;; We don't model fmpyadd/fmpysub properly as those instructions
199 ;; keep both the FP ALU and MPY units busy. Given that these
200 ;; processors are obsolete, I'm not going to spend the time to
201 ;; model those instructions correctly.
203 (define_automaton "pa700")
204 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
206 (define_insn_reservation "W0" 4
207 (and (eq_attr "type" "fpcc")
208 (eq_attr "cpu" "700"))
211 (define_insn_reservation "W1" 3
212 (and (eq_attr "type" "fpalu")
213 (eq_attr "cpu" "700"))
216 (define_insn_reservation "W2" 3
217 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
218 (eq_attr "cpu" "700"))
221 (define_insn_reservation "W3" 10
222 (and (eq_attr "type" "fpdivsgl")
223 (eq_attr "cpu" "700"))
226 (define_insn_reservation "W4" 12
227 (and (eq_attr "type" "fpdivdbl")
228 (eq_attr "cpu" "700"))
231 (define_insn_reservation "W5" 14
232 (and (eq_attr "type" "fpsqrtsgl")
233 (eq_attr "cpu" "700"))
236 (define_insn_reservation "W6" 18
237 (and (eq_attr "type" "fpsqrtdbl")
238 (eq_attr "cpu" "700"))
241 (define_insn_reservation "W7" 2
242 (and (eq_attr "type" "load")
243 (eq_attr "cpu" "700"))
246 (define_insn_reservation "W8" 2
247 (and (eq_attr "type" "fpload")
248 (eq_attr "cpu" "700"))
251 (define_insn_reservation "W9" 3
252 (and (eq_attr "type" "store")
253 (eq_attr "cpu" "700"))
256 (define_insn_reservation "W10" 3
257 (and (eq_attr "type" "fpstore")
258 (eq_attr "cpu" "700"))
261 (define_insn_reservation "W11" 1
262 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
263 (eq_attr "cpu" "700"))
266 ;; We have a bypass for all computations in the FP unit which feed an
267 ;; FP store as long as the sizes are the same.
268 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
269 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
270 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
271 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
272 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
274 ;; We have an "anti-bypass" for FP loads which feed an FP store.
275 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
277 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
278 ;; floating point computations with non-floating point computations (fp loads
279 ;; and stores are not fp computations).
281 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
282 ;; take two cycles, during which no Dcache operations should be scheduled.
283 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
284 ;; all have the same memory characteristics if one disregards cache misses.
286 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
287 ;; There's no value in modeling the ALU and MUL separately though
288 ;; since there can never be a functional unit conflict given the
289 ;; latency and issue rates for those units.
292 ;; Instruction Time Unit Minimum Distance (unit contention)
299 ;; fmpyadd 2 ALU,MPY 1
300 ;; fmpysub 2 ALU,MPY 1
301 ;; fmpycfxt 2 ALU,MPY 1
305 ;; fdiv,dbl 15 DIV 15
307 ;; fsqrt,dbl 15 DIV 15
309 (define_automaton "pa7100")
310 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
312 (define_insn_reservation "X0" 2
313 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
314 (eq_attr "cpu" "7100"))
317 (define_insn_reservation "X1" 8
318 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
319 (eq_attr "cpu" "7100"))
320 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
322 (define_insn_reservation "X2" 15
323 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
324 (eq_attr "cpu" "7100"))
325 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
327 (define_insn_reservation "X3" 2
328 (and (eq_attr "type" "load")
329 (eq_attr "cpu" "7100"))
332 (define_insn_reservation "X4" 2
333 (and (eq_attr "type" "fpload")
334 (eq_attr "cpu" "7100"))
337 (define_insn_reservation "X5" 2
338 (and (eq_attr "type" "store")
339 (eq_attr "cpu" "7100"))
340 "i_7100+mem_7100,mem_7100")
342 (define_insn_reservation "X6" 2
343 (and (eq_attr "type" "fpstore")
344 (eq_attr "cpu" "7100"))
345 "i_7100+mem_7100,mem_7100")
347 (define_insn_reservation "X7" 1
348 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
349 (eq_attr "cpu" "7100"))
352 ;; We have a bypass for all computations in the FP unit which feed an
353 ;; FP store as long as the sizes are the same.
354 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
355 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
356 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
358 ;; We have an "anti-bypass" for FP loads which feed an FP store.
359 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
361 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
362 ;; There's no value in modeling the ALU and MUL separately though
363 ;; since there can never be a functional unit conflict that
364 ;; can be avoided given the latency, issue rates and mandatory
365 ;; one cycle cpu-wide lock for a double precision fp multiply.
368 ;; Instruction Time Unit Minimum Distance (unit contention)
375 ;; fmpyadd,sgl 2 ALU,MPY 1
376 ;; fmpyadd,dbl 3 ALU,MPY 2
377 ;; fmpysub,sgl 2 ALU,MPY 1
378 ;; fmpysub,dbl 3 ALU,MPY 2
379 ;; fmpycfxt,sgl 2 ALU,MPY 1
380 ;; fmpycfxt,dbl 3 ALU,MPY 2
385 ;; fdiv,dbl 15 DIV 15
387 ;; fsqrt,dbl 15 DIV 15
389 ;; The PA7200 is just like the PA7100LC except that there is
390 ;; no store-store penalty.
392 ;; The PA7300 is just like the PA7200 except that there is
393 ;; no store-load penalty.
395 ;; Note there are some aspects of the 7100LC we are not modeling
396 ;; at the moment. I'll be reviewing the 7100LC scheduling info
397 ;; shortly and updating this description.
401 ;; other issue modeling
403 (define_automaton "pa7100lc")
404 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
405 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
406 (define_cpu_unit "mem_7100lc" "pa7100lc")
408 ;; Double precision multiplies lock the entire CPU for one
409 ;; cycle. There is no way to avoid this lock and trying to
410 ;; schedule around the lock is pointless and thus there is no
411 ;; value in trying to model this lock.
413 ;; Not modeling the lock allows us to treat fp multiplies just
414 ;; like any other FP alu instruction. It allows for a smaller
415 ;; DFA and may reduce register pressure.
416 (define_insn_reservation "Y0" 2
417 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
418 (eq_attr "cpu" "7100LC,7200,7300"))
419 "f_7100lc,fpmac_7100lc")
421 ;; fp division and sqrt instructions lock the entire CPU for
422 ;; 7 cycles (single precision) or 14 cycles (double precision).
423 ;; There is no way to avoid this lock and trying to schedule
424 ;; around the lock is pointless and thus there is no value in
425 ;; trying to model this lock. Not modeling the lock allows
426 ;; for a smaller DFA and may reduce register pressure.
427 (define_insn_reservation "Y1" 1
428 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
429 (eq_attr "cpu" "7100LC,7200,7300"))
432 (define_insn_reservation "Y2" 2
433 (and (eq_attr "type" "load")
434 (eq_attr "cpu" "7100LC,7200,7300"))
435 "i1_7100lc+mem_7100lc")
437 (define_insn_reservation "Y3" 2
438 (and (eq_attr "type" "fpload")
439 (eq_attr "cpu" "7100LC,7200,7300"))
440 "i1_7100lc+mem_7100lc")
442 (define_insn_reservation "Y4" 2
443 (and (eq_attr "type" "store")
444 (eq_attr "cpu" "7100LC"))
445 "i1_7100lc+mem_7100lc,mem_7100lc")
447 (define_insn_reservation "Y5" 2
448 (and (eq_attr "type" "fpstore")
449 (eq_attr "cpu" "7100LC"))
450 "i1_7100lc+mem_7100lc,mem_7100lc")
452 (define_insn_reservation "Y6" 1
453 (and (eq_attr "type" "shift,nullshift")
454 (eq_attr "cpu" "7100LC,7200,7300"))
457 (define_insn_reservation "Y7" 1
458 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
459 (eq_attr "cpu" "7100LC,7200,7300"))
460 "(i0_7100lc|i1_7100lc)")
462 ;; The 7200 has a store-load penalty
463 (define_insn_reservation "Y8" 2
464 (and (eq_attr "type" "store")
465 (eq_attr "cpu" "7200"))
466 "i1_7100lc,mem_7100lc")
468 (define_insn_reservation "Y9" 2
469 (and (eq_attr "type" "fpstore")
470 (eq_attr "cpu" "7200"))
471 "i1_7100lc,mem_7100lc")
473 ;; The 7300 has no penalty for store-store or store-load
474 (define_insn_reservation "Y10" 2
475 (and (eq_attr "type" "store")
476 (eq_attr "cpu" "7300"))
479 (define_insn_reservation "Y11" 2
480 (and (eq_attr "type" "fpstore")
481 (eq_attr "cpu" "7300"))
484 ;; We have an "anti-bypass" for FP loads which feed an FP store.
485 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
487 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
488 ;; traditional architecture.
490 ;; The PA8000 has a large (56) entry reorder buffer that is split between
491 ;; memory and non-memory operations.
493 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
494 ;; the function units, with the exception of branches and multi-output
495 ;; instructions. The PA8000 can retire two non-memory operations per cycle
496 ;; and two memory operations per cycle, only one of which may be a store.
498 ;; Given the large reorder buffer, the processor can hide most latencies.
499 ;; According to HP, they've got the best results by scheduling for retirement
500 ;; bandwidth with limited latency scheduling for floating point operations.
501 ;; Latency for integer operations and memory references is ignored.
504 ;; We claim floating point operations have a 2 cycle latency and are
505 ;; fully pipelined, except for div and sqrt which are not pipelined and
506 ;; take from 17 to 31 cycles to complete.
508 ;; It's worth noting that there is no way to saturate all the functional
509 ;; units on the PA8000 as there is not enough issue bandwidth.
511 (define_automaton "pa8000")
512 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
513 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
514 (define_cpu_unit "store_8000" "pa8000")
515 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
516 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
517 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
518 (define_reservation "im_8000" "im0_8000 | im1_8000")
519 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
520 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
521 (define_reservation "f_8000" "f0_8000 | f1_8000")
522 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
524 ;; We can issue any two memops per cycle, but we can only retire
525 ;; one memory store per cycle. We assume that the reorder buffer
526 ;; will hide any memory latencies per HP's recommendation.
527 (define_insn_reservation "Z0" 0
529 (eq_attr "type" "load,fpload")
530 (eq_attr "cpu" "8000"))
533 (define_insn_reservation "Z1" 0
535 (eq_attr "type" "store,fpstore")
536 (eq_attr "cpu" "8000"))
537 "im_8000,rm_8000+store_8000")
539 ;; We can issue and retire two non-memory operations per cycle with
540 ;; a few exceptions (branches). This group catches those we want
541 ;; to assume have zero latency.
542 (define_insn_reservation "Z2" 0
544 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
545 (eq_attr "cpu" "8000"))
548 ;; Branches use both slots in the non-memory issue and
550 (define_insn_reservation "Z3" 0
552 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
553 (eq_attr "cpu" "8000"))
554 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
556 ;; We partial latency schedule the floating point units.
557 ;; They can issue/retire two at a time in the non-memory
558 ;; units. We fix their latency at 2 cycles and they
559 ;; are fully pipelined.
560 (define_insn_reservation "Z4" 1
562 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
563 (eq_attr "cpu" "8000"))
564 "inm_8000,f_8000,rnm_8000")
566 ;; The fdivsqrt units are not pipelined and have a very long latency.
567 ;; To keep the DFA from exploding, we do not show all the
568 ;; reservations for the divsqrt unit.
569 (define_insn_reservation "Z5" 17
571 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
572 (eq_attr "cpu" "8000"))
573 "inm_8000,fdivsqrt_8000*6,rnm_8000")
575 (define_insn_reservation "Z6" 31
577 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
578 (eq_attr "cpu" "8000"))
579 "inm_8000,fdivsqrt_8000*6,rnm_8000")
581 (include "predicates.md")
583 ;; Compare instructions.
584 ;; This controls RTL generation and register allocation.
586 ;; We generate RTL for comparisons and branches by having the cmpxx
587 ;; patterns store away the operands. Then, the scc and bcc patterns
588 ;; emit RTL for both the compare and the branch.
591 (define_expand "cmpdi"
593 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
594 (match_operand:DI 1 "register_operand" "")))]
599 hppa_compare_op0 = operands[0];
600 hppa_compare_op1 = operands[1];
601 hppa_branch_type = CMP_SI;
605 (define_expand "cmpsi"
607 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
608 (match_operand:SI 1 "arith5_operand" "")))]
612 hppa_compare_op0 = operands[0];
613 hppa_compare_op1 = operands[1];
614 hppa_branch_type = CMP_SI;
618 (define_expand "cmpsf"
620 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
621 (match_operand:SF 1 "reg_or_0_operand" "")))]
622 "! TARGET_SOFT_FLOAT"
625 hppa_compare_op0 = operands[0];
626 hppa_compare_op1 = operands[1];
627 hppa_branch_type = CMP_SF;
631 (define_expand "cmpdf"
633 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
634 (match_operand:DF 1 "reg_or_0_operand" "")))]
635 "! TARGET_SOFT_FLOAT"
638 hppa_compare_op0 = operands[0];
639 hppa_compare_op1 = operands[1];
640 hppa_branch_type = CMP_DF;
646 (match_operator:CCFP 2 "comparison_operator"
647 [(match_operand:SF 0 "reg_or_0_operand" "fG")
648 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,sgl,%Y2 %f0,%f1"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
656 (match_operator:CCFP 2 "comparison_operator"
657 [(match_operand:DF 0 "reg_or_0_operand" "fG")
658 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
659 "! TARGET_SOFT_FLOAT"
660 "fcmp,dbl,%Y2 %f0,%f1"
661 [(set_attr "length" "4")
662 (set_attr "type" "fpcc")])
664 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
665 ;; placeholders. This is necessary in rare situations when a
666 ;; placeholder is re-emitted (see PR 8705).
668 (define_expand "movccfp"
670 (match_operand 0 "const_int_operand" ""))]
671 "! TARGET_SOFT_FLOAT"
674 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
678 ;; The following patterns are optimization placeholders. In almost
679 ;; all cases, the user of the condition code will be simplified and the
680 ;; original condition code setting insn should be eliminated.
682 (define_insn "*movccfp0"
685 "! TARGET_SOFT_FLOAT"
686 "fcmp,dbl,= %%fr0,%%fr0"
687 [(set_attr "length" "4")
688 (set_attr "type" "fpcc")])
690 (define_insn "*movccfp1"
693 "! TARGET_SOFT_FLOAT"
694 "fcmp,dbl,!= %%fr0,%%fr0"
695 [(set_attr "length" "4")
696 (set_attr "type" "fpcc")])
701 [(set (match_operand:SI 0 "register_operand" "")
707 /* fp scc patterns rarely match, and are not a win on the PA. */
708 if (hppa_branch_type != CMP_SI)
710 /* set up operands from compare. */
711 operands[1] = hppa_compare_op0;
712 operands[2] = hppa_compare_op1;
713 /* fall through and generate default code */
717 [(set (match_operand:SI 0 "register_operand" "")
723 /* fp scc patterns rarely match, and are not a win on the PA. */
724 if (hppa_branch_type != CMP_SI)
726 operands[1] = hppa_compare_op0;
727 operands[2] = hppa_compare_op1;
731 [(set (match_operand:SI 0 "register_operand" "")
737 /* fp scc patterns rarely match, and are not a win on the PA. */
738 if (hppa_branch_type != CMP_SI)
740 operands[1] = hppa_compare_op0;
741 operands[2] = hppa_compare_op1;
745 [(set (match_operand:SI 0 "register_operand" "")
751 /* fp scc patterns rarely match, and are not a win on the PA. */
752 if (hppa_branch_type != CMP_SI)
754 operands[1] = hppa_compare_op0;
755 operands[2] = hppa_compare_op1;
759 [(set (match_operand:SI 0 "register_operand" "")
765 /* fp scc patterns rarely match, and are not a win on the PA. */
766 if (hppa_branch_type != CMP_SI)
768 operands[1] = hppa_compare_op0;
769 operands[2] = hppa_compare_op1;
773 [(set (match_operand:SI 0 "register_operand" "")
779 /* fp scc patterns rarely match, and are not a win on the PA. */
780 if (hppa_branch_type != CMP_SI)
782 operands[1] = hppa_compare_op0;
783 operands[2] = hppa_compare_op1;
786 (define_expand "sltu"
787 [(set (match_operand:SI 0 "register_operand" "")
788 (ltu:SI (match_dup 1)
793 if (hppa_branch_type != CMP_SI)
795 operands[1] = hppa_compare_op0;
796 operands[2] = hppa_compare_op1;
799 (define_expand "sgtu"
800 [(set (match_operand:SI 0 "register_operand" "")
801 (gtu:SI (match_dup 1)
806 if (hppa_branch_type != CMP_SI)
808 operands[1] = hppa_compare_op0;
809 operands[2] = hppa_compare_op1;
812 (define_expand "sleu"
813 [(set (match_operand:SI 0 "register_operand" "")
814 (leu:SI (match_dup 1)
819 if (hppa_branch_type != CMP_SI)
821 operands[1] = hppa_compare_op0;
822 operands[2] = hppa_compare_op1;
825 (define_expand "sgeu"
826 [(set (match_operand:SI 0 "register_operand" "")
827 (geu:SI (match_dup 1)
832 if (hppa_branch_type != CMP_SI)
834 operands[1] = hppa_compare_op0;
835 operands[2] = hppa_compare_op1;
838 ;; Instruction canonicalization puts immediate operands second, which
839 ;; is the reverse of what we want.
842 [(set (match_operand:SI 0 "register_operand" "=r")
843 (match_operator:SI 3 "comparison_operator"
844 [(match_operand:SI 1 "register_operand" "r")
845 (match_operand:SI 2 "arith11_operand" "rI")]))]
847 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "8")])
852 [(set (match_operand:DI 0 "register_operand" "=r")
853 (match_operator:DI 3 "comparison_operator"
854 [(match_operand:DI 1 "register_operand" "r")
855 (match_operand:DI 2 "arith11_operand" "rI")]))]
857 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
858 [(set_attr "type" "binary")
859 (set_attr "length" "8")])
861 (define_insn "iorscc"
862 [(set (match_operand:SI 0 "register_operand" "=r")
863 (ior:SI (match_operator:SI 3 "comparison_operator"
864 [(match_operand:SI 1 "register_operand" "r")
865 (match_operand:SI 2 "arith11_operand" "rI")])
866 (match_operator:SI 6 "comparison_operator"
867 [(match_operand:SI 4 "register_operand" "r")
868 (match_operand:SI 5 "arith11_operand" "rI")])))]
870 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
871 [(set_attr "type" "binary")
872 (set_attr "length" "12")])
875 [(set (match_operand:DI 0 "register_operand" "=r")
876 (ior:DI (match_operator:DI 3 "comparison_operator"
877 [(match_operand:DI 1 "register_operand" "r")
878 (match_operand:DI 2 "arith11_operand" "rI")])
879 (match_operator:DI 6 "comparison_operator"
880 [(match_operand:DI 4 "register_operand" "r")
881 (match_operand:DI 5 "arith11_operand" "rI")])))]
883 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
884 [(set_attr "type" "binary")
885 (set_attr "length" "12")])
887 ;; Combiner patterns for common operations performed with the output
888 ;; from an scc insn (negscc and incscc).
889 (define_insn "negscc"
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (neg:SI (match_operator:SI 3 "comparison_operator"
892 [(match_operand:SI 1 "register_operand" "r")
893 (match_operand:SI 2 "arith11_operand" "rI")])))]
895 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
900 [(set (match_operand:DI 0 "register_operand" "=r")
901 (neg:DI (match_operator:DI 3 "comparison_operator"
902 [(match_operand:DI 1 "register_operand" "r")
903 (match_operand:DI 2 "arith11_operand" "rI")])))]
905 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
906 [(set_attr "type" "binary")
907 (set_attr "length" "8")])
909 ;; Patterns for adding/subtracting the result of a boolean expression from
910 ;; a register. First we have special patterns that make use of the carry
911 ;; bit, and output only two instructions. For the cases we can't in
912 ;; general do in two instructions, the incscc pattern at the end outputs
913 ;; two or three instructions.
916 [(set (match_operand:SI 0 "register_operand" "=r")
917 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
918 (match_operand:SI 3 "arith11_operand" "rI"))
919 (match_operand:SI 1 "register_operand" "r")))]
921 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
922 [(set_attr "type" "binary")
923 (set_attr "length" "8")])
926 [(set (match_operand:DI 0 "register_operand" "=r")
927 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
928 (match_operand:DI 3 "arith11_operand" "rI"))
929 (match_operand:DI 1 "register_operand" "r")))]
931 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
932 [(set_attr "type" "binary")
933 (set_attr "length" "8")])
935 ; This need only accept registers for op3, since canonicalization
936 ; replaces geu with gtu when op3 is an integer.
938 [(set (match_operand:SI 0 "register_operand" "=r")
939 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
940 (match_operand:SI 3 "register_operand" "r"))
941 (match_operand:SI 1 "register_operand" "r")))]
943 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
944 [(set_attr "type" "binary")
945 (set_attr "length" "8")])
948 [(set (match_operand:DI 0 "register_operand" "=r")
949 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
950 (match_operand:DI 3 "register_operand" "r"))
951 (match_operand:DI 1 "register_operand" "r")))]
953 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
954 [(set_attr "type" "binary")
955 (set_attr "length" "8")])
957 ; Match only integers for op3 here. This is used as canonical form of the
958 ; geu pattern when op3 is an integer. Don't match registers since we can't
959 ; make better code than the general incscc pattern.
961 [(set (match_operand:SI 0 "register_operand" "=r")
962 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
963 (match_operand:SI 3 "int11_operand" "I"))
964 (match_operand:SI 1 "register_operand" "r")))]
966 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
967 [(set_attr "type" "binary")
968 (set_attr "length" "8")])
971 [(set (match_operand:DI 0 "register_operand" "=r")
972 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
973 (match_operand:DI 3 "int11_operand" "I"))
974 (match_operand:DI 1 "register_operand" "r")))]
976 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
980 (define_insn "incscc"
981 [(set (match_operand:SI 0 "register_operand" "=r,r")
982 (plus:SI (match_operator:SI 4 "comparison_operator"
983 [(match_operand:SI 2 "register_operand" "r,r")
984 (match_operand:SI 3 "arith11_operand" "rI,rI")])
985 (match_operand:SI 1 "register_operand" "0,?r")))]
988 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
989 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
990 [(set_attr "type" "binary,binary")
991 (set_attr "length" "8,12")])
994 [(set (match_operand:DI 0 "register_operand" "=r,r")
995 (plus:DI (match_operator:DI 4 "comparison_operator"
996 [(match_operand:DI 2 "register_operand" "r,r")
997 (match_operand:DI 3 "arith11_operand" "rI,rI")])
998 (match_operand:DI 1 "register_operand" "0,?r")))]
1001 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
1002 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1003 [(set_attr "type" "binary,binary")
1004 (set_attr "length" "8,12")])
1007 [(set (match_operand:SI 0 "register_operand" "=r")
1008 (minus:SI (match_operand:SI 1 "register_operand" "r")
1009 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1010 (match_operand:SI 3 "arith11_operand" "rI"))))]
1012 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1013 [(set_attr "type" "binary")
1014 (set_attr "length" "8")])
1017 [(set (match_operand:DI 0 "register_operand" "=r")
1018 (minus:DI (match_operand:DI 1 "register_operand" "r")
1019 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1020 (match_operand:DI 3 "arith11_operand" "rI"))))]
1022 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1023 [(set_attr "type" "binary")
1024 (set_attr "length" "8")])
1027 [(set (match_operand:SI 0 "register_operand" "=r")
1028 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1029 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1030 (match_operand:SI 3 "arith11_operand" "rI")))
1031 (match_operand:SI 4 "register_operand" "r")))]
1033 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1034 [(set_attr "type" "binary")
1035 (set_attr "length" "8")])
1038 [(set (match_operand:DI 0 "register_operand" "=r")
1039 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1040 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1041 (match_operand:DI 3 "arith11_operand" "rI")))
1042 (match_operand:DI 4 "register_operand" "r")))]
1044 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1045 [(set_attr "type" "binary")
1046 (set_attr "length" "8")])
1048 ; This need only accept registers for op3, since canonicalization
1049 ; replaces ltu with leu when op3 is an integer.
1051 [(set (match_operand:SI 0 "register_operand" "=r")
1052 (minus:SI (match_operand:SI 1 "register_operand" "r")
1053 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1054 (match_operand:SI 3 "register_operand" "r"))))]
1056 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1057 [(set_attr "type" "binary")
1058 (set_attr "length" "8")])
1061 [(set (match_operand:DI 0 "register_operand" "=r")
1062 (minus:DI (match_operand:DI 1 "register_operand" "r")
1063 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1064 (match_operand:DI 3 "register_operand" "r"))))]
1066 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1067 [(set_attr "type" "binary")
1068 (set_attr "length" "8")])
1071 [(set (match_operand:SI 0 "register_operand" "=r")
1072 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1073 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1074 (match_operand:SI 3 "register_operand" "r")))
1075 (match_operand:SI 4 "register_operand" "r")))]
1077 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1078 [(set_attr "type" "binary")
1079 (set_attr "length" "8")])
1082 [(set (match_operand:DI 0 "register_operand" "=r")
1083 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1084 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1085 (match_operand:DI 3 "register_operand" "r")))
1086 (match_operand:DI 4 "register_operand" "r")))]
1088 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1089 [(set_attr "type" "binary")
1090 (set_attr "length" "8")])
1092 ; Match only integers for op3 here. This is used as canonical form of the
1093 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1094 ; make better code than the general incscc pattern.
1096 [(set (match_operand:SI 0 "register_operand" "=r")
1097 (minus:SI (match_operand:SI 1 "register_operand" "r")
1098 (leu:SI (match_operand:SI 2 "register_operand" "r")
1099 (match_operand:SI 3 "int11_operand" "I"))))]
1101 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1102 [(set_attr "type" "binary")
1103 (set_attr "length" "8")])
1106 [(set (match_operand:DI 0 "register_operand" "=r")
1107 (minus:DI (match_operand:DI 1 "register_operand" "r")
1108 (leu:DI (match_operand:DI 2 "register_operand" "r")
1109 (match_operand:DI 3 "int11_operand" "I"))))]
1111 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1112 [(set_attr "type" "binary")
1113 (set_attr "length" "8")])
1116 [(set (match_operand:SI 0 "register_operand" "=r")
1117 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1118 (leu:SI (match_operand:SI 2 "register_operand" "r")
1119 (match_operand:SI 3 "int11_operand" "I")))
1120 (match_operand:SI 4 "register_operand" "r")))]
1122 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1123 [(set_attr "type" "binary")
1124 (set_attr "length" "8")])
1127 [(set (match_operand:DI 0 "register_operand" "=r")
1128 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1129 (leu:DI (match_operand:DI 2 "register_operand" "r")
1130 (match_operand:DI 3 "int11_operand" "I")))
1131 (match_operand:DI 4 "register_operand" "r")))]
1133 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1134 [(set_attr "type" "binary")
1135 (set_attr "length" "8")])
1137 (define_insn "decscc"
1138 [(set (match_operand:SI 0 "register_operand" "=r,r")
1139 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1140 (match_operator:SI 4 "comparison_operator"
1141 [(match_operand:SI 2 "register_operand" "r,r")
1142 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1145 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1146 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1147 [(set_attr "type" "binary,binary")
1148 (set_attr "length" "8,12")])
1151 [(set (match_operand:DI 0 "register_operand" "=r,r")
1152 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1153 (match_operator:DI 4 "comparison_operator"
1154 [(match_operand:DI 2 "register_operand" "r,r")
1155 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1158 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1159 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1160 [(set_attr "type" "binary,binary")
1161 (set_attr "length" "8,12")])
1163 ; Patterns for max and min. (There is no need for an earlyclobber in the
1164 ; last alternative since the middle alternative will match if op0 == op1.)
1166 (define_insn "sminsi3"
1167 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1168 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1169 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1172 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1173 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1174 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1175 [(set_attr "type" "multi,multi,multi")
1176 (set_attr "length" "8,8,8")])
1178 (define_insn "smindi3"
1179 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1180 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1181 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1184 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1185 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1186 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1187 [(set_attr "type" "multi,multi,multi")
1188 (set_attr "length" "8,8,8")])
1190 (define_insn "uminsi3"
1191 [(set (match_operand:SI 0 "register_operand" "=r,r")
1192 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1193 (match_operand:SI 2 "arith11_operand" "r,I")))]
1196 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1197 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1198 [(set_attr "type" "multi,multi")
1199 (set_attr "length" "8,8")])
1201 (define_insn "umindi3"
1202 [(set (match_operand:DI 0 "register_operand" "=r,r")
1203 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1204 (match_operand:DI 2 "arith11_operand" "r,I")))]
1207 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1208 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1209 [(set_attr "type" "multi,multi")
1210 (set_attr "length" "8,8")])
1212 (define_insn "smaxsi3"
1213 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1214 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1215 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1218 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1219 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1220 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1221 [(set_attr "type" "multi,multi,multi")
1222 (set_attr "length" "8,8,8")])
1224 (define_insn "smaxdi3"
1225 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1226 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1227 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1230 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1231 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1232 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1233 [(set_attr "type" "multi,multi,multi")
1234 (set_attr "length" "8,8,8")])
1236 (define_insn "umaxsi3"
1237 [(set (match_operand:SI 0 "register_operand" "=r,r")
1238 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1239 (match_operand:SI 2 "arith11_operand" "r,I")))]
1242 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1243 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1244 [(set_attr "type" "multi,multi")
1245 (set_attr "length" "8,8")])
1247 (define_insn "umaxdi3"
1248 [(set (match_operand:DI 0 "register_operand" "=r,r")
1249 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1250 (match_operand:DI 2 "arith11_operand" "r,I")))]
1253 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1254 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1255 [(set_attr "type" "multi,multi")
1256 (set_attr "length" "8,8")])
1258 (define_insn "abssi2"
1259 [(set (match_operand:SI 0 "register_operand" "=r")
1260 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1262 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1263 [(set_attr "type" "multi")
1264 (set_attr "length" "8")])
1266 (define_insn "absdi2"
1267 [(set (match_operand:DI 0 "register_operand" "=r")
1268 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1270 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1271 [(set_attr "type" "multi")
1272 (set_attr "length" "8")])
1274 ;;; Experimental conditional move patterns
1276 (define_expand "movsicc"
1277 [(set (match_operand:SI 0 "register_operand" "")
1279 (match_operator 1 "comparison_operator"
1282 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1283 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1287 enum rtx_code code = GET_CODE (operands[1]);
1289 if (hppa_branch_type != CMP_SI)
1292 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1293 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1296 /* operands[1] is currently the result of compare_from_rtx. We want to
1297 emit a compare of the original operands. */
1298 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1299 operands[4] = hppa_compare_op0;
1300 operands[5] = hppa_compare_op1;
1303 ;; We used to accept any register for op1.
1305 ;; However, it loses sometimes because the compiler will end up using
1306 ;; different registers for op0 and op1 in some critical cases. local-alloc
1307 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1309 ;; If/when global register allocation supports tying we should allow any
1310 ;; register for op1 again.
1312 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1314 (match_operator 2 "comparison_operator"
1315 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1316 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1317 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1321 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1322 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1323 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1324 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1325 [(set_attr "type" "multi,multi,multi,nullshift")
1326 (set_attr "length" "8,8,8,8")])
1329 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1331 (match_operator 5 "comparison_operator"
1332 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1333 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1334 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1335 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1338 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1339 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1340 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1341 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1342 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1343 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1344 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1345 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1346 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1347 (set_attr "length" "8,8,8,8,8,8,8,8")])
1349 (define_expand "movdicc"
1350 [(set (match_operand:DI 0 "register_operand" "")
1352 (match_operator 1 "comparison_operator"
1355 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1356 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1360 enum rtx_code code = GET_CODE (operands[1]);
1362 if (hppa_branch_type != CMP_SI)
1365 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1366 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1369 /* operands[1] is currently the result of compare_from_rtx. We want to
1370 emit a compare of the original operands. */
1371 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1372 operands[4] = hppa_compare_op0;
1373 operands[5] = hppa_compare_op1;
1376 ; We need the first constraint alternative in order to avoid
1377 ; earlyclobbers on all other alternatives.
1379 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1381 (match_operator 2 "comparison_operator"
1382 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1383 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1384 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1388 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1389 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1390 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1391 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1392 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1393 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1394 (set_attr "length" "8,8,8,8,8")])
1397 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1399 (match_operator 5 "comparison_operator"
1400 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1401 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1402 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1403 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1406 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1407 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1408 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1409 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1410 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1411 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1412 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1413 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1414 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1415 (set_attr "length" "8,8,8,8,8,8,8,8")])
1417 ;; Conditional Branches
1419 (define_expand "beq"
1421 (if_then_else (eq (match_dup 1) (match_dup 2))
1422 (label_ref (match_operand 0 "" ""))
1427 if (hppa_branch_type != CMP_SI)
1429 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1430 emit_bcond_fp (NE, operands[0]);
1433 /* set up operands from compare. */
1434 operands[1] = hppa_compare_op0;
1435 operands[2] = hppa_compare_op1;
1436 /* fall through and generate default code */
1439 (define_expand "bne"
1441 (if_then_else (ne (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bgt"
1459 (if_then_else (gt (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "blt"
1477 (if_then_else (lt (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bge"
1495 (if_then_else (ge (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1504 emit_bcond_fp (NE, operands[0]);
1507 operands[1] = hppa_compare_op0;
1508 operands[2] = hppa_compare_op1;
1511 (define_expand "ble"
1513 (if_then_else (le (match_dup 1) (match_dup 2))
1514 (label_ref (match_operand 0 "" ""))
1519 if (hppa_branch_type != CMP_SI)
1521 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1522 emit_bcond_fp (NE, operands[0]);
1525 operands[1] = hppa_compare_op0;
1526 operands[2] = hppa_compare_op1;
1529 (define_expand "bgtu"
1531 (if_then_else (gtu (match_dup 1) (match_dup 2))
1532 (label_ref (match_operand 0 "" ""))
1537 if (hppa_branch_type != CMP_SI)
1539 operands[1] = hppa_compare_op0;
1540 operands[2] = hppa_compare_op1;
1543 (define_expand "bltu"
1545 (if_then_else (ltu (match_dup 1) (match_dup 2))
1546 (label_ref (match_operand 0 "" ""))
1551 if (hppa_branch_type != CMP_SI)
1553 operands[1] = hppa_compare_op0;
1554 operands[2] = hppa_compare_op1;
1557 (define_expand "bgeu"
1559 (if_then_else (geu (match_dup 1) (match_dup 2))
1560 (label_ref (match_operand 0 "" ""))
1565 if (hppa_branch_type != CMP_SI)
1567 operands[1] = hppa_compare_op0;
1568 operands[2] = hppa_compare_op1;
1571 (define_expand "bleu"
1573 (if_then_else (leu (match_dup 1) (match_dup 2))
1574 (label_ref (match_operand 0 "" ""))
1579 if (hppa_branch_type != CMP_SI)
1581 operands[1] = hppa_compare_op0;
1582 operands[2] = hppa_compare_op1;
1585 (define_expand "bltgt"
1587 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1588 (label_ref (match_operand 0 "" ""))
1593 if (hppa_branch_type == CMP_SI)
1595 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1596 emit_bcond_fp (NE, operands[0]);
1600 (define_expand "bunle"
1602 (if_then_else (unle (match_dup 1) (match_dup 2))
1603 (label_ref (match_operand 0 "" ""))
1608 if (hppa_branch_type == CMP_SI)
1610 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1611 emit_bcond_fp (NE, operands[0]);
1615 (define_expand "bunlt"
1617 (if_then_else (unlt (match_dup 1) (match_dup 2))
1618 (label_ref (match_operand 0 "" ""))
1623 if (hppa_branch_type == CMP_SI)
1625 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1626 emit_bcond_fp (NE, operands[0]);
1630 (define_expand "bunge"
1632 (if_then_else (unge (match_dup 1) (match_dup 2))
1633 (label_ref (match_operand 0 "" ""))
1638 if (hppa_branch_type == CMP_SI)
1640 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1641 emit_bcond_fp (NE, operands[0]);
1645 (define_expand "bungt"
1647 (if_then_else (ungt (match_dup 1) (match_dup 2))
1648 (label_ref (match_operand 0 "" ""))
1653 if (hppa_branch_type == CMP_SI)
1655 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1656 emit_bcond_fp (NE, operands[0]);
1660 (define_expand "buneq"
1662 (if_then_else (uneq (match_dup 1) (match_dup 2))
1663 (label_ref (match_operand 0 "" ""))
1668 if (hppa_branch_type == CMP_SI)
1670 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1671 emit_bcond_fp (NE, operands[0]);
1675 (define_expand "bunordered"
1677 (if_then_else (unordered (match_dup 1) (match_dup 2))
1678 (label_ref (match_operand 0 "" ""))
1683 if (hppa_branch_type == CMP_SI)
1685 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1686 emit_bcond_fp (NE, operands[0]);
1690 (define_expand "bordered"
1692 (if_then_else (ordered (match_dup 1) (match_dup 2))
1693 (label_ref (match_operand 0 "" ""))
1698 if (hppa_branch_type == CMP_SI)
1700 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1701 emit_bcond_fp (NE, operands[0]);
1705 ;; Match the branch patterns.
1708 ;; Note a long backward conditional branch with an annulled delay slot
1709 ;; has a length of 12.
1713 (match_operator 3 "comparison_operator"
1714 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1715 (match_operand:SI 2 "arith5_operand" "rL")])
1716 (label_ref (match_operand 0 "" ""))
1721 return output_cbranch (operands, 0, insn);
1723 [(set_attr "type" "cbranch")
1724 (set (attr "length")
1725 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1726 (const_int MAX_12BIT_OFFSET))
1728 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1729 (const_int MAX_17BIT_OFFSET))
1731 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1733 (eq (symbol_ref "flag_pic") (const_int 0))
1737 ;; Match the negated branch.
1742 (match_operator 3 "comparison_operator"
1743 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1744 (match_operand:SI 2 "arith5_operand" "rL")])
1746 (label_ref (match_operand 0 "" ""))))]
1750 return output_cbranch (operands, 1, insn);
1752 [(set_attr "type" "cbranch")
1753 (set (attr "length")
1754 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1755 (const_int MAX_12BIT_OFFSET))
1757 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1758 (const_int MAX_17BIT_OFFSET))
1760 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1762 (eq (symbol_ref "flag_pic") (const_int 0))
1769 (match_operator 3 "comparison_operator"
1770 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1771 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1772 (label_ref (match_operand 0 "" ""))
1777 return output_cbranch (operands, 0, insn);
1779 [(set_attr "type" "cbranch")
1780 (set (attr "length")
1781 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1782 (const_int MAX_12BIT_OFFSET))
1784 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1785 (const_int MAX_17BIT_OFFSET))
1787 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1789 (eq (symbol_ref "flag_pic") (const_int 0))
1793 ;; Match the negated branch.
1798 (match_operator 3 "comparison_operator"
1799 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1800 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1802 (label_ref (match_operand 0 "" ""))))]
1806 return output_cbranch (operands, 1, insn);
1808 [(set_attr "type" "cbranch")
1809 (set (attr "length")
1810 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1811 (const_int MAX_12BIT_OFFSET))
1813 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1814 (const_int MAX_17BIT_OFFSET))
1816 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1818 (eq (symbol_ref "flag_pic") (const_int 0))
1824 (match_operator 3 "cmpib_comparison_operator"
1825 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1826 (match_operand:DI 2 "arith5_operand" "rL")])
1827 (label_ref (match_operand 0 "" ""))
1832 return output_cbranch (operands, 0, insn);
1834 [(set_attr "type" "cbranch")
1835 (set (attr "length")
1836 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1837 (const_int MAX_12BIT_OFFSET))
1839 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1840 (const_int MAX_17BIT_OFFSET))
1842 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1844 (eq (symbol_ref "flag_pic") (const_int 0))
1848 ;; Match the negated branch.
1853 (match_operator 3 "cmpib_comparison_operator"
1854 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1855 (match_operand:DI 2 "arith5_operand" "rL")])
1857 (label_ref (match_operand 0 "" ""))))]
1861 return output_cbranch (operands, 1, insn);
1863 [(set_attr "type" "cbranch")
1864 (set (attr "length")
1865 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1866 (const_int MAX_12BIT_OFFSET))
1868 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1869 (const_int MAX_17BIT_OFFSET))
1871 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1873 (eq (symbol_ref "flag_pic") (const_int 0))
1877 ;; Branch on Bit patterns.
1881 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1883 (match_operand:SI 1 "uint5_operand" ""))
1885 (label_ref (match_operand 2 "" ""))
1890 return output_bb (operands, 0, insn, 0);
1892 [(set_attr "type" "cbranch")
1893 (set (attr "length")
1894 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1895 (const_int MAX_12BIT_OFFSET))
1897 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1898 (const_int MAX_17BIT_OFFSET))
1900 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1902 (eq (symbol_ref "flag_pic") (const_int 0))
1909 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1911 (match_operand:DI 1 "uint32_operand" ""))
1913 (label_ref (match_operand 2 "" ""))
1918 return output_bb (operands, 0, insn, 0);
1920 [(set_attr "type" "cbranch")
1921 (set (attr "length")
1922 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1923 (const_int MAX_12BIT_OFFSET))
1925 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1926 (const_int MAX_17BIT_OFFSET))
1928 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1930 (eq (symbol_ref "flag_pic") (const_int 0))
1937 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1939 (match_operand:SI 1 "uint5_operand" ""))
1942 (label_ref (match_operand 2 "" ""))))]
1946 return output_bb (operands, 1, insn, 0);
1948 [(set_attr "type" "cbranch")
1949 (set (attr "length")
1950 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1951 (const_int MAX_12BIT_OFFSET))
1953 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1954 (const_int MAX_17BIT_OFFSET))
1956 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1958 (eq (symbol_ref "flag_pic") (const_int 0))
1965 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1967 (match_operand:DI 1 "uint32_operand" ""))
1970 (label_ref (match_operand 2 "" ""))))]
1974 return output_bb (operands, 1, insn, 0);
1976 [(set_attr "type" "cbranch")
1977 (set (attr "length")
1978 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1979 (const_int MAX_12BIT_OFFSET))
1981 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1982 (const_int MAX_17BIT_OFFSET))
1984 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1986 (eq (symbol_ref "flag_pic") (const_int 0))
1993 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1995 (match_operand:SI 1 "uint5_operand" ""))
1997 (label_ref (match_operand 2 "" ""))
2002 return output_bb (operands, 0, insn, 1);
2004 [(set_attr "type" "cbranch")
2005 (set (attr "length")
2006 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2007 (const_int MAX_12BIT_OFFSET))
2009 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2010 (const_int MAX_17BIT_OFFSET))
2012 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2014 (eq (symbol_ref "flag_pic") (const_int 0))
2021 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2023 (match_operand:DI 1 "uint32_operand" ""))
2025 (label_ref (match_operand 2 "" ""))
2030 return output_bb (operands, 0, insn, 1);
2032 [(set_attr "type" "cbranch")
2033 (set (attr "length")
2034 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2035 (const_int MAX_12BIT_OFFSET))
2037 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (const_int MAX_17BIT_OFFSET))
2040 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2042 (eq (symbol_ref "flag_pic") (const_int 0))
2049 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2051 (match_operand:SI 1 "uint5_operand" ""))
2054 (label_ref (match_operand 2 "" ""))))]
2058 return output_bb (operands, 1, insn, 1);
2060 [(set_attr "type" "cbranch")
2061 (set (attr "length")
2062 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2063 (const_int MAX_12BIT_OFFSET))
2065 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2066 (const_int MAX_17BIT_OFFSET))
2068 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2070 (eq (symbol_ref "flag_pic") (const_int 0))
2077 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2079 (match_operand:DI 1 "uint32_operand" ""))
2082 (label_ref (match_operand 2 "" ""))))]
2086 return output_bb (operands, 1, insn, 1);
2088 [(set_attr "type" "cbranch")
2089 (set (attr "length")
2090 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2091 (const_int MAX_12BIT_OFFSET))
2093 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2094 (const_int MAX_17BIT_OFFSET))
2096 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2098 (eq (symbol_ref "flag_pic") (const_int 0))
2102 ;; Branch on Variable Bit patterns.
2106 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2108 (match_operand:SI 1 "register_operand" "q"))
2110 (label_ref (match_operand 2 "" ""))
2115 return output_bvb (operands, 0, insn, 0);
2117 [(set_attr "type" "cbranch")
2118 (set (attr "length")
2119 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2120 (const_int MAX_12BIT_OFFSET))
2122 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2123 (const_int MAX_17BIT_OFFSET))
2125 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2127 (eq (symbol_ref "flag_pic") (const_int 0))
2134 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2136 (match_operand:DI 1 "register_operand" "q"))
2138 (label_ref (match_operand 2 "" ""))
2143 return output_bvb (operands, 0, insn, 0);
2145 [(set_attr "type" "cbranch")
2146 (set (attr "length")
2147 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (const_int MAX_12BIT_OFFSET))
2150 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2151 (const_int MAX_17BIT_OFFSET))
2153 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2155 (eq (symbol_ref "flag_pic") (const_int 0))
2162 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2164 (match_operand:SI 1 "register_operand" "q"))
2167 (label_ref (match_operand 2 "" ""))))]
2171 return output_bvb (operands, 1, insn, 0);
2173 [(set_attr "type" "cbranch")
2174 (set (attr "length")
2175 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2176 (const_int MAX_12BIT_OFFSET))
2178 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2179 (const_int MAX_17BIT_OFFSET))
2181 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2183 (eq (symbol_ref "flag_pic") (const_int 0))
2190 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2192 (match_operand:DI 1 "register_operand" "q"))
2195 (label_ref (match_operand 2 "" ""))))]
2199 return output_bvb (operands, 1, insn, 0);
2201 [(set_attr "type" "cbranch")
2202 (set (attr "length")
2203 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2204 (const_int MAX_12BIT_OFFSET))
2206 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2207 (const_int MAX_17BIT_OFFSET))
2209 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2211 (eq (symbol_ref "flag_pic") (const_int 0))
2218 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2220 (match_operand:SI 1 "register_operand" "q"))
2222 (label_ref (match_operand 2 "" ""))
2227 return output_bvb (operands, 0, insn, 1);
2229 [(set_attr "type" "cbranch")
2230 (set (attr "length")
2231 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2232 (const_int MAX_12BIT_OFFSET))
2234 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2235 (const_int MAX_17BIT_OFFSET))
2237 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2239 (eq (symbol_ref "flag_pic") (const_int 0))
2246 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2248 (match_operand:DI 1 "register_operand" "q"))
2250 (label_ref (match_operand 2 "" ""))
2255 return output_bvb (operands, 0, insn, 1);
2257 [(set_attr "type" "cbranch")
2258 (set (attr "length")
2259 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2260 (const_int MAX_12BIT_OFFSET))
2262 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2263 (const_int MAX_17BIT_OFFSET))
2265 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2267 (eq (symbol_ref "flag_pic") (const_int 0))
2274 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2276 (match_operand:SI 1 "register_operand" "q"))
2279 (label_ref (match_operand 2 "" ""))))]
2283 return output_bvb (operands, 1, insn, 1);
2285 [(set_attr "type" "cbranch")
2286 (set (attr "length")
2287 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2288 (const_int MAX_12BIT_OFFSET))
2290 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2291 (const_int MAX_17BIT_OFFSET))
2293 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2295 (eq (symbol_ref "flag_pic") (const_int 0))
2302 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2304 (match_operand:DI 1 "register_operand" "q"))
2307 (label_ref (match_operand 2 "" ""))))]
2311 return output_bvb (operands, 1, insn, 1);
2313 [(set_attr "type" "cbranch")
2314 (set (attr "length")
2315 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2316 (const_int MAX_12BIT_OFFSET))
2318 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2319 (const_int MAX_17BIT_OFFSET))
2321 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2323 (eq (symbol_ref "flag_pic") (const_int 0))
2327 ;; Floating point branches
2329 ;; ??? Nullification is handled differently from other branches.
2330 ;; If nullification is specified, the delay slot is nullified on any
2331 ;; taken branch regardless of branch direction.
2333 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2334 (label_ref (match_operand 0 "" ""))
2336 "!TARGET_SOFT_FLOAT"
2339 int length = get_attr_length (insn);
2341 int nullify, xdelay;
2344 return \"ftest\;b%* %l0\";
2346 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2350 xoperands[0] = GEN_INT (length - 8);
2356 xoperands[0] = GEN_INT (length - 4);
2360 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2362 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2363 return output_lbranch (operands[0], insn, xdelay);
2365 [(set_attr "type" "fbranch")
2366 (set (attr "length")
2367 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2368 (const_int MAX_17BIT_OFFSET))
2370 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2372 (eq (symbol_ref "flag_pic") (const_int 0))
2377 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2379 (label_ref (match_operand 0 "" ""))))]
2380 "!TARGET_SOFT_FLOAT"
2383 int length = get_attr_length (insn);
2385 int nullify, xdelay;
2388 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2390 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2394 xoperands[0] = GEN_INT (length - 4);
2400 xoperands[0] = GEN_INT (length);
2404 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2406 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2407 return output_lbranch (operands[0], insn, xdelay);
2409 [(set_attr "type" "fbranch")
2410 (set (attr "length")
2411 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2412 (const_int MAX_17BIT_OFFSET))
2414 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2416 (eq (symbol_ref "flag_pic") (const_int 0))
2420 ;; Move instructions
2422 (define_expand "movsi"
2423 [(set (match_operand:SI 0 "general_operand" "")
2424 (match_operand:SI 1 "general_operand" ""))]
2428 if (emit_move_sequence (operands, SImode, 0))
2432 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2433 (define_expand "reload_insi_r1"
2434 [(set (match_operand:SI 0 "register_operand" "=Z")
2435 (match_operand:SI 1 "non_hard_reg_operand" ""))
2436 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2440 if (emit_move_sequence (operands, SImode, operands[2]))
2443 /* We don't want the clobber emitted, so handle this ourselves. */
2444 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2448 ;; Handle SImode input reloads requiring a general register as a
2449 ;; scratch register.
2450 (define_expand "reload_insi"
2451 [(set (match_operand:SI 0 "register_operand" "=Z")
2452 (match_operand:SI 1 "non_hard_reg_operand" ""))
2453 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2457 if (emit_move_sequence (operands, SImode, operands[2]))
2460 /* We don't want the clobber emitted, so handle this ourselves. */
2461 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2465 ;; Handle SImode output reloads requiring a general register as a
2466 ;; scratch register.
2467 (define_expand "reload_outsi"
2468 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2469 (match_operand:SI 1 "register_operand" "Z"))
2470 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2474 if (emit_move_sequence (operands, SImode, operands[2]))
2477 /* We don't want the clobber emitted, so handle this ourselves. */
2478 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2483 [(set (match_operand:SI 0 "move_dest_operand"
2484 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2485 (match_operand:SI 1 "move_src_operand"
2486 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2487 "(register_operand (operands[0], SImode)
2488 || reg_or_0_operand (operands[1], SImode))
2489 && !TARGET_SOFT_FLOAT
2496 {zdepi|depwi,z} %Z1,%0
2500 {mfctl|mfctl,w} %%sar,%0
2504 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2505 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2506 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,move,move")
2507 (set_attr "pa_combine_type" "addmove")
2508 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2511 [(set (match_operand:SI 0 "move_dest_operand"
2512 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2513 (match_operand:SI 1 "move_src_operand"
2514 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2515 "(register_operand (operands[0], SImode)
2516 || reg_or_0_operand (operands[1], SImode))
2517 && !TARGET_SOFT_FLOAT
2524 {zdepi|depwi,z} %Z1,%0
2528 {mfctl|mfctl,w} %%sar,%0
2532 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2533 (set_attr "pa_combine_type" "addmove")
2534 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2537 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2538 (match_operand:SI 1 "register_operand" "f"))]
2540 && !TARGET_DISABLE_INDEXING
2541 && reload_completed"
2543 [(set_attr "type" "fpstore")
2544 (set_attr "pa_combine_type" "addmove")
2545 (set_attr "length" "4")])
2547 ; Rewrite RTL using an indexed store. This will allow the insn that
2548 ; computes the address to be deleted if the register it sets is dead.
2550 [(set (match_operand:SI 0 "register_operand" "")
2551 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2553 (match_operand:SI 2 "register_operand" "")))
2554 (set (mem:SI (match_dup 0))
2555 (match_operand:SI 3 "register_operand" ""))]
2557 && !TARGET_DISABLE_INDEXING
2558 && REG_OK_FOR_BASE_P (operands[2])
2559 && FP_REGNO_P (REGNO (operands[3]))"
2560 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2562 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2567 [(set (match_operand:SI 0 "register_operand" "")
2568 (plus:SI (match_operand:SI 2 "register_operand" "")
2569 (mult:SI (match_operand:SI 1 "register_operand" "")
2571 (set (mem:SI (match_dup 0))
2572 (match_operand:SI 3 "register_operand" ""))]
2574 && !TARGET_DISABLE_INDEXING
2575 && REG_OK_FOR_BASE_P (operands[2])
2576 && FP_REGNO_P (REGNO (operands[3]))"
2577 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2579 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2584 [(set (match_operand:DI 0 "register_operand" "")
2585 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2587 (match_operand:DI 2 "register_operand" "")))
2588 (set (mem:SI (match_dup 0))
2589 (match_operand:SI 3 "register_operand" ""))]
2591 && !TARGET_DISABLE_INDEXING
2593 && REG_OK_FOR_BASE_P (operands[2])
2594 && FP_REGNO_P (REGNO (operands[3]))"
2595 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2597 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2602 [(set (match_operand:DI 0 "register_operand" "")
2603 (plus:DI (match_operand:DI 2 "register_operand" "")
2604 (mult:DI (match_operand:DI 1 "register_operand" "")
2606 (set (mem:SI (match_dup 0))
2607 (match_operand:SI 3 "register_operand" ""))]
2609 && !TARGET_DISABLE_INDEXING
2611 && REG_OK_FOR_BASE_P (operands[2])
2612 && FP_REGNO_P (REGNO (operands[3]))"
2613 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2615 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2620 [(set (match_operand:SI 0 "register_operand" "")
2621 (plus:SI (match_operand:SI 1 "register_operand" "")
2622 (match_operand:SI 2 "register_operand" "")))
2623 (set (mem:SI (match_dup 0))
2624 (match_operand:SI 3 "register_operand" ""))]
2626 && !TARGET_DISABLE_INDEXING
2627 && TARGET_NO_SPACE_REGS
2628 && REG_OK_FOR_INDEX_P (operands[1])
2629 && REG_OK_FOR_BASE_P (operands[2])
2630 && FP_REGNO_P (REGNO (operands[3]))"
2631 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2633 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2637 [(set (match_operand:SI 0 "register_operand" "")
2638 (plus:SI (match_operand:SI 1 "register_operand" "")
2639 (match_operand:SI 2 "register_operand" "")))
2640 (set (mem:SI (match_dup 0))
2641 (match_operand:SI 3 "register_operand" ""))]
2643 && !TARGET_DISABLE_INDEXING
2644 && TARGET_NO_SPACE_REGS
2645 && REG_OK_FOR_BASE_P (operands[1])
2646 && REG_OK_FOR_INDEX_P (operands[2])
2647 && FP_REGNO_P (REGNO (operands[3]))"
2648 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2650 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (plus:DI (match_operand:DI 1 "register_operand" "")
2656 (match_operand:DI 2 "register_operand" "")))
2657 (set (mem:SI (match_dup 0))
2658 (match_operand:SI 3 "register_operand" ""))]
2660 && !TARGET_DISABLE_INDEXING
2662 && TARGET_NO_SPACE_REGS
2663 && REG_OK_FOR_INDEX_P (operands[1])
2664 && REG_OK_FOR_BASE_P (operands[2])
2665 && FP_REGNO_P (REGNO (operands[3]))"
2666 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2668 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2672 [(set (match_operand:DI 0 "register_operand" "")
2673 (plus:DI (match_operand:DI 1 "register_operand" "")
2674 (match_operand:DI 2 "register_operand" "")))
2675 (set (mem:SI (match_dup 0))
2676 (match_operand:SI 3 "register_operand" ""))]
2678 && !TARGET_DISABLE_INDEXING
2680 && TARGET_NO_SPACE_REGS
2681 && REG_OK_FOR_BASE_P (operands[1])
2682 && REG_OK_FOR_INDEX_P (operands[2])
2683 && FP_REGNO_P (REGNO (operands[3]))"
2684 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2686 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2690 [(set (match_operand:SI 0 "move_dest_operand"
2691 "=r,r,r,r,r,r,Q,!*q,!r")
2692 (match_operand:SI 1 "move_src_operand"
2693 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2694 "(register_operand (operands[0], SImode)
2695 || reg_or_0_operand (operands[1], SImode))
2696 && TARGET_SOFT_FLOAT"
2702 {zdepi|depwi,z} %Z1,%0
2706 {mfctl|mfctl,w} %%sar,%0"
2707 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2708 (set_attr "pa_combine_type" "addmove")
2709 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2711 ;; Load or store with base-register modification.
2713 [(set (match_operand:SI 0 "register_operand" "=r")
2714 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2715 (match_operand:DI 2 "int5_operand" "L"))))
2717 (plus:DI (match_dup 1) (match_dup 2)))]
2720 [(set_attr "type" "load")
2721 (set_attr "length" "4")])
2723 ; And a zero extended variant.
2725 [(set (match_operand:DI 0 "register_operand" "=r")
2726 (zero_extend:DI (mem:SI
2728 (match_operand:DI 1 "register_operand" "+r")
2729 (match_operand:DI 2 "int5_operand" "L")))))
2731 (plus:DI (match_dup 1) (match_dup 2)))]
2734 [(set_attr "type" "load")
2735 (set_attr "length" "4")])
2737 (define_expand "pre_load"
2738 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2739 (mem (plus (match_operand 1 "register_operand" "")
2740 (match_operand 2 "pre_cint_operand" ""))))
2742 (plus (match_dup 1) (match_dup 2)))])]
2748 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2751 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2755 (define_insn "pre_ldw"
2756 [(set (match_operand:SI 0 "register_operand" "=r")
2757 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2758 (match_operand:SI 2 "pre_cint_operand" ""))))
2760 (plus:SI (match_dup 1) (match_dup 2)))]
2764 if (INTVAL (operands[2]) < 0)
2765 return \"{ldwm|ldw,mb} %2(%1),%0\";
2766 return \"{ldws|ldw},mb %2(%1),%0\";
2768 [(set_attr "type" "load")
2769 (set_attr "length" "4")])
2771 (define_insn "pre_ldd"
2772 [(set (match_operand:DI 0 "register_operand" "=r")
2773 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2774 (match_operand:DI 2 "pre_cint_operand" ""))))
2776 (plus:DI (match_dup 1) (match_dup 2)))]
2779 [(set_attr "type" "load")
2780 (set_attr "length" "4")])
2783 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2784 (match_operand:SI 1 "pre_cint_operand" "")))
2785 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2787 (plus:SI (match_dup 0) (match_dup 1)))]
2791 if (INTVAL (operands[1]) < 0)
2792 return \"{stwm|stw,mb} %r2,%1(%0)\";
2793 return \"{stws|stw},mb %r2,%1(%0)\";
2795 [(set_attr "type" "store")
2796 (set_attr "length" "4")])
2799 [(set (match_operand:SI 0 "register_operand" "=r")
2800 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2802 (plus:SI (match_dup 1)
2803 (match_operand:SI 2 "post_cint_operand" "")))]
2807 if (INTVAL (operands[2]) > 0)
2808 return \"{ldwm|ldw,ma} %2(%1),%0\";
2809 return \"{ldws|ldw},ma %2(%1),%0\";
2811 [(set_attr "type" "load")
2812 (set_attr "length" "4")])
2814 (define_expand "post_store"
2815 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2816 (match_operand 1 "reg_or_0_operand" ""))
2819 (match_operand 2 "post_cint_operand" "")))])]
2825 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2828 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2832 (define_insn "post_stw"
2833 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2834 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2836 (plus:SI (match_dup 0)
2837 (match_operand:SI 2 "post_cint_operand" "")))]
2841 if (INTVAL (operands[2]) > 0)
2842 return \"{stwm|stw,ma} %r1,%2(%0)\";
2843 return \"{stws|stw},ma %r1,%2(%0)\";
2845 [(set_attr "type" "store")
2846 (set_attr "length" "4")])
2848 (define_insn "post_std"
2849 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2850 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2852 (plus:DI (match_dup 0)
2853 (match_operand:DI 2 "post_cint_operand" "")))]
2856 [(set_attr "type" "store")
2857 (set_attr "length" "4")])
2859 ;; For loading the address of a label while generating PIC code.
2860 ;; Note since this pattern can be created at reload time (via movsi), all
2861 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2863 [(set (match_operand 0 "pmode_register_operand" "=a")
2864 (match_operand 1 "pic_label_operand" ""))]
2870 xoperands[0] = operands[0];
2871 xoperands[1] = operands[1];
2872 xoperands[2] = gen_label_rtx ();
2874 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2875 CODE_LABEL_NUMBER (xoperands[2]));
2876 output_asm_insn (\"mfia %0\", xoperands);
2878 /* If we're trying to load the address of a label that happens to be
2879 close, then we can use a shorter sequence. */
2880 if (GET_CODE (operands[1]) == LABEL_REF
2881 && !LABEL_REF_NONLOCAL_P (operands[1])
2882 && INSN_ADDRESSES_SET_P ()
2883 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2884 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2885 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2888 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2889 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2893 [(set_attr "type" "multi")
2894 (set_attr "length" "12")]) ; 8 or 12
2897 [(set (match_operand 0 "pmode_register_operand" "=a")
2898 (match_operand 1 "pic_label_operand" ""))]
2904 xoperands[0] = operands[0];
2905 xoperands[1] = operands[1];
2906 xoperands[2] = gen_label_rtx ();
2908 output_asm_insn (\"bl .+8,%0\", xoperands);
2909 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2910 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2911 CODE_LABEL_NUMBER (xoperands[2]));
2913 /* If we're trying to load the address of a label that happens to be
2914 close, then we can use a shorter sequence. */
2915 if (GET_CODE (operands[1]) == LABEL_REF
2916 && !LABEL_REF_NONLOCAL_P (operands[1])
2917 && INSN_ADDRESSES_SET_P ()
2918 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2919 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2920 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2923 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2924 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2928 [(set_attr "type" "multi")
2929 (set_attr "length" "16")]) ; 12 or 16
2932 [(set (match_operand:SI 0 "register_operand" "=a")
2933 (plus:SI (match_operand:SI 1 "register_operand" "r")
2934 (high:SI (match_operand 2 "" ""))))]
2935 "symbolic_operand (operands[2], Pmode)
2936 && ! function_label_operand (operands[2], Pmode)
2939 [(set_attr "type" "binary")
2940 (set_attr "length" "4")])
2943 [(set (match_operand:DI 0 "register_operand" "=a")
2944 (plus:DI (match_operand:DI 1 "register_operand" "r")
2945 (high:DI (match_operand 2 "" ""))))]
2946 "symbolic_operand (operands[2], Pmode)
2947 && ! function_label_operand (operands[2], Pmode)
2951 [(set_attr "type" "binary")
2952 (set_attr "length" "4")])
2954 ;; Always use addil rather than ldil;add sequences. This allows the
2955 ;; HP linker to eliminate the dp relocation if the symbolic operand
2956 ;; lives in the TEXT space.
2958 [(set (match_operand:SI 0 "register_operand" "=a")
2959 (high:SI (match_operand 1 "" "")))]
2960 "symbolic_operand (operands[1], Pmode)
2961 && ! function_label_operand (operands[1], Pmode)
2962 && ! read_only_operand (operands[1], Pmode)
2966 if (TARGET_LONG_LOAD_STORE)
2967 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2969 return \"addil LR'%H1,%%r27\";
2971 [(set_attr "type" "binary")
2972 (set (attr "length")
2973 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2978 ;; This is for use in the prologue/epilogue code. We need it
2979 ;; to add large constants to a stack pointer or frame pointer.
2980 ;; Because of the additional %r1 pressure, we probably do not
2981 ;; want to use this in general code, so make it available
2982 ;; only after reload.
2984 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2985 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2986 (high:SI (match_operand 2 "const_int_operand" ""))))]
2990 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2991 [(set_attr "type" "binary,binary")
2992 (set_attr "length" "4,8")])
2995 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2996 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2997 (high:DI (match_operand 2 "const_int_operand" ""))))]
2998 "reload_completed && TARGET_64BIT"
3001 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3002 [(set_attr "type" "binary,binary")
3003 (set_attr "length" "4,8")])
3006 [(set (match_operand:SI 0 "register_operand" "=r")
3007 (high:SI (match_operand 1 "" "")))]
3008 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
3009 && !is_function_label_plus_const (operands[1])"
3012 if (symbolic_operand (operands[1], Pmode))
3013 return \"ldil LR'%H1,%0\";
3015 return \"ldil L'%G1,%0\";
3017 [(set_attr "type" "move")
3018 (set_attr "length" "4")])
3021 [(set (match_operand:DI 0 "register_operand" "=r")
3022 (high:DI (match_operand 1 "const_int_operand" "")))]
3025 [(set_attr "type" "move")
3026 (set_attr "length" "4")])
3029 [(set (match_operand:DI 0 "register_operand" "=r")
3030 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3031 (match_operand:DI 2 "const_int_operand" "i")))]
3034 [(set_attr "type" "move")
3035 (set_attr "length" "4")])
3038 [(set (match_operand:SI 0 "register_operand" "=r")
3039 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3040 (match_operand:SI 2 "immediate_operand" "i")))]
3041 "!is_function_label_plus_const (operands[2])"
3044 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
3046 if (symbolic_operand (operands[2], Pmode))
3047 return \"ldo RR'%G2(%1),%0\";
3049 return \"ldo R'%G2(%1),%0\";
3051 [(set_attr "type" "move")
3052 (set_attr "length" "4")])
3054 ;; Now that a symbolic_address plus a constant is broken up early
3055 ;; in the compilation phase (for better CSE) we need a special
3056 ;; combiner pattern to load the symbolic address plus the constant
3057 ;; in only 2 instructions. (For cases where the symbolic address
3058 ;; was not a common subexpression.)
3060 [(set (match_operand:SI 0 "register_operand" "")
3061 (match_operand:SI 1 "symbolic_operand" ""))
3062 (clobber (match_operand:SI 2 "register_operand" ""))]
3063 "! (flag_pic && pic_label_operand (operands[1], SImode))"
3064 [(set (match_dup 2) (high:SI (match_dup 1)))
3065 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
3068 ;; hppa_legitimize_address goes to a great deal of trouble to
3069 ;; create addresses which use indexing. In some cases, this
3070 ;; is a lose because there isn't any store instructions which
3071 ;; allow indexed addresses (with integer register source).
3073 ;; These define_splits try to turn a 3 insn store into
3074 ;; a 2 insn store with some creative RTL rewriting.
3076 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3077 (match_operand:SI 1 "shadd_operand" ""))
3078 (plus:SI (match_operand:SI 2 "register_operand" "")
3079 (match_operand:SI 3 "const_int_operand" ""))))
3080 (match_operand:SI 4 "register_operand" ""))
3081 (clobber (match_operand:SI 5 "register_operand" ""))]
3083 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3085 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3089 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3090 (match_operand:SI 1 "shadd_operand" ""))
3091 (plus:SI (match_operand:SI 2 "register_operand" "")
3092 (match_operand:SI 3 "const_int_operand" ""))))
3093 (match_operand:HI 4 "register_operand" ""))
3094 (clobber (match_operand:SI 5 "register_operand" ""))]
3096 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3098 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3102 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3103 (match_operand:SI 1 "shadd_operand" ""))
3104 (plus:SI (match_operand:SI 2 "register_operand" "")
3105 (match_operand:SI 3 "const_int_operand" ""))))
3106 (match_operand:QI 4 "register_operand" ""))
3107 (clobber (match_operand:SI 5 "register_operand" ""))]
3109 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3111 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3114 (define_expand "movhi"
3115 [(set (match_operand:HI 0 "general_operand" "")
3116 (match_operand:HI 1 "general_operand" ""))]
3120 if (emit_move_sequence (operands, HImode, 0))
3125 [(set (match_operand:HI 0 "move_dest_operand"
3126 "=r,r,r,r,r,Q,!*q,!r,!*f,?r,?*f")
3127 (match_operand:HI 1 "move_src_operand"
3128 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,*f,r"))]
3129 "(register_operand (operands[0], HImode)
3130 || reg_or_0_operand (operands[1], HImode))
3131 && !TARGET_SOFT_FLOAT
3137 {zdepi|depwi,z} %Z1,%0
3141 {mfctl|mfctl,w} %sar,%0
3143 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3144 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3145 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
3146 (set_attr "pa_combine_type" "addmove")
3147 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3150 [(set (match_operand:HI 0 "move_dest_operand"
3151 "=r,r,r,r,r,Q,!*q,!r,!*f")
3152 (match_operand:HI 1 "move_src_operand"
3153 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3154 "(register_operand (operands[0], HImode)
3155 || reg_or_0_operand (operands[1], HImode))
3156 && !TARGET_SOFT_FLOAT
3162 {zdepi|depwi,z} %Z1,%0
3166 {mfctl|mfctl,w} %sar,%0
3168 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3169 (set_attr "pa_combine_type" "addmove")
3170 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3173 [(set (match_operand:HI 0 "move_dest_operand"
3174 "=r,r,r,r,r,Q,!*q,!r")
3175 (match_operand:HI 1 "move_src_operand"
3176 "r,J,N,K,RQ,rM,!rM,!*q"))]
3177 "(register_operand (operands[0], HImode)
3178 || reg_or_0_operand (operands[1], HImode))
3179 && TARGET_SOFT_FLOAT"
3184 {zdepi|depwi,z} %Z1,%0
3188 {mfctl|mfctl,w} %sar,%0"
3189 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3190 (set_attr "pa_combine_type" "addmove")
3191 (set_attr "length" "4,4,4,4,4,4,4,4")])
3194 [(set (match_operand:HI 0 "register_operand" "=r")
3195 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3196 (match_operand:SI 2 "int5_operand" "L"))))
3198 (plus:SI (match_dup 1) (match_dup 2)))]
3200 "{ldhs|ldh},mb %2(%1),%0"
3201 [(set_attr "type" "load")
3202 (set_attr "length" "4")])
3205 [(set (match_operand:HI 0 "register_operand" "=r")
3206 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3207 (match_operand:DI 2 "int5_operand" "L"))))
3209 (plus:DI (match_dup 1) (match_dup 2)))]
3212 [(set_attr "type" "load")
3213 (set_attr "length" "4")])
3215 ; And a zero extended variant.
3217 [(set (match_operand:DI 0 "register_operand" "=r")
3218 (zero_extend:DI (mem:HI
3220 (match_operand:DI 1 "register_operand" "+r")
3221 (match_operand:DI 2 "int5_operand" "L")))))
3223 (plus:DI (match_dup 1) (match_dup 2)))]
3226 [(set_attr "type" "load")
3227 (set_attr "length" "4")])
3230 [(set (match_operand:SI 0 "register_operand" "=r")
3231 (zero_extend:SI (mem:HI
3233 (match_operand:SI 1 "register_operand" "+r")
3234 (match_operand:SI 2 "int5_operand" "L")))))
3236 (plus:SI (match_dup 1) (match_dup 2)))]
3238 "{ldhs|ldh},mb %2(%1),%0"
3239 [(set_attr "type" "load")
3240 (set_attr "length" "4")])
3243 [(set (match_operand:SI 0 "register_operand" "=r")
3244 (zero_extend:SI (mem:HI
3246 (match_operand:DI 1 "register_operand" "+r")
3247 (match_operand:DI 2 "int5_operand" "L")))))
3249 (plus:DI (match_dup 1) (match_dup 2)))]
3252 [(set_attr "type" "load")
3253 (set_attr "length" "4")])
3256 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3257 (match_operand:SI 1 "int5_operand" "L")))
3258 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3260 (plus:SI (match_dup 0) (match_dup 1)))]
3262 "{sths|sth},mb %r2,%1(%0)"
3263 [(set_attr "type" "store")
3264 (set_attr "length" "4")])
3267 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3268 (match_operand:DI 1 "int5_operand" "L")))
3269 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3271 (plus:DI (match_dup 0) (match_dup 1)))]
3274 [(set_attr "type" "store")
3275 (set_attr "length" "4")])
3278 [(set (match_operand:HI 0 "register_operand" "=r")
3279 (plus:HI (match_operand:HI 1 "register_operand" "r")
3280 (match_operand 2 "const_int_operand" "J")))]
3283 [(set_attr "type" "binary")
3284 (set_attr "pa_combine_type" "addmove")
3285 (set_attr "length" "4")])
3287 (define_expand "movqi"
3288 [(set (match_operand:QI 0 "general_operand" "")
3289 (match_operand:QI 1 "general_operand" ""))]
3293 if (emit_move_sequence (operands, QImode, 0))
3298 [(set (match_operand:QI 0 "move_dest_operand"
3299 "=r,r,r,r,r,Q,!*q,!r,!*f,?r,?*f")
3300 (match_operand:QI 1 "move_src_operand"
3301 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,*f,r"))]
3302 "(register_operand (operands[0], QImode)
3303 || reg_or_0_operand (operands[1], QImode))
3304 && !TARGET_SOFT_FLOAT
3310 {zdepi|depwi,z} %Z1,%0
3314 {mfctl|mfctl,w} %%sar,%0
3316 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3317 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3318 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
3319 (set_attr "pa_combine_type" "addmove")
3320 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3323 [(set (match_operand:QI 0 "move_dest_operand"
3324 "=r,r,r,r,r,Q,!*q,!r,!*f")
3325 (match_operand:QI 1 "move_src_operand"
3326 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3327 "(register_operand (operands[0], QImode)
3328 || reg_or_0_operand (operands[1], QImode))
3329 && !TARGET_SOFT_FLOAT
3335 {zdepi|depwi,z} %Z1,%0
3339 {mfctl|mfctl,w} %%sar,%0
3341 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3342 (set_attr "pa_combine_type" "addmove")
3343 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3346 [(set (match_operand:QI 0 "move_dest_operand"
3347 "=r,r,r,r,r,Q,!*q,!r")
3348 (match_operand:QI 1 "move_src_operand"
3349 "r,J,N,K,RQ,rM,!rM,!*q"))]
3350 "(register_operand (operands[0], QImode)
3351 || reg_or_0_operand (operands[1], QImode))
3352 && TARGET_SOFT_FLOAT"
3357 {zdepi|depwi,z} %Z1,%0
3361 {mfctl|mfctl,w} %%sar,%0"
3362 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3363 (set_attr "pa_combine_type" "addmove")
3364 (set_attr "length" "4,4,4,4,4,4,4,4")])
3367 [(set (match_operand:QI 0 "register_operand" "=r")
3368 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3369 (match_operand:SI 2 "int5_operand" "L"))))
3370 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3372 "{ldbs|ldb},mb %2(%1),%0"
3373 [(set_attr "type" "load")
3374 (set_attr "length" "4")])
3377 [(set (match_operand:QI 0 "register_operand" "=r")
3378 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3379 (match_operand:DI 2 "int5_operand" "L"))))
3380 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3383 [(set_attr "type" "load")
3384 (set_attr "length" "4")])
3386 ; Now the same thing with zero extensions.
3388 [(set (match_operand:DI 0 "register_operand" "=r")
3389 (zero_extend:DI (mem:QI (plus:DI
3390 (match_operand:DI 1 "register_operand" "+r")
3391 (match_operand:DI 2 "int5_operand" "L")))))
3392 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3395 [(set_attr "type" "load")
3396 (set_attr "length" "4")])
3399 [(set (match_operand:SI 0 "register_operand" "=r")
3400 (zero_extend:SI (mem:QI (plus:SI
3401 (match_operand:SI 1 "register_operand" "+r")
3402 (match_operand:SI 2 "int5_operand" "L")))))
3403 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3405 "{ldbs|ldb},mb %2(%1),%0"
3406 [(set_attr "type" "load")
3407 (set_attr "length" "4")])
3410 [(set (match_operand:SI 0 "register_operand" "=r")
3411 (zero_extend:SI (mem:QI (plus:DI
3412 (match_operand:DI 1 "register_operand" "+r")
3413 (match_operand:DI 2 "int5_operand" "L")))))
3414 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3417 [(set_attr "type" "load")
3418 (set_attr "length" "4")])
3421 [(set (match_operand:HI 0 "register_operand" "=r")
3422 (zero_extend:HI (mem:QI (plus:SI
3423 (match_operand:SI 1 "register_operand" "+r")
3424 (match_operand:SI 2 "int5_operand" "L")))))
3425 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3427 "{ldbs|ldb},mb %2(%1),%0"
3428 [(set_attr "type" "load")
3429 (set_attr "length" "4")])
3432 [(set (match_operand:HI 0 "register_operand" "=r")
3433 (zero_extend:HI (mem:QI (plus:DI
3434 (match_operand:DI 1 "register_operand" "+r")
3435 (match_operand:DI 2 "int5_operand" "L")))))
3436 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3439 [(set_attr "type" "load")
3440 (set_attr "length" "4")])
3443 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3444 (match_operand:SI 1 "int5_operand" "L")))
3445 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3447 (plus:SI (match_dup 0) (match_dup 1)))]
3449 "{stbs|stb},mb %r2,%1(%0)"
3450 [(set_attr "type" "store")
3451 (set_attr "length" "4")])
3454 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3455 (match_operand:DI 1 "int5_operand" "L")))
3456 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3458 (plus:DI (match_dup 0) (match_dup 1)))]
3461 [(set_attr "type" "store")
3462 (set_attr "length" "4")])
3464 ;; The definition of this insn does not really explain what it does,
3465 ;; but it should suffice that anything generated as this insn will be
3466 ;; recognized as a movmemsi operation, and that it will not successfully
3467 ;; combine with anything.
3468 (define_expand "movmemsi"
3469 [(parallel [(set (match_operand:BLK 0 "" "")
3470 (match_operand:BLK 1 "" ""))
3471 (clobber (match_dup 4))
3472 (clobber (match_dup 5))
3473 (clobber (match_dup 6))
3474 (clobber (match_dup 7))
3475 (clobber (match_dup 8))
3476 (use (match_operand:SI 2 "arith_operand" ""))
3477 (use (match_operand:SI 3 "const_int_operand" ""))])]
3478 "!TARGET_64BIT && optimize > 0"
3483 /* HP provides very fast block move library routine for the PA;
3484 this routine includes:
3486 4x4 byte at a time block moves,
3487 1x4 byte at a time with alignment checked at runtime with
3488 attempts to align the source and destination as needed
3491 With that in mind, here's the heuristics to try and guess when
3492 the inlined block move will be better than the library block
3495 If the size isn't constant, then always use the library routines.
3497 If the size is large in respect to the known alignment, then use
3498 the library routines.
3500 If the size is small in respect to the known alignment, then open
3501 code the copy (since that will lead to better scheduling).
3503 Else use the block move pattern. */
3505 /* Undetermined size, use the library routine. */
3506 if (GET_CODE (operands[2]) != CONST_INT)
3509 size = INTVAL (operands[2]);
3510 align = INTVAL (operands[3]);
3511 align = align > 4 ? 4 : align;
3513 /* If size/alignment is large, then use the library routines. */
3514 if (size / align > 16)
3517 /* This does happen, but not often enough to worry much about. */
3518 if (size / align < MOVE_RATIO)
3521 /* Fall through means we're going to use our block move pattern. */
3523 = replace_equiv_address (operands[0],
3524 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3526 = replace_equiv_address (operands[1],
3527 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3528 operands[4] = gen_reg_rtx (SImode);
3529 operands[5] = gen_reg_rtx (SImode);
3530 operands[6] = gen_reg_rtx (SImode);
3531 operands[7] = gen_reg_rtx (SImode);
3532 operands[8] = gen_reg_rtx (SImode);
3535 ;; The operand constraints are written like this to support both compile-time
3536 ;; and run-time determined byte counts. The expander and output_block_move
3537 ;; only support compile-time determined counts at this time.
3539 ;; If the count is run-time determined, the register with the byte count
3540 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3542 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3543 ;; broke this semantic for pseudo registers. We can't use match_scratch
3544 ;; as this requires two registers in the class R1_REGS when the MEMs for
3545 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3546 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3547 ;; respectively. We then split or peephole optimize after reload.
3548 (define_insn "movmemsi_prereload"
3549 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3550 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3551 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3552 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3553 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3554 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3555 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3556 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3557 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3560 [(set_attr "type" "multi,multi")])
3563 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3564 (match_operand:BLK 1 "memory_operand" ""))
3565 (clobber (match_operand:SI 2 "register_operand" ""))
3566 (clobber (match_operand:SI 3 "register_operand" ""))
3567 (clobber (match_operand:SI 6 "register_operand" ""))
3568 (clobber (match_operand:SI 7 "register_operand" ""))
3569 (clobber (match_operand:SI 8 "register_operand" ""))
3570 (use (match_operand:SI 4 "arith_operand" ""))
3571 (use (match_operand:SI 5 "const_int_operand" ""))])]
3572 "!TARGET_64BIT && reload_completed && !flag_peephole2
3573 && GET_CODE (operands[0]) == MEM
3574 && register_operand (XEXP (operands[0], 0), SImode)
3575 && GET_CODE (operands[1]) == MEM
3576 && register_operand (XEXP (operands[1], 0), SImode)"
3577 [(set (match_dup 7) (match_dup 9))
3578 (set (match_dup 8) (match_dup 10))
3579 (parallel [(set (match_dup 0) (match_dup 1))
3580 (clobber (match_dup 2))
3581 (clobber (match_dup 3))
3582 (clobber (match_dup 6))
3583 (clobber (match_dup 7))
3584 (clobber (match_dup 8))
3590 operands[9] = XEXP (operands[0], 0);
3591 operands[10] = XEXP (operands[1], 0);
3592 operands[0] = replace_equiv_address (operands[0], operands[7]);
3593 operands[1] = replace_equiv_address (operands[1], operands[8]);
3597 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3598 (match_operand:BLK 1 "memory_operand" ""))
3599 (clobber (match_operand:SI 2 "register_operand" ""))
3600 (clobber (match_operand:SI 3 "register_operand" ""))
3601 (clobber (match_operand:SI 6 "register_operand" ""))
3602 (clobber (match_operand:SI 7 "register_operand" ""))
3603 (clobber (match_operand:SI 8 "register_operand" ""))
3604 (use (match_operand:SI 4 "arith_operand" ""))
3605 (use (match_operand:SI 5 "const_int_operand" ""))])]
3607 && GET_CODE (operands[0]) == MEM
3608 && register_operand (XEXP (operands[0], 0), SImode)
3609 && GET_CODE (operands[1]) == MEM
3610 && register_operand (XEXP (operands[1], 0), SImode)"
3611 [(parallel [(set (match_dup 0) (match_dup 1))
3612 (clobber (match_dup 2))
3613 (clobber (match_dup 3))
3614 (clobber (match_dup 6))
3615 (clobber (match_dup 7))
3616 (clobber (match_dup 8))
3622 rtx addr = XEXP (operands[0], 0);
3623 if (dead_or_set_p (curr_insn, addr))
3627 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3628 operands[0] = replace_equiv_address (operands[0], operands[7]);
3631 addr = XEXP (operands[1], 0);
3632 if (dead_or_set_p (curr_insn, addr))
3636 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3637 operands[1] = replace_equiv_address (operands[1], operands[8]);
3641 (define_insn "movmemsi_postreload"
3642 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3643 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3644 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3645 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3646 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3647 (clobber (match_dup 0))
3648 (clobber (match_dup 1))
3649 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3650 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3652 "!TARGET_64BIT && reload_completed"
3653 "* return output_block_move (operands, !which_alternative);"
3654 [(set_attr "type" "multi,multi")])
3656 (define_expand "movmemdi"
3657 [(parallel [(set (match_operand:BLK 0 "" "")
3658 (match_operand:BLK 1 "" ""))
3659 (clobber (match_dup 4))
3660 (clobber (match_dup 5))
3661 (clobber (match_dup 6))
3662 (clobber (match_dup 7))
3663 (clobber (match_dup 8))
3664 (use (match_operand:DI 2 "arith_operand" ""))
3665 (use (match_operand:DI 3 "const_int_operand" ""))])]
3666 "TARGET_64BIT && optimize > 0"
3671 /* HP provides very fast block move library routine for the PA;
3672 this routine includes:
3674 4x4 byte at a time block moves,
3675 1x4 byte at a time with alignment checked at runtime with
3676 attempts to align the source and destination as needed
3679 With that in mind, here's the heuristics to try and guess when
3680 the inlined block move will be better than the library block
3683 If the size isn't constant, then always use the library routines.
3685 If the size is large in respect to the known alignment, then use
3686 the library routines.
3688 If the size is small in respect to the known alignment, then open
3689 code the copy (since that will lead to better scheduling).
3691 Else use the block move pattern. */
3693 /* Undetermined size, use the library routine. */
3694 if (GET_CODE (operands[2]) != CONST_INT)
3697 size = INTVAL (operands[2]);
3698 align = INTVAL (operands[3]);
3699 align = align > 8 ? 8 : align;
3701 /* If size/alignment is large, then use the library routines. */
3702 if (size / align > 16)
3705 /* This does happen, but not often enough to worry much about. */
3706 if (size / align < MOVE_RATIO)
3709 /* Fall through means we're going to use our block move pattern. */
3711 = replace_equiv_address (operands[0],
3712 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3714 = replace_equiv_address (operands[1],
3715 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3716 operands[4] = gen_reg_rtx (DImode);
3717 operands[5] = gen_reg_rtx (DImode);
3718 operands[6] = gen_reg_rtx (DImode);
3719 operands[7] = gen_reg_rtx (DImode);
3720 operands[8] = gen_reg_rtx (DImode);
3723 ;; The operand constraints are written like this to support both compile-time
3724 ;; and run-time determined byte counts. The expander and output_block_move
3725 ;; only support compile-time determined counts at this time.
3727 ;; If the count is run-time determined, the register with the byte count
3728 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3730 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3731 ;; broke this semantic for pseudo registers. We can't use match_scratch
3732 ;; as this requires two registers in the class R1_REGS when the MEMs for
3733 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3734 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3735 ;; respectively. We then split or peephole optimize after reload.
3736 (define_insn "movmemdi_prereload"
3737 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3738 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3739 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3740 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3741 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3742 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3743 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3744 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3745 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3748 [(set_attr "type" "multi,multi")])
3751 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3752 (match_operand:BLK 1 "memory_operand" ""))
3753 (clobber (match_operand:DI 2 "register_operand" ""))
3754 (clobber (match_operand:DI 3 "register_operand" ""))
3755 (clobber (match_operand:DI 6 "register_operand" ""))
3756 (clobber (match_operand:DI 7 "register_operand" ""))
3757 (clobber (match_operand:DI 8 "register_operand" ""))
3758 (use (match_operand:DI 4 "arith_operand" ""))
3759 (use (match_operand:DI 5 "const_int_operand" ""))])]
3760 "TARGET_64BIT && reload_completed && !flag_peephole2
3761 && GET_CODE (operands[0]) == MEM
3762 && register_operand (XEXP (operands[0], 0), DImode)
3763 && GET_CODE (operands[1]) == MEM
3764 && register_operand (XEXP (operands[1], 0), DImode)"
3765 [(set (match_dup 7) (match_dup 9))
3766 (set (match_dup 8) (match_dup 10))
3767 (parallel [(set (match_dup 0) (match_dup 1))
3768 (clobber (match_dup 2))
3769 (clobber (match_dup 3))
3770 (clobber (match_dup 6))
3771 (clobber (match_dup 7))
3772 (clobber (match_dup 8))
3778 operands[9] = XEXP (operands[0], 0);
3779 operands[10] = XEXP (operands[1], 0);
3780 operands[0] = replace_equiv_address (operands[0], operands[7]);
3781 operands[1] = replace_equiv_address (operands[1], operands[8]);
3785 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3786 (match_operand:BLK 1 "memory_operand" ""))
3787 (clobber (match_operand:DI 2 "register_operand" ""))
3788 (clobber (match_operand:DI 3 "register_operand" ""))
3789 (clobber (match_operand:DI 6 "register_operand" ""))
3790 (clobber (match_operand:DI 7 "register_operand" ""))
3791 (clobber (match_operand:DI 8 "register_operand" ""))
3792 (use (match_operand:DI 4 "arith_operand" ""))
3793 (use (match_operand:DI 5 "const_int_operand" ""))])]
3795 && GET_CODE (operands[0]) == MEM
3796 && register_operand (XEXP (operands[0], 0), DImode)
3797 && GET_CODE (operands[1]) == MEM
3798 && register_operand (XEXP (operands[1], 0), DImode)"
3799 [(parallel [(set (match_dup 0) (match_dup 1))
3800 (clobber (match_dup 2))
3801 (clobber (match_dup 3))
3802 (clobber (match_dup 6))
3803 (clobber (match_dup 7))
3804 (clobber (match_dup 8))
3810 rtx addr = XEXP (operands[0], 0);
3811 if (dead_or_set_p (curr_insn, addr))
3815 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3816 operands[0] = replace_equiv_address (operands[0], operands[7]);
3819 addr = XEXP (operands[1], 0);
3820 if (dead_or_set_p (curr_insn, addr))
3824 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3825 operands[1] = replace_equiv_address (operands[1], operands[8]);
3829 (define_insn "movmemdi_postreload"
3830 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3831 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3832 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3833 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3834 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3835 (clobber (match_dup 0))
3836 (clobber (match_dup 1))
3837 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3838 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3840 "TARGET_64BIT && reload_completed"
3841 "* return output_block_move (operands, !which_alternative);"
3842 [(set_attr "type" "multi,multi")])
3844 (define_expand "setmemsi"
3845 [(parallel [(set (match_operand:BLK 0 "" "")
3846 (match_operand 2 "const_int_operand" ""))
3847 (clobber (match_dup 4))
3848 (clobber (match_dup 5))
3849 (use (match_operand:SI 1 "arith_operand" ""))
3850 (use (match_operand:SI 3 "const_int_operand" ""))])]
3851 "!TARGET_64BIT && optimize > 0"
3856 /* If value to set is not zero, use the library routine. */
3857 if (operands[2] != const0_rtx)
3860 /* Undetermined size, use the library routine. */
3861 if (GET_CODE (operands[1]) != CONST_INT)
3864 size = INTVAL (operands[1]);
3865 align = INTVAL (operands[3]);
3866 align = align > 4 ? 4 : align;
3868 /* If size/alignment is large, then use the library routines. */
3869 if (size / align > 16)
3872 /* This does happen, but not often enough to worry much about. */
3873 if (size / align < MOVE_RATIO)
3876 /* Fall through means we're going to use our block clear pattern. */
3878 = replace_equiv_address (operands[0],
3879 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3880 operands[4] = gen_reg_rtx (SImode);
3881 operands[5] = gen_reg_rtx (SImode);
3884 (define_insn "clrmemsi_prereload"
3885 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3887 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3888 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3889 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3890 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3893 [(set_attr "type" "multi,multi")])
3896 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3898 (clobber (match_operand:SI 1 "register_operand" ""))
3899 (clobber (match_operand:SI 4 "register_operand" ""))
3900 (use (match_operand:SI 2 "arith_operand" ""))
3901 (use (match_operand:SI 3 "const_int_operand" ""))])]
3902 "!TARGET_64BIT && reload_completed && !flag_peephole2
3903 && GET_CODE (operands[0]) == MEM
3904 && register_operand (XEXP (operands[0], 0), SImode)"
3905 [(set (match_dup 4) (match_dup 5))
3906 (parallel [(set (match_dup 0) (const_int 0))
3907 (clobber (match_dup 1))
3908 (clobber (match_dup 4))
3914 operands[5] = XEXP (operands[0], 0);
3915 operands[0] = replace_equiv_address (operands[0], operands[4]);
3919 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3921 (clobber (match_operand:SI 1 "register_operand" ""))
3922 (clobber (match_operand:SI 4 "register_operand" ""))
3923 (use (match_operand:SI 2 "arith_operand" ""))
3924 (use (match_operand:SI 3 "const_int_operand" ""))])]
3926 && GET_CODE (operands[0]) == MEM
3927 && register_operand (XEXP (operands[0], 0), SImode)"
3928 [(parallel [(set (match_dup 0) (const_int 0))
3929 (clobber (match_dup 1))
3930 (clobber (match_dup 4))
3936 rtx addr = XEXP (operands[0], 0);
3937 if (dead_or_set_p (curr_insn, addr))
3941 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3942 operands[0] = replace_equiv_address (operands[0], operands[4]);
3946 (define_insn "clrmemsi_postreload"
3947 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3949 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3950 (clobber (match_dup 0))
3951 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3952 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3954 "!TARGET_64BIT && reload_completed"
3955 "* return output_block_clear (operands, !which_alternative);"
3956 [(set_attr "type" "multi,multi")])
3958 (define_expand "setmemdi"
3959 [(parallel [(set (match_operand:BLK 0 "" "")
3960 (match_operand 2 "const_int_operand" ""))
3961 (clobber (match_dup 4))
3962 (clobber (match_dup 5))
3963 (use (match_operand:DI 1 "arith_operand" ""))
3964 (use (match_operand:DI 3 "const_int_operand" ""))])]
3965 "TARGET_64BIT && optimize > 0"
3970 /* If value to set is not zero, use the library routine. */
3971 if (operands[2] != const0_rtx)
3974 /* Undetermined size, use the library routine. */
3975 if (GET_CODE (operands[1]) != CONST_INT)
3978 size = INTVAL (operands[1]);
3979 align = INTVAL (operands[3]);
3980 align = align > 8 ? 8 : align;
3982 /* If size/alignment is large, then use the library routines. */
3983 if (size / align > 16)
3986 /* This does happen, but not often enough to worry much about. */
3987 if (size / align < MOVE_RATIO)
3990 /* Fall through means we're going to use our block clear pattern. */
3992 = replace_equiv_address (operands[0],
3993 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3994 operands[4] = gen_reg_rtx (DImode);
3995 operands[5] = gen_reg_rtx (DImode);
3998 (define_insn "clrmemdi_prereload"
3999 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
4001 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4002 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
4003 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4004 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
4007 [(set_attr "type" "multi,multi")])
4010 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4012 (clobber (match_operand:DI 1 "register_operand" ""))
4013 (clobber (match_operand:DI 4 "register_operand" ""))
4014 (use (match_operand:DI 2 "arith_operand" ""))
4015 (use (match_operand:DI 3 "const_int_operand" ""))])]
4016 "TARGET_64BIT && reload_completed && !flag_peephole2
4017 && GET_CODE (operands[0]) == MEM
4018 && register_operand (XEXP (operands[0], 0), DImode)"
4019 [(set (match_dup 4) (match_dup 5))
4020 (parallel [(set (match_dup 0) (const_int 0))
4021 (clobber (match_dup 1))
4022 (clobber (match_dup 4))
4028 operands[5] = XEXP (operands[0], 0);
4029 operands[0] = replace_equiv_address (operands[0], operands[4]);
4033 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4035 (clobber (match_operand:DI 1 "register_operand" ""))
4036 (clobber (match_operand:DI 4 "register_operand" ""))
4037 (use (match_operand:DI 2 "arith_operand" ""))
4038 (use (match_operand:DI 3 "const_int_operand" ""))])]
4040 && GET_CODE (operands[0]) == MEM
4041 && register_operand (XEXP (operands[0], 0), DImode)"
4042 [(parallel [(set (match_dup 0) (const_int 0))
4043 (clobber (match_dup 1))
4044 (clobber (match_dup 4))
4050 rtx addr = XEXP (operands[0], 0);
4051 if (dead_or_set_p (curr_insn, addr))
4055 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4056 operands[0] = replace_equiv_address (operands[0], operands[4]);
4060 (define_insn "clrmemdi_postreload"
4061 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
4063 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4064 (clobber (match_dup 0))
4065 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4066 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
4068 "TARGET_64BIT && reload_completed"
4069 "* return output_block_clear (operands, !which_alternative);"
4070 [(set_attr "type" "multi,multi")])
4072 ;; Floating point move insns
4074 ;; This pattern forces (set (reg:DF ...) (const_double ...))
4075 ;; to be reloaded by putting the constant into memory when
4076 ;; reg is a floating point register.
4078 ;; For integer registers we use ldil;ldo to set the appropriate
4081 ;; This must come before the movdf pattern, and it must be present
4082 ;; to handle obscure reloading cases.
4084 [(set (match_operand:DF 0 "register_operand" "=?r,f")
4085 (match_operand:DF 1 "" "?F,m"))]
4086 "GET_CODE (operands[1]) == CONST_DOUBLE
4087 && operands[1] != CONST0_RTX (DFmode)
4089 && !TARGET_SOFT_FLOAT"
4090 "* return (which_alternative == 0 ? output_move_double (operands)
4091 : \"fldd%F1 %1,%0\");"
4092 [(set_attr "type" "move,fpload")
4093 (set_attr "length" "16,4")])
4095 (define_expand "movdf"
4096 [(set (match_operand:DF 0 "general_operand" "")
4097 (match_operand:DF 1 "general_operand" ""))]
4101 if (GET_CODE (operands[1]) == CONST_DOUBLE
4102 && operands[1] != CONST0_RTX (DFmode))
4104 /* Reject CONST_DOUBLE loads to all hard registers when
4105 generating 64-bit code and to floating point registers
4106 when generating 32-bit code. */
4107 if (REG_P (operands[0])
4108 && HARD_REGISTER_P (operands[0])
4109 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
4113 operands[1] = force_const_mem (DFmode, operands[1]);
4116 if (emit_move_sequence (operands, DFmode, 0))
4120 ;; Handle DFmode input reloads requiring a general register as a
4121 ;; scratch register.
4122 (define_expand "reload_indf"
4123 [(set (match_operand:DF 0 "register_operand" "=Z")
4124 (match_operand:DF 1 "non_hard_reg_operand" ""))
4125 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4129 if (emit_move_sequence (operands, DFmode, operands[2]))
4132 /* We don't want the clobber emitted, so handle this ourselves. */
4133 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4137 ;; Handle DFmode output reloads requiring a general register as a
4138 ;; scratch register.
4139 (define_expand "reload_outdf"
4140 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
4141 (match_operand:DF 1 "register_operand" "Z"))
4142 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4146 if (emit_move_sequence (operands, DFmode, operands[2]))
4149 /* We don't want the clobber emitted, so handle this ourselves. */
4150 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4155 [(set (match_operand:DF 0 "move_dest_operand"
4156 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
4157 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4158 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
4159 "(register_operand (operands[0], DFmode)
4160 || reg_or_0_operand (operands[1], DFmode))
4161 && !(GET_CODE (operands[1]) == CONST_DOUBLE
4162 && GET_CODE (operands[0]) == MEM)
4164 && !TARGET_SOFT_FLOAT"
4167 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4168 || operands[1] == CONST0_RTX (DFmode))
4169 && !(REG_P (operands[0]) && REG_P (operands[1])
4170 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4171 return output_fp_move_double (operands);
4172 return output_move_double (operands);
4174 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,move,move")
4175 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
4178 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
4179 (match_operand:DF 1 "reg_or_0_operand" "f"))]
4181 && !TARGET_DISABLE_INDEXING
4182 && reload_completed"
4184 [(set_attr "type" "fpstore")
4185 (set_attr "pa_combine_type" "addmove")
4186 (set_attr "length" "4")])
4189 [(set (match_operand:SI 0 "register_operand" "")
4190 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4192 (match_operand:SI 2 "register_operand" "")))
4193 (set (mem:DF (match_dup 0))
4194 (match_operand:DF 3 "register_operand" ""))]
4196 && !TARGET_DISABLE_INDEXING
4197 && REG_OK_FOR_BASE_P (operands[2])
4198 && FP_REGNO_P (REGNO (operands[3]))"
4199 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4201 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4206 [(set (match_operand:SI 0 "register_operand" "")
4207 (plus:SI (match_operand:SI 2 "register_operand" "")
4208 (mult:SI (match_operand:SI 1 "register_operand" "")
4210 (set (mem:DF (match_dup 0))
4211 (match_operand:DF 3 "register_operand" ""))]
4213 && !TARGET_DISABLE_INDEXING
4214 && REG_OK_FOR_BASE_P (operands[2])
4215 && FP_REGNO_P (REGNO (operands[3]))"
4216 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4218 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4223 [(set (match_operand:DI 0 "register_operand" "")
4224 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4226 (match_operand:DI 2 "register_operand" "")))
4227 (set (mem:DF (match_dup 0))
4228 (match_operand:DF 3 "register_operand" ""))]
4230 && !TARGET_DISABLE_INDEXING
4232 && REG_OK_FOR_BASE_P (operands[2])
4233 && FP_REGNO_P (REGNO (operands[3]))"
4234 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4236 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4241 [(set (match_operand:DI 0 "register_operand" "")
4242 (plus:DI (match_operand:DI 2 "register_operand" "")
4243 (mult:DI (match_operand:DI 1 "register_operand" "")
4245 (set (mem:DF (match_dup 0))
4246 (match_operand:DF 3 "register_operand" ""))]
4248 && !TARGET_DISABLE_INDEXING
4250 && REG_OK_FOR_BASE_P (operands[2])
4251 && FP_REGNO_P (REGNO (operands[3]))"
4252 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4254 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4259 [(set (match_operand:SI 0 "register_operand" "")
4260 (plus:SI (match_operand:SI 1 "register_operand" "")
4261 (match_operand:SI 2 "register_operand" "")))
4262 (set (mem:DF (match_dup 0))
4263 (match_operand:DF 3 "register_operand" ""))]
4265 && !TARGET_DISABLE_INDEXING
4266 && TARGET_NO_SPACE_REGS
4267 && REG_OK_FOR_INDEX_P (operands[1])
4268 && REG_OK_FOR_BASE_P (operands[2])
4269 && FP_REGNO_P (REGNO (operands[3]))"
4270 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
4272 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4276 [(set (match_operand:SI 0 "register_operand" "")
4277 (plus:SI (match_operand:SI 1 "register_operand" "")
4278 (match_operand:SI 2 "register_operand" "")))
4279 (set (mem:DF (match_dup 0))
4280 (match_operand:DF 3 "register_operand" ""))]
4282 && !TARGET_DISABLE_INDEXING
4283 && TARGET_NO_SPACE_REGS
4284 && REG_OK_FOR_BASE_P (operands[1])
4285 && REG_OK_FOR_INDEX_P (operands[2])
4286 && FP_REGNO_P (REGNO (operands[3]))"
4287 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
4289 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4293 [(set (match_operand:DI 0 "register_operand" "")
4294 (plus:DI (match_operand:DI 1 "register_operand" "")
4295 (match_operand:DI 2 "register_operand" "")))
4296 (set (mem:DF (match_dup 0))
4297 (match_operand:DF 3 "register_operand" ""))]
4299 && !TARGET_DISABLE_INDEXING
4301 && TARGET_NO_SPACE_REGS
4302 && REG_OK_FOR_INDEX_P (operands[1])
4303 && REG_OK_FOR_BASE_P (operands[2])
4304 && FP_REGNO_P (REGNO (operands[3]))"
4305 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4307 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4311 [(set (match_operand:DI 0 "register_operand" "")
4312 (plus:DI (match_operand:DI 1 "register_operand" "")
4313 (match_operand:DI 2 "register_operand" "")))
4314 (set (mem:DF (match_dup 0))
4315 (match_operand:DF 3 "register_operand" ""))]
4317 && !TARGET_DISABLE_INDEXING
4319 && TARGET_NO_SPACE_REGS
4320 && REG_OK_FOR_BASE_P (operands[1])
4321 && REG_OK_FOR_INDEX_P (operands[2])
4322 && FP_REGNO_P (REGNO (operands[3]))"
4323 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4325 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4329 [(set (match_operand:DF 0 "move_dest_operand"
4331 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4333 "(register_operand (operands[0], DFmode)
4334 || reg_or_0_operand (operands[1], DFmode))
4336 && TARGET_SOFT_FLOAT"
4339 return output_move_double (operands);
4341 [(set_attr "type" "move,store,store,load,load")
4342 (set_attr "length" "8,8,16,8,16")])
4345 [(set (match_operand:DF 0 "move_dest_operand"
4346 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4347 (match_operand:DF 1 "move_src_operand"
4348 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4349 "(register_operand (operands[0], DFmode)
4350 || reg_or_0_operand (operands[1], DFmode))
4351 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4362 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4363 (set_attr "pa_combine_type" "addmove")
4364 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4367 (define_expand "movdi"
4368 [(set (match_operand:DI 0 "general_operand" "")
4369 (match_operand:DI 1 "general_operand" ""))]
4373 /* Except for zero, we don't support loading a CONST_INT directly
4374 to a hard floating-point register since a scratch register is
4375 needed for the operation. While the operation could be handled
4376 before no_new_pseudos is true, the simplest solution is to fail. */
4378 && GET_CODE (operands[1]) == CONST_INT
4379 && operands[1] != CONST0_RTX (DImode)
4380 && REG_P (operands[0])
4381 && HARD_REGISTER_P (operands[0])
4382 && REGNO (operands[0]) >= 32)
4385 if (emit_move_sequence (operands, DImode, 0))
4389 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4390 (define_expand "reload_indi_r1"
4391 [(set (match_operand:DI 0 "register_operand" "=Z")
4392 (match_operand:DI 1 "non_hard_reg_operand" ""))
4393 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4397 if (emit_move_sequence (operands, DImode, operands[2]))
4400 /* We don't want the clobber emitted, so handle this ourselves. */
4401 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4405 ;; Handle DImode input reloads requiring a general register as a
4406 ;; scratch register.
4407 (define_expand "reload_indi"
4408 [(set (match_operand:DI 0 "register_operand" "=Z")
4409 (match_operand:DI 1 "non_hard_reg_operand" ""))
4410 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4414 if (emit_move_sequence (operands, DImode, operands[2]))
4417 /* We don't want the clobber emitted, so handle this ourselves. */
4418 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4422 ;; Handle DImode output reloads requiring a general register as a
4423 ;; scratch register.
4424 (define_expand "reload_outdi"
4425 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4426 (match_operand:DI 1 "register_operand" "Z"))
4427 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4431 if (emit_move_sequence (operands, DImode, operands[2]))
4434 /* We don't want the clobber emitted, so handle this ourselves. */
4435 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4440 [(set (match_operand:DI 0 "register_operand" "=r")
4441 (high:DI (match_operand 1 "" "")))]
4445 rtx op0 = operands[0];
4446 rtx op1 = operands[1];
4448 switch (GET_CODE (op1))
4451 #if HOST_BITS_PER_WIDE_INT <= 32
4452 operands[0] = operand_subword (op0, 1, 0, DImode);
4453 output_asm_insn (\"ldil L'%1,%0\", operands);
4455 operands[0] = operand_subword (op0, 0, 0, DImode);
4456 if (INTVAL (op1) < 0)
4457 output_asm_insn (\"ldi -1,%0\", operands);
4459 output_asm_insn (\"ldi 0,%0\", operands);
4461 operands[0] = operand_subword (op0, 1, 0, DImode);
4462 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4463 output_asm_insn (\"ldil L'%1,%0\", operands);
4465 operands[0] = operand_subword (op0, 0, 0, DImode);
4466 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4467 output_asm_insn (singlemove_string (operands), operands);
4472 operands[0] = operand_subword (op0, 1, 0, DImode);
4473 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4474 output_asm_insn (\"ldil L'%1,%0\", operands);
4476 operands[0] = operand_subword (op0, 0, 0, DImode);
4477 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4478 output_asm_insn (singlemove_string (operands), operands);
4486 [(set_attr "type" "move")
4487 (set_attr "length" "12")])
4490 [(set (match_operand:DI 0 "move_dest_operand"
4491 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4492 (match_operand:DI 1 "general_operand"
4493 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4494 "(register_operand (operands[0], DImode)
4495 || reg_or_0_operand (operands[1], DImode))
4497 && !TARGET_SOFT_FLOAT"
4500 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4501 || operands[1] == CONST0_RTX (DFmode))
4502 && !(REG_P (operands[0]) && REG_P (operands[1])
4503 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4504 return output_fp_move_double (operands);
4505 return output_move_double (operands);
4508 "move,store,store,load,load,multi,fpalu,fpload,fpstore,move,move")
4509 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4512 [(set (match_operand:DI 0 "move_dest_operand"
4513 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4514 (match_operand:DI 1 "move_src_operand"
4515 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4516 "(register_operand (operands[0], DImode)
4517 || reg_or_0_operand (operands[1], DImode))
4518 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4528 {mfctl|mfctl,w} %%sar,%0
4532 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4533 (set_attr "pa_combine_type" "addmove")
4534 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4537 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4538 (match_operand:DI 1 "register_operand" "f"))]
4541 && !TARGET_DISABLE_INDEXING
4542 && reload_completed"
4544 [(set_attr "type" "fpstore")
4545 (set_attr "pa_combine_type" "addmove")
4546 (set_attr "length" "4")])
4549 [(set (match_operand:DI 0 "register_operand" "")
4550 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4552 (match_operand:DI 2 "register_operand" "")))
4553 (set (mem:DI (match_dup 0))
4554 (match_operand:DI 3 "register_operand" ""))]
4556 && !TARGET_DISABLE_INDEXING
4558 && REG_OK_FOR_BASE_P (operands[2])
4559 && FP_REGNO_P (REGNO (operands[3]))"
4560 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4562 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4567 [(set (match_operand:DI 0 "register_operand" "")
4568 (plus:DI (match_operand:DI 2 "register_operand" "")
4569 (mult:DI (match_operand:DI 1 "register_operand" "")
4571 (set (mem:DI (match_dup 0))
4572 (match_operand:DI 3 "register_operand" ""))]
4574 && !TARGET_DISABLE_INDEXING
4576 && REG_OK_FOR_BASE_P (operands[2])
4577 && FP_REGNO_P (REGNO (operands[3]))"
4578 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4580 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4585 [(set (match_operand:DI 0 "register_operand" "")
4586 (plus:DI (match_operand:DI 1 "register_operand" "")
4587 (match_operand:DI 2 "register_operand" "")))
4588 (set (mem:DI (match_dup 0))
4589 (match_operand:DI 3 "register_operand" ""))]
4591 && !TARGET_DISABLE_INDEXING
4593 && TARGET_NO_SPACE_REGS
4594 && REG_OK_FOR_INDEX_P (operands[1])
4595 && REG_OK_FOR_BASE_P (operands[2])
4596 && FP_REGNO_P (REGNO (operands[3]))"
4597 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4599 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4603 [(set (match_operand:DI 0 "register_operand" "")
4604 (plus:DI (match_operand:DI 1 "register_operand" "")
4605 (match_operand:DI 2 "register_operand" "")))
4606 (set (mem:DI (match_dup 0))
4607 (match_operand:DI 3 "register_operand" ""))]
4609 && !TARGET_DISABLE_INDEXING
4611 && TARGET_NO_SPACE_REGS
4612 && REG_OK_FOR_BASE_P (operands[1])
4613 && REG_OK_FOR_INDEX_P (operands[2])
4614 && FP_REGNO_P (REGNO (operands[3]))"
4615 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4617 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4621 [(set (match_operand:DI 0 "move_dest_operand"
4623 (match_operand:DI 1 "general_operand"
4625 "(register_operand (operands[0], DImode)
4626 || reg_or_0_operand (operands[1], DImode))
4628 && TARGET_SOFT_FLOAT"
4631 return output_move_double (operands);
4633 [(set_attr "type" "move,store,store,load,load,multi")
4634 (set_attr "length" "8,8,16,8,16,16")])
4637 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4638 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4639 (match_operand:DI 2 "immediate_operand" "i,i")))]
4643 /* Don't output a 64-bit constant, since we can't trust the assembler to
4644 handle it correctly. */
4645 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4646 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4647 else if (HOST_BITS_PER_WIDE_INT > 32
4648 && GET_CODE (operands[2]) == CONST_INT)
4649 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4650 if (which_alternative == 1)
4651 output_asm_insn (\"copy %1,%0\", operands);
4652 return \"ldo R'%G2(%R1),%R0\";
4654 [(set_attr "type" "move,move")
4655 (set_attr "length" "4,8")])
4657 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4658 ;; to be reloaded by putting the constant into memory when
4659 ;; reg is a floating point register.
4661 ;; For integer registers we use ldil;ldo to set the appropriate
4664 ;; This must come before the movsf pattern, and it must be present
4665 ;; to handle obscure reloading cases.
4667 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4668 (match_operand:SF 1 "" "?F,m"))]
4669 "GET_CODE (operands[1]) == CONST_DOUBLE
4670 && operands[1] != CONST0_RTX (SFmode)
4671 && ! TARGET_SOFT_FLOAT"
4672 "* return (which_alternative == 0 ? singlemove_string (operands)
4673 : \" fldw%F1 %1,%0\");"
4674 [(set_attr "type" "move,fpload")
4675 (set_attr "length" "8,4")])
4677 (define_expand "movsf"
4678 [(set (match_operand:SF 0 "general_operand" "")
4679 (match_operand:SF 1 "general_operand" ""))]
4683 /* Reject CONST_DOUBLE loads to floating point registers. */
4684 if (GET_CODE (operands[1]) == CONST_DOUBLE
4685 && operands[1] != CONST0_RTX (SFmode)
4686 && REG_P (operands[0])
4687 && HARD_REGISTER_P (operands[0])
4688 && REGNO (operands[0]) >= 32)
4691 if (emit_move_sequence (operands, SFmode, 0))
4695 ;; Handle SFmode input reloads requiring a general register as a
4696 ;; scratch register.
4697 (define_expand "reload_insf"
4698 [(set (match_operand:SF 0 "register_operand" "=Z")
4699 (match_operand:SF 1 "non_hard_reg_operand" ""))
4700 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4704 if (emit_move_sequence (operands, SFmode, operands[2]))
4707 /* We don't want the clobber emitted, so handle this ourselves. */
4708 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4712 ;; Handle SFmode output reloads requiring a general register as a
4713 ;; scratch register.
4714 (define_expand "reload_outsf"
4715 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4716 (match_operand:SF 1 "register_operand" "Z"))
4717 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4721 if (emit_move_sequence (operands, SFmode, operands[2]))
4724 /* We don't want the clobber emitted, so handle this ourselves. */
4725 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4730 [(set (match_operand:SF 0 "move_dest_operand"
4731 "=f,!*r,f,*r,Q,Q,?*r,?f")
4732 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4733 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4734 "(register_operand (operands[0], SFmode)
4735 || reg_or_0_operand (operands[1], SFmode))
4736 && !TARGET_SOFT_FLOAT
4745 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4746 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4747 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,move,move")
4748 (set_attr "pa_combine_type" "addmove")
4749 (set_attr "length" "4,4,4,4,4,4,8,8")])
4752 [(set (match_operand:SF 0 "move_dest_operand"
4754 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4755 "fG,!*rG,RQ,RQ,f,*rG"))]
4756 "(register_operand (operands[0], SFmode)
4757 || reg_or_0_operand (operands[1], SFmode))
4758 && !TARGET_SOFT_FLOAT
4767 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4768 (set_attr "pa_combine_type" "addmove")
4769 (set_attr "length" "4,4,4,4,4,4")])
4772 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4773 (match_operand:SF 1 "register_operand" "f"))]
4775 && !TARGET_DISABLE_INDEXING
4776 && reload_completed"
4778 [(set_attr "type" "fpstore")
4779 (set_attr "pa_combine_type" "addmove")
4780 (set_attr "length" "4")])
4783 [(set (match_operand:SI 0 "register_operand" "")
4784 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4786 (match_operand:SI 2 "register_operand" "")))
4787 (set (mem:SF (match_dup 0))
4788 (match_operand:SF 3 "register_operand" ""))]
4790 && !TARGET_DISABLE_INDEXING
4791 && REG_OK_FOR_BASE_P (operands[2])
4792 && FP_REGNO_P (REGNO (operands[3]))"
4793 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4795 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4800 [(set (match_operand:SI 0 "register_operand" "")
4801 (plus:SI (match_operand:SI 2 "register_operand" "")
4802 (mult:SI (match_operand:SI 1 "register_operand" "")
4804 (set (mem:SF (match_dup 0))
4805 (match_operand:SF 3 "register_operand" ""))]
4807 && !TARGET_DISABLE_INDEXING
4808 && REG_OK_FOR_BASE_P (operands[2])
4809 && FP_REGNO_P (REGNO (operands[3]))"
4810 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4812 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4817 [(set (match_operand:DI 0 "register_operand" "")
4818 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4820 (match_operand:DI 2 "register_operand" "")))
4821 (set (mem:SF (match_dup 0))
4822 (match_operand:SF 3 "register_operand" ""))]
4824 && !TARGET_DISABLE_INDEXING
4826 && REG_OK_FOR_BASE_P (operands[2])
4827 && FP_REGNO_P (REGNO (operands[3]))"
4828 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4830 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4835 [(set (match_operand:DI 0 "register_operand" "")
4836 (plus:DI (match_operand:DI 2 "register_operand" "")
4837 (mult:DI (match_operand:DI 1 "register_operand" "")
4839 (set (mem:SF (match_dup 0))
4840 (match_operand:SF 3 "register_operand" ""))]
4842 && !TARGET_DISABLE_INDEXING
4844 && REG_OK_FOR_BASE_P (operands[2])
4845 && FP_REGNO_P (REGNO (operands[3]))"
4846 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4848 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4853 [(set (match_operand:SI 0 "register_operand" "")
4854 (plus:SI (match_operand:SI 1 "register_operand" "")
4855 (match_operand:SI 2 "register_operand" "")))
4856 (set (mem:SF (match_dup 0))
4857 (match_operand:SF 3 "register_operand" ""))]
4859 && !TARGET_DISABLE_INDEXING
4860 && TARGET_NO_SPACE_REGS
4861 && REG_OK_FOR_INDEX_P (operands[1])
4862 && REG_OK_FOR_BASE_P (operands[2])
4863 && FP_REGNO_P (REGNO (operands[3]))"
4864 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4866 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4870 [(set (match_operand:SI 0 "register_operand" "")
4871 (plus:SI (match_operand:SI 1 "register_operand" "")
4872 (match_operand:SI 2 "register_operand" "")))
4873 (set (mem:SF (match_dup 0))
4874 (match_operand:SF 3 "register_operand" ""))]
4876 && !TARGET_DISABLE_INDEXING
4877 && TARGET_NO_SPACE_REGS
4878 && REG_OK_FOR_BASE_P (operands[1])
4879 && REG_OK_FOR_INDEX_P (operands[2])
4880 && FP_REGNO_P (REGNO (operands[3]))"
4881 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4883 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4887 [(set (match_operand:DI 0 "register_operand" "")
4888 (plus:DI (match_operand:DI 1 "register_operand" "")
4889 (match_operand:DI 2 "register_operand" "")))
4890 (set (mem:SF (match_dup 0))
4891 (match_operand:SF 3 "register_operand" ""))]
4893 && !TARGET_DISABLE_INDEXING
4895 && TARGET_NO_SPACE_REGS
4896 && REG_OK_FOR_INDEX_P (operands[1])
4897 && REG_OK_FOR_BASE_P (operands[2])
4898 && FP_REGNO_P (REGNO (operands[3]))"
4899 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4901 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4905 [(set (match_operand:DI 0 "register_operand" "")
4906 (plus:DI (match_operand:DI 1 "register_operand" "")
4907 (match_operand:DI 2 "register_operand" "")))
4908 (set (mem:SF (match_dup 0))
4909 (match_operand:SF 3 "register_operand" ""))]
4911 && !TARGET_DISABLE_INDEXING
4913 && TARGET_NO_SPACE_REGS
4914 && REG_OK_FOR_BASE_P (operands[1])
4915 && REG_OK_FOR_INDEX_P (operands[2])
4916 && FP_REGNO_P (REGNO (operands[3]))"
4917 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4919 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4923 [(set (match_operand:SF 0 "move_dest_operand"
4925 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4927 "(register_operand (operands[0], SFmode)
4928 || reg_or_0_operand (operands[1], SFmode))
4929 && TARGET_SOFT_FLOAT"
4934 [(set_attr "type" "move,load,store")
4935 (set_attr "pa_combine_type" "addmove")
4936 (set_attr "length" "4,4,4")])
4940 ;;- zero extension instructions
4941 ;; We have define_expand for zero extension patterns to make sure the
4942 ;; operands get loaded into registers. The define_insns accept
4943 ;; memory operands. This gives us better overall code than just
4944 ;; having a pattern that does or does not accept memory operands.
4946 (define_expand "zero_extendqihi2"
4947 [(set (match_operand:HI 0 "register_operand" "")
4949 (match_operand:QI 1 "register_operand" "")))]
4954 [(set (match_operand:HI 0 "register_operand" "=r,r")
4956 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4957 "GET_CODE (operands[1]) != CONST_INT"
4959 {extru|extrw,u} %1,31,8,%0
4961 [(set_attr "type" "shift,load")
4962 (set_attr "length" "4,4")])
4964 (define_expand "zero_extendqisi2"
4965 [(set (match_operand:SI 0 "register_operand" "")
4967 (match_operand:QI 1 "register_operand" "")))]
4972 [(set (match_operand:SI 0 "register_operand" "=r,r")
4974 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4975 "GET_CODE (operands[1]) != CONST_INT"
4977 {extru|extrw,u} %1,31,8,%0
4979 [(set_attr "type" "shift,load")
4980 (set_attr "length" "4,4")])
4982 (define_expand "zero_extendhisi2"
4983 [(set (match_operand:SI 0 "register_operand" "")
4985 (match_operand:HI 1 "register_operand" "")))]
4990 [(set (match_operand:SI 0 "register_operand" "=r,r")
4992 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4993 "GET_CODE (operands[1]) != CONST_INT"
4995 {extru|extrw,u} %1,31,16,%0
4997 [(set_attr "type" "shift,load")
4998 (set_attr "length" "4,4")])
5000 (define_expand "zero_extendqidi2"
5001 [(set (match_operand:DI 0 "register_operand" "")
5003 (match_operand:QI 1 "register_operand" "")))]
5008 [(set (match_operand:DI 0 "register_operand" "=r,r")
5010 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
5011 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5015 [(set_attr "type" "shift,load")
5016 (set_attr "length" "4,4")])
5018 (define_expand "zero_extendhidi2"
5019 [(set (match_operand:DI 0 "register_operand" "")
5021 (match_operand:HI 1 "register_operand" "")))]
5026 [(set (match_operand:DI 0 "register_operand" "=r,r")
5028 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
5029 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5033 [(set_attr "type" "shift,load")
5034 (set_attr "length" "4,4")])
5036 (define_expand "zero_extendsidi2"
5037 [(set (match_operand:DI 0 "register_operand" "")
5039 (match_operand:SI 1 "register_operand" "")))]
5044 [(set (match_operand:DI 0 "register_operand" "=r,r")
5046 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
5047 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5051 [(set_attr "type" "shift,load")
5052 (set_attr "length" "4,4")])
5054 ;;- sign extension instructions
5056 (define_insn "extendhisi2"
5057 [(set (match_operand:SI 0 "register_operand" "=r")
5058 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
5060 "{extrs|extrw,s} %1,31,16,%0"
5061 [(set_attr "type" "shift")
5062 (set_attr "length" "4")])
5064 (define_insn "extendqihi2"
5065 [(set (match_operand:HI 0 "register_operand" "=r")
5066 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
5068 "{extrs|extrw,s} %1,31,8,%0"
5069 [(set_attr "type" "shift")
5070 (set_attr "length" "4")])
5072 (define_insn "extendqisi2"
5073 [(set (match_operand:SI 0 "register_operand" "=r")
5074 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
5076 "{extrs|extrw,s} %1,31,8,%0"
5077 [(set_attr "type" "shift")
5078 (set_attr "length" "4")])
5080 (define_insn "extendqidi2"
5081 [(set (match_operand:DI 0 "register_operand" "=r")
5082 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
5084 "extrd,s %1,63,8,%0"
5085 [(set_attr "type" "shift")
5086 (set_attr "length" "4")])
5088 (define_insn "extendhidi2"
5089 [(set (match_operand:DI 0 "register_operand" "=r")
5090 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
5092 "extrd,s %1,63,16,%0"
5093 [(set_attr "type" "shift")
5094 (set_attr "length" "4")])
5096 (define_insn "extendsidi2"
5097 [(set (match_operand:DI 0 "register_operand" "=r")
5098 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
5100 "extrd,s %1,63,32,%0"
5101 [(set_attr "type" "shift")
5102 (set_attr "length" "4")])
5105 ;; Conversions between float and double.
5107 (define_insn "extendsfdf2"
5108 [(set (match_operand:DF 0 "register_operand" "=f")
5110 (match_operand:SF 1 "register_operand" "f")))]
5111 "! TARGET_SOFT_FLOAT"
5112 "{fcnvff|fcnv},sgl,dbl %1,%0"
5113 [(set_attr "type" "fpalu")
5114 (set_attr "length" "4")])
5116 (define_insn "truncdfsf2"
5117 [(set (match_operand:SF 0 "register_operand" "=f")
5119 (match_operand:DF 1 "register_operand" "f")))]
5120 "! TARGET_SOFT_FLOAT"
5121 "{fcnvff|fcnv},dbl,sgl %1,%0"
5122 [(set_attr "type" "fpalu")
5123 (set_attr "length" "4")])
5125 ;; Conversion between fixed point and floating point.
5126 ;; Note that among the fix-to-float insns
5127 ;; the ones that start with SImode come first.
5128 ;; That is so that an operand that is a CONST_INT
5129 ;; (and therefore lacks a specific machine mode).
5130 ;; will be recognized as SImode (which is always valid)
5131 ;; rather than as QImode or HImode.
5133 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
5134 ;; to be reloaded by putting the constant into memory.
5135 ;; It must come before the more general floatsisf2 pattern.
5137 [(set (match_operand:SF 0 "register_operand" "=f")
5138 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
5139 "! TARGET_SOFT_FLOAT"
5140 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
5141 [(set_attr "type" "fpalu")
5142 (set_attr "length" "8")])
5144 (define_insn "floatsisf2"
5145 [(set (match_operand:SF 0 "register_operand" "=f")
5146 (float:SF (match_operand:SI 1 "register_operand" "f")))]
5147 "! TARGET_SOFT_FLOAT"
5148 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
5149 [(set_attr "type" "fpalu")
5150 (set_attr "length" "4")])
5152 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
5153 ;; to be reloaded by putting the constant into memory.
5154 ;; It must come before the more general floatsidf2 pattern.
5156 [(set (match_operand:DF 0 "register_operand" "=f")
5157 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
5158 "! TARGET_SOFT_FLOAT"
5159 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
5160 [(set_attr "type" "fpalu")
5161 (set_attr "length" "8")])
5163 (define_insn "floatsidf2"
5164 [(set (match_operand:DF 0 "register_operand" "=f")
5165 (float:DF (match_operand:SI 1 "register_operand" "f")))]
5166 "! TARGET_SOFT_FLOAT"
5167 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
5168 [(set_attr "type" "fpalu")
5169 (set_attr "length" "4")])
5171 (define_expand "floatunssisf2"
5172 [(set (subreg:SI (match_dup 2) 4)
5173 (match_operand:SI 1 "register_operand" ""))
5174 (set (subreg:SI (match_dup 2) 0)
5176 (set (match_operand:SF 0 "register_operand" "")
5177 (float:SF (match_dup 2)))]
5178 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5183 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
5186 operands[2] = gen_reg_rtx (DImode);
5189 (define_expand "floatunssidf2"
5190 [(set (subreg:SI (match_dup 2) 4)
5191 (match_operand:SI 1 "register_operand" ""))
5192 (set (subreg:SI (match_dup 2) 0)
5194 (set (match_operand:DF 0 "register_operand" "")
5195 (float:DF (match_dup 2)))]
5196 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5201 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
5204 operands[2] = gen_reg_rtx (DImode);
5207 (define_insn "floatdisf2"
5208 [(set (match_operand:SF 0 "register_operand" "=f")
5209 (float:SF (match_operand:DI 1 "register_operand" "f")))]
5210 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5211 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
5212 [(set_attr "type" "fpalu")
5213 (set_attr "length" "4")])
5215 (define_insn "floatdidf2"
5216 [(set (match_operand:DF 0 "register_operand" "=f")
5217 (float:DF (match_operand:DI 1 "register_operand" "f")))]
5218 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5219 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
5220 [(set_attr "type" "fpalu")
5221 (set_attr "length" "4")])
5223 ;; Convert a float to an actual integer.
5224 ;; Truncation is performed as part of the conversion.
5226 (define_insn "fix_truncsfsi2"
5227 [(set (match_operand:SI 0 "register_operand" "=f")
5228 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5229 "! TARGET_SOFT_FLOAT"
5230 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
5231 [(set_attr "type" "fpalu")
5232 (set_attr "length" "4")])
5234 (define_insn "fix_truncdfsi2"
5235 [(set (match_operand:SI 0 "register_operand" "=f")
5236 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5237 "! TARGET_SOFT_FLOAT"
5238 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
5239 [(set_attr "type" "fpalu")
5240 (set_attr "length" "4")])
5242 (define_insn "fix_truncsfdi2"
5243 [(set (match_operand:DI 0 "register_operand" "=f")
5244 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5245 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5246 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
5247 [(set_attr "type" "fpalu")
5248 (set_attr "length" "4")])
5250 (define_insn "fix_truncdfdi2"
5251 [(set (match_operand:DI 0 "register_operand" "=f")
5252 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5253 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5254 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
5255 [(set_attr "type" "fpalu")
5256 (set_attr "length" "4")])
5258 (define_insn "floatunssidf2_pa20"
5259 [(set (match_operand:DF 0 "register_operand" "=f")
5260 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
5261 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5263 [(set_attr "type" "fpalu")
5264 (set_attr "length" "4")])
5266 (define_insn "floatunssisf2_pa20"
5267 [(set (match_operand:SF 0 "register_operand" "=f")
5268 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
5269 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5271 [(set_attr "type" "fpalu")
5272 (set_attr "length" "4")])
5274 (define_insn "floatunsdisf2"
5275 [(set (match_operand:SF 0 "register_operand" "=f")
5276 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
5277 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5278 "fcnv,udw,sgl %1,%0"
5279 [(set_attr "type" "fpalu")
5280 (set_attr "length" "4")])
5282 (define_insn "floatunsdidf2"
5283 [(set (match_operand:DF 0 "register_operand" "=f")
5284 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
5285 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5286 "fcnv,udw,dbl %1,%0"
5287 [(set_attr "type" "fpalu")
5288 (set_attr "length" "4")])
5290 (define_insn "fixuns_truncsfsi2"
5291 [(set (match_operand:SI 0 "register_operand" "=f")
5292 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5293 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5294 "fcnv,t,sgl,uw %1,%0"
5295 [(set_attr "type" "fpalu")
5296 (set_attr "length" "4")])
5298 (define_insn "fixuns_truncdfsi2"
5299 [(set (match_operand:SI 0 "register_operand" "=f")
5300 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5301 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5302 "fcnv,t,dbl,uw %1,%0"
5303 [(set_attr "type" "fpalu")
5304 (set_attr "length" "4")])
5306 (define_insn "fixuns_truncsfdi2"
5307 [(set (match_operand:DI 0 "register_operand" "=f")
5308 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5309 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5310 "fcnv,t,sgl,udw %1,%0"
5311 [(set_attr "type" "fpalu")
5312 (set_attr "length" "4")])
5314 (define_insn "fixuns_truncdfdi2"
5315 [(set (match_operand:DI 0 "register_operand" "=f")
5316 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5317 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5318 "fcnv,t,dbl,udw %1,%0"
5319 [(set_attr "type" "fpalu")
5320 (set_attr "length" "4")])
5322 ;;- arithmetic instructions
5324 (define_expand "adddi3"
5325 [(set (match_operand:DI 0 "register_operand" "")
5326 (plus:DI (match_operand:DI 1 "register_operand" "")
5327 (match_operand:DI 2 "adddi3_operand" "")))]
5332 [(set (match_operand:DI 0 "register_operand" "=r")
5333 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5334 (match_operand:DI 2 "arith11_operand" "rI")))]
5338 if (GET_CODE (operands[2]) == CONST_INT)
5340 if (INTVAL (operands[2]) >= 0)
5341 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5343 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5346 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5348 [(set_attr "type" "binary")
5349 (set_attr "length" "8")])
5352 [(set (match_operand:DI 0 "register_operand" "=r,r")
5353 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5354 (match_operand:DI 2 "arith_operand" "r,J")))]
5359 [(set_attr "type" "binary,binary")
5360 (set_attr "pa_combine_type" "addmove")
5361 (set_attr "length" "4,4")])
5364 [(set (match_operand:DI 0 "register_operand" "=r")
5365 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5366 (match_operand:DI 2 "register_operand" "r")))]
5369 [(set_attr "type" "binary")
5370 (set_attr "length" "4")])
5373 [(set (match_operand:SI 0 "register_operand" "=r")
5374 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5375 (match_operand:SI 2 "register_operand" "r")))]
5378 [(set_attr "type" "binary")
5379 (set_attr "length" "4")])
5381 (define_expand "addvdi3"
5382 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5383 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
5384 (match_operand:DI 2 "arith11_operand" "")))
5385 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5386 (sign_extend:TI (match_dup 2)))
5387 (sign_extend:TI (plus:DI (match_dup 1)
5394 [(set (match_operand:DI 0 "register_operand" "=r,r")
5395 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
5396 (match_operand:DI 2 "arith11_operand" "r,I")))
5397 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5398 (sign_extend:TI (match_dup 2)))
5399 (sign_extend:TI (plus:DI (match_dup 1)
5405 addi,tsv,* %2,%1,%0"
5406 [(set_attr "type" "binary,binary")
5407 (set_attr "length" "4,4")])
5410 [(set (match_operand:DI 0 "register_operand" "=r")
5411 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5412 (match_operand:DI 2 "arith11_operand" "rI")))
5413 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5414 (sign_extend:TI (match_dup 2)))
5415 (sign_extend:TI (plus:DI (match_dup 1)
5421 if (GET_CODE (operands[2]) == CONST_INT)
5423 if (INTVAL (operands[2]) >= 0)
5424 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5426 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5429 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5431 [(set_attr "type" "binary")
5432 (set_attr "length" "8")])
5434 ;; define_splits to optimize cases of adding a constant integer
5435 ;; to a register when the constant does not fit in 14 bits. */
5437 [(set (match_operand:SI 0 "register_operand" "")
5438 (plus:SI (match_operand:SI 1 "register_operand" "")
5439 (match_operand:SI 2 "const_int_operand" "")))
5440 (clobber (match_operand:SI 4 "register_operand" ""))]
5441 "! cint_ok_for_move (INTVAL (operands[2]))
5442 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5443 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5444 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5447 int val = INTVAL (operands[2]);
5448 int low = (val < 0) ? -0x2000 : 0x1fff;
5449 int rest = val - low;
5451 operands[2] = GEN_INT (rest);
5452 operands[3] = GEN_INT (low);
5456 [(set (match_operand:SI 0 "register_operand" "")
5457 (plus:SI (match_operand:SI 1 "register_operand" "")
5458 (match_operand:SI 2 "const_int_operand" "")))
5459 (clobber (match_operand:SI 4 "register_operand" ""))]
5460 "! cint_ok_for_move (INTVAL (operands[2]))"
5461 [(set (match_dup 4) (match_dup 2))
5462 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5466 HOST_WIDE_INT intval = INTVAL (operands[2]);
5468 /* Try dividing the constant by 2, then 4, and finally 8 to see
5469 if we can get a constant which can be loaded into a register
5470 in a single instruction (cint_ok_for_move).
5472 If that fails, try to negate the constant and subtract it
5473 from our input operand. */
5474 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5476 operands[2] = GEN_INT (intval / 2);
5477 operands[3] = const2_rtx;
5479 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5481 operands[2] = GEN_INT (intval / 4);
5482 operands[3] = GEN_INT (4);
5484 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5486 operands[2] = GEN_INT (intval / 8);
5487 operands[3] = GEN_INT (8);
5489 else if (cint_ok_for_move (-intval))
5491 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5492 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5499 (define_insn "addsi3"
5500 [(set (match_operand:SI 0 "register_operand" "=r,r")
5501 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5502 (match_operand:SI 2 "arith_operand" "r,J")))]
5505 {addl|add,l} %1,%2,%0
5507 [(set_attr "type" "binary,binary")
5508 (set_attr "pa_combine_type" "addmove")
5509 (set_attr "length" "4,4")])
5511 (define_insn "addvsi3"
5512 [(set (match_operand:SI 0 "register_operand" "=r,r")
5513 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5514 (match_operand:SI 2 "arith11_operand" "r,I")))
5515 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5516 (sign_extend:DI (match_dup 2)))
5517 (sign_extend:DI (plus:SI (match_dup 1)
5522 {addo|add,tsv} %2,%1,%0
5523 {addio|addi,tsv} %2,%1,%0"
5524 [(set_attr "type" "binary,binary")
5525 (set_attr "length" "4,4")])
5527 (define_expand "subdi3"
5528 [(set (match_operand:DI 0 "register_operand" "")
5529 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5530 (match_operand:DI 2 "reg_or_0_operand" "")))]
5535 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5536 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5537 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5543 [(set_attr "type" "binary,binary,move")
5544 (set_attr "length" "4,4,4")])
5547 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5548 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5549 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5553 if (GET_CODE (operands[1]) == CONST_INT)
5555 if (INTVAL (operands[1]) >= 0)
5556 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5558 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5561 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5563 [(set_attr "type" "binary")
5564 (set (attr "length")
5565 (if_then_else (eq_attr "alternative" "0")
5567 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5572 (define_expand "subvdi3"
5573 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5574 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5575 (match_operand:DI 2 "reg_or_0_operand" "")))
5576 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5577 (sign_extend:TI (match_dup 2)))
5578 (sign_extend:TI (minus:DI (match_dup 1)
5585 [(set (match_operand:DI 0 "register_operand" "=r,r")
5586 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5587 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5588 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5589 (sign_extend:TI (match_dup 2)))
5590 (sign_extend:TI (minus:DI (match_dup 1)
5595 {subo|sub,tsv} %1,%2,%0
5596 {subio|subi,tsv} %1,%2,%0"
5597 [(set_attr "type" "binary,binary")
5598 (set_attr "length" "4,4")])
5601 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5602 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5603 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5604 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5605 (sign_extend:TI (match_dup 2)))
5606 (sign_extend:TI (minus:DI (match_dup 1)
5612 if (GET_CODE (operands[1]) == CONST_INT)
5614 if (INTVAL (operands[1]) >= 0)
5615 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5617 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5620 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5622 [(set_attr "type" "binary,binary")
5623 (set (attr "length")
5624 (if_then_else (eq_attr "alternative" "0")
5626 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5631 (define_expand "subsi3"
5632 [(set (match_operand:SI 0 "register_operand" "")
5633 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5634 (match_operand:SI 2 "register_operand" "")))]
5639 [(set (match_operand:SI 0 "register_operand" "=r,r")
5640 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5641 (match_operand:SI 2 "register_operand" "r,r")))]
5646 [(set_attr "type" "binary,binary")
5647 (set_attr "length" "4,4")])
5650 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5651 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5652 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5658 [(set_attr "type" "binary,binary,move")
5659 (set_attr "length" "4,4,4")])
5661 (define_insn "subvsi3"
5662 [(set (match_operand:SI 0 "register_operand" "=r,r")
5663 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5664 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5665 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5666 (sign_extend:DI (match_dup 2)))
5667 (sign_extend:DI (minus:SI (match_dup 1)
5672 {subo|sub,tsv} %1,%2,%0
5673 {subio|subi,tsv} %1,%2,%0"
5674 [(set_attr "type" "binary,binary")
5675 (set_attr "length" "4,4")])
5677 ;; Clobbering a "register_operand" instead of a match_scratch
5678 ;; in operand3 of millicode calls avoids spilling %r1 and
5679 ;; produces better code.
5681 ;; The mulsi3 insns set up registers for the millicode call.
5682 (define_expand "mulsi3"
5683 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5684 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5685 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5686 (clobber (match_dup 3))
5687 (clobber (reg:SI 26))
5688 (clobber (reg:SI 25))
5689 (clobber (match_dup 4))])
5690 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5694 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5695 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5697 rtx scratch = gen_reg_rtx (DImode);
5698 operands[1] = force_reg (SImode, operands[1]);
5699 operands[2] = force_reg (SImode, operands[2]);
5700 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5701 emit_insn (gen_movsi (operands[0],
5702 gen_rtx_SUBREG (SImode, scratch,
5703 GET_MODE_SIZE (SImode))));
5706 operands[3] = gen_reg_rtx (SImode);
5709 (define_insn "umulsidi3"
5710 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5711 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5712 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5713 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5715 [(set_attr "type" "fpmuldbl")
5716 (set_attr "length" "4")])
5719 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5720 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5721 (match_operand:DI 2 "uint32_operand" "f")))]
5722 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5724 [(set_attr "type" "fpmuldbl")
5725 (set_attr "length" "4")])
5728 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5729 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5730 (match_operand:DI 2 "uint32_operand" "f")))]
5731 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5733 [(set_attr "type" "fpmuldbl")
5734 (set_attr "length" "4")])
5737 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5738 (clobber (match_operand:SI 0 "register_operand" "=a"))
5739 (clobber (reg:SI 26))
5740 (clobber (reg:SI 25))
5741 (clobber (reg:SI 31))]
5743 "* return output_mul_insn (0, insn);"
5744 [(set_attr "type" "milli")
5745 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5748 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5749 (clobber (match_operand:SI 0 "register_operand" "=a"))
5750 (clobber (reg:SI 26))
5751 (clobber (reg:SI 25))
5752 (clobber (reg:SI 2))]
5754 "* return output_mul_insn (0, insn);"
5755 [(set_attr "type" "milli")
5756 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5758 (define_expand "muldi3"
5759 [(set (match_operand:DI 0 "register_operand" "")
5760 (mult:DI (match_operand:DI 1 "register_operand" "")
5761 (match_operand:DI 2 "register_operand" "")))]
5762 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5765 rtx low_product = gen_reg_rtx (DImode);
5766 rtx cross_product1 = gen_reg_rtx (DImode);
5767 rtx cross_product2 = gen_reg_rtx (DImode);
5768 rtx cross_scratch = gen_reg_rtx (DImode);
5769 rtx cross_product = gen_reg_rtx (DImode);
5770 rtx op1l, op1r, op2l, op2r;
5771 rtx op1shifted, op2shifted;
5773 op1shifted = gen_reg_rtx (DImode);
5774 op2shifted = gen_reg_rtx (DImode);
5775 op1l = gen_reg_rtx (SImode);
5776 op1r = gen_reg_rtx (SImode);
5777 op2l = gen_reg_rtx (SImode);
5778 op2r = gen_reg_rtx (SImode);
5780 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5782 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5784 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5785 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5786 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5787 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5789 /* Emit multiplies for the cross products. */
5790 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5791 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5793 /* Emit a multiply for the low sub-word. */
5794 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5796 /* Sum the cross products and shift them into proper position. */
5797 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5798 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5800 /* Add the cross product to the low product and store the result
5801 into the output operand . */
5802 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5806 ;;; Division and mod.
5807 (define_expand "divsi3"
5808 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5809 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5810 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5811 (clobber (match_dup 3))
5812 (clobber (match_dup 4))
5813 (clobber (reg:SI 26))
5814 (clobber (reg:SI 25))
5815 (clobber (match_dup 5))])
5816 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5820 operands[3] = gen_reg_rtx (SImode);
5823 operands[5] = gen_rtx_REG (SImode, 2);
5824 operands[4] = operands[5];
5828 operands[5] = gen_rtx_REG (SImode, 31);
5829 operands[4] = gen_reg_rtx (SImode);
5831 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5837 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5838 (clobber (match_operand:SI 1 "register_operand" "=a"))
5839 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5840 (clobber (reg:SI 26))
5841 (clobber (reg:SI 25))
5842 (clobber (reg:SI 31))]
5845 return output_div_insn (operands, 0, insn);"
5846 [(set_attr "type" "milli")
5847 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5851 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5852 (clobber (match_operand:SI 1 "register_operand" "=a"))
5853 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5854 (clobber (reg:SI 26))
5855 (clobber (reg:SI 25))
5856 (clobber (reg:SI 2))]
5859 return output_div_insn (operands, 0, insn);"
5860 [(set_attr "type" "milli")
5861 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5863 (define_expand "udivsi3"
5864 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5865 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5866 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5867 (clobber (match_dup 3))
5868 (clobber (match_dup 4))
5869 (clobber (reg:SI 26))
5870 (clobber (reg:SI 25))
5871 (clobber (match_dup 5))])
5872 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5876 operands[3] = gen_reg_rtx (SImode);
5880 operands[5] = gen_rtx_REG (SImode, 2);
5881 operands[4] = operands[5];
5885 operands[5] = gen_rtx_REG (SImode, 31);
5886 operands[4] = gen_reg_rtx (SImode);
5888 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5894 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5895 (clobber (match_operand:SI 1 "register_operand" "=a"))
5896 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5897 (clobber (reg:SI 26))
5898 (clobber (reg:SI 25))
5899 (clobber (reg:SI 31))]
5902 return output_div_insn (operands, 1, insn);"
5903 [(set_attr "type" "milli")
5904 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5908 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5909 (clobber (match_operand:SI 1 "register_operand" "=a"))
5910 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5911 (clobber (reg:SI 26))
5912 (clobber (reg:SI 25))
5913 (clobber (reg:SI 2))]
5916 return output_div_insn (operands, 1, insn);"
5917 [(set_attr "type" "milli")
5918 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5920 (define_expand "modsi3"
5921 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5922 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5923 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5924 (clobber (match_dup 3))
5925 (clobber (match_dup 4))
5926 (clobber (reg:SI 26))
5927 (clobber (reg:SI 25))
5928 (clobber (match_dup 5))])
5929 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5935 operands[5] = gen_rtx_REG (SImode, 2);
5936 operands[4] = operands[5];
5940 operands[5] = gen_rtx_REG (SImode, 31);
5941 operands[4] = gen_reg_rtx (SImode);
5943 operands[3] = gen_reg_rtx (SImode);
5947 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5948 (clobber (match_operand:SI 0 "register_operand" "=a"))
5949 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5950 (clobber (reg:SI 26))
5951 (clobber (reg:SI 25))
5952 (clobber (reg:SI 31))]
5955 return output_mod_insn (0, insn);"
5956 [(set_attr "type" "milli")
5957 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5960 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5961 (clobber (match_operand:SI 0 "register_operand" "=a"))
5962 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5963 (clobber (reg:SI 26))
5964 (clobber (reg:SI 25))
5965 (clobber (reg:SI 2))]
5968 return output_mod_insn (0, insn);"
5969 [(set_attr "type" "milli")
5970 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5972 (define_expand "umodsi3"
5973 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5974 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5975 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5976 (clobber (match_dup 3))
5977 (clobber (match_dup 4))
5978 (clobber (reg:SI 26))
5979 (clobber (reg:SI 25))
5980 (clobber (match_dup 5))])
5981 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5987 operands[5] = gen_rtx_REG (SImode, 2);
5988 operands[4] = operands[5];
5992 operands[5] = gen_rtx_REG (SImode, 31);
5993 operands[4] = gen_reg_rtx (SImode);
5995 operands[3] = gen_reg_rtx (SImode);
5999 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6000 (clobber (match_operand:SI 0 "register_operand" "=a"))
6001 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6002 (clobber (reg:SI 26))
6003 (clobber (reg:SI 25))
6004 (clobber (reg:SI 31))]
6007 return output_mod_insn (1, insn);"
6008 [(set_attr "type" "milli")
6009 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6012 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6013 (clobber (match_operand:SI 0 "register_operand" "=a"))
6014 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6015 (clobber (reg:SI 26))
6016 (clobber (reg:SI 25))
6017 (clobber (reg:SI 2))]
6020 return output_mod_insn (1, insn);"
6021 [(set_attr "type" "milli")
6022 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6024 ;;- and instructions
6025 ;; We define DImode `and` so with DImode `not` we can get
6026 ;; DImode `andn`. Other combinations are possible.
6028 (define_expand "anddi3"
6029 [(set (match_operand:DI 0 "register_operand" "")
6030 (and:DI (match_operand:DI 1 "register_operand" "")
6031 (match_operand:DI 2 "and_operand" "")))]
6035 /* Both operands must be register operands. */
6036 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6041 [(set (match_operand:DI 0 "register_operand" "=r")
6042 (and:DI (match_operand:DI 1 "register_operand" "%r")
6043 (match_operand:DI 2 "register_operand" "r")))]
6045 "and %1,%2,%0\;and %R1,%R2,%R0"
6046 [(set_attr "type" "binary")
6047 (set_attr "length" "8")])
6050 [(set (match_operand:DI 0 "register_operand" "=r,r")
6051 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
6052 (match_operand:DI 2 "and_operand" "rO,P")))]
6054 "* return output_64bit_and (operands); "
6055 [(set_attr "type" "binary")
6056 (set_attr "length" "4")])
6058 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
6059 ; constant with ldil;ldo.
6060 (define_insn "andsi3"
6061 [(set (match_operand:SI 0 "register_operand" "=r,r")
6062 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
6063 (match_operand:SI 2 "and_operand" "rO,P")))]
6065 "* return output_and (operands); "
6066 [(set_attr "type" "binary,shift")
6067 (set_attr "length" "4,4")])
6070 [(set (match_operand:DI 0 "register_operand" "=r")
6071 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6072 (match_operand:DI 2 "register_operand" "r")))]
6074 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
6075 [(set_attr "type" "binary")
6076 (set_attr "length" "8")])
6079 [(set (match_operand:DI 0 "register_operand" "=r")
6080 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6081 (match_operand:DI 2 "register_operand" "r")))]
6084 [(set_attr "type" "binary")
6085 (set_attr "length" "4")])
6088 [(set (match_operand:SI 0 "register_operand" "=r")
6089 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
6090 (match_operand:SI 2 "register_operand" "r")))]
6093 [(set_attr "type" "binary")
6094 (set_attr "length" "4")])
6096 (define_expand "iordi3"
6097 [(set (match_operand:DI 0 "register_operand" "")
6098 (ior:DI (match_operand:DI 1 "register_operand" "")
6099 (match_operand:DI 2 "ior_operand" "")))]
6103 /* Both operands must be register operands. */
6104 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6109 [(set (match_operand:DI 0 "register_operand" "=r")
6110 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6111 (match_operand:DI 2 "register_operand" "r")))]
6113 "or %1,%2,%0\;or %R1,%R2,%R0"
6114 [(set_attr "type" "binary")
6115 (set_attr "length" "8")])
6118 [(set (match_operand:DI 0 "register_operand" "=r,r")
6119 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
6120 (match_operand:DI 2 "ior_operand" "M,i")))]
6122 "* return output_64bit_ior (operands); "
6123 [(set_attr "type" "binary,shift")
6124 (set_attr "length" "4,4")])
6127 [(set (match_operand:DI 0 "register_operand" "=r")
6128 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6129 (match_operand:DI 2 "register_operand" "r")))]
6132 [(set_attr "type" "binary")
6133 (set_attr "length" "4")])
6135 ;; Need a define_expand because we've run out of CONST_OK... characters.
6136 (define_expand "iorsi3"
6137 [(set (match_operand:SI 0 "register_operand" "")
6138 (ior:SI (match_operand:SI 1 "register_operand" "")
6139 (match_operand:SI 2 "arith32_operand" "")))]
6143 if (! (ior_operand (operands[2], SImode)
6144 || register_operand (operands[2], SImode)))
6145 operands[2] = force_reg (SImode, operands[2]);
6149 [(set (match_operand:SI 0 "register_operand" "=r,r")
6150 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
6151 (match_operand:SI 2 "ior_operand" "M,i")))]
6153 "* return output_ior (operands); "
6154 [(set_attr "type" "binary,shift")
6155 (set_attr "length" "4,4")])
6158 [(set (match_operand:SI 0 "register_operand" "=r")
6159 (ior:SI (match_operand:SI 1 "register_operand" "%r")
6160 (match_operand:SI 2 "register_operand" "r")))]
6163 [(set_attr "type" "binary")
6164 (set_attr "length" "4")])
6166 (define_expand "xordi3"
6167 [(set (match_operand:DI 0 "register_operand" "")
6168 (xor:DI (match_operand:DI 1 "register_operand" "")
6169 (match_operand:DI 2 "register_operand" "")))]
6176 [(set (match_operand:DI 0 "register_operand" "=r")
6177 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6178 (match_operand:DI 2 "register_operand" "r")))]
6180 "xor %1,%2,%0\;xor %R1,%R2,%R0"
6181 [(set_attr "type" "binary")
6182 (set_attr "length" "8")])
6185 [(set (match_operand:DI 0 "register_operand" "=r")
6186 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6187 (match_operand:DI 2 "register_operand" "r")))]
6190 [(set_attr "type" "binary")
6191 (set_attr "length" "4")])
6193 (define_insn "xorsi3"
6194 [(set (match_operand:SI 0 "register_operand" "=r")
6195 (xor:SI (match_operand:SI 1 "register_operand" "%r")
6196 (match_operand:SI 2 "register_operand" "r")))]
6199 [(set_attr "type" "binary")
6200 (set_attr "length" "4")])
6202 (define_expand "negdi2"
6203 [(set (match_operand:DI 0 "register_operand" "")
6204 (neg:DI (match_operand:DI 1 "register_operand" "")))]
6209 [(set (match_operand:DI 0 "register_operand" "=r")
6210 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6212 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
6213 [(set_attr "type" "unary")
6214 (set_attr "length" "8")])
6217 [(set (match_operand:DI 0 "register_operand" "=r")
6218 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6221 [(set_attr "type" "unary")
6222 (set_attr "length" "4")])
6224 (define_expand "negvdi2"
6225 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6226 (neg:DI (match_operand:DI 1 "register_operand" "")))
6227 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6228 (sign_extend:TI (neg:DI (match_dup 1))))
6234 [(set (match_operand:DI 0 "register_operand" "=r")
6235 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6236 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6237 (sign_extend:TI (neg:DI (match_dup 1))))
6240 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
6241 [(set_attr "type" "unary")
6242 (set_attr "length" "8")])
6245 [(set (match_operand:DI 0 "register_operand" "=r")
6246 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6247 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6248 (sign_extend:TI (neg:DI (match_dup 1))))
6251 "sub,tsv %%r0,%1,%0"
6252 [(set_attr "type" "unary")
6253 (set_attr "length" "4")])
6255 (define_insn "negsi2"
6256 [(set (match_operand:SI 0 "register_operand" "=r")
6257 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
6260 [(set_attr "type" "unary")
6261 (set_attr "length" "4")])
6263 (define_insn "negvsi2"
6264 [(set (match_operand:SI 0 "register_operand" "=r")
6265 (neg:SI (match_operand:SI 1 "register_operand" "r")))
6266 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
6267 (sign_extend:DI (neg:SI (match_dup 1))))
6270 "{subo|sub,tsv} %%r0,%1,%0"
6271 [(set_attr "type" "unary")
6272 (set_attr "length" "4")])
6274 (define_expand "one_cmpldi2"
6275 [(set (match_operand:DI 0 "register_operand" "")
6276 (not:DI (match_operand:DI 1 "register_operand" "")))]
6283 [(set (match_operand:DI 0 "register_operand" "=r")
6284 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6286 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
6287 [(set_attr "type" "unary")
6288 (set_attr "length" "8")])
6291 [(set (match_operand:DI 0 "register_operand" "=r")
6292 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6295 [(set_attr "type" "unary")
6296 (set_attr "length" "4")])
6298 (define_insn "one_cmplsi2"
6299 [(set (match_operand:SI 0 "register_operand" "=r")
6300 (not:SI (match_operand:SI 1 "register_operand" "r")))]
6303 [(set_attr "type" "unary")
6304 (set_attr "length" "4")])
6306 ;; Floating point arithmetic instructions.
6308 (define_insn "adddf3"
6309 [(set (match_operand:DF 0 "register_operand" "=f")
6310 (plus:DF (match_operand:DF 1 "register_operand" "f")
6311 (match_operand:DF 2 "register_operand" "f")))]
6312 "! TARGET_SOFT_FLOAT"
6314 [(set_attr "type" "fpalu")
6315 (set_attr "pa_combine_type" "faddsub")
6316 (set_attr "length" "4")])
6318 (define_insn "addsf3"
6319 [(set (match_operand:SF 0 "register_operand" "=f")
6320 (plus:SF (match_operand:SF 1 "register_operand" "f")
6321 (match_operand:SF 2 "register_operand" "f")))]
6322 "! TARGET_SOFT_FLOAT"
6324 [(set_attr "type" "fpalu")
6325 (set_attr "pa_combine_type" "faddsub")
6326 (set_attr "length" "4")])
6328 (define_insn "subdf3"
6329 [(set (match_operand:DF 0 "register_operand" "=f")
6330 (minus:DF (match_operand:DF 1 "register_operand" "f")
6331 (match_operand:DF 2 "register_operand" "f")))]
6332 "! TARGET_SOFT_FLOAT"
6334 [(set_attr "type" "fpalu")
6335 (set_attr "pa_combine_type" "faddsub")
6336 (set_attr "length" "4")])
6338 (define_insn "subsf3"
6339 [(set (match_operand:SF 0 "register_operand" "=f")
6340 (minus:SF (match_operand:SF 1 "register_operand" "f")
6341 (match_operand:SF 2 "register_operand" "f")))]
6342 "! TARGET_SOFT_FLOAT"
6344 [(set_attr "type" "fpalu")
6345 (set_attr "pa_combine_type" "faddsub")
6346 (set_attr "length" "4")])
6348 (define_insn "muldf3"
6349 [(set (match_operand:DF 0 "register_operand" "=f")
6350 (mult:DF (match_operand:DF 1 "register_operand" "f")
6351 (match_operand:DF 2 "register_operand" "f")))]
6352 "! TARGET_SOFT_FLOAT"
6354 [(set_attr "type" "fpmuldbl")
6355 (set_attr "pa_combine_type" "fmpy")
6356 (set_attr "length" "4")])
6358 (define_insn "mulsf3"
6359 [(set (match_operand:SF 0 "register_operand" "=f")
6360 (mult:SF (match_operand:SF 1 "register_operand" "f")
6361 (match_operand:SF 2 "register_operand" "f")))]
6362 "! TARGET_SOFT_FLOAT"
6364 [(set_attr "type" "fpmulsgl")
6365 (set_attr "pa_combine_type" "fmpy")
6366 (set_attr "length" "4")])
6368 (define_insn "divdf3"
6369 [(set (match_operand:DF 0 "register_operand" "=f")
6370 (div:DF (match_operand:DF 1 "register_operand" "f")
6371 (match_operand:DF 2 "register_operand" "f")))]
6372 "! TARGET_SOFT_FLOAT"
6374 [(set_attr "type" "fpdivdbl")
6375 (set_attr "length" "4")])
6377 (define_insn "divsf3"
6378 [(set (match_operand:SF 0 "register_operand" "=f")
6379 (div:SF (match_operand:SF 1 "register_operand" "f")
6380 (match_operand:SF 2 "register_operand" "f")))]
6381 "! TARGET_SOFT_FLOAT"
6383 [(set_attr "type" "fpdivsgl")
6384 (set_attr "length" "4")])
6386 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6387 ;; negation can be done by subtracting from plus zero. However, this
6388 ;; violates the IEEE standard when negating plus and minus zero.
6389 (define_expand "negdf2"
6390 [(parallel [(set (match_operand:DF 0 "register_operand" "")
6391 (neg:DF (match_operand:DF 1 "register_operand" "")))
6392 (use (match_dup 2))])]
6393 "! TARGET_SOFT_FLOAT"
6395 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6396 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6399 operands[2] = force_reg (DFmode,
6400 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
6401 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
6406 (define_insn "negdf2_fast"
6407 [(set (match_operand:DF 0 "register_operand" "=f")
6408 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6409 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6413 return \"fneg,dbl %1,%0\";
6415 return \"fsub,dbl %%fr0,%1,%0\";
6417 [(set_attr "type" "fpalu")
6418 (set_attr "length" "4")])
6420 (define_expand "negsf2"
6421 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6422 (neg:SF (match_operand:SF 1 "register_operand" "")))
6423 (use (match_dup 2))])]
6424 "! TARGET_SOFT_FLOAT"
6426 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6427 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6430 operands[2] = force_reg (SFmode,
6431 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6432 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6437 (define_insn "negsf2_fast"
6438 [(set (match_operand:SF 0 "register_operand" "=f")
6439 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6440 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6444 return \"fneg,sgl %1,%0\";
6446 return \"fsub,sgl %%fr0,%1,%0\";
6448 [(set_attr "type" "fpalu")
6449 (set_attr "length" "4")])
6451 (define_insn "absdf2"
6452 [(set (match_operand:DF 0 "register_operand" "=f")
6453 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6454 "! TARGET_SOFT_FLOAT"
6456 [(set_attr "type" "fpalu")
6457 (set_attr "length" "4")])
6459 (define_insn "abssf2"
6460 [(set (match_operand:SF 0 "register_operand" "=f")
6461 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6462 "! TARGET_SOFT_FLOAT"
6464 [(set_attr "type" "fpalu")
6465 (set_attr "length" "4")])
6467 (define_insn "sqrtdf2"
6468 [(set (match_operand:DF 0 "register_operand" "=f")
6469 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6470 "! TARGET_SOFT_FLOAT"
6472 [(set_attr "type" "fpsqrtdbl")
6473 (set_attr "length" "4")])
6475 (define_insn "sqrtsf2"
6476 [(set (match_operand:SF 0 "register_operand" "=f")
6477 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6478 "! TARGET_SOFT_FLOAT"
6480 [(set_attr "type" "fpsqrtsgl")
6481 (set_attr "length" "4")])
6483 ;; PA 2.0 floating point instructions
6487 [(set (match_operand:DF 0 "register_operand" "=f")
6488 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6489 (match_operand:DF 2 "register_operand" "f"))
6490 (match_operand:DF 3 "register_operand" "f")))]
6491 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6492 "fmpyfadd,dbl %1,%2,%3,%0"
6493 [(set_attr "type" "fpmuldbl")
6494 (set_attr "length" "4")])
6497 [(set (match_operand:DF 0 "register_operand" "=f")
6498 (plus:DF (match_operand:DF 1 "register_operand" "f")
6499 (mult:DF (match_operand:DF 2 "register_operand" "f")
6500 (match_operand:DF 3 "register_operand" "f"))))]
6501 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6502 "fmpyfadd,dbl %2,%3,%1,%0"
6503 [(set_attr "type" "fpmuldbl")
6504 (set_attr "length" "4")])
6507 [(set (match_operand:SF 0 "register_operand" "=f")
6508 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6509 (match_operand:SF 2 "register_operand" "f"))
6510 (match_operand:SF 3 "register_operand" "f")))]
6511 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6512 "fmpyfadd,sgl %1,%2,%3,%0"
6513 [(set_attr "type" "fpmulsgl")
6514 (set_attr "length" "4")])
6517 [(set (match_operand:SF 0 "register_operand" "=f")
6518 (plus:SF (match_operand:SF 1 "register_operand" "f")
6519 (mult:SF (match_operand:SF 2 "register_operand" "f")
6520 (match_operand:SF 3 "register_operand" "f"))))]
6521 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6522 "fmpyfadd,sgl %2,%3,%1,%0"
6523 [(set_attr "type" "fpmulsgl")
6524 (set_attr "length" "4")])
6526 ; fmpynfadd patterns
6528 [(set (match_operand:DF 0 "register_operand" "=f")
6529 (minus:DF (match_operand:DF 1 "register_operand" "f")
6530 (mult:DF (match_operand:DF 2 "register_operand" "f")
6531 (match_operand:DF 3 "register_operand" "f"))))]
6532 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6533 "fmpynfadd,dbl %2,%3,%1,%0"
6534 [(set_attr "type" "fpmuldbl")
6535 (set_attr "length" "4")])
6538 [(set (match_operand:SF 0 "register_operand" "=f")
6539 (minus:SF (match_operand:SF 1 "register_operand" "f")
6540 (mult:SF (match_operand:SF 2 "register_operand" "f")
6541 (match_operand:SF 3 "register_operand" "f"))))]
6542 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6543 "fmpynfadd,sgl %2,%3,%1,%0"
6544 [(set_attr "type" "fpmulsgl")
6545 (set_attr "length" "4")])
6549 [(set (match_operand:DF 0 "register_operand" "=f")
6550 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6551 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6553 [(set_attr "type" "fpalu")
6554 (set_attr "length" "4")])
6557 [(set (match_operand:SF 0 "register_operand" "=f")
6558 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6559 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6561 [(set_attr "type" "fpalu")
6562 (set_attr "length" "4")])
6564 ;; Generating a fused multiply sequence is a win for this case as it will
6565 ;; reduce the latency for the fused case without impacting the plain
6568 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6569 ;; perform two operations with the result of the first feeding the second.
6571 [(set (match_operand:DF 0 "register_operand" "=f")
6572 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6573 (match_operand:DF 2 "register_operand" "f"))
6574 (match_operand:DF 3 "register_operand" "f")))
6575 (set (match_operand:DF 4 "register_operand" "=&f")
6576 (mult:DF (match_dup 1) (match_dup 2)))]
6577 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6578 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6579 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6581 [(set_attr "type" "fpmuldbl")
6582 (set_attr "length" "8")])
6584 ;; We want to split this up during scheduling since we want both insns
6585 ;; to schedule independently.
6587 [(set (match_operand:DF 0 "register_operand" "")
6588 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6589 (match_operand:DF 2 "register_operand" ""))
6590 (match_operand:DF 3 "register_operand" "")))
6591 (set (match_operand:DF 4 "register_operand" "")
6592 (mult:DF (match_dup 1) (match_dup 2)))]
6593 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6594 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6595 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6600 [(set (match_operand:SF 0 "register_operand" "=f")
6601 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6602 (match_operand:SF 2 "register_operand" "f"))
6603 (match_operand:SF 3 "register_operand" "f")))
6604 (set (match_operand:SF 4 "register_operand" "=&f")
6605 (mult:SF (match_dup 1) (match_dup 2)))]
6606 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6607 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6608 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6610 [(set_attr "type" "fpmuldbl")
6611 (set_attr "length" "8")])
6613 ;; We want to split this up during scheduling since we want both insns
6614 ;; to schedule independently.
6616 [(set (match_operand:SF 0 "register_operand" "")
6617 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6618 (match_operand:SF 2 "register_operand" ""))
6619 (match_operand:SF 3 "register_operand" "")))
6620 (set (match_operand:SF 4 "register_operand" "")
6621 (mult:SF (match_dup 1) (match_dup 2)))]
6622 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6623 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6624 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6628 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6631 [(set (match_operand:DF 0 "register_operand" "=f")
6632 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6633 (match_operand:DF 2 "register_operand" "f"))))]
6634 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6635 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6636 [(set_attr "type" "fpmuldbl")
6637 (set_attr "length" "4")])
6640 [(set (match_operand:SF 0 "register_operand" "=f")
6641 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6642 (match_operand:SF 2 "register_operand" "f"))))]
6643 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6644 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6645 [(set_attr "type" "fpmuldbl")
6646 (set_attr "length" "4")])
6649 [(set (match_operand:DF 0 "register_operand" "=f")
6650 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6651 (match_operand:DF 2 "register_operand" "f"))))
6652 (set (match_operand:DF 3 "register_operand" "=&f")
6653 (mult:DF (match_dup 1) (match_dup 2)))]
6654 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6655 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6656 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6658 [(set_attr "type" "fpmuldbl")
6659 (set_attr "length" "8")])
6662 [(set (match_operand:DF 0 "register_operand" "")
6663 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6664 (match_operand:DF 2 "register_operand" ""))))
6665 (set (match_operand:DF 3 "register_operand" "")
6666 (mult:DF (match_dup 1) (match_dup 2)))]
6667 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6668 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6669 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6673 [(set (match_operand:SF 0 "register_operand" "=f")
6674 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6675 (match_operand:SF 2 "register_operand" "f"))))
6676 (set (match_operand:SF 3 "register_operand" "=&f")
6677 (mult:SF (match_dup 1) (match_dup 2)))]
6678 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6679 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6680 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6682 [(set_attr "type" "fpmuldbl")
6683 (set_attr "length" "8")])
6686 [(set (match_operand:SF 0 "register_operand" "")
6687 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6688 (match_operand:SF 2 "register_operand" ""))))
6689 (set (match_operand:SF 3 "register_operand" "")
6690 (mult:SF (match_dup 1) (match_dup 2)))]
6691 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6692 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6693 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6696 ;; Now fused multiplies with the result of the multiply negated.
6698 [(set (match_operand:DF 0 "register_operand" "=f")
6699 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6700 (match_operand:DF 2 "register_operand" "f")))
6701 (match_operand:DF 3 "register_operand" "f")))]
6702 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6703 "fmpynfadd,dbl %1,%2,%3,%0"
6704 [(set_attr "type" "fpmuldbl")
6705 (set_attr "length" "4")])
6708 [(set (match_operand:SF 0 "register_operand" "=f")
6709 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6710 (match_operand:SF 2 "register_operand" "f")))
6711 (match_operand:SF 3 "register_operand" "f")))]
6712 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6713 "fmpynfadd,sgl %1,%2,%3,%0"
6714 [(set_attr "type" "fpmuldbl")
6715 (set_attr "length" "4")])
6718 [(set (match_operand:DF 0 "register_operand" "=f")
6719 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6720 (match_operand:DF 2 "register_operand" "f")))
6721 (match_operand:DF 3 "register_operand" "f")))
6722 (set (match_operand:DF 4 "register_operand" "=&f")
6723 (mult:DF (match_dup 1) (match_dup 2)))]
6724 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6725 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6726 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6728 [(set_attr "type" "fpmuldbl")
6729 (set_attr "length" "8")])
6732 [(set (match_operand:DF 0 "register_operand" "")
6733 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6734 (match_operand:DF 2 "register_operand" "")))
6735 (match_operand:DF 3 "register_operand" "")))
6736 (set (match_operand:DF 4 "register_operand" "")
6737 (mult:DF (match_dup 1) (match_dup 2)))]
6738 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6739 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6740 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6745 [(set (match_operand:SF 0 "register_operand" "=f")
6746 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6747 (match_operand:SF 2 "register_operand" "f")))
6748 (match_operand:SF 3 "register_operand" "f")))
6749 (set (match_operand:SF 4 "register_operand" "=&f")
6750 (mult:SF (match_dup 1) (match_dup 2)))]
6751 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6752 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6753 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6755 [(set_attr "type" "fpmuldbl")
6756 (set_attr "length" "8")])
6759 [(set (match_operand:SF 0 "register_operand" "")
6760 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6761 (match_operand:SF 2 "register_operand" "")))
6762 (match_operand:SF 3 "register_operand" "")))
6763 (set (match_operand:SF 4 "register_operand" "")
6764 (mult:SF (match_dup 1) (match_dup 2)))]
6765 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6766 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6767 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6772 [(set (match_operand:DF 0 "register_operand" "=f")
6773 (minus:DF (match_operand:DF 3 "register_operand" "f")
6774 (mult:DF (match_operand:DF 1 "register_operand" "f")
6775 (match_operand:DF 2 "register_operand" "f"))))
6776 (set (match_operand:DF 4 "register_operand" "=&f")
6777 (mult:DF (match_dup 1) (match_dup 2)))]
6778 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6779 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6780 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6782 [(set_attr "type" "fpmuldbl")
6783 (set_attr "length" "8")])
6786 [(set (match_operand:DF 0 "register_operand" "")
6787 (minus:DF (match_operand:DF 3 "register_operand" "")
6788 (mult:DF (match_operand:DF 1 "register_operand" "")
6789 (match_operand:DF 2 "register_operand" ""))))
6790 (set (match_operand:DF 4 "register_operand" "")
6791 (mult:DF (match_dup 1) (match_dup 2)))]
6792 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6793 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6794 (set (match_dup 0) (minus:DF (match_dup 3)
6795 (mult:DF (match_dup 1) (match_dup 2))))]
6799 [(set (match_operand:SF 0 "register_operand" "=f")
6800 (minus:SF (match_operand:SF 3 "register_operand" "f")
6801 (mult:SF (match_operand:SF 1 "register_operand" "f")
6802 (match_operand:SF 2 "register_operand" "f"))))
6803 (set (match_operand:SF 4 "register_operand" "=&f")
6804 (mult:SF (match_dup 1) (match_dup 2)))]
6805 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6806 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6807 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6809 [(set_attr "type" "fpmuldbl")
6810 (set_attr "length" "8")])
6813 [(set (match_operand:SF 0 "register_operand" "")
6814 (minus:SF (match_operand:SF 3 "register_operand" "")
6815 (mult:SF (match_operand:SF 1 "register_operand" "")
6816 (match_operand:SF 2 "register_operand" ""))))
6817 (set (match_operand:SF 4 "register_operand" "")
6818 (mult:SF (match_dup 1) (match_dup 2)))]
6819 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6820 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6821 (set (match_dup 0) (minus:SF (match_dup 3)
6822 (mult:SF (match_dup 1) (match_dup 2))))]
6826 [(set (match_operand:DF 0 "register_operand" "=f")
6827 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6828 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6829 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6830 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6832 [(set_attr "type" "fpalu")
6833 (set_attr "length" "8")])
6836 [(set (match_operand:DF 0 "register_operand" "")
6837 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6838 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6839 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6840 [(set (match_dup 2) (abs:DF (match_dup 1)))
6841 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6845 [(set (match_operand:SF 0 "register_operand" "=f")
6846 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6847 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6848 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6849 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6851 [(set_attr "type" "fpalu")
6852 (set_attr "length" "8")])
6855 [(set (match_operand:SF 0 "register_operand" "")
6856 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6857 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6858 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6859 [(set (match_dup 2) (abs:SF (match_dup 1)))
6860 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6863 ;;- Shift instructions
6865 ;; Optimized special case of shifting.
6868 [(set (match_operand:SI 0 "register_operand" "=r")
6869 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6873 [(set_attr "type" "load")
6874 (set_attr "length" "4")])
6877 [(set (match_operand:SI 0 "register_operand" "=r")
6878 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6882 [(set_attr "type" "load")
6883 (set_attr "length" "4")])
6886 [(set (match_operand:SI 0 "register_operand" "=r")
6887 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6888 (match_operand:SI 3 "shadd_operand" ""))
6889 (match_operand:SI 1 "register_operand" "r")))]
6891 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6892 [(set_attr "type" "binary")
6893 (set_attr "length" "4")])
6896 [(set (match_operand:DI 0 "register_operand" "=r")
6897 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6898 (match_operand:DI 3 "shadd_operand" ""))
6899 (match_operand:DI 1 "register_operand" "r")))]
6901 "shladd,l %2,%O3,%1,%0"
6902 [(set_attr "type" "binary")
6903 (set_attr "length" "4")])
6905 (define_expand "ashlsi3"
6906 [(set (match_operand:SI 0 "register_operand" "")
6907 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6908 (match_operand:SI 2 "arith32_operand" "")))]
6912 if (GET_CODE (operands[2]) != CONST_INT)
6914 rtx temp = gen_reg_rtx (SImode);
6915 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6916 if (GET_CODE (operands[1]) == CONST_INT)
6917 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6919 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6922 /* Make sure both inputs are not constants,
6923 there are no patterns for that. */
6924 operands[1] = force_reg (SImode, operands[1]);
6928 [(set (match_operand:SI 0 "register_operand" "=r")
6929 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6930 (match_operand:SI 2 "const_int_operand" "n")))]
6932 "{zdep|depw,z} %1,%P2,%L2,%0"
6933 [(set_attr "type" "shift")
6934 (set_attr "length" "4")])
6936 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6937 ; Doing it like this makes slightly better code since reload can
6938 ; replace a register with a known value in range -16..15 with a
6939 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6940 ; but since we have no more CONST_OK... characters, that is not
6942 (define_insn "zvdep32"
6943 [(set (match_operand:SI 0 "register_operand" "=r,r")
6944 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6945 (minus:SI (const_int 31)
6946 (match_operand:SI 2 "register_operand" "q,q"))))]
6949 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6950 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6951 [(set_attr "type" "shift,shift")
6952 (set_attr "length" "4,4")])
6954 (define_insn "zvdep_imm32"
6955 [(set (match_operand:SI 0 "register_operand" "=r")
6956 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6957 (minus:SI (const_int 31)
6958 (match_operand:SI 2 "register_operand" "q"))))]
6962 int x = INTVAL (operands[1]);
6963 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6964 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6965 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6967 [(set_attr "type" "shift")
6968 (set_attr "length" "4")])
6970 (define_insn "vdepi_ior"
6971 [(set (match_operand:SI 0 "register_operand" "=r")
6972 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6973 (minus:SI (const_int 31)
6974 (match_operand:SI 2 "register_operand" "q")))
6975 (match_operand:SI 3 "register_operand" "0")))]
6976 ; accept ...0001...1, can this be generalized?
6977 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6980 int x = INTVAL (operands[1]);
6981 operands[2] = GEN_INT (exact_log2 (x + 1));
6982 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6984 [(set_attr "type" "shift")
6985 (set_attr "length" "4")])
6987 (define_insn "vdepi_and"
6988 [(set (match_operand:SI 0 "register_operand" "=r")
6989 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6990 (minus:SI (const_int 31)
6991 (match_operand:SI 2 "register_operand" "q")))
6992 (match_operand:SI 3 "register_operand" "0")))]
6993 ; this can be generalized...!
6994 "INTVAL (operands[1]) == -2"
6997 int x = INTVAL (operands[1]);
6998 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6999 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
7001 [(set_attr "type" "shift")
7002 (set_attr "length" "4")])
7004 (define_expand "ashldi3"
7005 [(set (match_operand:DI 0 "register_operand" "")
7006 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
7007 (match_operand:DI 2 "arith32_operand" "")))]
7011 if (GET_CODE (operands[2]) != CONST_INT)
7013 rtx temp = gen_reg_rtx (DImode);
7014 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7015 if (GET_CODE (operands[1]) == CONST_INT)
7016 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
7018 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
7021 /* Make sure both inputs are not constants,
7022 there are no patterns for that. */
7023 operands[1] = force_reg (DImode, operands[1]);
7027 [(set (match_operand:DI 0 "register_operand" "=r")
7028 (ashift:DI (match_operand:DI 1 "register_operand" "r")
7029 (match_operand:DI 2 "const_int_operand" "n")))]
7031 "depd,z %1,%p2,%Q2,%0"
7032 [(set_attr "type" "shift")
7033 (set_attr "length" "4")])
7035 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
7036 ; Doing it like this makes slightly better code since reload can
7037 ; replace a register with a known value in range -16..15 with a
7038 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
7039 ; but since we have no more CONST_OK... characters, that is not
7041 (define_insn "zvdep64"
7042 [(set (match_operand:DI 0 "register_operand" "=r,r")
7043 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
7044 (minus:DI (const_int 63)
7045 (match_operand:DI 2 "register_operand" "q,q"))))]
7048 depd,z %1,%%sar,64,%0
7049 depdi,z %1,%%sar,64,%0"
7050 [(set_attr "type" "shift,shift")
7051 (set_attr "length" "4,4")])
7053 (define_insn "zvdep_imm64"
7054 [(set (match_operand:DI 0 "register_operand" "=r")
7055 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
7056 (minus:DI (const_int 63)
7057 (match_operand:DI 2 "register_operand" "q"))))]
7061 int x = INTVAL (operands[1]);
7062 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
7063 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
7064 return \"depdi,z %1,%%sar,%2,%0\";
7066 [(set_attr "type" "shift")
7067 (set_attr "length" "4")])
7070 [(set (match_operand:DI 0 "register_operand" "=r")
7071 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
7072 (minus:DI (const_int 63)
7073 (match_operand:DI 2 "register_operand" "q")))
7074 (match_operand:DI 3 "register_operand" "0")))]
7075 ; accept ...0001...1, can this be generalized?
7076 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
7079 int x = INTVAL (operands[1]);
7080 operands[2] = GEN_INT (exact_log2 (x + 1));
7081 return \"depdi -1,%%sar,%2,%0\";
7083 [(set_attr "type" "shift")
7084 (set_attr "length" "4")])
7087 [(set (match_operand:DI 0 "register_operand" "=r")
7088 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
7089 (minus:DI (const_int 63)
7090 (match_operand:DI 2 "register_operand" "q")))
7091 (match_operand:DI 3 "register_operand" "0")))]
7092 ; this can be generalized...!
7093 "TARGET_64BIT && INTVAL (operands[1]) == -2"
7096 int x = INTVAL (operands[1]);
7097 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7098 return \"depdi 0,%%sar,%2,%0\";
7100 [(set_attr "type" "shift")
7101 (set_attr "length" "4")])
7103 (define_expand "ashrsi3"
7104 [(set (match_operand:SI 0 "register_operand" "")
7105 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
7106 (match_operand:SI 2 "arith32_operand" "")))]
7110 if (GET_CODE (operands[2]) != CONST_INT)
7112 rtx temp = gen_reg_rtx (SImode);
7113 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
7114 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
7120 [(set (match_operand:SI 0 "register_operand" "=r")
7121 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7122 (match_operand:SI 2 "const_int_operand" "n")))]
7124 "{extrs|extrw,s} %1,%P2,%L2,%0"
7125 [(set_attr "type" "shift")
7126 (set_attr "length" "4")])
7128 (define_insn "vextrs32"
7129 [(set (match_operand:SI 0 "register_operand" "=r")
7130 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7131 (minus:SI (const_int 31)
7132 (match_operand:SI 2 "register_operand" "q"))))]
7134 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
7135 [(set_attr "type" "shift")
7136 (set_attr "length" "4")])
7138 (define_expand "ashrdi3"
7139 [(set (match_operand:DI 0 "register_operand" "")
7140 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7141 (match_operand:DI 2 "arith32_operand" "")))]
7145 if (GET_CODE (operands[2]) != CONST_INT)
7147 rtx temp = gen_reg_rtx (DImode);
7148 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7149 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
7155 [(set (match_operand:DI 0 "register_operand" "=r")
7156 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7157 (match_operand:DI 2 "const_int_operand" "n")))]
7159 "extrd,s %1,%p2,%Q2,%0"
7160 [(set_attr "type" "shift")
7161 (set_attr "length" "4")])
7163 (define_insn "vextrs64"
7164 [(set (match_operand:DI 0 "register_operand" "=r")
7165 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7166 (minus:DI (const_int 63)
7167 (match_operand:DI 2 "register_operand" "q"))))]
7169 "extrd,s %1,%%sar,64,%0"
7170 [(set_attr "type" "shift")
7171 (set_attr "length" "4")])
7173 (define_insn "lshrsi3"
7174 [(set (match_operand:SI 0 "register_operand" "=r,r")
7175 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
7176 (match_operand:SI 2 "arith32_operand" "q,n")))]
7179 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
7180 {extru|extrw,u} %1,%P2,%L2,%0"
7181 [(set_attr "type" "shift")
7182 (set_attr "length" "4")])
7184 (define_insn "lshrdi3"
7185 [(set (match_operand:DI 0 "register_operand" "=r,r")
7186 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
7187 (match_operand:DI 2 "arith32_operand" "q,n")))]
7190 shrpd %%r0,%1,%%sar,%0
7191 extrd,u %1,%p2,%Q2,%0"
7192 [(set_attr "type" "shift")
7193 (set_attr "length" "4")])
7195 (define_insn "rotrsi3"
7196 [(set (match_operand:SI 0 "register_operand" "=r,r")
7197 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
7198 (match_operand:SI 2 "arith32_operand" "q,n")))]
7202 if (GET_CODE (operands[2]) == CONST_INT)
7204 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
7205 return \"{shd|shrpw} %1,%1,%2,%0\";
7208 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
7210 [(set_attr "type" "shift")
7211 (set_attr "length" "4")])
7213 (define_expand "rotlsi3"
7214 [(set (match_operand:SI 0 "register_operand" "")
7215 (rotate:SI (match_operand:SI 1 "register_operand" "")
7216 (match_operand:SI 2 "arith32_operand" "")))]
7220 if (GET_CODE (operands[2]) != CONST_INT)
7222 rtx temp = gen_reg_rtx (SImode);
7223 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
7224 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
7227 /* Else expand normally. */
7231 [(set (match_operand:SI 0 "register_operand" "=r")
7232 (rotate:SI (match_operand:SI 1 "register_operand" "r")
7233 (match_operand:SI 2 "const_int_operand" "n")))]
7237 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
7238 return \"{shd|shrpw} %1,%1,%2,%0\";
7240 [(set_attr "type" "shift")
7241 (set_attr "length" "4")])
7244 [(set (match_operand:SI 0 "register_operand" "=r")
7245 (match_operator:SI 5 "plus_xor_ior_operator"
7246 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
7247 (match_operand:SI 3 "const_int_operand" "n"))
7248 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7249 (match_operand:SI 4 "const_int_operand" "n"))]))]
7250 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7251 "{shd|shrpw} %1,%2,%4,%0"
7252 [(set_attr "type" "shift")
7253 (set_attr "length" "4")])
7256 [(set (match_operand:SI 0 "register_operand" "=r")
7257 (match_operator:SI 5 "plus_xor_ior_operator"
7258 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7259 (match_operand:SI 4 "const_int_operand" "n"))
7260 (ashift:SI (match_operand:SI 1 "register_operand" "r")
7261 (match_operand:SI 3 "const_int_operand" "n"))]))]
7262 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7263 "{shd|shrpw} %1,%2,%4,%0"
7264 [(set_attr "type" "shift")
7265 (set_attr "length" "4")])
7268 [(set (match_operand:SI 0 "register_operand" "=r")
7269 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
7270 (match_operand:SI 2 "const_int_operand" ""))
7271 (match_operand:SI 3 "const_int_operand" "")))]
7272 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
7275 int cnt = INTVAL (operands[2]) & 31;
7276 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
7277 operands[2] = GEN_INT (31 - cnt);
7278 return \"{zdep|depw,z} %1,%2,%3,%0\";
7280 [(set_attr "type" "shift")
7281 (set_attr "length" "4")])
7283 ;; Unconditional and other jump instructions.
7285 ;; This can only be used in a leaf function, so we do
7286 ;; not need to use the PIC register when generating PIC code.
7287 (define_insn "return"
7291 "hppa_can_use_return_insn_p ()"
7295 return \"bve%* (%%r2)\";
7296 return \"bv%* %%r0(%%r2)\";
7298 [(set_attr "type" "branch")
7299 (set_attr "length" "4")])
7301 ;; Emit a different pattern for functions which have non-trivial
7302 ;; epilogues so as not to confuse jump and reorg.
7303 (define_insn "return_internal"
7311 return \"bve%* (%%r2)\";
7312 return \"bv%* %%r0(%%r2)\";
7314 [(set_attr "type" "branch")
7315 (set_attr "length" "4")])
7317 ;; This is used for eh returns which bypass the return stub.
7318 (define_insn "return_external_pic"
7320 (clobber (reg:SI 1))
7322 "!TARGET_NO_SPACE_REGS
7324 && flag_pic && current_function_calls_eh_return"
7325 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
7326 [(set_attr "type" "branch")
7327 (set_attr "length" "12")])
7329 (define_expand "prologue"
7332 "hppa_expand_prologue ();DONE;")
7334 (define_expand "sibcall_epilogue"
7339 hppa_expand_epilogue ();
7343 (define_expand "epilogue"
7348 /* Try to use the trivial return first. Else use the full
7350 if (hppa_can_use_return_insn_p ())
7351 emit_jump_insn (gen_return ());
7356 hppa_expand_epilogue ();
7358 /* EH returns bypass the normal return stub. Thus, we must do an
7359 interspace branch to return from functions that call eh_return.
7360 This is only a problem for returns from shared code on ports
7361 using space registers. */
7362 if (!TARGET_NO_SPACE_REGS
7364 && flag_pic && current_function_calls_eh_return)
7365 x = gen_return_external_pic ();
7367 x = gen_return_internal ();
7374 ; Used by hppa_profile_hook to load the starting address of the current
7375 ; function; operand 1 contains the address of the label in operand 3
7376 (define_insn "load_offset_label_address"
7377 [(set (match_operand:SI 0 "register_operand" "=r")
7378 (plus:SI (match_operand:SI 1 "register_operand" "r")
7379 (minus:SI (match_operand:SI 2 "" "")
7380 (label_ref:SI (match_operand 3 "" "")))))]
7383 [(set_attr "type" "multi")
7384 (set_attr "length" "4")])
7386 ; Output a code label and load its address.
7387 (define_insn "lcla1"
7388 [(set (match_operand:SI 0 "register_operand" "=r")
7389 (label_ref:SI (match_operand 1 "" "")))
7394 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
7395 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7396 CODE_LABEL_NUMBER (operands[1]));
7399 [(set_attr "type" "multi")
7400 (set_attr "length" "8")])
7402 (define_insn "lcla2"
7403 [(set (match_operand:SI 0 "register_operand" "=r")
7404 (label_ref:SI (match_operand 1 "" "")))
7409 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7410 CODE_LABEL_NUMBER (operands[1]));
7413 [(set_attr "type" "move")
7414 (set_attr "length" "4")])
7416 (define_insn "blockage"
7417 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
7420 [(set_attr "length" "0")])
7423 [(set (pc) (label_ref (match_operand 0 "" "")))]
7427 /* An unconditional branch which can reach its target. */
7428 if (get_attr_length (insn) < 16)
7431 return output_lbranch (operands[0], insn, 1);
7433 [(set_attr "type" "uncond_branch")
7434 (set_attr "pa_combine_type" "uncond_branch")
7435 (set (attr "length")
7436 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7437 (if_then_else (lt (abs (minus (match_dup 0)
7438 (plus (pc) (const_int 8))))
7439 (const_int MAX_12BIT_OFFSET))
7442 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7443 (const_int MAX_17BIT_OFFSET))
7445 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7447 (eq (symbol_ref "flag_pic") (const_int 0))
7451 ;;; Hope this is only within a function...
7452 (define_insn "indirect_jump"
7453 [(set (pc) (match_operand 0 "register_operand" "r"))]
7454 "GET_MODE (operands[0]) == word_mode"
7456 [(set_attr "type" "branch")
7457 (set_attr "length" "4")])
7459 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7460 ;;; SOM target doesn't allow branching to a label inside a function.
7461 ;;; We also don't correctly compute branch distances for labels
7462 ;;; outside the current function. Thus, we use an indirect jump can't
7463 ;;; be optimized to a direct jump for all targets. We assume that
7464 ;;; the branch target is in the same space (i.e., nested function
7465 ;;; jumping to a label in an outer function in the same translation
7467 (define_expand "nonlocal_goto"
7468 [(use (match_operand 0 "general_operand" ""))
7469 (use (match_operand 1 "general_operand" ""))
7470 (use (match_operand 2 "general_operand" ""))
7471 (use (match_operand 3 "general_operand" ""))]
7474 rtx lab = operands[1];
7475 rtx stack = operands[2];
7476 rtx fp = operands[3];
7478 lab = copy_to_reg (lab);
7480 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7481 gen_rtx_MEM (BLKmode,
7482 gen_rtx_SCRATCH (VOIDmode))));
7483 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7484 gen_rtx_MEM (BLKmode,
7485 hard_frame_pointer_rtx)));
7487 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7488 instead of the hard_frame_pointer_rtx in the save area. As a
7489 result, an extra instruction is needed to adjust for the offset
7490 of the virtual stack variables and the frame pointer. */
7491 if (GET_CODE (fp) != REG)
7492 fp = force_reg (Pmode, fp);
7493 emit_move_insn (virtual_stack_vars_rtx, fp);
7495 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7497 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7498 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7500 /* Nonlocal goto jumps are only used between functions in the same
7501 translation unit. Thus, we can avoid the extra overhead of an
7503 emit_jump_insn (gen_indirect_goto (lab));
7508 (define_insn "indirect_goto"
7509 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7510 "GET_MODE (operands[0]) == word_mode"
7512 [(set_attr "type" "branch")
7513 (set_attr "length" "4")])
7515 ;;; This jump is used in branch tables where the insn length is fixed.
7516 ;;; The length of this insn is adjusted if the delay slot is not filled.
7517 (define_insn "short_jump"
7518 [(set (pc) (label_ref (match_operand 0 "" "")))
7522 [(set_attr "type" "btable_branch")
7523 (set_attr "length" "4")])
7525 ;; Subroutines of "casesi".
7526 ;; operand 0 is index
7527 ;; operand 1 is the minimum bound
7528 ;; operand 2 is the maximum bound - minimum bound + 1
7529 ;; operand 3 is CODE_LABEL for the table;
7530 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7532 (define_expand "casesi"
7533 [(match_operand:SI 0 "general_operand" "")
7534 (match_operand:SI 1 "const_int_operand" "")
7535 (match_operand:SI 2 "const_int_operand" "")
7536 (match_operand 3 "" "")
7537 (match_operand 4 "" "")]
7541 if (GET_CODE (operands[0]) != REG)
7542 operands[0] = force_reg (SImode, operands[0]);
7544 if (operands[1] != const0_rtx)
7546 rtx index = gen_reg_rtx (SImode);
7548 operands[1] = GEN_INT (-INTVAL (operands[1]));
7549 if (!INT_14_BITS (operands[1]))
7550 operands[1] = force_reg (SImode, operands[1]);
7551 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7552 operands[0] = index;
7555 /* In 64bit mode we must make sure to wipe the upper bits of the register
7556 just in case the addition overflowed or we had random bits in the
7557 high part of the register. */
7560 rtx index = gen_reg_rtx (DImode);
7562 emit_insn (gen_extendsidi2 (index, operands[0]));
7563 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
7566 if (!INT_5_BITS (operands[2]))
7567 operands[2] = force_reg (SImode, operands[2]);
7569 /* This branch prevents us finding an insn for the delay slot of the
7570 following vectored branch. It might be possible to use the delay
7571 slot if an index value of -1 was used to transfer to the out-of-range
7572 label. In order to do this, we would have to output the -1 vector
7573 element after the delay insn. The casesi output code would have to
7574 check if the casesi insn is in a delay branch sequence and output
7575 the delay insn if one is found. If this was done, then it might
7576 then be worthwhile to split the casesi patterns to improve scheduling.
7577 However, it's not clear that all this extra complexity is worth
7579 emit_insn (gen_cmpsi (operands[0], operands[2]));
7580 emit_jump_insn (gen_bgtu (operands[4]));
7582 if (TARGET_BIG_SWITCH)
7586 rtx tmp1 = gen_reg_rtx (DImode);
7587 rtx tmp2 = gen_reg_rtx (DImode);
7589 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
7594 rtx tmp1 = gen_reg_rtx (SImode);
7598 rtx tmp2 = gen_reg_rtx (SImode);
7600 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
7604 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
7608 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7612 ;;; The rtl for this pattern doesn't accurately describe what the insn
7613 ;;; actually does, particularly when case-vector elements are exploded
7614 ;;; in pa_reorg. However, the initial SET in these patterns must show
7615 ;;; the connection of the insn to the following jump table.
7616 (define_insn "casesi0"
7617 [(set (pc) (mem:SI (plus:SI
7618 (mult:SI (match_operand:SI 0 "register_operand" "r")
7620 (label_ref (match_operand 1 "" "")))))]
7622 "blr,n %0,%%r0\;nop"
7623 [(set_attr "type" "multi")
7624 (set_attr "length" "8")])
7626 ;;; 32-bit code, absolute branch table.
7627 (define_insn "casesi32"
7628 [(set (pc) (mem:SI (plus:SI
7629 (mult:SI (match_operand:SI 0 "register_operand" "r")
7631 (label_ref (match_operand 1 "" "")))))
7632 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
7633 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7634 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7635 [(set_attr "type" "multi")
7636 (set_attr "length" "16")])
7638 ;;; 32-bit code, relative branch table.
7639 (define_insn "casesi32p"
7640 [(set (pc) (mem:SI (plus:SI
7641 (mult:SI (match_operand:SI 0 "register_operand" "r")
7643 (label_ref (match_operand 1 "" "")))))
7644 (clobber (match_operand:SI 2 "register_operand" "=&a"))
7645 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
7646 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7647 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7648 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7649 [(set_attr "type" "multi")
7650 (set (attr "length")
7651 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7655 ;;; 64-bit code, 32-bit relative branch table.
7656 (define_insn "casesi64p"
7657 [(set (pc) (mem:DI (plus:DI
7658 (mult:DI (sign_extend:DI
7659 (match_operand:SI 0 "register_operand" "r"))
7661 (label_ref (match_operand 1 "" "")))))
7662 (clobber (match_operand:DI 2 "register_operand" "=&r"))
7663 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
7664 "TARGET_64BIT && TARGET_BIG_SWITCH"
7665 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7666 add,l %2,%3,%3\;bv,n %%r0(%3)"
7667 [(set_attr "type" "multi")
7668 (set_attr "length" "24")])
7672 ;;- jump to subroutine
7674 (define_expand "call"
7675 [(parallel [(call (match_operand:SI 0 "" "")
7676 (match_operand 1 "" ""))
7677 (clobber (reg:SI 2))])]
7682 rtx nb = operands[1];
7684 if (TARGET_PORTABLE_RUNTIME)
7685 op = force_reg (SImode, XEXP (operands[0], 0));
7687 op = XEXP (operands[0], 0);
7691 if (!virtuals_instantiated)
7692 emit_move_insn (arg_pointer_rtx,
7693 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7697 /* The loop pass can generate new libcalls after the virtual
7698 registers are instantiated when fpregs are disabled because
7699 the only method that we have for doing DImode multiplication
7700 is with a libcall. This could be trouble if we haven't
7701 allocated enough space for the outgoing arguments. */
7702 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
7704 emit_move_insn (arg_pointer_rtx,
7705 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7706 GEN_INT (STACK_POINTER_OFFSET + 64)));
7710 /* Use two different patterns for calls to explicitly named functions
7711 and calls through function pointers. This is necessary as these two
7712 types of calls use different calling conventions, and CSE might try
7713 to change the named call into an indirect call in some cases (using
7714 two patterns keeps CSE from performing this optimization).
7716 We now use even more call patterns as there was a subtle bug in
7717 attempting to restore the pic register after a call using a simple
7718 move insn. During reload, a instruction involving a pseudo register
7719 with no explicit dependence on the PIC register can be converted
7720 to an equivalent load from memory using the PIC register. If we
7721 emit a simple move to restore the PIC register in the initial rtl
7722 generation, then it can potentially be repositioned during scheduling.
7723 and an instruction that eventually uses the PIC register may end up
7724 between the call and the PIC register restore.
7726 This only worked because there is a post call group of instructions
7727 that are scheduled with the call. These instructions are included
7728 in the same basic block as the call. However, calls can throw in
7729 C++ code and a basic block has to terminate at the call if the call
7730 can throw. This results in the PIC register restore being scheduled
7731 independently from the call. So, we now hide the save and restore
7732 of the PIC register in the call pattern until after reload. Then,
7733 we split the moves out. A small side benefit is that we now don't
7734 need to have a use of the PIC register in the return pattern and
7735 the final save/restore operation is not needed.
7737 I elected to just clobber %r4 in the PIC patterns and use it instead
7738 of trying to force hppa_pic_save_rtx () to a callee saved register.
7739 This might have required a new register class and constraint. It
7740 was also simpler to just handle the restore from a register than a
7744 if (GET_CODE (op) == SYMBOL_REF)
7745 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7748 op = force_reg (word_mode, op);
7749 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7754 if (GET_CODE (op) == SYMBOL_REF)
7757 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7759 call_insn = emit_call_insn (gen_call_symref (op, nb));
7763 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7765 emit_move_insn (tmpreg, force_reg (word_mode, op));
7767 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7769 call_insn = emit_call_insn (gen_call_reg (nb));
7776 ;; We use function calls to set the attribute length of calls and millicode
7777 ;; calls. This is necessary because of the large variety of call sequences.
7778 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7779 ;; we need the same calculation in several places, maintenance becomes a
7782 ;; However, this has a subtle impact on branch shortening. When the
7783 ;; expression used to set the length attribute of an instruction depends
7784 ;; on a relative address (e.g., pc or a branch address), genattrtab
7785 ;; notes that the insn's length is variable, and attempts to determine a
7786 ;; worst-case default length and code to compute an insn's current length.
7788 ;; The use of a function call hides the variable dependence of our calls
7789 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7790 ;; as variable and it only generates code for the default case using our
7791 ;; function call. Because of this, calls and millicode calls have a fixed
7792 ;; length in the branch shortening pass, and some branches will use a longer
7793 ;; code sequence than necessary. However, the length of any given call
7794 ;; will still reflect its final code location and it may be shorter than
7795 ;; the initial length estimate.
7797 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7798 ;; in the set. However, when genattrtab hits a function call in its attempt
7799 ;; to compute the default length, it marks the result as unknown and sets
7800 ;; the default result to MAX_INT ;-( One possible fix that would allow
7801 ;; calls to participate in branch shortening would be to make the call to
7802 ;; insn_default_length a target option. Then, we could massage unknown
7803 ;; results. Another fix might be to change genattrtab so that it just does
7804 ;; the call in the variable case as it already does for the fixed case.
7806 (define_insn "call_symref"
7807 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7808 (match_operand 1 "" "i"))
7809 (clobber (reg:SI 1))
7810 (clobber (reg:SI 2))
7811 (use (const_int 0))]
7812 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7815 output_arg_descriptor (insn);
7816 return output_call (insn, operands[0], 0);
7818 [(set_attr "type" "call")
7819 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7821 (define_insn "call_symref_pic"
7822 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7823 (match_operand 1 "" "i"))
7824 (clobber (reg:SI 1))
7825 (clobber (reg:SI 2))
7826 (clobber (reg:SI 4))
7828 (use (const_int 0))]
7829 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7832 output_arg_descriptor (insn);
7833 return output_call (insn, operands[0], 0);
7835 [(set_attr "type" "call")
7836 (set (attr "length")
7837 (plus (symbol_ref "attr_length_call (insn, 0)")
7838 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7840 ;; Split out the PIC register save and restore after reload. This is
7841 ;; done only if the function returns. As the split is done after reload,
7842 ;; there are some situations in which we unnecessarily save and restore
7843 ;; %r4. This happens when there is a single call and the PIC register
7844 ;; is "dead" after the call. This isn't easy to fix as the usage of
7845 ;; the PIC register isn't completely determined until the reload pass.
7847 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7848 (match_operand 1 "" ""))
7849 (clobber (reg:SI 1))
7850 (clobber (reg:SI 2))
7851 (clobber (reg:SI 4))
7853 (use (const_int 0))])]
7854 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7856 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7857 [(set (reg:SI 4) (reg:SI 19))
7858 (parallel [(call (mem:SI (match_dup 0))
7860 (clobber (reg:SI 1))
7861 (clobber (reg:SI 2))
7863 (use (const_int 0))])
7864 (set (reg:SI 19) (reg:SI 4))]
7867 ;; Remove the clobber of register 4 when optimizing. This has to be
7868 ;; done with a peephole optimization rather than a split because the
7869 ;; split sequence for a call must be longer than one instruction.
7871 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7872 (match_operand 1 "" ""))
7873 (clobber (reg:SI 1))
7874 (clobber (reg:SI 2))
7875 (clobber (reg:SI 4))
7877 (use (const_int 0))])]
7878 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7879 [(parallel [(call (mem:SI (match_dup 0))
7881 (clobber (reg:SI 1))
7882 (clobber (reg:SI 2))
7884 (use (const_int 0))])]
7887 (define_insn "*call_symref_pic_post_reload"
7888 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7889 (match_operand 1 "" "i"))
7890 (clobber (reg:SI 1))
7891 (clobber (reg:SI 2))
7893 (use (const_int 0))]
7894 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7897 output_arg_descriptor (insn);
7898 return output_call (insn, operands[0], 0);
7900 [(set_attr "type" "call")
7901 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7903 ;; This pattern is split if it is necessary to save and restore the
7905 (define_insn "call_symref_64bit"
7906 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7907 (match_operand 1 "" "i"))
7908 (clobber (reg:DI 1))
7909 (clobber (reg:DI 2))
7910 (clobber (reg:DI 4))
7913 (use (const_int 0))]
7917 output_arg_descriptor (insn);
7918 return output_call (insn, operands[0], 0);
7920 [(set_attr "type" "call")
7921 (set (attr "length")
7922 (plus (symbol_ref "attr_length_call (insn, 0)")
7923 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7925 ;; Split out the PIC register save and restore after reload. This is
7926 ;; done only if the function returns. As the split is done after reload,
7927 ;; there are some situations in which we unnecessarily save and restore
7928 ;; %r4. This happens when there is a single call and the PIC register
7929 ;; is "dead" after the call. This isn't easy to fix as the usage of
7930 ;; the PIC register isn't completely determined until the reload pass.
7932 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7933 (match_operand 1 "" ""))
7934 (clobber (reg:DI 1))
7935 (clobber (reg:DI 2))
7936 (clobber (reg:DI 4))
7939 (use (const_int 0))])]
7942 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7943 [(set (reg:DI 4) (reg:DI 27))
7944 (parallel [(call (mem:SI (match_dup 0))
7946 (clobber (reg:DI 1))
7947 (clobber (reg:DI 2))
7950 (use (const_int 0))])
7951 (set (reg:DI 27) (reg:DI 4))]
7954 ;; Remove the clobber of register 4 when optimizing. This has to be
7955 ;; done with a peephole optimization rather than a split because the
7956 ;; split sequence for a call must be longer than one instruction.
7958 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7959 (match_operand 1 "" ""))
7960 (clobber (reg:DI 1))
7961 (clobber (reg:DI 2))
7962 (clobber (reg:DI 4))
7965 (use (const_int 0))])]
7966 "TARGET_64BIT && reload_completed"
7967 [(parallel [(call (mem:SI (match_dup 0))
7969 (clobber (reg:DI 1))
7970 (clobber (reg:DI 2))
7973 (use (const_int 0))])]
7976 (define_insn "*call_symref_64bit_post_reload"
7977 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7978 (match_operand 1 "" "i"))
7979 (clobber (reg:DI 1))
7980 (clobber (reg:DI 2))
7983 (use (const_int 0))]
7987 output_arg_descriptor (insn);
7988 return output_call (insn, operands[0], 0);
7990 [(set_attr "type" "call")
7991 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7993 (define_insn "call_reg"
7994 [(call (mem:SI (reg:SI 22))
7995 (match_operand 0 "" "i"))
7996 (clobber (reg:SI 1))
7997 (clobber (reg:SI 2))
7998 (use (const_int 1))]
8002 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8004 [(set_attr "type" "dyncall")
8005 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8007 ;; This pattern is split if it is necessary to save and restore the
8009 (define_insn "call_reg_pic"
8010 [(call (mem:SI (reg:SI 22))
8011 (match_operand 0 "" "i"))
8012 (clobber (reg:SI 1))
8013 (clobber (reg:SI 2))
8014 (clobber (reg:SI 4))
8016 (use (const_int 1))]
8020 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8022 [(set_attr "type" "dyncall")
8023 (set (attr "length")
8024 (plus (symbol_ref "attr_length_indirect_call (insn)")
8025 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8027 ;; Split out the PIC register save and restore after reload. This is
8028 ;; done only if the function returns. As the split is done after reload,
8029 ;; there are some situations in which we unnecessarily save and restore
8030 ;; %r4. This happens when there is a single call and the PIC register
8031 ;; is "dead" after the call. This isn't easy to fix as the usage of
8032 ;; the PIC register isn't completely determined until the reload pass.
8034 [(parallel [(call (mem:SI (reg:SI 22))
8035 (match_operand 0 "" ""))
8036 (clobber (reg:SI 1))
8037 (clobber (reg:SI 2))
8038 (clobber (reg:SI 4))
8040 (use (const_int 1))])]
8043 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8044 [(set (reg:SI 4) (reg:SI 19))
8045 (parallel [(call (mem:SI (reg:SI 22))
8047 (clobber (reg:SI 1))
8048 (clobber (reg:SI 2))
8050 (use (const_int 1))])
8051 (set (reg:SI 19) (reg:SI 4))]
8054 ;; Remove the clobber of register 4 when optimizing. This has to be
8055 ;; done with a peephole optimization rather than a split because the
8056 ;; split sequence for a call must be longer than one instruction.
8058 [(parallel [(call (mem:SI (reg:SI 22))
8059 (match_operand 0 "" ""))
8060 (clobber (reg:SI 1))
8061 (clobber (reg:SI 2))
8062 (clobber (reg:SI 4))
8064 (use (const_int 1))])]
8065 "!TARGET_64BIT && reload_completed"
8066 [(parallel [(call (mem:SI (reg:SI 22))
8068 (clobber (reg:SI 1))
8069 (clobber (reg:SI 2))
8071 (use (const_int 1))])]
8074 (define_insn "*call_reg_pic_post_reload"
8075 [(call (mem:SI (reg:SI 22))
8076 (match_operand 0 "" "i"))
8077 (clobber (reg:SI 1))
8078 (clobber (reg:SI 2))
8080 (use (const_int 1))]
8084 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8086 [(set_attr "type" "dyncall")
8087 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8089 ;; This pattern is split if it is necessary to save and restore the
8091 (define_insn "call_reg_64bit"
8092 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8093 (match_operand 1 "" "i"))
8094 (clobber (reg:DI 2))
8095 (clobber (reg:DI 4))
8098 (use (const_int 1))]
8102 return output_indirect_call (insn, operands[0]);
8104 [(set_attr "type" "dyncall")
8105 (set (attr "length")
8106 (plus (symbol_ref "attr_length_indirect_call (insn)")
8107 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8109 ;; Split out the PIC register save and restore after reload. This is
8110 ;; done only if the function returns. As the split is done after reload,
8111 ;; there are some situations in which we unnecessarily save and restore
8112 ;; %r4. This happens when there is a single call and the PIC register
8113 ;; is "dead" after the call. This isn't easy to fix as the usage of
8114 ;; the PIC register isn't completely determined until the reload pass.
8116 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8117 (match_operand 1 "" ""))
8118 (clobber (reg:DI 2))
8119 (clobber (reg:DI 4))
8122 (use (const_int 1))])]
8125 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8126 [(set (reg:DI 4) (reg:DI 27))
8127 (parallel [(call (mem:SI (match_dup 0))
8129 (clobber (reg:DI 2))
8132 (use (const_int 1))])
8133 (set (reg:DI 27) (reg:DI 4))]
8136 ;; Remove the clobber of register 4 when optimizing. This has to be
8137 ;; done with a peephole optimization rather than a split because the
8138 ;; split sequence for a call must be longer than one instruction.
8140 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8141 (match_operand 1 "" ""))
8142 (clobber (reg:DI 2))
8143 (clobber (reg:DI 4))
8146 (use (const_int 1))])]
8147 "TARGET_64BIT && reload_completed"
8148 [(parallel [(call (mem:SI (match_dup 0))
8150 (clobber (reg:DI 2))
8153 (use (const_int 1))])]
8156 (define_insn "*call_reg_64bit_post_reload"
8157 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8158 (match_operand 1 "" "i"))
8159 (clobber (reg:DI 2))
8162 (use (const_int 1))]
8166 return output_indirect_call (insn, operands[0]);
8168 [(set_attr "type" "dyncall")
8169 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8171 (define_expand "call_value"
8172 [(parallel [(set (match_operand 0 "" "")
8173 (call (match_operand:SI 1 "" "")
8174 (match_operand 2 "" "")))
8175 (clobber (reg:SI 2))])]
8180 rtx dst = operands[0];
8181 rtx nb = operands[2];
8183 if (TARGET_PORTABLE_RUNTIME)
8184 op = force_reg (SImode, XEXP (operands[1], 0));
8186 op = XEXP (operands[1], 0);
8190 if (!virtuals_instantiated)
8191 emit_move_insn (arg_pointer_rtx,
8192 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8196 /* The loop pass can generate new libcalls after the virtual
8197 registers are instantiated when fpregs are disabled because
8198 the only method that we have for doing DImode multiplication
8199 is with a libcall. This could be trouble if we haven't
8200 allocated enough space for the outgoing arguments. */
8201 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8203 emit_move_insn (arg_pointer_rtx,
8204 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8205 GEN_INT (STACK_POINTER_OFFSET + 64)));
8209 /* Use two different patterns for calls to explicitly named functions
8210 and calls through function pointers. This is necessary as these two
8211 types of calls use different calling conventions, and CSE might try
8212 to change the named call into an indirect call in some cases (using
8213 two patterns keeps CSE from performing this optimization).
8215 We now use even more call patterns as there was a subtle bug in
8216 attempting to restore the pic register after a call using a simple
8217 move insn. During reload, a instruction involving a pseudo register
8218 with no explicit dependence on the PIC register can be converted
8219 to an equivalent load from memory using the PIC register. If we
8220 emit a simple move to restore the PIC register in the initial rtl
8221 generation, then it can potentially be repositioned during scheduling.
8222 and an instruction that eventually uses the PIC register may end up
8223 between the call and the PIC register restore.
8225 This only worked because there is a post call group of instructions
8226 that are scheduled with the call. These instructions are included
8227 in the same basic block as the call. However, calls can throw in
8228 C++ code and a basic block has to terminate at the call if the call
8229 can throw. This results in the PIC register restore being scheduled
8230 independently from the call. So, we now hide the save and restore
8231 of the PIC register in the call pattern until after reload. Then,
8232 we split the moves out. A small side benefit is that we now don't
8233 need to have a use of the PIC register in the return pattern and
8234 the final save/restore operation is not needed.
8236 I elected to just clobber %r4 in the PIC patterns and use it instead
8237 of trying to force hppa_pic_save_rtx () to a callee saved register.
8238 This might have required a new register class and constraint. It
8239 was also simpler to just handle the restore from a register than a
8243 if (GET_CODE (op) == SYMBOL_REF)
8244 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
8247 op = force_reg (word_mode, op);
8248 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
8253 if (GET_CODE (op) == SYMBOL_REF)
8256 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
8258 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
8262 rtx tmpreg = gen_rtx_REG (word_mode, 22);
8264 emit_move_insn (tmpreg, force_reg (word_mode, op));
8266 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
8268 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
8275 (define_insn "call_val_symref"
8276 [(set (match_operand 0 "" "")
8277 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8278 (match_operand 2 "" "i")))
8279 (clobber (reg:SI 1))
8280 (clobber (reg:SI 2))
8281 (use (const_int 0))]
8282 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8285 output_arg_descriptor (insn);
8286 return output_call (insn, operands[1], 0);
8288 [(set_attr "type" "call")
8289 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8291 (define_insn "call_val_symref_pic"
8292 [(set (match_operand 0 "" "")
8293 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8294 (match_operand 2 "" "i")))
8295 (clobber (reg:SI 1))
8296 (clobber (reg:SI 2))
8297 (clobber (reg:SI 4))
8299 (use (const_int 0))]
8300 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8303 output_arg_descriptor (insn);
8304 return output_call (insn, operands[1], 0);
8306 [(set_attr "type" "call")
8307 (set (attr "length")
8308 (plus (symbol_ref "attr_length_call (insn, 0)")
8309 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8311 ;; Split out the PIC register save and restore after reload. This is
8312 ;; done only if the function returns. As the split is done after reload,
8313 ;; there are some situations in which we unnecessarily save and restore
8314 ;; %r4. This happens when there is a single call and the PIC register
8315 ;; is "dead" after the call. This isn't easy to fix as the usage of
8316 ;; the PIC register isn't completely determined until the reload pass.
8318 [(parallel [(set (match_operand 0 "" "")
8319 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8320 (match_operand 2 "" "")))
8321 (clobber (reg:SI 1))
8322 (clobber (reg:SI 2))
8323 (clobber (reg:SI 4))
8325 (use (const_int 0))])]
8326 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
8328 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8329 [(set (reg:SI 4) (reg:SI 19))
8330 (parallel [(set (match_dup 0)
8331 (call (mem:SI (match_dup 1))
8333 (clobber (reg:SI 1))
8334 (clobber (reg:SI 2))
8336 (use (const_int 0))])
8337 (set (reg:SI 19) (reg:SI 4))]
8340 ;; Remove the clobber of register 4 when optimizing. This has to be
8341 ;; done with a peephole optimization rather than a split because the
8342 ;; split sequence for a call must be longer than one instruction.
8344 [(parallel [(set (match_operand 0 "" "")
8345 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8346 (match_operand 2 "" "")))
8347 (clobber (reg:SI 1))
8348 (clobber (reg:SI 2))
8349 (clobber (reg:SI 4))
8351 (use (const_int 0))])]
8352 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8353 [(parallel [(set (match_dup 0)
8354 (call (mem:SI (match_dup 1))
8356 (clobber (reg:SI 1))
8357 (clobber (reg:SI 2))
8359 (use (const_int 0))])]
8362 (define_insn "*call_val_symref_pic_post_reload"
8363 [(set (match_operand 0 "" "")
8364 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8365 (match_operand 2 "" "i")))
8366 (clobber (reg:SI 1))
8367 (clobber (reg:SI 2))
8369 (use (const_int 0))]
8370 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8373 output_arg_descriptor (insn);
8374 return output_call (insn, operands[1], 0);
8376 [(set_attr "type" "call")
8377 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8379 ;; This pattern is split if it is necessary to save and restore the
8381 (define_insn "call_val_symref_64bit"
8382 [(set (match_operand 0 "" "")
8383 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8384 (match_operand 2 "" "i")))
8385 (clobber (reg:DI 1))
8386 (clobber (reg:DI 2))
8387 (clobber (reg:DI 4))
8390 (use (const_int 0))]
8394 output_arg_descriptor (insn);
8395 return output_call (insn, operands[1], 0);
8397 [(set_attr "type" "call")
8398 (set (attr "length")
8399 (plus (symbol_ref "attr_length_call (insn, 0)")
8400 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8402 ;; Split out the PIC register save and restore after reload. This is
8403 ;; done only if the function returns. As the split is done after reload,
8404 ;; there are some situations in which we unnecessarily save and restore
8405 ;; %r4. This happens when there is a single call and the PIC register
8406 ;; is "dead" after the call. This isn't easy to fix as the usage of
8407 ;; the PIC register isn't completely determined until the reload pass.
8409 [(parallel [(set (match_operand 0 "" "")
8410 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8411 (match_operand 2 "" "")))
8412 (clobber (reg:DI 1))
8413 (clobber (reg:DI 2))
8414 (clobber (reg:DI 4))
8417 (use (const_int 0))])]
8420 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8421 [(set (reg:DI 4) (reg:DI 27))
8422 (parallel [(set (match_dup 0)
8423 (call (mem:SI (match_dup 1))
8425 (clobber (reg:DI 1))
8426 (clobber (reg:DI 2))
8429 (use (const_int 0))])
8430 (set (reg:DI 27) (reg:DI 4))]
8433 ;; Remove the clobber of register 4 when optimizing. This has to be
8434 ;; done with a peephole optimization rather than a split because the
8435 ;; split sequence for a call must be longer than one instruction.
8437 [(parallel [(set (match_operand 0 "" "")
8438 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8439 (match_operand 2 "" "")))
8440 (clobber (reg:DI 1))
8441 (clobber (reg:DI 2))
8442 (clobber (reg:DI 4))
8445 (use (const_int 0))])]
8446 "TARGET_64BIT && reload_completed"
8447 [(parallel [(set (match_dup 0)
8448 (call (mem:SI (match_dup 1))
8450 (clobber (reg:DI 1))
8451 (clobber (reg:DI 2))
8454 (use (const_int 0))])]
8457 (define_insn "*call_val_symref_64bit_post_reload"
8458 [(set (match_operand 0 "" "")
8459 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8460 (match_operand 2 "" "i")))
8461 (clobber (reg:DI 1))
8462 (clobber (reg:DI 2))
8465 (use (const_int 0))]
8469 output_arg_descriptor (insn);
8470 return output_call (insn, operands[1], 0);
8472 [(set_attr "type" "call")
8473 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8475 (define_insn "call_val_reg"
8476 [(set (match_operand 0 "" "")
8477 (call (mem:SI (reg:SI 22))
8478 (match_operand 1 "" "i")))
8479 (clobber (reg:SI 1))
8480 (clobber (reg:SI 2))
8481 (use (const_int 1))]
8485 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8487 [(set_attr "type" "dyncall")
8488 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8490 ;; This pattern is split if it is necessary to save and restore the
8492 (define_insn "call_val_reg_pic"
8493 [(set (match_operand 0 "" "")
8494 (call (mem:SI (reg:SI 22))
8495 (match_operand 1 "" "i")))
8496 (clobber (reg:SI 1))
8497 (clobber (reg:SI 2))
8498 (clobber (reg:SI 4))
8500 (use (const_int 1))]
8504 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8506 [(set_attr "type" "dyncall")
8507 (set (attr "length")
8508 (plus (symbol_ref "attr_length_indirect_call (insn)")
8509 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8511 ;; Split out the PIC register save and restore after reload. This is
8512 ;; done only if the function returns. As the split is done after reload,
8513 ;; there are some situations in which we unnecessarily save and restore
8514 ;; %r4. This happens when there is a single call and the PIC register
8515 ;; is "dead" after the call. This isn't easy to fix as the usage of
8516 ;; the PIC register isn't completely determined until the reload pass.
8518 [(parallel [(set (match_operand 0 "" "")
8519 (call (mem:SI (reg:SI 22))
8520 (match_operand 1 "" "")))
8521 (clobber (reg:SI 1))
8522 (clobber (reg:SI 2))
8523 (clobber (reg:SI 4))
8525 (use (const_int 1))])]
8528 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8529 [(set (reg:SI 4) (reg:SI 19))
8530 (parallel [(set (match_dup 0)
8531 (call (mem:SI (reg:SI 22))
8533 (clobber (reg:SI 1))
8534 (clobber (reg:SI 2))
8536 (use (const_int 1))])
8537 (set (reg:SI 19) (reg:SI 4))]
8540 ;; Remove the clobber of register 4 when optimizing. This has to be
8541 ;; done with a peephole optimization rather than a split because the
8542 ;; split sequence for a call must be longer than one instruction.
8544 [(parallel [(set (match_operand 0 "" "")
8545 (call (mem:SI (reg:SI 22))
8546 (match_operand 1 "" "")))
8547 (clobber (reg:SI 1))
8548 (clobber (reg:SI 2))
8549 (clobber (reg:SI 4))
8551 (use (const_int 1))])]
8552 "!TARGET_64BIT && reload_completed"
8553 [(parallel [(set (match_dup 0)
8554 (call (mem:SI (reg:SI 22))
8556 (clobber (reg:SI 1))
8557 (clobber (reg:SI 2))
8559 (use (const_int 1))])]
8562 (define_insn "*call_val_reg_pic_post_reload"
8563 [(set (match_operand 0 "" "")
8564 (call (mem:SI (reg:SI 22))
8565 (match_operand 1 "" "i")))
8566 (clobber (reg:SI 1))
8567 (clobber (reg:SI 2))
8569 (use (const_int 1))]
8573 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8575 [(set_attr "type" "dyncall")
8576 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8578 ;; This pattern is split if it is necessary to save and restore the
8580 (define_insn "call_val_reg_64bit"
8581 [(set (match_operand 0 "" "")
8582 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8583 (match_operand 2 "" "i")))
8584 (clobber (reg:DI 2))
8585 (clobber (reg:DI 4))
8588 (use (const_int 1))]
8592 return output_indirect_call (insn, operands[1]);
8594 [(set_attr "type" "dyncall")
8595 (set (attr "length")
8596 (plus (symbol_ref "attr_length_indirect_call (insn)")
8597 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8599 ;; Split out the PIC register save and restore after reload. This is
8600 ;; done only if the function returns. As the split is done after reload,
8601 ;; there are some situations in which we unnecessarily save and restore
8602 ;; %r4. This happens when there is a single call and the PIC register
8603 ;; is "dead" after the call. This isn't easy to fix as the usage of
8604 ;; the PIC register isn't completely determined until the reload pass.
8606 [(parallel [(set (match_operand 0 "" "")
8607 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8608 (match_operand 2 "" "")))
8609 (clobber (reg:DI 2))
8610 (clobber (reg:DI 4))
8613 (use (const_int 1))])]
8616 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8617 [(set (reg:DI 4) (reg:DI 27))
8618 (parallel [(set (match_dup 0)
8619 (call (mem:SI (match_dup 1))
8621 (clobber (reg:DI 2))
8624 (use (const_int 1))])
8625 (set (reg:DI 27) (reg:DI 4))]
8628 ;; Remove the clobber of register 4 when optimizing. This has to be
8629 ;; done with a peephole optimization rather than a split because the
8630 ;; split sequence for a call must be longer than one instruction.
8632 [(parallel [(set (match_operand 0 "" "")
8633 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8634 (match_operand 2 "" "")))
8635 (clobber (reg:DI 2))
8636 (clobber (reg:DI 4))
8639 (use (const_int 1))])]
8640 "TARGET_64BIT && reload_completed"
8641 [(parallel [(set (match_dup 0)
8642 (call (mem:SI (match_dup 1))
8644 (clobber (reg:DI 2))
8647 (use (const_int 1))])]
8650 (define_insn "*call_val_reg_64bit_post_reload"
8651 [(set (match_operand 0 "" "")
8652 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8653 (match_operand 2 "" "i")))
8654 (clobber (reg:DI 2))
8657 (use (const_int 1))]
8661 return output_indirect_call (insn, operands[1]);
8663 [(set_attr "type" "dyncall")
8664 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8666 ;; Call subroutine returning any type.
8668 (define_expand "untyped_call"
8669 [(parallel [(call (match_operand 0 "" "")
8671 (match_operand 1 "" "")
8672 (match_operand 2 "" "")])]
8678 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8680 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8682 rtx set = XVECEXP (operands[2], 0, i);
8683 emit_move_insn (SET_DEST (set), SET_SRC (set));
8686 /* The optimizer does not know that the call sets the function value
8687 registers we stored in the result block. We avoid problems by
8688 claiming that all hard registers are used and clobbered at this
8690 emit_insn (gen_blockage ());
8695 (define_expand "sibcall"
8696 [(call (match_operand:SI 0 "" "")
8697 (match_operand 1 "" ""))]
8698 "!TARGET_PORTABLE_RUNTIME"
8702 rtx nb = operands[1];
8704 op = XEXP (operands[0], 0);
8708 if (!virtuals_instantiated)
8709 emit_move_insn (arg_pointer_rtx,
8710 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8714 /* The loop pass can generate new libcalls after the virtual
8715 registers are instantiated when fpregs are disabled because
8716 the only method that we have for doing DImode multiplication
8717 is with a libcall. This could be trouble if we haven't
8718 allocated enough space for the outgoing arguments. */
8719 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8721 emit_move_insn (arg_pointer_rtx,
8722 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8723 GEN_INT (STACK_POINTER_OFFSET + 64)));
8727 /* Indirect sibling calls are not allowed. */
8729 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8731 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8733 call_insn = emit_call_insn (call_insn);
8736 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8738 /* We don't have to restore the PIC register. */
8740 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8745 (define_insn "sibcall_internal_symref"
8746 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8747 (match_operand 1 "" "i"))
8748 (clobber (reg:SI 1))
8750 (use (const_int 0))]
8751 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8754 output_arg_descriptor (insn);
8755 return output_call (insn, operands[0], 1);
8757 [(set_attr "type" "call")
8758 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8760 (define_insn "sibcall_internal_symref_64bit"
8761 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8762 (match_operand 1 "" "i"))
8763 (clobber (reg:DI 1))
8765 (use (const_int 0))]
8769 output_arg_descriptor (insn);
8770 return output_call (insn, operands[0], 1);
8772 [(set_attr "type" "call")
8773 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8775 (define_expand "sibcall_value"
8776 [(set (match_operand 0 "" "")
8777 (call (match_operand:SI 1 "" "")
8778 (match_operand 2 "" "")))]
8779 "!TARGET_PORTABLE_RUNTIME"
8783 rtx nb = operands[1];
8785 op = XEXP (operands[1], 0);
8789 if (!virtuals_instantiated)
8790 emit_move_insn (arg_pointer_rtx,
8791 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8795 /* The loop pass can generate new libcalls after the virtual
8796 registers are instantiated when fpregs are disabled because
8797 the only method that we have for doing DImode multiplication
8798 is with a libcall. This could be trouble if we haven't
8799 allocated enough space for the outgoing arguments. */
8800 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8802 emit_move_insn (arg_pointer_rtx,
8803 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8804 GEN_INT (STACK_POINTER_OFFSET + 64)));
8808 /* Indirect sibling calls are not allowed. */
8811 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8814 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8816 call_insn = emit_call_insn (call_insn);
8819 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8821 /* We don't have to restore the PIC register. */
8823 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8828 (define_insn "sibcall_value_internal_symref"
8829 [(set (match_operand 0 "" "")
8830 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8831 (match_operand 2 "" "i")))
8832 (clobber (reg:SI 1))
8834 (use (const_int 0))]
8835 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8838 output_arg_descriptor (insn);
8839 return output_call (insn, operands[1], 1);
8841 [(set_attr "type" "call")
8842 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8844 (define_insn "sibcall_value_internal_symref_64bit"
8845 [(set (match_operand 0 "" "")
8846 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8847 (match_operand 2 "" "i")))
8848 (clobber (reg:DI 1))
8850 (use (const_int 0))]
8854 output_arg_descriptor (insn);
8855 return output_call (insn, operands[1], 1);
8857 [(set_attr "type" "call")
8858 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8864 [(set_attr "type" "move")
8865 (set_attr "length" "4")])
8867 ;; These are just placeholders so we know where branch tables
8869 (define_insn "begin_brtab"
8874 /* Only GAS actually supports this pseudo-op. */
8876 return \".begin_brtab\";
8880 [(set_attr "type" "move")
8881 (set_attr "length" "0")])
8883 (define_insn "end_brtab"
8888 /* Only GAS actually supports this pseudo-op. */
8890 return \".end_brtab\";
8894 [(set_attr "type" "move")
8895 (set_attr "length" "0")])
8897 ;;; EH does longjmp's from and within the data section. Thus,
8898 ;;; an interspace branch is required for the longjmp implementation.
8899 ;;; Registers r1 and r2 are used as scratch registers for the jump
8901 (define_expand "interspace_jump"
8903 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8904 (clobber (match_dup 1))])]
8908 operands[1] = gen_rtx_REG (word_mode, 2);
8912 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8913 (clobber (reg:SI 2))]
8914 "TARGET_PA_20 && !TARGET_64BIT"
8916 [(set_attr "type" "branch")
8917 (set_attr "length" "4")])
8920 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8921 (clobber (reg:SI 2))]
8922 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8924 [(set_attr "type" "branch")
8925 (set_attr "length" "4")])
8928 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8929 (clobber (reg:SI 2))]
8931 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8932 [(set_attr "type" "branch")
8933 (set_attr "length" "12")])
8936 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8937 (clobber (reg:DI 2))]
8940 [(set_attr "type" "branch")
8941 (set_attr "length" "4")])
8943 (define_expand "builtin_longjmp"
8944 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8948 /* The elements of the buffer are, in order: */
8949 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8950 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8951 POINTER_SIZE / BITS_PER_UNIT));
8952 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8953 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8954 rtx pv = gen_rtx_REG (Pmode, 1);
8956 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8957 gen_rtx_MEM (BLKmode,
8958 gen_rtx_SCRATCH (VOIDmode))));
8959 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8960 gen_rtx_MEM (BLKmode,
8961 hard_frame_pointer_rtx)));
8963 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8964 instead of the hard_frame_pointer_rtx in the save area. We need
8965 to adjust for the offset between these two values when we have
8966 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8967 pattern, the receiver performs the adjustment. */
8968 #ifdef HAVE_nonlocal_goto
8969 if (HAVE_nonlocal_goto)
8970 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8973 emit_move_insn (hard_frame_pointer_rtx, fp);
8975 /* This bit is the same as expand_builtin_longjmp. */
8976 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8977 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8978 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8980 /* Load the label we are jumping through into r1 so that we know
8981 where to look for it when we get back to setjmp's function for
8982 restoring the gp. */
8983 emit_move_insn (pv, lab);
8985 /* Prevent the insns above from being scheduled into the delay slot
8986 of the interspace jump because the space register could change. */
8987 emit_insn (gen_blockage ());
8989 emit_jump_insn (gen_interspace_jump (pv));
8994 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8995 (define_expand "extzv"
8996 [(set (match_operand 0 "register_operand" "")
8997 (zero_extract (match_operand 1 "register_operand" "")
8998 (match_operand 2 "uint32_operand" "")
8999 (match_operand 3 "uint32_operand" "")))]
9003 HOST_WIDE_INT len = INTVAL (operands[2]);
9004 HOST_WIDE_INT pos = INTVAL (operands[3]);
9006 /* PA extraction insns don't support zero length bitfields or fields
9007 extending beyond the left or right-most bits. Also, we reject lengths
9008 equal to a word as they are better handled by the move patterns. */
9009 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9012 /* From mips.md: extract_bit_field doesn't verify that our source
9013 matches the predicate, so check it again here. */
9014 if (!register_operand (operands[1], VOIDmode))
9018 emit_insn (gen_extzv_64 (operands[0], operands[1],
9019 operands[2], operands[3]));
9021 emit_insn (gen_extzv_32 (operands[0], operands[1],
9022 operands[2], operands[3]));
9026 (define_insn "extzv_32"
9027 [(set (match_operand:SI 0 "register_operand" "=r")
9028 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9029 (match_operand:SI 2 "uint5_operand" "")
9030 (match_operand:SI 3 "uint5_operand" "")))]
9032 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
9033 [(set_attr "type" "shift")
9034 (set_attr "length" "4")])
9037 [(set (match_operand:SI 0 "register_operand" "=r")
9038 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9040 (match_operand:SI 2 "register_operand" "q")))]
9042 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
9043 [(set_attr "type" "shift")
9044 (set_attr "length" "4")])
9046 (define_insn "extzv_64"
9047 [(set (match_operand:DI 0 "register_operand" "=r")
9048 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9049 (match_operand:DI 2 "uint32_operand" "")
9050 (match_operand:DI 3 "uint32_operand" "")))]
9052 "extrd,u %1,%3+%2-1,%2,%0"
9053 [(set_attr "type" "shift")
9054 (set_attr "length" "4")])
9057 [(set (match_operand:DI 0 "register_operand" "=r")
9058 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9060 (match_operand:DI 2 "register_operand" "q")))]
9062 "extrd,u %1,%%sar,1,%0"
9063 [(set_attr "type" "shift")
9064 (set_attr "length" "4")])
9066 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
9067 (define_expand "extv"
9068 [(set (match_operand 0 "register_operand" "")
9069 (sign_extract (match_operand 1 "register_operand" "")
9070 (match_operand 2 "uint32_operand" "")
9071 (match_operand 3 "uint32_operand" "")))]
9075 HOST_WIDE_INT len = INTVAL (operands[2]);
9076 HOST_WIDE_INT pos = INTVAL (operands[3]);
9078 /* PA extraction insns don't support zero length bitfields or fields
9079 extending beyond the left or right-most bits. Also, we reject lengths
9080 equal to a word as they are better handled by the move patterns. */
9081 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9084 /* From mips.md: extract_bit_field doesn't verify that our source
9085 matches the predicate, so check it again here. */
9086 if (!register_operand (operands[1], VOIDmode))
9090 emit_insn (gen_extv_64 (operands[0], operands[1],
9091 operands[2], operands[3]));
9093 emit_insn (gen_extv_32 (operands[0], operands[1],
9094 operands[2], operands[3]));
9098 (define_insn "extv_32"
9099 [(set (match_operand:SI 0 "register_operand" "=r")
9100 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9101 (match_operand:SI 2 "uint5_operand" "")
9102 (match_operand:SI 3 "uint5_operand" "")))]
9104 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
9105 [(set_attr "type" "shift")
9106 (set_attr "length" "4")])
9109 [(set (match_operand:SI 0 "register_operand" "=r")
9110 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9112 (match_operand:SI 2 "register_operand" "q")))]
9114 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
9115 [(set_attr "type" "shift")
9116 (set_attr "length" "4")])
9118 (define_insn "extv_64"
9119 [(set (match_operand:DI 0 "register_operand" "=r")
9120 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9121 (match_operand:DI 2 "uint32_operand" "")
9122 (match_operand:DI 3 "uint32_operand" "")))]
9124 "extrd,s %1,%3+%2-1,%2,%0"
9125 [(set_attr "type" "shift")
9126 (set_attr "length" "4")])
9129 [(set (match_operand:DI 0 "register_operand" "=r")
9130 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9132 (match_operand:DI 2 "register_operand" "q")))]
9134 "extrd,s %1,%%sar,1,%0"
9135 [(set_attr "type" "shift")
9136 (set_attr "length" "4")])
9138 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
9139 (define_expand "insv"
9140 [(set (zero_extract (match_operand 0 "register_operand" "")
9141 (match_operand 1 "uint32_operand" "")
9142 (match_operand 2 "uint32_operand" ""))
9143 (match_operand 3 "arith5_operand" ""))]
9147 HOST_WIDE_INT len = INTVAL (operands[1]);
9148 HOST_WIDE_INT pos = INTVAL (operands[2]);
9150 /* PA insertion insns don't support zero length bitfields or fields
9151 extending beyond the left or right-most bits. Also, we reject lengths
9152 equal to a word as they are better handled by the move patterns. */
9153 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9156 /* From mips.md: insert_bit_field doesn't verify that our destination
9157 matches the predicate, so check it again here. */
9158 if (!register_operand (operands[0], VOIDmode))
9162 emit_insn (gen_insv_64 (operands[0], operands[1],
9163 operands[2], operands[3]));
9165 emit_insn (gen_insv_32 (operands[0], operands[1],
9166 operands[2], operands[3]));
9170 (define_insn "insv_32"
9171 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
9172 (match_operand:SI 1 "uint5_operand" "")
9173 (match_operand:SI 2 "uint5_operand" ""))
9174 (match_operand:SI 3 "arith5_operand" "r,L"))]
9177 {dep|depw} %3,%2+%1-1,%1,%0
9178 {depi|depwi} %3,%2+%1-1,%1,%0"
9179 [(set_attr "type" "shift,shift")
9180 (set_attr "length" "4,4")])
9182 ;; Optimize insertion of const_int values of type 1...1xxxx.
9184 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
9185 (match_operand:SI 1 "uint5_operand" "")
9186 (match_operand:SI 2 "uint5_operand" ""))
9187 (match_operand:SI 3 "const_int_operand" ""))]
9188 "(INTVAL (operands[3]) & 0x10) != 0 &&
9189 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9192 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9193 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
9195 [(set_attr "type" "shift")
9196 (set_attr "length" "4")])
9198 (define_insn "insv_64"
9199 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
9200 (match_operand:DI 1 "uint32_operand" "")
9201 (match_operand:DI 2 "uint32_operand" ""))
9202 (match_operand:DI 3 "arith32_operand" "r,L"))]
9205 depd %3,%2+%1-1,%1,%0
9206 depdi %3,%2+%1-1,%1,%0"
9207 [(set_attr "type" "shift,shift")
9208 (set_attr "length" "4,4")])
9210 ;; Optimize insertion of const_int values of type 1...1xxxx.
9212 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9213 (match_operand:DI 1 "uint32_operand" "")
9214 (match_operand:DI 2 "uint32_operand" ""))
9215 (match_operand:DI 3 "const_int_operand" ""))]
9216 "(INTVAL (operands[3]) & 0x10) != 0
9218 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9221 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9222 return \"depdi %3,%2+%1-1,%1,%0\";
9224 [(set_attr "type" "shift")
9225 (set_attr "length" "4")])
9228 [(set (match_operand:DI 0 "register_operand" "=r")
9229 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9232 "depd,z %1,31,32,%0"
9233 [(set_attr "type" "shift")
9234 (set_attr "length" "4")])
9236 ;; This insn is used for some loop tests, typically loops reversed when
9237 ;; strength reduction is used. It is actually created when the instruction
9238 ;; combination phase combines the special loop test. Since this insn
9239 ;; is both a jump insn and has an output, it must deal with its own
9240 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
9241 ;; to not choose the register alternatives in the event a reload is needed.
9242 (define_insn "decrement_and_branch_until_zero"
9245 (match_operator 2 "comparison_operator"
9247 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
9248 (match_operand:SI 1 "int5_operand" "L,L,L"))
9250 (label_ref (match_operand 3 "" ""))
9253 (plus:SI (match_dup 0) (match_dup 1)))
9254 (clobber (match_scratch:SI 4 "=X,r,r"))]
9256 "* return output_dbra (operands, insn, which_alternative); "
9257 ;; Do not expect to understand this the first time through.
9258 [(set_attr "type" "cbranch,multi,multi")
9259 (set (attr "length")
9260 (if_then_else (eq_attr "alternative" "0")
9261 ;; Loop counter in register case
9262 ;; Short branch has length of 4
9263 ;; Long branch has length of 8, 20, 24 or 28
9264 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9265 (const_int MAX_12BIT_OFFSET))
9267 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9268 (const_int MAX_17BIT_OFFSET))
9270 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9272 (eq (symbol_ref "flag_pic") (const_int 0))
9276 ;; Loop counter in FP reg case.
9277 ;; Extra goo to deal with additional reload insns.
9278 (if_then_else (eq_attr "alternative" "1")
9279 (if_then_else (lt (match_dup 3) (pc))
9280 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9281 (const_int MAX_12BIT_OFFSET))
9283 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9284 (const_int MAX_17BIT_OFFSET))
9286 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9288 (eq (symbol_ref "flag_pic") (const_int 0))
9291 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9292 (const_int MAX_12BIT_OFFSET))
9294 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9295 (const_int MAX_17BIT_OFFSET))
9297 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9299 (eq (symbol_ref "flag_pic") (const_int 0))
9303 ;; Loop counter in memory case.
9304 ;; Extra goo to deal with additional reload insns.
9305 (if_then_else (lt (match_dup 3) (pc))
9306 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9307 (const_int MAX_12BIT_OFFSET))
9309 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9310 (const_int MAX_17BIT_OFFSET))
9312 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9314 (eq (symbol_ref "flag_pic") (const_int 0))
9317 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9318 (const_int MAX_12BIT_OFFSET))
9320 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9321 (const_int MAX_17BIT_OFFSET))
9323 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9325 (eq (symbol_ref "flag_pic") (const_int 0))
9327 (const_int 36))))))])
9332 (match_operator 2 "movb_comparison_operator"
9333 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9334 (label_ref (match_operand 3 "" ""))
9336 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9339 "* return output_movb (operands, insn, which_alternative, 0); "
9340 ;; Do not expect to understand this the first time through.
9341 [(set_attr "type" "cbranch,multi,multi,multi")
9342 (set (attr "length")
9343 (if_then_else (eq_attr "alternative" "0")
9344 ;; Loop counter in register case
9345 ;; Short branch has length of 4
9346 ;; Long branch has length of 8, 20, 24 or 28
9347 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9348 (const_int MAX_12BIT_OFFSET))
9350 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9351 (const_int MAX_17BIT_OFFSET))
9353 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9355 (eq (symbol_ref "flag_pic") (const_int 0))
9359 ;; Loop counter in FP reg case.
9360 ;; Extra goo to deal with additional reload insns.
9361 (if_then_else (eq_attr "alternative" "1")
9362 (if_then_else (lt (match_dup 3) (pc))
9363 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9364 (const_int MAX_12BIT_OFFSET))
9366 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9367 (const_int MAX_17BIT_OFFSET))
9369 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9371 (eq (symbol_ref "flag_pic") (const_int 0))
9374 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9375 (const_int MAX_12BIT_OFFSET))
9377 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9378 (const_int MAX_17BIT_OFFSET))
9380 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9382 (eq (symbol_ref "flag_pic") (const_int 0))
9386 ;; Loop counter in memory or sar case.
9387 ;; Extra goo to deal with additional reload insns.
9388 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9389 (const_int MAX_12BIT_OFFSET))
9391 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9392 (const_int MAX_17BIT_OFFSET))
9394 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9396 (eq (symbol_ref "flag_pic") (const_int 0))
9398 (const_int 32)))))])
9400 ;; Handle negated branch.
9404 (match_operator 2 "movb_comparison_operator"
9405 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9407 (label_ref (match_operand 3 "" ""))))
9408 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9411 "* return output_movb (operands, insn, which_alternative, 1); "
9412 ;; Do not expect to understand this the first time through.
9413 [(set_attr "type" "cbranch,multi,multi,multi")
9414 (set (attr "length")
9415 (if_then_else (eq_attr "alternative" "0")
9416 ;; Loop counter in register case
9417 ;; Short branch has length of 4
9418 ;; Long branch has length of 8
9419 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9420 (const_int MAX_12BIT_OFFSET))
9422 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9423 (const_int MAX_17BIT_OFFSET))
9425 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9427 (eq (symbol_ref "flag_pic") (const_int 0))
9431 ;; Loop counter in FP reg case.
9432 ;; Extra goo to deal with additional reload insns.
9433 (if_then_else (eq_attr "alternative" "1")
9434 (if_then_else (lt (match_dup 3) (pc))
9435 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9436 (const_int MAX_12BIT_OFFSET))
9438 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9439 (const_int MAX_17BIT_OFFSET))
9441 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9443 (eq (symbol_ref "flag_pic") (const_int 0))
9446 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9447 (const_int MAX_12BIT_OFFSET))
9449 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9450 (const_int MAX_17BIT_OFFSET))
9452 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9454 (eq (symbol_ref "flag_pic") (const_int 0))
9458 ;; Loop counter in memory or SAR case.
9459 ;; Extra goo to deal with additional reload insns.
9460 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9461 (const_int MAX_12BIT_OFFSET))
9463 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9464 (const_int MAX_17BIT_OFFSET))
9466 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9468 (eq (symbol_ref "flag_pic") (const_int 0))
9470 (const_int 32)))))])
9473 [(set (pc) (label_ref (match_operand 3 "" "" )))
9474 (set (match_operand:SI 0 "ireg_operand" "=r")
9475 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9476 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9477 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9480 return output_parallel_addb (operands, insn);
9482 [(set_attr "type" "parallel_branch")
9483 (set (attr "length")
9484 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9485 (const_int MAX_12BIT_OFFSET))
9487 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9488 (const_int MAX_17BIT_OFFSET))
9490 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9492 (eq (symbol_ref "flag_pic") (const_int 0))
9497 [(set (pc) (label_ref (match_operand 2 "" "" )))
9498 (set (match_operand:SF 0 "ireg_operand" "=r")
9499 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9503 return output_parallel_movb (operands, insn);
9505 [(set_attr "type" "parallel_branch")
9506 (set (attr "length")
9507 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9508 (const_int MAX_12BIT_OFFSET))
9510 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9511 (const_int MAX_17BIT_OFFSET))
9513 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9515 (eq (symbol_ref "flag_pic") (const_int 0))
9520 [(set (pc) (label_ref (match_operand 2 "" "" )))
9521 (set (match_operand:SI 0 "ireg_operand" "=r")
9522 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9526 return output_parallel_movb (operands, insn);
9528 [(set_attr "type" "parallel_branch")
9529 (set (attr "length")
9530 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9531 (const_int MAX_12BIT_OFFSET))
9533 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9534 (const_int MAX_17BIT_OFFSET))
9536 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9538 (eq (symbol_ref "flag_pic") (const_int 0))
9543 [(set (pc) (label_ref (match_operand 2 "" "" )))
9544 (set (match_operand:HI 0 "ireg_operand" "=r")
9545 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9549 return output_parallel_movb (operands, insn);
9551 [(set_attr "type" "parallel_branch")
9552 (set (attr "length")
9553 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9554 (const_int MAX_12BIT_OFFSET))
9556 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9557 (const_int MAX_17BIT_OFFSET))
9559 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9561 (eq (symbol_ref "flag_pic") (const_int 0))
9566 [(set (pc) (label_ref (match_operand 2 "" "" )))
9567 (set (match_operand:QI 0 "ireg_operand" "=r")
9568 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9572 return output_parallel_movb (operands, insn);
9574 [(set_attr "type" "parallel_branch")
9575 (set (attr "length")
9576 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9577 (const_int MAX_12BIT_OFFSET))
9579 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9580 (const_int MAX_17BIT_OFFSET))
9582 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9584 (eq (symbol_ref "flag_pic") (const_int 0))
9589 [(set (match_operand 0 "register_operand" "=f")
9590 (mult (match_operand 1 "register_operand" "f")
9591 (match_operand 2 "register_operand" "f")))
9592 (set (match_operand 3 "register_operand" "+f")
9593 (plus (match_operand 4 "register_operand" "f")
9594 (match_operand 5 "register_operand" "f")))]
9595 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9596 && reload_completed && fmpyaddoperands (operands)"
9599 if (GET_MODE (operands[0]) == DFmode)
9601 if (rtx_equal_p (operands[3], operands[5]))
9602 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9604 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9608 if (rtx_equal_p (operands[3], operands[5]))
9609 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9611 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9614 [(set_attr "type" "fpalu")
9615 (set_attr "length" "4")])
9618 [(set (match_operand 3 "register_operand" "+f")
9619 (plus (match_operand 4 "register_operand" "f")
9620 (match_operand 5 "register_operand" "f")))
9621 (set (match_operand 0 "register_operand" "=f")
9622 (mult (match_operand 1 "register_operand" "f")
9623 (match_operand 2 "register_operand" "f")))]
9624 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9625 && reload_completed && fmpyaddoperands (operands)"
9628 if (GET_MODE (operands[0]) == DFmode)
9630 if (rtx_equal_p (operands[3], operands[5]))
9631 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9633 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9637 if (rtx_equal_p (operands[3], operands[5]))
9638 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9640 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9643 [(set_attr "type" "fpalu")
9644 (set_attr "length" "4")])
9647 [(set (match_operand 0 "register_operand" "=f")
9648 (mult (match_operand 1 "register_operand" "f")
9649 (match_operand 2 "register_operand" "f")))
9650 (set (match_operand 3 "register_operand" "+f")
9651 (minus (match_operand 4 "register_operand" "f")
9652 (match_operand 5 "register_operand" "f")))]
9653 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9654 && reload_completed && fmpysuboperands (operands)"
9657 if (GET_MODE (operands[0]) == DFmode)
9658 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9660 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9662 [(set_attr "type" "fpalu")
9663 (set_attr "length" "4")])
9666 [(set (match_operand 3 "register_operand" "+f")
9667 (minus (match_operand 4 "register_operand" "f")
9668 (match_operand 5 "register_operand" "f")))
9669 (set (match_operand 0 "register_operand" "=f")
9670 (mult (match_operand 1 "register_operand" "f")
9671 (match_operand 2 "register_operand" "f")))]
9672 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9673 && reload_completed && fmpysuboperands (operands)"
9676 if (GET_MODE (operands[0]) == DFmode)
9677 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9679 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9681 [(set_attr "type" "fpalu")
9682 (set_attr "length" "4")])
9684 ;; Flush the I and D cache lines from the start address (operand0)
9685 ;; to the end address (operand1). No lines are flushed if the end
9686 ;; address is less than the start address (unsigned).
9688 ;; Because the range of memory flushed is variable and the size of
9689 ;; a MEM can only be a CONST_INT, the patterns specify that they
9690 ;; perform an unspecified volatile operation on all memory.
9692 ;; The address range for an icache flush must lie within a single
9693 ;; space on targets with non-equivalent space registers.
9695 ;; This is used by the trampoline code for nested functions.
9697 ;; Operand 0 contains the start address.
9698 ;; Operand 1 contains the end address.
9699 ;; Operand 2 contains the line length to use.
9700 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
9701 (define_insn "dcacheflush"
9703 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9704 (use (match_operand 0 "pmode_register_operand" "r"))
9705 (use (match_operand 1 "pmode_register_operand" "r"))
9706 (use (match_operand 2 "pmode_register_operand" "r"))
9707 (clobber (match_scratch 3 "=&0"))]
9712 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9714 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9716 [(set_attr "type" "multi")
9717 (set_attr "length" "12")])
9719 (define_insn "icacheflush"
9721 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9722 (use (match_operand 0 "pmode_register_operand" "r"))
9723 (use (match_operand 1 "pmode_register_operand" "r"))
9724 (use (match_operand 2 "pmode_register_operand" "r"))
9725 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9726 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9727 (clobber (match_scratch 5 "=&0"))]
9732 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9734 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9736 [(set_attr "type" "multi")
9737 (set_attr "length" "52")])
9739 ;; An out-of-line prologue.
9740 (define_insn "outline_prologue_call"
9741 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9742 (clobber (reg:SI 31))
9743 (clobber (reg:SI 22))
9744 (clobber (reg:SI 21))
9745 (clobber (reg:SI 20))
9746 (clobber (reg:SI 19))
9747 (clobber (reg:SI 1))]
9751 extern int frame_pointer_needed;
9753 /* We need two different versions depending on whether or not we
9754 need a frame pointer. Also note that we return to the instruction
9755 immediately after the branch rather than two instructions after the
9756 break as normally is the case. */
9757 if (frame_pointer_needed)
9759 /* Must import the magic millicode routine(s). */
9760 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9762 if (TARGET_PORTABLE_RUNTIME)
9764 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9765 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9769 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9773 /* Must import the magic millicode routine(s). */
9774 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9776 if (TARGET_PORTABLE_RUNTIME)
9778 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9779 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9782 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9786 [(set_attr "type" "multi")
9787 (set_attr "length" "8")])
9789 ;; An out-of-line epilogue.
9790 (define_insn "outline_epilogue_call"
9791 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9794 (clobber (reg:SI 31))
9795 (clobber (reg:SI 22))
9796 (clobber (reg:SI 21))
9797 (clobber (reg:SI 20))
9798 (clobber (reg:SI 19))
9799 (clobber (reg:SI 2))
9800 (clobber (reg:SI 1))]
9804 extern int frame_pointer_needed;
9806 /* We need two different versions depending on whether or not we
9807 need a frame pointer. Also note that we return to the instruction
9808 immediately after the branch rather than two instructions after the
9809 break as normally is the case. */
9810 if (frame_pointer_needed)
9812 /* Must import the magic millicode routine. */
9813 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9815 /* The out-of-line prologue will make sure we return to the right
9817 if (TARGET_PORTABLE_RUNTIME)
9819 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9820 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9824 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9828 /* Must import the magic millicode routine. */
9829 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9831 /* The out-of-line prologue will make sure we return to the right
9833 if (TARGET_PORTABLE_RUNTIME)
9835 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9836 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9839 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9843 [(set_attr "type" "multi")
9844 (set_attr "length" "8")])
9846 ;; Given a function pointer, canonicalize it so it can be
9847 ;; reliably compared to another function pointer. */
9848 (define_expand "canonicalize_funcptr_for_compare"
9849 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9850 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9851 (clobber (match_dup 2))
9852 (clobber (reg:SI 26))
9853 (clobber (reg:SI 22))
9854 (clobber (reg:SI 31))])
9855 (set (match_operand:SI 0 "register_operand" "")
9857 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9862 rtx canonicalize_funcptr_for_compare_libfunc
9863 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9865 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9866 operands[0], LCT_NORMAL, Pmode,
9867 1, operands[1], Pmode);
9871 operands[2] = gen_reg_rtx (SImode);
9872 if (GET_CODE (operands[1]) != REG)
9874 rtx tmp = gen_reg_rtx (Pmode);
9875 emit_move_insn (tmp, operands[1]);
9880 (define_insn "*$$sh_func_adrs"
9881 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9882 (clobber (match_operand:SI 0 "register_operand" "=a"))
9883 (clobber (reg:SI 26))
9884 (clobber (reg:SI 22))
9885 (clobber (reg:SI 31))]
9889 int length = get_attr_length (insn);
9892 xoperands[0] = GEN_INT (length - 8);
9893 xoperands[1] = GEN_INT (length - 16);
9895 /* Must import the magic millicode routine. */
9896 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9898 /* This is absolutely amazing.
9900 First, copy our input parameter into %r29 just in case we don't
9901 need to call $$sh_func_adrs. */
9902 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9903 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9905 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9906 we use %r26 unchanged. */
9907 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9908 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9910 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9911 4096, then again we use %r26 unchanged. */
9912 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9914 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9915 return output_millicode_call (insn,
9916 gen_rtx_SYMBOL_REF (SImode,
9917 \"$$sh_func_adrs\"));
9919 [(set_attr "type" "multi")
9920 (set (attr "length")
9921 (plus (symbol_ref "attr_length_millicode_call (insn)")
9924 ;; On the PA, the PIC register is call clobbered, so it must
9925 ;; be saved & restored around calls by the caller. If the call
9926 ;; doesn't return normally (nonlocal goto, or an exception is
9927 ;; thrown), then the code at the exception handler label must
9928 ;; restore the PIC register.
9929 (define_expand "exception_receiver"
9934 /* On the 64-bit port, we need a blockage because there is
9935 confusion regarding the dependence of the restore on the
9936 frame pointer. As a result, the frame pointer and pic
9937 register restores sometimes are interchanged erroneously. */
9939 emit_insn (gen_blockage ());
9940 /* Restore the PIC register using hppa_pic_save_rtx (). The
9941 PIC register is not saved in the frame in 64-bit ABI. */
9942 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9943 emit_insn (gen_blockage ());
9947 (define_expand "builtin_setjmp_receiver"
9948 [(label_ref (match_operand 0 "" ""))]
9953 emit_insn (gen_blockage ());
9954 /* Restore the PIC register. Hopefully, this will always be from
9955 a stack slot. The only registers that are valid after a
9956 builtin_longjmp are the stack and frame pointers. */
9957 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9958 emit_insn (gen_blockage ());
9962 ;; Allocate new stack space and update the saved stack pointer in the
9963 ;; frame marker. The HP C compilers also copy additional words in the
9964 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9965 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9966 ;; currently don't copy these values.
9968 ;; Since the copy of the frame marker can't be done atomically, I
9969 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9970 ;; The HP compilers appear to raise the stack and copy the frame
9971 ;; marker in a strict instruction sequence. This suggests that the
9972 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9973 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9974 ;; as GAS doesn't support it, or try to keep the instructions emitted
9975 ;; here in strict sequence.
9976 (define_expand "allocate_stack"
9977 [(match_operand 0 "" "")
9978 (match_operand 1 "" "")]
9984 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9985 in operand 0 before adjusting the stack. */
9986 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9987 anti_adjust_stack (operands[1]);
9988 if (TARGET_HPUX_UNWIND_LIBRARY)
9990 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9991 GEN_INT (TARGET_64BIT ? -8 : -4));
9992 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9994 if (!TARGET_64BIT && flag_pic)
9996 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9997 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
10002 (define_expand "prefetch"
10003 [(match_operand 0 "address_operand" "")
10004 (match_operand 1 "const_int_operand" "")
10005 (match_operand 2 "const_int_operand" "")]
10008 int locality = INTVAL (operands[2]);
10010 gcc_assert (locality >= 0 && locality <= 3);
10012 /* Change operand[0] to a MEM as we don't have the infrastructure
10013 to output all the supported address modes for ldw/ldd when we use
10014 the address directly. However, we do have it for MEMs. */
10015 operands[0] = gen_rtx_MEM (QImode, operands[0]);
10017 /* If the address isn't valid for the prefetch, replace it. */
10020 if (!prefetch_nocc_operand (operands[0], QImode))
10022 = replace_equiv_address (operands[0],
10023 copy_to_mode_reg (Pmode,
10024 XEXP (operands[0], 0)));
10025 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
10029 if (!prefetch_cc_operand (operands[0], QImode))
10031 = replace_equiv_address (operands[0],
10032 copy_to_mode_reg (Pmode,
10033 XEXP (operands[0], 0)));
10034 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
10039 (define_insn "prefetch_cc"
10040 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
10041 (match_operand:SI 1 "const_int_operand" "n")
10042 (match_operand:SI 2 "const_int_operand" "n"))]
10043 "TARGET_PA_20 && operands[2] == const0_rtx"
10045 /* The SL cache-control completor indicates good spatial locality but
10046 poor temporal locality. The ldw instruction with a target of general
10047 register 0 prefetches a cache line for a read. The ldd instruction
10048 prefetches a cache line for a write. */
10049 static const char * const instr[2] = {
10050 "ldw%M0,sl %0,%%r0",
10051 "ldd%M0,sl %0,%%r0"
10053 int read_or_write = INTVAL (operands[1]);
10055 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10057 return instr [read_or_write];
10059 [(set_attr "type" "load")
10060 (set_attr "length" "4")])
10062 (define_insn "prefetch_nocc"
10063 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
10064 (match_operand:SI 1 "const_int_operand" "n,n")
10065 (match_operand:SI 2 "const_int_operand" "n,n"))]
10066 "TARGET_PA_20 && operands[2] != const0_rtx"
10068 /* The ldw instruction with a target of general register 0 prefetches
10069 a cache line for a read. The ldd instruction prefetches a cache line
10071 static const char * const instr[2][2] = {
10081 int read_or_write = INTVAL (operands[1]);
10083 gcc_assert (which_alternative == 0 || which_alternative == 1);
10084 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10086 return instr [which_alternative][read_or_write];
10088 [(set_attr "type" "load")
10089 (set_attr "length" "4")])
10093 (define_insn "tgd_load"
10094 [(set (match_operand:SI 0 "register_operand" "=r")
10095 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
10096 (clobber (reg:SI 1))]
10101 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
10103 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
10105 [(set_attr "type" "multi")
10106 (set_attr "length" "8")])
10108 (define_insn "tld_load"
10109 [(set (match_operand:SI 0 "register_operand" "=r")
10110 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
10111 (clobber (reg:SI 1))]
10116 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
10118 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
10120 [(set_attr "type" "multi")
10121 (set_attr "length" "8")])
10123 (define_insn "tld_offset_load"
10124 [(set (match_operand:SI 0 "register_operand" "=r")
10125 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
10127 (match_operand:SI 2 "register_operand" "r")))
10128 (clobber (reg:SI 1))]
10132 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
10134 [(set_attr "type" "multi")
10135 (set_attr "length" "8")])
10137 (define_insn "tp_load"
10138 [(set (match_operand:SI 0 "register_operand" "=r")
10139 (unspec:SI [(const_int 0)] UNSPEC_TP))]
10142 [(set_attr "type" "multi")
10143 (set_attr "length" "4")])
10145 (define_insn "tie_load"
10146 [(set (match_operand:SI 0 "register_operand" "=r")
10147 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
10148 (clobber (reg:SI 1))]
10153 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
10155 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
10157 [(set_attr "type" "multi")
10158 (set_attr "length" "8")])
10160 (define_insn "tle_load"
10161 [(set (match_operand:SI 0 "register_operand" "=r")
10162 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
10164 (match_operand:SI 2 "register_operand" "r")))
10165 (clobber (reg:SI 1))]
10167 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
10168 [(set_attr "type" "multi")
10169 (set_attr "length" "8")])