1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; This gcc Version 2 machine description is inspired by sparc.md and
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Uses of UNSPEC in this file:
31 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
32 (UNSPEC_GOTO 1) ; indirect_goto
33 (UNSPEC_DLTIND14R 2) ;
42 (UNSPEC_TLSLDM_PIC 11)
49 [(UNSPECV_BLOCKAGE 0) ; blockage
50 (UNSPECV_DCACHE 1) ; dcacheflush
51 (UNSPECV_ICACHE 2) ; icacheflush
52 (UNSPECV_OPC 3) ; outline_prologue_call
53 (UNSPECV_OEC 4) ; outline_epilogue_call
54 (UNSPECV_LONGJMP 5) ; builtin_longjmp
57 ;; Maximum pc-relative branch offsets.
59 ;; These numbers are a bit smaller than the maximum allowable offsets
60 ;; so that a few instructions may be inserted before the actual branch.
63 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
64 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
67 ;; Mode and code iterators
69 ;; This mode iterator allows :P to be used for patterns that operate on
70 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
71 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
73 ;; This attribute defines the condition prefix for word and double word
74 ;; add, compare, subtract and logical instructions.
75 (define_mode_attr dwc [(SI "") (DI "*")])
77 ;; Insn type. Used to default other attribute values.
79 ;; type "unary" insns have one input operand (1) and one output operand (0)
80 ;; type "binary" insns have two input operands (1,2) and one output (0)
83 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
84 (const_string "binary"))
86 (define_attr "pa_combine_type"
87 "fmpy,faddsub,uncond_branch,addmove,none"
88 (const_string "none"))
90 ;; Processor type (for scheduling, not code generation) -- this attribute
91 ;; must exactly match the processor_type enumeration in pa.h.
93 ;; FIXME: Add 800 scheduling for completeness?
95 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
97 ;; Length (in # of bytes).
98 (define_attr "length" ""
99 (cond [(eq_attr "type" "load,fpload")
100 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
101 (const_int 8) (const_int 4))
103 (eq_attr "type" "store,fpstore")
104 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
105 (const_int 8) (const_int 4))
107 (eq_attr "type" "binary,shift,nullshift")
108 (if_then_else (match_operand 2 "arith_operand" "")
109 (const_int 4) (const_int 12))
111 (eq_attr "type" "move,unary,shift,nullshift")
112 (if_then_else (match_operand 1 "arith_operand" "")
113 (const_int 4) (const_int 8))]
117 (define_asm_attributes
118 [(set_attr "length" "4")
119 (set_attr "type" "multi")])
121 ;; Attributes for instruction and branch scheduling
123 ;; For conditional branches.
124 (define_attr "in_branch_delay" "false,true"
125 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
126 (eq_attr "length" "4"))
127 (const_string "true")
128 (const_string "false")))
130 ;; Disallow instructions which use the FPU since they will tie up the FPU
131 ;; even if the instruction is nullified.
132 (define_attr "in_nullified_branch_delay" "false,true"
133 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
134 (eq_attr "length" "4"))
135 (const_string "true")
136 (const_string "false")))
138 ;; For calls and millicode calls. Allow unconditional branches in the
140 (define_attr "in_call_delay" "false,true"
141 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
142 (eq_attr "length" "4"))
143 (const_string "true")
144 (eq_attr "type" "uncond_branch")
145 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
147 (const_string "true")
148 (const_string "false"))]
149 (const_string "false")))
152 ;; Call delay slot description.
153 (define_delay (eq_attr "type" "call")
154 [(eq_attr "in_call_delay" "true") (nil) (nil)])
156 ;; Millicode call delay slot description.
157 (define_delay (eq_attr "type" "milli")
158 [(eq_attr "in_call_delay" "true") (nil) (nil)])
160 ;; Return and other similar instructions.
161 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
162 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
164 ;; Floating point conditional branch delay slot description.
165 (define_delay (eq_attr "type" "fbranch")
166 [(eq_attr "in_branch_delay" "true")
167 (eq_attr "in_nullified_branch_delay" "true")
170 ;; Integer conditional branch delay slot description.
171 ;; Nullification of conditional branches on the PA is dependent on the
172 ;; direction of the branch. Forward branches nullify true and
173 ;; backward branches nullify false. If the direction is unknown
174 ;; then nullification is not allowed.
175 (define_delay (eq_attr "type" "cbranch")
176 [(eq_attr "in_branch_delay" "true")
177 (and (eq_attr "in_nullified_branch_delay" "true")
178 (attr_flag "forward"))
179 (and (eq_attr "in_nullified_branch_delay" "true")
180 (attr_flag "backward"))])
182 (define_delay (and (eq_attr "type" "uncond_branch")
183 (eq (symbol_ref "following_call (insn)")
185 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
187 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
188 ;; load: 2, fpload: 3
189 ;; store, fpstore: 3, no D-cache operations should be scheduled.
191 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
193 ;; Instruction Time Unit Minimum Distance (unit contention)
200 ;; fmpyadd 3 ALU,MPY 2
201 ;; fmpysub 3 ALU,MPY 2
202 ;; fmpycfxt 3 ALU,MPY 2
205 ;; fdiv,sgl 10 MPY 10
206 ;; fdiv,dbl 12 MPY 12
207 ;; fsqrt,sgl 14 MPY 14
208 ;; fsqrt,dbl 18 MPY 18
210 ;; We don't model fmpyadd/fmpysub properly as those instructions
211 ;; keep both the FP ALU and MPY units busy. Given that these
212 ;; processors are obsolete, I'm not going to spend the time to
213 ;; model those instructions correctly.
215 (define_automaton "pa700")
216 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
218 (define_insn_reservation "W0" 4
219 (and (eq_attr "type" "fpcc")
220 (eq_attr "cpu" "700"))
223 (define_insn_reservation "W1" 3
224 (and (eq_attr "type" "fpalu")
225 (eq_attr "cpu" "700"))
228 (define_insn_reservation "W2" 3
229 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
230 (eq_attr "cpu" "700"))
233 (define_insn_reservation "W3" 10
234 (and (eq_attr "type" "fpdivsgl")
235 (eq_attr "cpu" "700"))
238 (define_insn_reservation "W4" 12
239 (and (eq_attr "type" "fpdivdbl")
240 (eq_attr "cpu" "700"))
243 (define_insn_reservation "W5" 14
244 (and (eq_attr "type" "fpsqrtsgl")
245 (eq_attr "cpu" "700"))
248 (define_insn_reservation "W6" 18
249 (and (eq_attr "type" "fpsqrtdbl")
250 (eq_attr "cpu" "700"))
253 (define_insn_reservation "W7" 2
254 (and (eq_attr "type" "load")
255 (eq_attr "cpu" "700"))
258 (define_insn_reservation "W8" 2
259 (and (eq_attr "type" "fpload")
260 (eq_attr "cpu" "700"))
263 (define_insn_reservation "W9" 3
264 (and (eq_attr "type" "store")
265 (eq_attr "cpu" "700"))
268 (define_insn_reservation "W10" 3
269 (and (eq_attr "type" "fpstore")
270 (eq_attr "cpu" "700"))
273 (define_insn_reservation "W11" 5
274 (and (eq_attr "type" "fpstore_load")
275 (eq_attr "cpu" "700"))
278 (define_insn_reservation "W12" 6
279 (and (eq_attr "type" "store_fpload")
280 (eq_attr "cpu" "700"))
283 (define_insn_reservation "W13" 1
284 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
285 (eq_attr "cpu" "700"))
288 ;; We have a bypass for all computations in the FP unit which feed an
289 ;; FP store as long as the sizes are the same.
290 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
291 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
292 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
293 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
294 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
296 ;; We have an "anti-bypass" for FP loads which feed an FP store.
297 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
299 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
300 ;; floating point computations with non-floating point computations (fp loads
301 ;; and stores are not fp computations).
303 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
304 ;; take two cycles, during which no Dcache operations should be scheduled.
305 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
306 ;; all have the same memory characteristics if one disregards cache misses.
308 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
309 ;; There's no value in modeling the ALU and MUL separately though
310 ;; since there can never be a functional unit conflict given the
311 ;; latency and issue rates for those units.
314 ;; Instruction Time Unit Minimum Distance (unit contention)
321 ;; fmpyadd 2 ALU,MPY 1
322 ;; fmpysub 2 ALU,MPY 1
323 ;; fmpycfxt 2 ALU,MPY 1
327 ;; fdiv,dbl 15 DIV 15
329 ;; fsqrt,dbl 15 DIV 15
331 (define_automaton "pa7100")
332 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
334 (define_insn_reservation "X0" 2
335 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
336 (eq_attr "cpu" "7100"))
339 (define_insn_reservation "X1" 8
340 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
341 (eq_attr "cpu" "7100"))
342 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
344 (define_insn_reservation "X2" 15
345 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
346 (eq_attr "cpu" "7100"))
347 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
349 (define_insn_reservation "X3" 2
350 (and (eq_attr "type" "load")
351 (eq_attr "cpu" "7100"))
354 (define_insn_reservation "X4" 2
355 (and (eq_attr "type" "fpload")
356 (eq_attr "cpu" "7100"))
359 (define_insn_reservation "X5" 2
360 (and (eq_attr "type" "store")
361 (eq_attr "cpu" "7100"))
362 "i_7100+mem_7100,mem_7100")
364 (define_insn_reservation "X6" 2
365 (and (eq_attr "type" "fpstore")
366 (eq_attr "cpu" "7100"))
367 "i_7100+mem_7100,mem_7100")
369 (define_insn_reservation "X7" 4
370 (and (eq_attr "type" "fpstore_load")
371 (eq_attr "cpu" "7100"))
372 "i_7100+mem_7100,mem_7100*3")
374 (define_insn_reservation "X8" 4
375 (and (eq_attr "type" "store_fpload")
376 (eq_attr "cpu" "7100"))
377 "i_7100+mem_7100,mem_7100*3")
379 (define_insn_reservation "X9" 1
380 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
381 (eq_attr "cpu" "7100"))
384 ;; We have a bypass for all computations in the FP unit which feed an
385 ;; FP store as long as the sizes are the same.
386 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
387 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
388 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
390 ;; We have an "anti-bypass" for FP loads which feed an FP store.
391 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
393 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
394 ;; There's no value in modeling the ALU and MUL separately though
395 ;; since there can never be a functional unit conflict that
396 ;; can be avoided given the latency, issue rates and mandatory
397 ;; one cycle cpu-wide lock for a double precision fp multiply.
400 ;; Instruction Time Unit Minimum Distance (unit contention)
407 ;; fmpyadd,sgl 2 ALU,MPY 1
408 ;; fmpyadd,dbl 3 ALU,MPY 2
409 ;; fmpysub,sgl 2 ALU,MPY 1
410 ;; fmpysub,dbl 3 ALU,MPY 2
411 ;; fmpycfxt,sgl 2 ALU,MPY 1
412 ;; fmpycfxt,dbl 3 ALU,MPY 2
417 ;; fdiv,dbl 15 DIV 15
419 ;; fsqrt,dbl 15 DIV 15
421 ;; The PA7200 is just like the PA7100LC except that there is
422 ;; no store-store penalty.
424 ;; The PA7300 is just like the PA7200 except that there is
425 ;; no store-load penalty.
427 ;; Note there are some aspects of the 7100LC we are not modeling
428 ;; at the moment. I'll be reviewing the 7100LC scheduling info
429 ;; shortly and updating this description.
433 ;; other issue modeling
435 (define_automaton "pa7100lc")
436 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
437 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
438 (define_cpu_unit "mem_7100lc" "pa7100lc")
440 ;; Double precision multiplies lock the entire CPU for one
441 ;; cycle. There is no way to avoid this lock and trying to
442 ;; schedule around the lock is pointless and thus there is no
443 ;; value in trying to model this lock.
445 ;; Not modeling the lock allows us to treat fp multiplies just
446 ;; like any other FP alu instruction. It allows for a smaller
447 ;; DFA and may reduce register pressure.
448 (define_insn_reservation "Y0" 2
449 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
450 (eq_attr "cpu" "7100LC,7200,7300"))
451 "f_7100lc,fpmac_7100lc")
453 ;; fp division and sqrt instructions lock the entire CPU for
454 ;; 7 cycles (single precision) or 14 cycles (double precision).
455 ;; There is no way to avoid this lock and trying to schedule
456 ;; around the lock is pointless and thus there is no value in
457 ;; trying to model this lock. Not modeling the lock allows
458 ;; for a smaller DFA and may reduce register pressure.
459 (define_insn_reservation "Y1" 1
460 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
461 (eq_attr "cpu" "7100LC,7200,7300"))
464 (define_insn_reservation "Y2" 2
465 (and (eq_attr "type" "load")
466 (eq_attr "cpu" "7100LC,7200,7300"))
467 "i1_7100lc+mem_7100lc")
469 (define_insn_reservation "Y3" 2
470 (and (eq_attr "type" "fpload")
471 (eq_attr "cpu" "7100LC,7200,7300"))
472 "i1_7100lc+mem_7100lc")
474 (define_insn_reservation "Y4" 2
475 (and (eq_attr "type" "store")
476 (eq_attr "cpu" "7100LC"))
477 "i1_7100lc+mem_7100lc,mem_7100lc")
479 (define_insn_reservation "Y5" 2
480 (and (eq_attr "type" "fpstore")
481 (eq_attr "cpu" "7100LC"))
482 "i1_7100lc+mem_7100lc,mem_7100lc")
484 (define_insn_reservation "Y6" 4
485 (and (eq_attr "type" "fpstore_load")
486 (eq_attr "cpu" "7100LC"))
487 "i1_7100lc+mem_7100lc,mem_7100lc*3")
489 (define_insn_reservation "Y7" 4
490 (and (eq_attr "type" "store_fpload")
491 (eq_attr "cpu" "7100LC"))
492 "i1_7100lc+mem_7100lc,mem_7100lc*3")
494 (define_insn_reservation "Y8" 1
495 (and (eq_attr "type" "shift,nullshift")
496 (eq_attr "cpu" "7100LC,7200,7300"))
499 (define_insn_reservation "Y9" 1
500 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
501 (eq_attr "cpu" "7100LC,7200,7300"))
502 "(i0_7100lc|i1_7100lc)")
504 ;; The 7200 has a store-load penalty
505 (define_insn_reservation "Y10" 2
506 (and (eq_attr "type" "store")
507 (eq_attr "cpu" "7200"))
508 "i1_7100lc,mem_7100lc")
510 (define_insn_reservation "Y11" 2
511 (and (eq_attr "type" "fpstore")
512 (eq_attr "cpu" "7200"))
513 "i1_7100lc,mem_7100lc")
515 (define_insn_reservation "Y12" 4
516 (and (eq_attr "type" "fpstore_load")
517 (eq_attr "cpu" "7200"))
518 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
520 (define_insn_reservation "Y13" 4
521 (and (eq_attr "type" "store_fpload")
522 (eq_attr "cpu" "7200"))
523 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
525 ;; The 7300 has no penalty for store-store or store-load
526 (define_insn_reservation "Y14" 2
527 (and (eq_attr "type" "store")
528 (eq_attr "cpu" "7300"))
531 (define_insn_reservation "Y15" 2
532 (and (eq_attr "type" "fpstore")
533 (eq_attr "cpu" "7300"))
536 (define_insn_reservation "Y16" 4
537 (and (eq_attr "type" "fpstore_load")
538 (eq_attr "cpu" "7300"))
539 "i1_7100lc,i1_7100lc+mem_7100lc")
541 (define_insn_reservation "Y17" 4
542 (and (eq_attr "type" "store_fpload")
543 (eq_attr "cpu" "7300"))
544 "i1_7100lc,i1_7100lc+mem_7100lc")
546 ;; We have an "anti-bypass" for FP loads which feed an FP store.
547 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
549 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
550 ;; traditional architecture.
552 ;; The PA8000 has a large (56) entry reorder buffer that is split between
553 ;; memory and non-memory operations.
555 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
556 ;; the function units, with the exception of branches and multi-output
557 ;; instructions. The PA8000 can retire two non-memory operations per cycle
558 ;; and two memory operations per cycle, only one of which may be a store.
560 ;; Given the large reorder buffer, the processor can hide most latencies.
561 ;; According to HP, they've got the best results by scheduling for retirement
562 ;; bandwidth with limited latency scheduling for floating point operations.
563 ;; Latency for integer operations and memory references is ignored.
566 ;; We claim floating point operations have a 2 cycle latency and are
567 ;; fully pipelined, except for div and sqrt which are not pipelined and
568 ;; take from 17 to 31 cycles to complete.
570 ;; It's worth noting that there is no way to saturate all the functional
571 ;; units on the PA8000 as there is not enough issue bandwidth.
573 (define_automaton "pa8000")
574 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
575 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
576 (define_cpu_unit "store_8000" "pa8000")
577 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
578 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
579 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
580 (define_reservation "im_8000" "im0_8000 | im1_8000")
581 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
582 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
583 (define_reservation "f_8000" "f0_8000 | f1_8000")
584 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
586 ;; We can issue any two memops per cycle, but we can only retire
587 ;; one memory store per cycle. We assume that the reorder buffer
588 ;; will hide any memory latencies per HP's recommendation.
589 (define_insn_reservation "Z0" 0
591 (eq_attr "type" "load,fpload")
592 (eq_attr "cpu" "8000"))
595 (define_insn_reservation "Z1" 0
597 (eq_attr "type" "store,fpstore")
598 (eq_attr "cpu" "8000"))
599 "im_8000,rm_8000+store_8000")
601 (define_insn_reservation "Z2" 0
602 (and (eq_attr "type" "fpstore_load,store_fpload")
603 (eq_attr "cpu" "8000"))
604 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
606 ;; We can issue and retire two non-memory operations per cycle with
607 ;; a few exceptions (branches). This group catches those we want
608 ;; to assume have zero latency.
609 (define_insn_reservation "Z3" 0
611 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
612 (eq_attr "cpu" "8000"))
615 ;; Branches use both slots in the non-memory issue and
617 (define_insn_reservation "Z4" 0
619 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
620 (eq_attr "cpu" "8000"))
621 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
623 ;; We partial latency schedule the floating point units.
624 ;; They can issue/retire two at a time in the non-memory
625 ;; units. We fix their latency at 2 cycles and they
626 ;; are fully pipelined.
627 (define_insn_reservation "Z5" 1
629 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
630 (eq_attr "cpu" "8000"))
631 "inm_8000,f_8000,rnm_8000")
633 ;; The fdivsqrt units are not pipelined and have a very long latency.
634 ;; To keep the DFA from exploding, we do not show all the
635 ;; reservations for the divsqrt unit.
636 (define_insn_reservation "Z6" 17
638 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
639 (eq_attr "cpu" "8000"))
640 "inm_8000,fdivsqrt_8000*6,rnm_8000")
642 (define_insn_reservation "Z7" 31
644 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
645 (eq_attr "cpu" "8000"))
646 "inm_8000,fdivsqrt_8000*6,rnm_8000")
648 ;; Operand and operator predicates and constraints
650 (include "predicates.md")
651 (include "constraints.md")
653 ;; Compare instructions.
654 ;; This controls RTL generation and register allocation.
656 ;; We generate RTL for comparisons and branches by having the cmpxx
657 ;; patterns store away the operands. Then, the scc and bcc patterns
658 ;; emit RTL for both the compare and the branch.
661 (define_expand "cmpdi"
663 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
664 (match_operand:DI 1 "register_operand" "")))]
669 hppa_compare_op0 = operands[0];
670 hppa_compare_op1 = operands[1];
671 hppa_branch_type = CMP_SI;
675 (define_expand "cmpsi"
677 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
678 (match_operand:SI 1 "arith5_operand" "")))]
682 hppa_compare_op0 = operands[0];
683 hppa_compare_op1 = operands[1];
684 hppa_branch_type = CMP_SI;
688 (define_expand "cmpsf"
690 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
691 (match_operand:SF 1 "reg_or_0_operand" "")))]
692 "! TARGET_SOFT_FLOAT"
695 hppa_compare_op0 = operands[0];
696 hppa_compare_op1 = operands[1];
697 hppa_branch_type = CMP_SF;
701 (define_expand "cmpdf"
703 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
704 (match_operand:DF 1 "reg_or_0_operand" "")))]
705 "! TARGET_SOFT_FLOAT"
708 hppa_compare_op0 = operands[0];
709 hppa_compare_op1 = operands[1];
710 hppa_branch_type = CMP_DF;
716 (match_operator:CCFP 2 "comparison_operator"
717 [(match_operand:SF 0 "reg_or_0_operand" "fG")
718 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
719 "! TARGET_SOFT_FLOAT"
720 "fcmp,sgl,%Y2 %f0,%f1"
721 [(set_attr "length" "4")
722 (set_attr "type" "fpcc")])
726 (match_operator:CCFP 2 "comparison_operator"
727 [(match_operand:DF 0 "reg_or_0_operand" "fG")
728 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
729 "! TARGET_SOFT_FLOAT"
730 "fcmp,dbl,%Y2 %f0,%f1"
731 [(set_attr "length" "4")
732 (set_attr "type" "fpcc")])
734 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
735 ;; placeholders. This is necessary in rare situations when a
736 ;; placeholder is re-emitted (see PR 8705).
738 (define_expand "movccfp"
740 (match_operand 0 "const_int_operand" ""))]
741 "! TARGET_SOFT_FLOAT"
744 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
748 ;; The following patterns are optimization placeholders. In almost
749 ;; all cases, the user of the condition code will be simplified and the
750 ;; original condition code setting insn should be eliminated.
752 (define_insn "*movccfp0"
755 "! TARGET_SOFT_FLOAT"
756 "fcmp,dbl,= %%fr0,%%fr0"
757 [(set_attr "length" "4")
758 (set_attr "type" "fpcc")])
760 (define_insn "*movccfp1"
763 "! TARGET_SOFT_FLOAT"
764 "fcmp,dbl,!= %%fr0,%%fr0"
765 [(set_attr "length" "4")
766 (set_attr "type" "fpcc")])
771 [(set (match_operand:SI 0 "register_operand" "")
777 /* fp scc patterns rarely match, and are not a win on the PA. */
778 if (hppa_branch_type != CMP_SI)
780 /* set up operands from compare. */
781 operands[1] = hppa_compare_op0;
782 operands[2] = hppa_compare_op1;
783 /* fall through and generate default code */
787 [(set (match_operand:SI 0 "register_operand" "")
793 /* fp scc patterns rarely match, and are not a win on the PA. */
794 if (hppa_branch_type != CMP_SI)
796 operands[1] = hppa_compare_op0;
797 operands[2] = hppa_compare_op1;
801 [(set (match_operand:SI 0 "register_operand" "")
807 /* fp scc patterns rarely match, and are not a win on the PA. */
808 if (hppa_branch_type != CMP_SI)
810 operands[1] = hppa_compare_op0;
811 operands[2] = hppa_compare_op1;
815 [(set (match_operand:SI 0 "register_operand" "")
821 /* fp scc patterns rarely match, and are not a win on the PA. */
822 if (hppa_branch_type != CMP_SI)
824 operands[1] = hppa_compare_op0;
825 operands[2] = hppa_compare_op1;
829 [(set (match_operand:SI 0 "register_operand" "")
835 /* fp scc patterns rarely match, and are not a win on the PA. */
836 if (hppa_branch_type != CMP_SI)
838 operands[1] = hppa_compare_op0;
839 operands[2] = hppa_compare_op1;
843 [(set (match_operand:SI 0 "register_operand" "")
849 /* fp scc patterns rarely match, and are not a win on the PA. */
850 if (hppa_branch_type != CMP_SI)
852 operands[1] = hppa_compare_op0;
853 operands[2] = hppa_compare_op1;
856 (define_expand "sltu"
857 [(set (match_operand:SI 0 "register_operand" "")
858 (ltu:SI (match_dup 1)
863 if (hppa_branch_type != CMP_SI)
865 operands[1] = hppa_compare_op0;
866 operands[2] = hppa_compare_op1;
869 (define_expand "sgtu"
870 [(set (match_operand:SI 0 "register_operand" "")
871 (gtu:SI (match_dup 1)
876 if (hppa_branch_type != CMP_SI)
878 operands[1] = hppa_compare_op0;
879 operands[2] = hppa_compare_op1;
882 (define_expand "sleu"
883 [(set (match_operand:SI 0 "register_operand" "")
884 (leu:SI (match_dup 1)
889 if (hppa_branch_type != CMP_SI)
891 operands[1] = hppa_compare_op0;
892 operands[2] = hppa_compare_op1;
895 (define_expand "sgeu"
896 [(set (match_operand:SI 0 "register_operand" "")
897 (geu:SI (match_dup 1)
902 if (hppa_branch_type != CMP_SI)
904 operands[1] = hppa_compare_op0;
905 operands[2] = hppa_compare_op1;
908 ;; Instruction canonicalization puts immediate operands second, which
909 ;; is the reverse of what we want.
912 [(set (match_operand:SI 0 "register_operand" "=r")
913 (match_operator:SI 3 "comparison_operator"
914 [(match_operand:SI 1 "register_operand" "r")
915 (match_operand:SI 2 "arith11_operand" "rI")]))]
917 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
922 [(set (match_operand:DI 0 "register_operand" "=r")
923 (match_operator:DI 3 "comparison_operator"
924 [(match_operand:DI 1 "register_operand" "r")
925 (match_operand:DI 2 "arith11_operand" "rI")]))]
927 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
928 [(set_attr "type" "binary")
929 (set_attr "length" "8")])
931 (define_insn "iorscc"
932 [(set (match_operand:SI 0 "register_operand" "=r")
933 (ior:SI (match_operator:SI 3 "comparison_operator"
934 [(match_operand:SI 1 "register_operand" "r")
935 (match_operand:SI 2 "arith11_operand" "rI")])
936 (match_operator:SI 6 "comparison_operator"
937 [(match_operand:SI 4 "register_operand" "r")
938 (match_operand:SI 5 "arith11_operand" "rI")])))]
940 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "12")])
945 [(set (match_operand:DI 0 "register_operand" "=r")
946 (ior:DI (match_operator:DI 3 "comparison_operator"
947 [(match_operand:DI 1 "register_operand" "r")
948 (match_operand:DI 2 "arith11_operand" "rI")])
949 (match_operator:DI 6 "comparison_operator"
950 [(match_operand:DI 4 "register_operand" "r")
951 (match_operand:DI 5 "arith11_operand" "rI")])))]
953 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
954 [(set_attr "type" "binary")
955 (set_attr "length" "12")])
957 ;; Combiner patterns for common operations performed with the output
958 ;; from an scc insn (negscc and incscc).
959 (define_insn "negscc"
960 [(set (match_operand:SI 0 "register_operand" "=r")
961 (neg:SI (match_operator:SI 3 "comparison_operator"
962 [(match_operand:SI 1 "register_operand" "r")
963 (match_operand:SI 2 "arith11_operand" "rI")])))]
965 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
966 [(set_attr "type" "binary")
967 (set_attr "length" "8")])
970 [(set (match_operand:DI 0 "register_operand" "=r")
971 (neg:DI (match_operator:DI 3 "comparison_operator"
972 [(match_operand:DI 1 "register_operand" "r")
973 (match_operand:DI 2 "arith11_operand" "rI")])))]
975 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
976 [(set_attr "type" "binary")
977 (set_attr "length" "8")])
979 ;; Patterns for adding/subtracting the result of a boolean expression from
980 ;; a register. First we have special patterns that make use of the carry
981 ;; bit, and output only two instructions. For the cases we can't in
982 ;; general do in two instructions, the incscc pattern at the end outputs
983 ;; two or three instructions.
986 [(set (match_operand:SI 0 "register_operand" "=r")
987 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
988 (match_operand:SI 3 "arith11_operand" "rI"))
989 (match_operand:SI 1 "register_operand" "r")))]
991 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
992 [(set_attr "type" "binary")
993 (set_attr "length" "8")])
996 [(set (match_operand:DI 0 "register_operand" "=r")
997 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
998 (match_operand:DI 3 "arith11_operand" "rI"))
999 (match_operand:DI 1 "register_operand" "r")))]
1001 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
1002 [(set_attr "type" "binary")
1003 (set_attr "length" "8")])
1005 ; This need only accept registers for op3, since canonicalization
1006 ; replaces geu with gtu when op3 is an integer.
1008 [(set (match_operand:SI 0 "register_operand" "=r")
1009 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
1010 (match_operand:SI 3 "register_operand" "r"))
1011 (match_operand:SI 1 "register_operand" "r")))]
1013 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
1014 [(set_attr "type" "binary")
1015 (set_attr "length" "8")])
1018 [(set (match_operand:DI 0 "register_operand" "=r")
1019 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
1020 (match_operand:DI 3 "register_operand" "r"))
1021 (match_operand:DI 1 "register_operand" "r")))]
1023 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
1024 [(set_attr "type" "binary")
1025 (set_attr "length" "8")])
1027 ; Match only integers for op3 here. This is used as canonical form of the
1028 ; geu pattern when op3 is an integer. Don't match registers since we can't
1029 ; make better code than the general incscc pattern.
1031 [(set (match_operand:SI 0 "register_operand" "=r")
1032 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
1033 (match_operand:SI 3 "int11_operand" "I"))
1034 (match_operand:SI 1 "register_operand" "r")))]
1036 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
1037 [(set_attr "type" "binary")
1038 (set_attr "length" "8")])
1041 [(set (match_operand:DI 0 "register_operand" "=r")
1042 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
1043 (match_operand:DI 3 "int11_operand" "I"))
1044 (match_operand:DI 1 "register_operand" "r")))]
1046 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
1047 [(set_attr "type" "binary")
1048 (set_attr "length" "8")])
1050 (define_insn "incscc"
1051 [(set (match_operand:SI 0 "register_operand" "=r,r")
1052 (plus:SI (match_operator:SI 4 "comparison_operator"
1053 [(match_operand:SI 2 "register_operand" "r,r")
1054 (match_operand:SI 3 "arith11_operand" "rI,rI")])
1055 (match_operand:SI 1 "register_operand" "0,?r")))]
1058 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
1059 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1060 [(set_attr "type" "binary,binary")
1061 (set_attr "length" "8,12")])
1064 [(set (match_operand:DI 0 "register_operand" "=r,r")
1065 (plus:DI (match_operator:DI 4 "comparison_operator"
1066 [(match_operand:DI 2 "register_operand" "r,r")
1067 (match_operand:DI 3 "arith11_operand" "rI,rI")])
1068 (match_operand:DI 1 "register_operand" "0,?r")))]
1071 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
1072 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1073 [(set_attr "type" "binary,binary")
1074 (set_attr "length" "8,12")])
1077 [(set (match_operand:SI 0 "register_operand" "=r")
1078 (minus:SI (match_operand:SI 1 "register_operand" "r")
1079 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1080 (match_operand:SI 3 "arith11_operand" "rI"))))]
1082 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1083 [(set_attr "type" "binary")
1084 (set_attr "length" "8")])
1087 [(set (match_operand:DI 0 "register_operand" "=r")
1088 (minus:DI (match_operand:DI 1 "register_operand" "r")
1089 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1090 (match_operand:DI 3 "arith11_operand" "rI"))))]
1092 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1093 [(set_attr "type" "binary")
1094 (set_attr "length" "8")])
1097 [(set (match_operand:SI 0 "register_operand" "=r")
1098 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1099 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1100 (match_operand:SI 3 "arith11_operand" "rI")))
1101 (match_operand:SI 4 "register_operand" "r")))]
1103 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1104 [(set_attr "type" "binary")
1105 (set_attr "length" "8")])
1108 [(set (match_operand:DI 0 "register_operand" "=r")
1109 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1110 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1111 (match_operand:DI 3 "arith11_operand" "rI")))
1112 (match_operand:DI 4 "register_operand" "r")))]
1114 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1115 [(set_attr "type" "binary")
1116 (set_attr "length" "8")])
1118 ; This need only accept registers for op3, since canonicalization
1119 ; replaces ltu with leu when op3 is an integer.
1121 [(set (match_operand:SI 0 "register_operand" "=r")
1122 (minus:SI (match_operand:SI 1 "register_operand" "r")
1123 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1124 (match_operand:SI 3 "register_operand" "r"))))]
1126 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1127 [(set_attr "type" "binary")
1128 (set_attr "length" "8")])
1131 [(set (match_operand:DI 0 "register_operand" "=r")
1132 (minus:DI (match_operand:DI 1 "register_operand" "r")
1133 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1134 (match_operand:DI 3 "register_operand" "r"))))]
1136 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1137 [(set_attr "type" "binary")
1138 (set_attr "length" "8")])
1141 [(set (match_operand:SI 0 "register_operand" "=r")
1142 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1143 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1144 (match_operand:SI 3 "register_operand" "r")))
1145 (match_operand:SI 4 "register_operand" "r")))]
1147 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1148 [(set_attr "type" "binary")
1149 (set_attr "length" "8")])
1152 [(set (match_operand:DI 0 "register_operand" "=r")
1153 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1154 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1155 (match_operand:DI 3 "register_operand" "r")))
1156 (match_operand:DI 4 "register_operand" "r")))]
1158 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1159 [(set_attr "type" "binary")
1160 (set_attr "length" "8")])
1162 ; Match only integers for op3 here. This is used as canonical form of the
1163 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1164 ; make better code than the general incscc pattern.
1166 [(set (match_operand:SI 0 "register_operand" "=r")
1167 (minus:SI (match_operand:SI 1 "register_operand" "r")
1168 (leu:SI (match_operand:SI 2 "register_operand" "r")
1169 (match_operand:SI 3 "int11_operand" "I"))))]
1171 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1172 [(set_attr "type" "binary")
1173 (set_attr "length" "8")])
1176 [(set (match_operand:DI 0 "register_operand" "=r")
1177 (minus:DI (match_operand:DI 1 "register_operand" "r")
1178 (leu:DI (match_operand:DI 2 "register_operand" "r")
1179 (match_operand:DI 3 "int11_operand" "I"))))]
1181 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1182 [(set_attr "type" "binary")
1183 (set_attr "length" "8")])
1186 [(set (match_operand:SI 0 "register_operand" "=r")
1187 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1188 (leu:SI (match_operand:SI 2 "register_operand" "r")
1189 (match_operand:SI 3 "int11_operand" "I")))
1190 (match_operand:SI 4 "register_operand" "r")))]
1192 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1193 [(set_attr "type" "binary")
1194 (set_attr "length" "8")])
1197 [(set (match_operand:DI 0 "register_operand" "=r")
1198 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1199 (leu:DI (match_operand:DI 2 "register_operand" "r")
1200 (match_operand:DI 3 "int11_operand" "I")))
1201 (match_operand:DI 4 "register_operand" "r")))]
1203 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1204 [(set_attr "type" "binary")
1205 (set_attr "length" "8")])
1207 (define_insn "decscc"
1208 [(set (match_operand:SI 0 "register_operand" "=r,r")
1209 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1210 (match_operator:SI 4 "comparison_operator"
1211 [(match_operand:SI 2 "register_operand" "r,r")
1212 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1215 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1216 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1217 [(set_attr "type" "binary,binary")
1218 (set_attr "length" "8,12")])
1221 [(set (match_operand:DI 0 "register_operand" "=r,r")
1222 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1223 (match_operator:DI 4 "comparison_operator"
1224 [(match_operand:DI 2 "register_operand" "r,r")
1225 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1228 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1229 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1230 [(set_attr "type" "binary,binary")
1231 (set_attr "length" "8,12")])
1233 ; Patterns for max and min. (There is no need for an earlyclobber in the
1234 ; last alternative since the middle alternative will match if op0 == op1.)
1236 (define_insn "sminsi3"
1237 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1238 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1239 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1242 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1243 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1244 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1245 [(set_attr "type" "multi,multi,multi")
1246 (set_attr "length" "8,8,8")])
1248 (define_insn "smindi3"
1249 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1250 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1251 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1254 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1255 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1256 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1257 [(set_attr "type" "multi,multi,multi")
1258 (set_attr "length" "8,8,8")])
1260 (define_insn "uminsi3"
1261 [(set (match_operand:SI 0 "register_operand" "=r,r")
1262 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1263 (match_operand:SI 2 "arith11_operand" "r,I")))]
1266 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1267 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1268 [(set_attr "type" "multi,multi")
1269 (set_attr "length" "8,8")])
1271 (define_insn "umindi3"
1272 [(set (match_operand:DI 0 "register_operand" "=r,r")
1273 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1274 (match_operand:DI 2 "arith11_operand" "r,I")))]
1277 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1278 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1279 [(set_attr "type" "multi,multi")
1280 (set_attr "length" "8,8")])
1282 (define_insn "smaxsi3"
1283 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1284 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1285 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1288 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1289 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1290 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1291 [(set_attr "type" "multi,multi,multi")
1292 (set_attr "length" "8,8,8")])
1294 (define_insn "smaxdi3"
1295 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1296 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1297 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1300 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1301 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1302 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1303 [(set_attr "type" "multi,multi,multi")
1304 (set_attr "length" "8,8,8")])
1306 (define_insn "umaxsi3"
1307 [(set (match_operand:SI 0 "register_operand" "=r,r")
1308 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1309 (match_operand:SI 2 "arith11_operand" "r,I")))]
1312 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1313 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1314 [(set_attr "type" "multi,multi")
1315 (set_attr "length" "8,8")])
1317 (define_insn "umaxdi3"
1318 [(set (match_operand:DI 0 "register_operand" "=r,r")
1319 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1320 (match_operand:DI 2 "arith11_operand" "r,I")))]
1323 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1324 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1325 [(set_attr "type" "multi,multi")
1326 (set_attr "length" "8,8")])
1328 (define_insn "abssi2"
1329 [(set (match_operand:SI 0 "register_operand" "=r")
1330 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1332 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1333 [(set_attr "type" "multi")
1334 (set_attr "length" "8")])
1336 (define_insn "absdi2"
1337 [(set (match_operand:DI 0 "register_operand" "=r")
1338 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1340 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1341 [(set_attr "type" "multi")
1342 (set_attr "length" "8")])
1344 ;;; Experimental conditional move patterns
1346 (define_expand "movsicc"
1347 [(set (match_operand:SI 0 "register_operand" "")
1349 (match_operator 1 "comparison_operator"
1352 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1353 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1357 enum rtx_code code = GET_CODE (operands[1]);
1359 if (hppa_branch_type != CMP_SI)
1362 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1363 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1366 /* operands[1] is currently the result of compare_from_rtx. We want to
1367 emit a compare of the original operands. */
1368 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1369 operands[4] = hppa_compare_op0;
1370 operands[5] = hppa_compare_op1;
1373 ;; We used to accept any register for op1.
1375 ;; However, it loses sometimes because the compiler will end up using
1376 ;; different registers for op0 and op1 in some critical cases. local-alloc
1377 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1379 ;; If/when global register allocation supports tying we should allow any
1380 ;; register for op1 again.
1382 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1384 (match_operator 2 "comparison_operator"
1385 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1386 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1387 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1391 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1392 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1393 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1394 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1395 [(set_attr "type" "multi,multi,multi,nullshift")
1396 (set_attr "length" "8,8,8,8")])
1399 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1401 (match_operator 5 "comparison_operator"
1402 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1403 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1404 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1405 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1408 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1409 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1410 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1411 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1412 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1413 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1414 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1415 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1416 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1417 (set_attr "length" "8,8,8,8,8,8,8,8")])
1419 (define_expand "movdicc"
1420 [(set (match_operand:DI 0 "register_operand" "")
1422 (match_operator 1 "comparison_operator"
1425 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1426 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1430 enum rtx_code code = GET_CODE (operands[1]);
1432 if (hppa_branch_type != CMP_SI)
1435 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1436 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1439 /* operands[1] is currently the result of compare_from_rtx. We want to
1440 emit a compare of the original operands. */
1441 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1442 operands[4] = hppa_compare_op0;
1443 operands[5] = hppa_compare_op1;
1446 ; We need the first constraint alternative in order to avoid
1447 ; earlyclobbers on all other alternatives.
1449 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1451 (match_operator 2 "comparison_operator"
1452 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1453 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1454 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1458 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1459 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1460 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1461 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1462 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1463 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1464 (set_attr "length" "8,8,8,8,8")])
1467 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1469 (match_operator 5 "comparison_operator"
1470 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1471 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1472 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1473 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1476 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1477 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1478 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1479 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1480 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1481 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1482 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1483 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1484 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1485 (set_attr "length" "8,8,8,8,8,8,8,8")])
1487 ;; Conditional Branches
1489 (define_expand "beq"
1491 (if_then_else (eq (match_dup 1) (match_dup 2))
1492 (label_ref (match_operand 0 "" ""))
1497 if (hppa_branch_type != CMP_SI)
1499 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1500 emit_bcond_fp (NE, operands[0]);
1503 /* set up operands from compare. */
1504 operands[1] = hppa_compare_op0;
1505 operands[2] = hppa_compare_op1;
1506 /* fall through and generate default code */
1509 (define_expand "bne"
1511 (if_then_else (ne (match_dup 1) (match_dup 2))
1512 (label_ref (match_operand 0 "" ""))
1517 if (hppa_branch_type != CMP_SI)
1519 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1520 emit_bcond_fp (NE, operands[0]);
1523 operands[1] = hppa_compare_op0;
1524 operands[2] = hppa_compare_op1;
1527 (define_expand "bgt"
1529 (if_then_else (gt (match_dup 1) (match_dup 2))
1530 (label_ref (match_operand 0 "" ""))
1535 if (hppa_branch_type != CMP_SI)
1537 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1538 emit_bcond_fp (NE, operands[0]);
1541 operands[1] = hppa_compare_op0;
1542 operands[2] = hppa_compare_op1;
1545 (define_expand "blt"
1547 (if_then_else (lt (match_dup 1) (match_dup 2))
1548 (label_ref (match_operand 0 "" ""))
1553 if (hppa_branch_type != CMP_SI)
1555 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1556 emit_bcond_fp (NE, operands[0]);
1559 operands[1] = hppa_compare_op0;
1560 operands[2] = hppa_compare_op1;
1563 (define_expand "bge"
1565 (if_then_else (ge (match_dup 1) (match_dup 2))
1566 (label_ref (match_operand 0 "" ""))
1571 if (hppa_branch_type != CMP_SI)
1573 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1574 emit_bcond_fp (NE, operands[0]);
1577 operands[1] = hppa_compare_op0;
1578 operands[2] = hppa_compare_op1;
1581 (define_expand "ble"
1583 (if_then_else (le (match_dup 1) (match_dup 2))
1584 (label_ref (match_operand 0 "" ""))
1589 if (hppa_branch_type != CMP_SI)
1591 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1592 emit_bcond_fp (NE, operands[0]);
1595 operands[1] = hppa_compare_op0;
1596 operands[2] = hppa_compare_op1;
1599 (define_expand "bgtu"
1601 (if_then_else (gtu (match_dup 1) (match_dup 2))
1602 (label_ref (match_operand 0 "" ""))
1607 if (hppa_branch_type != CMP_SI)
1609 operands[1] = hppa_compare_op0;
1610 operands[2] = hppa_compare_op1;
1613 (define_expand "bltu"
1615 (if_then_else (ltu (match_dup 1) (match_dup 2))
1616 (label_ref (match_operand 0 "" ""))
1621 if (hppa_branch_type != CMP_SI)
1623 operands[1] = hppa_compare_op0;
1624 operands[2] = hppa_compare_op1;
1627 (define_expand "bgeu"
1629 (if_then_else (geu (match_dup 1) (match_dup 2))
1630 (label_ref (match_operand 0 "" ""))
1635 if (hppa_branch_type != CMP_SI)
1637 operands[1] = hppa_compare_op0;
1638 operands[2] = hppa_compare_op1;
1641 (define_expand "bleu"
1643 (if_then_else (leu (match_dup 1) (match_dup 2))
1644 (label_ref (match_operand 0 "" ""))
1649 if (hppa_branch_type != CMP_SI)
1651 operands[1] = hppa_compare_op0;
1652 operands[2] = hppa_compare_op1;
1655 (define_expand "bltgt"
1657 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1658 (label_ref (match_operand 0 "" ""))
1663 if (hppa_branch_type == CMP_SI)
1665 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1666 emit_bcond_fp (NE, operands[0]);
1670 (define_expand "bunle"
1672 (if_then_else (unle (match_dup 1) (match_dup 2))
1673 (label_ref (match_operand 0 "" ""))
1678 if (hppa_branch_type == CMP_SI)
1680 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1681 emit_bcond_fp (NE, operands[0]);
1685 (define_expand "bunlt"
1687 (if_then_else (unlt (match_dup 1) (match_dup 2))
1688 (label_ref (match_operand 0 "" ""))
1693 if (hppa_branch_type == CMP_SI)
1695 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1696 emit_bcond_fp (NE, operands[0]);
1700 (define_expand "bunge"
1702 (if_then_else (unge (match_dup 1) (match_dup 2))
1703 (label_ref (match_operand 0 "" ""))
1708 if (hppa_branch_type == CMP_SI)
1710 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1711 emit_bcond_fp (NE, operands[0]);
1715 (define_expand "bungt"
1717 (if_then_else (ungt (match_dup 1) (match_dup 2))
1718 (label_ref (match_operand 0 "" ""))
1723 if (hppa_branch_type == CMP_SI)
1725 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1726 emit_bcond_fp (NE, operands[0]);
1730 (define_expand "buneq"
1732 (if_then_else (uneq (match_dup 1) (match_dup 2))
1733 (label_ref (match_operand 0 "" ""))
1738 if (hppa_branch_type == CMP_SI)
1740 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1741 emit_bcond_fp (NE, operands[0]);
1745 (define_expand "bunordered"
1747 (if_then_else (unordered (match_dup 1) (match_dup 2))
1748 (label_ref (match_operand 0 "" ""))
1753 if (hppa_branch_type == CMP_SI)
1755 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1756 emit_bcond_fp (NE, operands[0]);
1760 (define_expand "bordered"
1762 (if_then_else (ordered (match_dup 1) (match_dup 2))
1763 (label_ref (match_operand 0 "" ""))
1768 if (hppa_branch_type == CMP_SI)
1770 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1771 emit_bcond_fp (NE, operands[0]);
1775 ;; Match the branch patterns.
1778 ;; Note a long backward conditional branch with an annulled delay slot
1779 ;; has a length of 12.
1783 (match_operator 3 "comparison_operator"
1784 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1785 (match_operand:SI 2 "arith5_operand" "rL")])
1786 (label_ref (match_operand 0 "" ""))
1791 return output_cbranch (operands, 0, insn);
1793 [(set_attr "type" "cbranch")
1794 (set (attr "length")
1795 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1796 (const_int MAX_12BIT_OFFSET))
1798 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1799 (const_int MAX_17BIT_OFFSET))
1801 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "comparison_operator"
1813 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1814 (match_operand:SI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, 1, insn);
1822 [(set_attr "type" "cbranch")
1823 (set (attr "length")
1824 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1825 (const_int MAX_12BIT_OFFSET))
1827 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (const_int MAX_17BIT_OFFSET))
1830 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1832 (eq (symbol_ref "flag_pic") (const_int 0))
1839 (match_operator 3 "comparison_operator"
1840 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1841 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1842 (label_ref (match_operand 0 "" ""))
1847 return output_cbranch (operands, 0, insn);
1849 [(set_attr "type" "cbranch")
1850 (set (attr "length")
1851 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1852 (const_int MAX_12BIT_OFFSET))
1854 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1855 (const_int MAX_17BIT_OFFSET))
1857 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1859 (eq (symbol_ref "flag_pic") (const_int 0))
1863 ;; Match the negated branch.
1868 (match_operator 3 "comparison_operator"
1869 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1870 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1872 (label_ref (match_operand 0 "" ""))))]
1876 return output_cbranch (operands, 1, insn);
1878 [(set_attr "type" "cbranch")
1879 (set (attr "length")
1880 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1881 (const_int MAX_12BIT_OFFSET))
1883 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1884 (const_int MAX_17BIT_OFFSET))
1886 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1888 (eq (symbol_ref "flag_pic") (const_int 0))
1894 (match_operator 3 "cmpib_comparison_operator"
1895 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1896 (match_operand:DI 2 "arith5_operand" "rL")])
1897 (label_ref (match_operand 0 "" ""))
1902 return output_cbranch (operands, 0, insn);
1904 [(set_attr "type" "cbranch")
1905 (set (attr "length")
1906 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1907 (const_int MAX_12BIT_OFFSET))
1909 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1910 (const_int MAX_17BIT_OFFSET))
1912 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1914 (eq (symbol_ref "flag_pic") (const_int 0))
1918 ;; Match the negated branch.
1923 (match_operator 3 "cmpib_comparison_operator"
1924 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1925 (match_operand:DI 2 "arith5_operand" "rL")])
1927 (label_ref (match_operand 0 "" ""))))]
1931 return output_cbranch (operands, 1, insn);
1933 [(set_attr "type" "cbranch")
1934 (set (attr "length")
1935 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1936 (const_int MAX_12BIT_OFFSET))
1938 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1939 (const_int MAX_17BIT_OFFSET))
1941 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1943 (eq (symbol_ref "flag_pic") (const_int 0))
1947 ;; Branch on Bit patterns.
1951 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1953 (match_operand:SI 1 "uint5_operand" ""))
1955 (label_ref (match_operand 2 "" ""))
1960 return output_bb (operands, 0, insn, 0);
1962 [(set_attr "type" "cbranch")
1963 (set (attr "length")
1964 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1965 (const_int MAX_12BIT_OFFSET))
1967 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1968 (const_int MAX_17BIT_OFFSET))
1970 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1972 (eq (symbol_ref "flag_pic") (const_int 0))
1979 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1981 (match_operand:DI 1 "uint32_operand" ""))
1983 (label_ref (match_operand 2 "" ""))
1988 return output_bb (operands, 0, insn, 0);
1990 [(set_attr "type" "cbranch")
1991 (set (attr "length")
1992 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (const_int MAX_12BIT_OFFSET))
1995 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1996 (const_int MAX_17BIT_OFFSET))
1998 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2000 (eq (symbol_ref "flag_pic") (const_int 0))
2007 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2009 (match_operand:SI 1 "uint5_operand" ""))
2012 (label_ref (match_operand 2 "" ""))))]
2016 return output_bb (operands, 1, insn, 0);
2018 [(set_attr "type" "cbranch")
2019 (set (attr "length")
2020 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2021 (const_int MAX_12BIT_OFFSET))
2023 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2024 (const_int MAX_17BIT_OFFSET))
2026 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2028 (eq (symbol_ref "flag_pic") (const_int 0))
2035 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2037 (match_operand:DI 1 "uint32_operand" ""))
2040 (label_ref (match_operand 2 "" ""))))]
2044 return output_bb (operands, 1, insn, 0);
2046 [(set_attr "type" "cbranch")
2047 (set (attr "length")
2048 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2049 (const_int MAX_12BIT_OFFSET))
2051 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2052 (const_int MAX_17BIT_OFFSET))
2054 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2056 (eq (symbol_ref "flag_pic") (const_int 0))
2063 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2065 (match_operand:SI 1 "uint5_operand" ""))
2067 (label_ref (match_operand 2 "" ""))
2072 return output_bb (operands, 0, insn, 1);
2074 [(set_attr "type" "cbranch")
2075 (set (attr "length")
2076 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2077 (const_int MAX_12BIT_OFFSET))
2079 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2080 (const_int MAX_17BIT_OFFSET))
2082 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2084 (eq (symbol_ref "flag_pic") (const_int 0))
2091 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2093 (match_operand:DI 1 "uint32_operand" ""))
2095 (label_ref (match_operand 2 "" ""))
2100 return output_bb (operands, 0, insn, 1);
2102 [(set_attr "type" "cbranch")
2103 (set (attr "length")
2104 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2105 (const_int MAX_12BIT_OFFSET))
2107 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2108 (const_int MAX_17BIT_OFFSET))
2110 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2112 (eq (symbol_ref "flag_pic") (const_int 0))
2119 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2121 (match_operand:SI 1 "uint5_operand" ""))
2124 (label_ref (match_operand 2 "" ""))))]
2128 return output_bb (operands, 1, insn, 1);
2130 [(set_attr "type" "cbranch")
2131 (set (attr "length")
2132 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2133 (const_int MAX_12BIT_OFFSET))
2135 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2136 (const_int MAX_17BIT_OFFSET))
2138 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2140 (eq (symbol_ref "flag_pic") (const_int 0))
2147 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2149 (match_operand:DI 1 "uint32_operand" ""))
2152 (label_ref (match_operand 2 "" ""))))]
2156 return output_bb (operands, 1, insn, 1);
2158 [(set_attr "type" "cbranch")
2159 (set (attr "length")
2160 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2161 (const_int MAX_12BIT_OFFSET))
2163 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2164 (const_int MAX_17BIT_OFFSET))
2166 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2168 (eq (symbol_ref "flag_pic") (const_int 0))
2172 ;; Branch on Variable Bit patterns.
2176 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2178 (match_operand:SI 1 "register_operand" "q"))
2180 (label_ref (match_operand 2 "" ""))
2185 return output_bvb (operands, 0, insn, 0);
2187 [(set_attr "type" "cbranch")
2188 (set (attr "length")
2189 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2190 (const_int MAX_12BIT_OFFSET))
2192 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2193 (const_int MAX_17BIT_OFFSET))
2195 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2197 (eq (symbol_ref "flag_pic") (const_int 0))
2204 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2206 (match_operand:DI 1 "register_operand" "q"))
2208 (label_ref (match_operand 2 "" ""))
2213 return output_bvb (operands, 0, insn, 0);
2215 [(set_attr "type" "cbranch")
2216 (set (attr "length")
2217 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2218 (const_int MAX_12BIT_OFFSET))
2220 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2221 (const_int MAX_17BIT_OFFSET))
2223 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2225 (eq (symbol_ref "flag_pic") (const_int 0))
2232 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2234 (match_operand:SI 1 "register_operand" "q"))
2237 (label_ref (match_operand 2 "" ""))))]
2241 return output_bvb (operands, 1, insn, 0);
2243 [(set_attr "type" "cbranch")
2244 (set (attr "length")
2245 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2246 (const_int MAX_12BIT_OFFSET))
2248 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2249 (const_int MAX_17BIT_OFFSET))
2251 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2253 (eq (symbol_ref "flag_pic") (const_int 0))
2260 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2262 (match_operand:DI 1 "register_operand" "q"))
2265 (label_ref (match_operand 2 "" ""))))]
2269 return output_bvb (operands, 1, insn, 0);
2271 [(set_attr "type" "cbranch")
2272 (set (attr "length")
2273 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2274 (const_int MAX_12BIT_OFFSET))
2276 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2277 (const_int MAX_17BIT_OFFSET))
2279 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2281 (eq (symbol_ref "flag_pic") (const_int 0))
2288 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2290 (match_operand:SI 1 "register_operand" "q"))
2292 (label_ref (match_operand 2 "" ""))
2297 return output_bvb (operands, 0, insn, 1);
2299 [(set_attr "type" "cbranch")
2300 (set (attr "length")
2301 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2302 (const_int MAX_12BIT_OFFSET))
2304 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2305 (const_int MAX_17BIT_OFFSET))
2307 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2309 (eq (symbol_ref "flag_pic") (const_int 0))
2316 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2318 (match_operand:DI 1 "register_operand" "q"))
2320 (label_ref (match_operand 2 "" ""))
2325 return output_bvb (operands, 0, insn, 1);
2327 [(set_attr "type" "cbranch")
2328 (set (attr "length")
2329 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2330 (const_int MAX_12BIT_OFFSET))
2332 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2333 (const_int MAX_17BIT_OFFSET))
2335 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2337 (eq (symbol_ref "flag_pic") (const_int 0))
2344 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2346 (match_operand:SI 1 "register_operand" "q"))
2349 (label_ref (match_operand 2 "" ""))))]
2353 return output_bvb (operands, 1, insn, 1);
2355 [(set_attr "type" "cbranch")
2356 (set (attr "length")
2357 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2358 (const_int MAX_12BIT_OFFSET))
2360 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2361 (const_int MAX_17BIT_OFFSET))
2363 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2365 (eq (symbol_ref "flag_pic") (const_int 0))
2372 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2374 (match_operand:DI 1 "register_operand" "q"))
2377 (label_ref (match_operand 2 "" ""))))]
2381 return output_bvb (operands, 1, insn, 1);
2383 [(set_attr "type" "cbranch")
2384 (set (attr "length")
2385 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2386 (const_int MAX_12BIT_OFFSET))
2388 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2389 (const_int MAX_17BIT_OFFSET))
2391 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2393 (eq (symbol_ref "flag_pic") (const_int 0))
2397 ;; Floating point branches
2399 ;; ??? Nullification is handled differently from other branches.
2400 ;; If nullification is specified, the delay slot is nullified on any
2401 ;; taken branch regardless of branch direction.
2403 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2404 (label_ref (match_operand 0 "" ""))
2406 "!TARGET_SOFT_FLOAT"
2409 int length = get_attr_length (insn);
2411 int nullify, xdelay;
2414 return \"ftest\;b%* %l0\";
2416 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2420 xoperands[0] = GEN_INT (length - 8);
2426 xoperands[0] = GEN_INT (length - 4);
2430 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2432 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2433 return output_lbranch (operands[0], insn, xdelay);
2435 [(set_attr "type" "fbranch")
2436 (set (attr "length")
2437 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2438 (const_int MAX_17BIT_OFFSET))
2440 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2442 (eq (symbol_ref "flag_pic") (const_int 0))
2447 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2449 (label_ref (match_operand 0 "" ""))))]
2450 "!TARGET_SOFT_FLOAT"
2453 int length = get_attr_length (insn);
2455 int nullify, xdelay;
2458 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2460 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2464 xoperands[0] = GEN_INT (length - 4);
2470 xoperands[0] = GEN_INT (length);
2474 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2476 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2477 return output_lbranch (operands[0], insn, xdelay);
2479 [(set_attr "type" "fbranch")
2480 (set (attr "length")
2481 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2482 (const_int MAX_17BIT_OFFSET))
2484 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2486 (eq (symbol_ref "flag_pic") (const_int 0))
2490 ;; Move instructions
2492 (define_expand "movsi"
2493 [(set (match_operand:SI 0 "general_operand" "")
2494 (match_operand:SI 1 "general_operand" ""))]
2498 if (emit_move_sequence (operands, SImode, 0))
2502 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2503 (define_expand "reload_insi_r1"
2504 [(set (match_operand:SI 0 "register_operand" "=Z")
2505 (match_operand:SI 1 "non_hard_reg_operand" ""))
2506 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2510 if (emit_move_sequence (operands, SImode, operands[2]))
2513 /* We don't want the clobber emitted, so handle this ourselves. */
2514 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2518 ;; Handle SImode input reloads requiring a general register as a
2519 ;; scratch register.
2520 (define_expand "reload_insi"
2521 [(set (match_operand:SI 0 "register_operand" "=Z")
2522 (match_operand:SI 1 "non_hard_reg_operand" ""))
2523 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2527 if (emit_move_sequence (operands, SImode, operands[2]))
2530 /* We don't want the clobber emitted, so handle this ourselves. */
2531 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2535 ;; Handle SImode output reloads requiring a general register as a
2536 ;; scratch register.
2537 (define_expand "reload_outsi"
2538 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2539 (match_operand:SI 1 "register_operand" "Z"))
2540 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2544 if (emit_move_sequence (operands, SImode, operands[2]))
2547 /* We don't want the clobber emitted, so handle this ourselves. */
2548 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2553 [(set (match_operand:SI 0 "move_dest_operand"
2554 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2555 (match_operand:SI 1 "move_src_operand"
2556 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2557 "(register_operand (operands[0], SImode)
2558 || reg_or_0_operand (operands[1], SImode))
2559 && !TARGET_SOFT_FLOAT
2566 {zdepi|depwi,z} %Z1,%0
2570 {mfctl|mfctl,w} %%sar,%0
2574 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2575 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2576 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2577 (set_attr "pa_combine_type" "addmove")
2578 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2581 [(set (match_operand:SI 0 "move_dest_operand"
2582 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2583 (match_operand:SI 1 "move_src_operand"
2584 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2585 "(register_operand (operands[0], SImode)
2586 || reg_or_0_operand (operands[1], SImode))
2587 && !TARGET_SOFT_FLOAT
2594 {zdepi|depwi,z} %Z1,%0
2598 {mfctl|mfctl,w} %%sar,%0
2602 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2603 (set_attr "pa_combine_type" "addmove")
2604 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2607 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2608 (match_operand:SI 1 "register_operand" "f"))]
2610 && !TARGET_DISABLE_INDEXING
2611 && reload_completed"
2613 [(set_attr "type" "fpstore")
2614 (set_attr "pa_combine_type" "addmove")
2615 (set_attr "length" "4")])
2617 ; Rewrite RTL using an indexed store. This will allow the insn that
2618 ; computes the address to be deleted if the register it sets is dead.
2620 [(set (match_operand:SI 0 "register_operand" "")
2621 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2623 (match_operand:SI 2 "register_operand" "")))
2624 (set (mem:SI (match_dup 0))
2625 (match_operand:SI 3 "register_operand" ""))]
2627 && !TARGET_DISABLE_INDEXING
2628 && REG_OK_FOR_BASE_P (operands[2])
2629 && FP_REGNO_P (REGNO (operands[3]))"
2630 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2632 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2637 [(set (match_operand:SI 0 "register_operand" "")
2638 (plus:SI (match_operand:SI 2 "register_operand" "")
2639 (mult:SI (match_operand:SI 1 "register_operand" "")
2641 (set (mem:SI (match_dup 0))
2642 (match_operand:SI 3 "register_operand" ""))]
2644 && !TARGET_DISABLE_INDEXING
2645 && REG_OK_FOR_BASE_P (operands[2])
2646 && FP_REGNO_P (REGNO (operands[3]))"
2647 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2649 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2657 (match_operand:DI 2 "register_operand" "")))
2658 (set (mem:SI (match_dup 0))
2659 (match_operand:SI 3 "register_operand" ""))]
2661 && !TARGET_DISABLE_INDEXING
2663 && REG_OK_FOR_BASE_P (operands[2])
2664 && FP_REGNO_P (REGNO (operands[3]))"
2665 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2667 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2672 [(set (match_operand:DI 0 "register_operand" "")
2673 (plus:DI (match_operand:DI 2 "register_operand" "")
2674 (mult:DI (match_operand:DI 1 "register_operand" "")
2676 (set (mem:SI (match_dup 0))
2677 (match_operand:SI 3 "register_operand" ""))]
2679 && !TARGET_DISABLE_INDEXING
2681 && REG_OK_FOR_BASE_P (operands[2])
2682 && FP_REGNO_P (REGNO (operands[3]))"
2683 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2685 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2690 [(set (match_operand:SI 0 "register_operand" "")
2691 (plus:SI (match_operand:SI 1 "register_operand" "")
2692 (match_operand:SI 2 "register_operand" "")))
2693 (set (mem:SI (match_dup 0))
2694 (match_operand:SI 3 "register_operand" ""))]
2696 && !TARGET_DISABLE_INDEXING
2697 && TARGET_NO_SPACE_REGS
2698 && REG_OK_FOR_INDEX_P (operands[1])
2699 && REG_OK_FOR_BASE_P (operands[2])
2700 && FP_REGNO_P (REGNO (operands[3]))"
2701 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2703 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2707 [(set (match_operand:SI 0 "register_operand" "")
2708 (plus:SI (match_operand:SI 1 "register_operand" "")
2709 (match_operand:SI 2 "register_operand" "")))
2710 (set (mem:SI (match_dup 0))
2711 (match_operand:SI 3 "register_operand" ""))]
2713 && !TARGET_DISABLE_INDEXING
2714 && TARGET_NO_SPACE_REGS
2715 && REG_OK_FOR_BASE_P (operands[1])
2716 && REG_OK_FOR_INDEX_P (operands[2])
2717 && FP_REGNO_P (REGNO (operands[3]))"
2718 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2720 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2724 [(set (match_operand:DI 0 "register_operand" "")
2725 (plus:DI (match_operand:DI 1 "register_operand" "")
2726 (match_operand:DI 2 "register_operand" "")))
2727 (set (mem:SI (match_dup 0))
2728 (match_operand:SI 3 "register_operand" ""))]
2730 && !TARGET_DISABLE_INDEXING
2732 && TARGET_NO_SPACE_REGS
2733 && REG_OK_FOR_INDEX_P (operands[1])
2734 && REG_OK_FOR_BASE_P (operands[2])
2735 && FP_REGNO_P (REGNO (operands[3]))"
2736 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2738 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2742 [(set (match_operand:DI 0 "register_operand" "")
2743 (plus:DI (match_operand:DI 1 "register_operand" "")
2744 (match_operand:DI 2 "register_operand" "")))
2745 (set (mem:SI (match_dup 0))
2746 (match_operand:SI 3 "register_operand" ""))]
2748 && !TARGET_DISABLE_INDEXING
2750 && TARGET_NO_SPACE_REGS
2751 && REG_OK_FOR_BASE_P (operands[1])
2752 && REG_OK_FOR_INDEX_P (operands[2])
2753 && FP_REGNO_P (REGNO (operands[3]))"
2754 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2756 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2760 [(set (match_operand:SI 0 "move_dest_operand"
2761 "=r,r,r,r,r,r,Q,!*q,!r")
2762 (match_operand:SI 1 "move_src_operand"
2763 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2764 "(register_operand (operands[0], SImode)
2765 || reg_or_0_operand (operands[1], SImode))
2766 && TARGET_SOFT_FLOAT"
2772 {zdepi|depwi,z} %Z1,%0
2776 {mfctl|mfctl,w} %%sar,%0"
2777 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2778 (set_attr "pa_combine_type" "addmove")
2779 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2781 ;; Load or store with base-register modification.
2783 [(set (match_operand:SI 0 "register_operand" "=r")
2784 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2785 (match_operand:DI 2 "int5_operand" "L"))))
2787 (plus:DI (match_dup 1) (match_dup 2)))]
2790 [(set_attr "type" "load")
2791 (set_attr "length" "4")])
2793 ; And a zero extended variant.
2795 [(set (match_operand:DI 0 "register_operand" "=r")
2796 (zero_extend:DI (mem:SI
2798 (match_operand:DI 1 "register_operand" "+r")
2799 (match_operand:DI 2 "int5_operand" "L")))))
2801 (plus:DI (match_dup 1) (match_dup 2)))]
2804 [(set_attr "type" "load")
2805 (set_attr "length" "4")])
2807 (define_expand "pre_load"
2808 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2809 (mem (plus (match_operand 1 "register_operand" "")
2810 (match_operand 2 "pre_cint_operand" ""))))
2812 (plus (match_dup 1) (match_dup 2)))])]
2818 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2821 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2825 (define_insn "pre_ldw"
2826 [(set (match_operand:SI 0 "register_operand" "=r")
2827 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2828 (match_operand:SI 2 "pre_cint_operand" ""))))
2830 (plus:SI (match_dup 1) (match_dup 2)))]
2834 if (INTVAL (operands[2]) < 0)
2835 return \"{ldwm|ldw,mb} %2(%1),%0\";
2836 return \"{ldws|ldw},mb %2(%1),%0\";
2838 [(set_attr "type" "load")
2839 (set_attr "length" "4")])
2841 (define_insn "pre_ldd"
2842 [(set (match_operand:DI 0 "register_operand" "=r")
2843 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2844 (match_operand:DI 2 "pre_cint_operand" ""))))
2846 (plus:DI (match_dup 1) (match_dup 2)))]
2849 [(set_attr "type" "load")
2850 (set_attr "length" "4")])
2853 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2854 (match_operand:SI 1 "pre_cint_operand" "")))
2855 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2857 (plus:SI (match_dup 0) (match_dup 1)))]
2861 if (INTVAL (operands[1]) < 0)
2862 return \"{stwm|stw,mb} %r2,%1(%0)\";
2863 return \"{stws|stw},mb %r2,%1(%0)\";
2865 [(set_attr "type" "store")
2866 (set_attr "length" "4")])
2869 [(set (match_operand:SI 0 "register_operand" "=r")
2870 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2872 (plus:SI (match_dup 1)
2873 (match_operand:SI 2 "post_cint_operand" "")))]
2877 if (INTVAL (operands[2]) > 0)
2878 return \"{ldwm|ldw,ma} %2(%1),%0\";
2879 return \"{ldws|ldw},ma %2(%1),%0\";
2881 [(set_attr "type" "load")
2882 (set_attr "length" "4")])
2884 (define_expand "post_store"
2885 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2886 (match_operand 1 "reg_or_0_operand" ""))
2889 (match_operand 2 "post_cint_operand" "")))])]
2895 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2898 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2902 (define_insn "post_stw"
2903 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2904 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2906 (plus:SI (match_dup 0)
2907 (match_operand:SI 2 "post_cint_operand" "")))]
2911 if (INTVAL (operands[2]) > 0)
2912 return \"{stwm|stw,ma} %r1,%2(%0)\";
2913 return \"{stws|stw},ma %r1,%2(%0)\";
2915 [(set_attr "type" "store")
2916 (set_attr "length" "4")])
2918 (define_insn "post_std"
2919 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2920 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2922 (plus:DI (match_dup 0)
2923 (match_operand:DI 2 "post_cint_operand" "")))]
2926 [(set_attr "type" "store")
2927 (set_attr "length" "4")])
2929 ;; For loading the address of a label while generating PIC code.
2930 ;; Note since this pattern can be created at reload time (via movsi), all
2931 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2933 [(set (match_operand 0 "pmode_register_operand" "=a")
2934 (match_operand 1 "pic_label_operand" ""))]
2940 xoperands[0] = operands[0];
2941 xoperands[1] = operands[1];
2942 xoperands[2] = gen_label_rtx ();
2944 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2945 CODE_LABEL_NUMBER (xoperands[2]));
2946 output_asm_insn (\"mfia %0\", xoperands);
2948 /* If we're trying to load the address of a label that happens to be
2949 close, then we can use a shorter sequence. */
2950 if (GET_CODE (operands[1]) == LABEL_REF
2951 && !LABEL_REF_NONLOCAL_P (operands[1])
2952 && INSN_ADDRESSES_SET_P ()
2953 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2954 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2955 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2958 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2959 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2963 [(set_attr "type" "multi")
2964 (set_attr "length" "12")]) ; 8 or 12
2967 [(set (match_operand 0 "pmode_register_operand" "=a")
2968 (match_operand 1 "pic_label_operand" ""))]
2974 xoperands[0] = operands[0];
2975 xoperands[1] = operands[1];
2976 xoperands[2] = gen_label_rtx ();
2978 output_asm_insn (\"bl .+8,%0\", xoperands);
2979 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2980 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2981 CODE_LABEL_NUMBER (xoperands[2]));
2983 /* If we're trying to load the address of a label that happens to be
2984 close, then we can use a shorter sequence. */
2985 if (GET_CODE (operands[1]) == LABEL_REF
2986 && !LABEL_REF_NONLOCAL_P (operands[1])
2987 && INSN_ADDRESSES_SET_P ()
2988 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2989 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2990 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2993 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2994 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2998 [(set_attr "type" "multi")
2999 (set_attr "length" "16")]) ; 12 or 16
3002 [(set (match_operand:SI 0 "register_operand" "=a")
3003 (plus:SI (match_operand:SI 1 "register_operand" "r")
3004 (high:SI (match_operand 2 "" ""))))]
3005 "symbolic_operand (operands[2], Pmode)
3006 && ! function_label_operand (operands[2], Pmode)
3009 [(set_attr "type" "binary")
3010 (set_attr "length" "4")])
3013 [(set (match_operand:DI 0 "register_operand" "=a")
3014 (plus:DI (match_operand:DI 1 "register_operand" "r")
3015 (high:DI (match_operand 2 "" ""))))]
3016 "symbolic_operand (operands[2], Pmode)
3017 && ! function_label_operand (operands[2], Pmode)
3021 [(set_attr "type" "binary")
3022 (set_attr "length" "4")])
3024 ;; Always use addil rather than ldil;add sequences. This allows the
3025 ;; HP linker to eliminate the dp relocation if the symbolic operand
3026 ;; lives in the TEXT space.
3028 [(set (match_operand:SI 0 "register_operand" "=a")
3029 (high:SI (match_operand 1 "" "")))]
3030 "symbolic_operand (operands[1], Pmode)
3031 && ! function_label_operand (operands[1], Pmode)
3032 && ! read_only_operand (operands[1], Pmode)
3036 if (TARGET_LONG_LOAD_STORE)
3037 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
3039 return \"addil LR'%H1,%%r27\";
3041 [(set_attr "type" "binary")
3042 (set (attr "length")
3043 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
3048 ;; This is for use in the prologue/epilogue code. We need it
3049 ;; to add large constants to a stack pointer or frame pointer.
3050 ;; Because of the additional %r1 pressure, we probably do not
3051 ;; want to use this in general code, so make it available
3052 ;; only after reload.
3054 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
3055 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
3056 (high:SI (match_operand 2 "const_int_operand" ""))))]
3060 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3061 [(set_attr "type" "binary,binary")
3062 (set_attr "length" "4,8")])
3065 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
3066 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
3067 (high:DI (match_operand 2 "const_int_operand" ""))))]
3068 "reload_completed && TARGET_64BIT"
3071 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3072 [(set_attr "type" "binary,binary")
3073 (set_attr "length" "4,8")])
3076 [(set (match_operand:SI 0 "register_operand" "=r")
3077 (high:SI (match_operand 1 "" "")))]
3078 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
3079 && !is_function_label_plus_const (operands[1])"
3082 if (symbolic_operand (operands[1], Pmode))
3083 return \"ldil LR'%H1,%0\";
3085 return \"ldil L'%G1,%0\";
3087 [(set_attr "type" "move")
3088 (set_attr "length" "4")])
3091 [(set (match_operand:DI 0 "register_operand" "=r")
3092 (high:DI (match_operand 1 "const_int_operand" "")))]
3095 [(set_attr "type" "move")
3096 (set_attr "length" "4")])
3099 [(set (match_operand:DI 0 "register_operand" "=r")
3100 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3101 (match_operand:DI 2 "const_int_operand" "i")))]
3104 [(set_attr "type" "move")
3105 (set_attr "length" "4")])
3108 [(set (match_operand:SI 0 "register_operand" "=r")
3109 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3110 (match_operand:SI 2 "immediate_operand" "i")))]
3111 "!is_function_label_plus_const (operands[2])"
3114 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
3116 if (symbolic_operand (operands[2], Pmode))
3117 return \"ldo RR'%G2(%1),%0\";
3119 return \"ldo R'%G2(%1),%0\";
3121 [(set_attr "type" "move")
3122 (set_attr "length" "4")])
3124 ;; Now that a symbolic_address plus a constant is broken up early
3125 ;; in the compilation phase (for better CSE) we need a special
3126 ;; combiner pattern to load the symbolic address plus the constant
3127 ;; in only 2 instructions. (For cases where the symbolic address
3128 ;; was not a common subexpression.)
3130 [(set (match_operand:SI 0 "register_operand" "")
3131 (match_operand:SI 1 "symbolic_operand" ""))
3132 (clobber (match_operand:SI 2 "register_operand" ""))]
3133 "! (flag_pic && pic_label_operand (operands[1], SImode))"
3134 [(set (match_dup 2) (high:SI (match_dup 1)))
3135 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
3138 ;; hppa_legitimize_address goes to a great deal of trouble to
3139 ;; create addresses which use indexing. In some cases, this
3140 ;; is a lose because there isn't any store instructions which
3141 ;; allow indexed addresses (with integer register source).
3143 ;; These define_splits try to turn a 3 insn store into
3144 ;; a 2 insn store with some creative RTL rewriting.
3146 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3147 (match_operand:SI 1 "shadd_operand" ""))
3148 (plus:SI (match_operand:SI 2 "register_operand" "")
3149 (match_operand:SI 3 "const_int_operand" ""))))
3150 (match_operand:SI 4 "register_operand" ""))
3151 (clobber (match_operand:SI 5 "register_operand" ""))]
3153 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3155 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3159 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3160 (match_operand:SI 1 "shadd_operand" ""))
3161 (plus:SI (match_operand:SI 2 "register_operand" "")
3162 (match_operand:SI 3 "const_int_operand" ""))))
3163 (match_operand:HI 4 "register_operand" ""))
3164 (clobber (match_operand:SI 5 "register_operand" ""))]
3166 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3168 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3172 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3173 (match_operand:SI 1 "shadd_operand" ""))
3174 (plus:SI (match_operand:SI 2 "register_operand" "")
3175 (match_operand:SI 3 "const_int_operand" ""))))
3176 (match_operand:QI 4 "register_operand" ""))
3177 (clobber (match_operand:SI 5 "register_operand" ""))]
3179 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3181 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3184 (define_expand "movhi"
3185 [(set (match_operand:HI 0 "general_operand" "")
3186 (match_operand:HI 1 "general_operand" ""))]
3190 if (emit_move_sequence (operands, HImode, 0))
3195 [(set (match_operand:HI 0 "move_dest_operand"
3196 "=r,r,r,r,r,Q,!*q,!r")
3197 (match_operand:HI 1 "move_src_operand"
3198 "r,J,N,K,RQ,rM,!rM,!*q"))]
3199 "(register_operand (operands[0], HImode)
3200 || reg_or_0_operand (operands[1], HImode))"
3205 {zdepi|depwi,z} %Z1,%0
3209 {mfctl|mfctl,w} %sar,%0"
3210 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3211 (set_attr "pa_combine_type" "addmove")
3212 (set_attr "length" "4,4,4,4,4,4,4,4")])
3215 [(set (match_operand:HI 0 "register_operand" "=r")
3216 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3217 (match_operand:SI 2 "int5_operand" "L"))))
3219 (plus:SI (match_dup 1) (match_dup 2)))]
3221 "{ldhs|ldh},mb %2(%1),%0"
3222 [(set_attr "type" "load")
3223 (set_attr "length" "4")])
3226 [(set (match_operand:HI 0 "register_operand" "=r")
3227 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3228 (match_operand:DI 2 "int5_operand" "L"))))
3230 (plus:DI (match_dup 1) (match_dup 2)))]
3233 [(set_attr "type" "load")
3234 (set_attr "length" "4")])
3236 ; And a zero extended variant.
3238 [(set (match_operand:DI 0 "register_operand" "=r")
3239 (zero_extend:DI (mem:HI
3241 (match_operand:DI 1 "register_operand" "+r")
3242 (match_operand:DI 2 "int5_operand" "L")))))
3244 (plus:DI (match_dup 1) (match_dup 2)))]
3247 [(set_attr "type" "load")
3248 (set_attr "length" "4")])
3251 [(set (match_operand:SI 0 "register_operand" "=r")
3252 (zero_extend:SI (mem:HI
3254 (match_operand:SI 1 "register_operand" "+r")
3255 (match_operand:SI 2 "int5_operand" "L")))))
3257 (plus:SI (match_dup 1) (match_dup 2)))]
3259 "{ldhs|ldh},mb %2(%1),%0"
3260 [(set_attr "type" "load")
3261 (set_attr "length" "4")])
3264 [(set (match_operand:SI 0 "register_operand" "=r")
3265 (zero_extend:SI (mem:HI
3267 (match_operand:DI 1 "register_operand" "+r")
3268 (match_operand:DI 2 "int5_operand" "L")))))
3270 (plus:DI (match_dup 1) (match_dup 2)))]
3273 [(set_attr "type" "load")
3274 (set_attr "length" "4")])
3277 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3278 (match_operand:SI 1 "int5_operand" "L")))
3279 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3281 (plus:SI (match_dup 0) (match_dup 1)))]
3283 "{sths|sth},mb %r2,%1(%0)"
3284 [(set_attr "type" "store")
3285 (set_attr "length" "4")])
3288 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3289 (match_operand:DI 1 "int5_operand" "L")))
3290 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3292 (plus:DI (match_dup 0) (match_dup 1)))]
3295 [(set_attr "type" "store")
3296 (set_attr "length" "4")])
3299 [(set (match_operand:HI 0 "register_operand" "=r")
3300 (plus:HI (match_operand:HI 1 "register_operand" "r")
3301 (match_operand 2 "const_int_operand" "J")))]
3304 [(set_attr "type" "binary")
3305 (set_attr "pa_combine_type" "addmove")
3306 (set_attr "length" "4")])
3308 (define_expand "movqi"
3309 [(set (match_operand:QI 0 "general_operand" "")
3310 (match_operand:QI 1 "general_operand" ""))]
3314 if (emit_move_sequence (operands, QImode, 0))
3319 [(set (match_operand:QI 0 "move_dest_operand"
3320 "=r,r,r,r,r,Q,!*q,!r")
3321 (match_operand:QI 1 "move_src_operand"
3322 "r,J,N,K,RQ,rM,!rM,!*q"))]
3323 "(register_operand (operands[0], QImode)
3324 || reg_or_0_operand (operands[1], QImode))"
3329 {zdepi|depwi,z} %Z1,%0
3333 {mfctl|mfctl,w} %%sar,%0"
3334 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3335 (set_attr "pa_combine_type" "addmove")
3336 (set_attr "length" "4,4,4,4,4,4,4,4")])
3339 [(set (match_operand:QI 0 "register_operand" "=r")
3340 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3341 (match_operand:SI 2 "int5_operand" "L"))))
3342 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3344 "{ldbs|ldb},mb %2(%1),%0"
3345 [(set_attr "type" "load")
3346 (set_attr "length" "4")])
3349 [(set (match_operand:QI 0 "register_operand" "=r")
3350 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3351 (match_operand:DI 2 "int5_operand" "L"))))
3352 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3355 [(set_attr "type" "load")
3356 (set_attr "length" "4")])
3358 ; Now the same thing with zero extensions.
3360 [(set (match_operand:DI 0 "register_operand" "=r")
3361 (zero_extend:DI (mem:QI (plus:DI
3362 (match_operand:DI 1 "register_operand" "+r")
3363 (match_operand:DI 2 "int5_operand" "L")))))
3364 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3367 [(set_attr "type" "load")
3368 (set_attr "length" "4")])
3371 [(set (match_operand:SI 0 "register_operand" "=r")
3372 (zero_extend:SI (mem:QI (plus:SI
3373 (match_operand:SI 1 "register_operand" "+r")
3374 (match_operand:SI 2 "int5_operand" "L")))))
3375 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3377 "{ldbs|ldb},mb %2(%1),%0"
3378 [(set_attr "type" "load")
3379 (set_attr "length" "4")])
3382 [(set (match_operand:SI 0 "register_operand" "=r")
3383 (zero_extend:SI (mem:QI (plus:DI
3384 (match_operand:DI 1 "register_operand" "+r")
3385 (match_operand:DI 2 "int5_operand" "L")))))
3386 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3389 [(set_attr "type" "load")
3390 (set_attr "length" "4")])
3393 [(set (match_operand:HI 0 "register_operand" "=r")
3394 (zero_extend:HI (mem:QI (plus:SI
3395 (match_operand:SI 1 "register_operand" "+r")
3396 (match_operand:SI 2 "int5_operand" "L")))))
3397 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3399 "{ldbs|ldb},mb %2(%1),%0"
3400 [(set_attr "type" "load")
3401 (set_attr "length" "4")])
3404 [(set (match_operand:HI 0 "register_operand" "=r")
3405 (zero_extend:HI (mem:QI (plus:DI
3406 (match_operand:DI 1 "register_operand" "+r")
3407 (match_operand:DI 2 "int5_operand" "L")))))
3408 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3411 [(set_attr "type" "load")
3412 (set_attr "length" "4")])
3415 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3416 (match_operand:SI 1 "int5_operand" "L")))
3417 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3419 (plus:SI (match_dup 0) (match_dup 1)))]
3421 "{stbs|stb},mb %r2,%1(%0)"
3422 [(set_attr "type" "store")
3423 (set_attr "length" "4")])
3426 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3427 (match_operand:DI 1 "int5_operand" "L")))
3428 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3430 (plus:DI (match_dup 0) (match_dup 1)))]
3433 [(set_attr "type" "store")
3434 (set_attr "length" "4")])
3436 ;; The definition of this insn does not really explain what it does,
3437 ;; but it should suffice that anything generated as this insn will be
3438 ;; recognized as a movmemsi operation, and that it will not successfully
3439 ;; combine with anything.
3440 (define_expand "movmemsi"
3441 [(parallel [(set (match_operand:BLK 0 "" "")
3442 (match_operand:BLK 1 "" ""))
3443 (clobber (match_dup 4))
3444 (clobber (match_dup 5))
3445 (clobber (match_dup 6))
3446 (clobber (match_dup 7))
3447 (clobber (match_dup 8))
3448 (use (match_operand:SI 2 "arith_operand" ""))
3449 (use (match_operand:SI 3 "const_int_operand" ""))])]
3450 "!TARGET_64BIT && optimize > 0"
3455 /* HP provides very fast block move library routine for the PA;
3456 this routine includes:
3458 4x4 byte at a time block moves,
3459 1x4 byte at a time with alignment checked at runtime with
3460 attempts to align the source and destination as needed
3463 With that in mind, here's the heuristics to try and guess when
3464 the inlined block move will be better than the library block
3467 If the size isn't constant, then always use the library routines.
3469 If the size is large in respect to the known alignment, then use
3470 the library routines.
3472 If the size is small in respect to the known alignment, then open
3473 code the copy (since that will lead to better scheduling).
3475 Else use the block move pattern. */
3477 /* Undetermined size, use the library routine. */
3478 if (GET_CODE (operands[2]) != CONST_INT)
3481 size = INTVAL (operands[2]);
3482 align = INTVAL (operands[3]);
3483 align = align > 4 ? 4 : align;
3485 /* If size/alignment is large, then use the library routines. */
3486 if (size / align > 16)
3489 /* This does happen, but not often enough to worry much about. */
3490 if (size / align < MOVE_RATIO)
3493 /* Fall through means we're going to use our block move pattern. */
3495 = replace_equiv_address (operands[0],
3496 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3498 = replace_equiv_address (operands[1],
3499 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3500 operands[4] = gen_reg_rtx (SImode);
3501 operands[5] = gen_reg_rtx (SImode);
3502 operands[6] = gen_reg_rtx (SImode);
3503 operands[7] = gen_reg_rtx (SImode);
3504 operands[8] = gen_reg_rtx (SImode);
3507 ;; The operand constraints are written like this to support both compile-time
3508 ;; and run-time determined byte counts. The expander and output_block_move
3509 ;; only support compile-time determined counts at this time.
3511 ;; If the count is run-time determined, the register with the byte count
3512 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3514 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3515 ;; broke this semantic for pseudo registers. We can't use match_scratch
3516 ;; as this requires two registers in the class R1_REGS when the MEMs for
3517 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3518 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3519 ;; respectively. We then split or peephole optimize after reload.
3520 (define_insn "movmemsi_prereload"
3521 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3522 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3523 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3524 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3525 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3526 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3527 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3528 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3529 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3532 [(set_attr "type" "multi,multi")])
3535 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3536 (match_operand:BLK 1 "memory_operand" ""))
3537 (clobber (match_operand:SI 2 "register_operand" ""))
3538 (clobber (match_operand:SI 3 "register_operand" ""))
3539 (clobber (match_operand:SI 6 "register_operand" ""))
3540 (clobber (match_operand:SI 7 "register_operand" ""))
3541 (clobber (match_operand:SI 8 "register_operand" ""))
3542 (use (match_operand:SI 4 "arith_operand" ""))
3543 (use (match_operand:SI 5 "const_int_operand" ""))])]
3544 "!TARGET_64BIT && reload_completed && !flag_peephole2
3545 && GET_CODE (operands[0]) == MEM
3546 && register_operand (XEXP (operands[0], 0), SImode)
3547 && GET_CODE (operands[1]) == MEM
3548 && register_operand (XEXP (operands[1], 0), SImode)"
3549 [(set (match_dup 7) (match_dup 9))
3550 (set (match_dup 8) (match_dup 10))
3551 (parallel [(set (match_dup 0) (match_dup 1))
3552 (clobber (match_dup 2))
3553 (clobber (match_dup 3))
3554 (clobber (match_dup 6))
3555 (clobber (match_dup 7))
3556 (clobber (match_dup 8))
3562 operands[9] = XEXP (operands[0], 0);
3563 operands[10] = XEXP (operands[1], 0);
3564 operands[0] = replace_equiv_address (operands[0], operands[7]);
3565 operands[1] = replace_equiv_address (operands[1], operands[8]);
3569 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3570 (match_operand:BLK 1 "memory_operand" ""))
3571 (clobber (match_operand:SI 2 "register_operand" ""))
3572 (clobber (match_operand:SI 3 "register_operand" ""))
3573 (clobber (match_operand:SI 6 "register_operand" ""))
3574 (clobber (match_operand:SI 7 "register_operand" ""))
3575 (clobber (match_operand:SI 8 "register_operand" ""))
3576 (use (match_operand:SI 4 "arith_operand" ""))
3577 (use (match_operand:SI 5 "const_int_operand" ""))])]
3579 && GET_CODE (operands[0]) == MEM
3580 && register_operand (XEXP (operands[0], 0), SImode)
3581 && GET_CODE (operands[1]) == MEM
3582 && register_operand (XEXP (operands[1], 0), SImode)"
3583 [(parallel [(set (match_dup 0) (match_dup 1))
3584 (clobber (match_dup 2))
3585 (clobber (match_dup 3))
3586 (clobber (match_dup 6))
3587 (clobber (match_dup 7))
3588 (clobber (match_dup 8))
3594 rtx addr = XEXP (operands[0], 0);
3595 if (dead_or_set_p (curr_insn, addr))
3599 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3600 operands[0] = replace_equiv_address (operands[0], operands[7]);
3603 addr = XEXP (operands[1], 0);
3604 if (dead_or_set_p (curr_insn, addr))
3608 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3609 operands[1] = replace_equiv_address (operands[1], operands[8]);
3613 (define_insn "movmemsi_postreload"
3614 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3615 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3616 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3617 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3618 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3619 (clobber (match_dup 0))
3620 (clobber (match_dup 1))
3621 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3622 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3624 "!TARGET_64BIT && reload_completed"
3625 "* return output_block_move (operands, !which_alternative);"
3626 [(set_attr "type" "multi,multi")])
3628 (define_expand "movmemdi"
3629 [(parallel [(set (match_operand:BLK 0 "" "")
3630 (match_operand:BLK 1 "" ""))
3631 (clobber (match_dup 4))
3632 (clobber (match_dup 5))
3633 (clobber (match_dup 6))
3634 (clobber (match_dup 7))
3635 (clobber (match_dup 8))
3636 (use (match_operand:DI 2 "arith_operand" ""))
3637 (use (match_operand:DI 3 "const_int_operand" ""))])]
3638 "TARGET_64BIT && optimize > 0"
3643 /* HP provides very fast block move library routine for the PA;
3644 this routine includes:
3646 4x4 byte at a time block moves,
3647 1x4 byte at a time with alignment checked at runtime with
3648 attempts to align the source and destination as needed
3651 With that in mind, here's the heuristics to try and guess when
3652 the inlined block move will be better than the library block
3655 If the size isn't constant, then always use the library routines.
3657 If the size is large in respect to the known alignment, then use
3658 the library routines.
3660 If the size is small in respect to the known alignment, then open
3661 code the copy (since that will lead to better scheduling).
3663 Else use the block move pattern. */
3665 /* Undetermined size, use the library routine. */
3666 if (GET_CODE (operands[2]) != CONST_INT)
3669 size = INTVAL (operands[2]);
3670 align = INTVAL (operands[3]);
3671 align = align > 8 ? 8 : align;
3673 /* If size/alignment is large, then use the library routines. */
3674 if (size / align > 16)
3677 /* This does happen, but not often enough to worry much about. */
3678 if (size / align < MOVE_RATIO)
3681 /* Fall through means we're going to use our block move pattern. */
3683 = replace_equiv_address (operands[0],
3684 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3686 = replace_equiv_address (operands[1],
3687 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3688 operands[4] = gen_reg_rtx (DImode);
3689 operands[5] = gen_reg_rtx (DImode);
3690 operands[6] = gen_reg_rtx (DImode);
3691 operands[7] = gen_reg_rtx (DImode);
3692 operands[8] = gen_reg_rtx (DImode);
3695 ;; The operand constraints are written like this to support both compile-time
3696 ;; and run-time determined byte counts. The expander and output_block_move
3697 ;; only support compile-time determined counts at this time.
3699 ;; If the count is run-time determined, the register with the byte count
3700 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3702 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3703 ;; broke this semantic for pseudo registers. We can't use match_scratch
3704 ;; as this requires two registers in the class R1_REGS when the MEMs for
3705 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3706 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3707 ;; respectively. We then split or peephole optimize after reload.
3708 (define_insn "movmemdi_prereload"
3709 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3710 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3711 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3712 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3713 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3714 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3715 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3716 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3717 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3720 [(set_attr "type" "multi,multi")])
3723 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3724 (match_operand:BLK 1 "memory_operand" ""))
3725 (clobber (match_operand:DI 2 "register_operand" ""))
3726 (clobber (match_operand:DI 3 "register_operand" ""))
3727 (clobber (match_operand:DI 6 "register_operand" ""))
3728 (clobber (match_operand:DI 7 "register_operand" ""))
3729 (clobber (match_operand:DI 8 "register_operand" ""))
3730 (use (match_operand:DI 4 "arith_operand" ""))
3731 (use (match_operand:DI 5 "const_int_operand" ""))])]
3732 "TARGET_64BIT && reload_completed && !flag_peephole2
3733 && GET_CODE (operands[0]) == MEM
3734 && register_operand (XEXP (operands[0], 0), DImode)
3735 && GET_CODE (operands[1]) == MEM
3736 && register_operand (XEXP (operands[1], 0), DImode)"
3737 [(set (match_dup 7) (match_dup 9))
3738 (set (match_dup 8) (match_dup 10))
3739 (parallel [(set (match_dup 0) (match_dup 1))
3740 (clobber (match_dup 2))
3741 (clobber (match_dup 3))
3742 (clobber (match_dup 6))
3743 (clobber (match_dup 7))
3744 (clobber (match_dup 8))
3750 operands[9] = XEXP (operands[0], 0);
3751 operands[10] = XEXP (operands[1], 0);
3752 operands[0] = replace_equiv_address (operands[0], operands[7]);
3753 operands[1] = replace_equiv_address (operands[1], operands[8]);
3757 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3758 (match_operand:BLK 1 "memory_operand" ""))
3759 (clobber (match_operand:DI 2 "register_operand" ""))
3760 (clobber (match_operand:DI 3 "register_operand" ""))
3761 (clobber (match_operand:DI 6 "register_operand" ""))
3762 (clobber (match_operand:DI 7 "register_operand" ""))
3763 (clobber (match_operand:DI 8 "register_operand" ""))
3764 (use (match_operand:DI 4 "arith_operand" ""))
3765 (use (match_operand:DI 5 "const_int_operand" ""))])]
3767 && GET_CODE (operands[0]) == MEM
3768 && register_operand (XEXP (operands[0], 0), DImode)
3769 && GET_CODE (operands[1]) == MEM
3770 && register_operand (XEXP (operands[1], 0), DImode)"
3771 [(parallel [(set (match_dup 0) (match_dup 1))
3772 (clobber (match_dup 2))
3773 (clobber (match_dup 3))
3774 (clobber (match_dup 6))
3775 (clobber (match_dup 7))
3776 (clobber (match_dup 8))
3782 rtx addr = XEXP (operands[0], 0);
3783 if (dead_or_set_p (curr_insn, addr))
3787 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3788 operands[0] = replace_equiv_address (operands[0], operands[7]);
3791 addr = XEXP (operands[1], 0);
3792 if (dead_or_set_p (curr_insn, addr))
3796 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3797 operands[1] = replace_equiv_address (operands[1], operands[8]);
3801 (define_insn "movmemdi_postreload"
3802 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3803 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3804 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3805 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3806 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3807 (clobber (match_dup 0))
3808 (clobber (match_dup 1))
3809 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3810 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3812 "TARGET_64BIT && reload_completed"
3813 "* return output_block_move (operands, !which_alternative);"
3814 [(set_attr "type" "multi,multi")])
3816 (define_expand "setmemsi"
3817 [(parallel [(set (match_operand:BLK 0 "" "")
3818 (match_operand 2 "const_int_operand" ""))
3819 (clobber (match_dup 4))
3820 (clobber (match_dup 5))
3821 (use (match_operand:SI 1 "arith_operand" ""))
3822 (use (match_operand:SI 3 "const_int_operand" ""))])]
3823 "!TARGET_64BIT && optimize > 0"
3828 /* If value to set is not zero, use the library routine. */
3829 if (operands[2] != const0_rtx)
3832 /* Undetermined size, use the library routine. */
3833 if (GET_CODE (operands[1]) != CONST_INT)
3836 size = INTVAL (operands[1]);
3837 align = INTVAL (operands[3]);
3838 align = align > 4 ? 4 : align;
3840 /* If size/alignment is large, then use the library routines. */
3841 if (size / align > 16)
3844 /* This does happen, but not often enough to worry much about. */
3845 if (size / align < MOVE_RATIO)
3848 /* Fall through means we're going to use our block clear pattern. */
3850 = replace_equiv_address (operands[0],
3851 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3852 operands[4] = gen_reg_rtx (SImode);
3853 operands[5] = gen_reg_rtx (SImode);
3856 (define_insn "clrmemsi_prereload"
3857 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3859 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3860 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3861 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3862 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3865 [(set_attr "type" "multi,multi")])
3868 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3870 (clobber (match_operand:SI 1 "register_operand" ""))
3871 (clobber (match_operand:SI 4 "register_operand" ""))
3872 (use (match_operand:SI 2 "arith_operand" ""))
3873 (use (match_operand:SI 3 "const_int_operand" ""))])]
3874 "!TARGET_64BIT && reload_completed && !flag_peephole2
3875 && GET_CODE (operands[0]) == MEM
3876 && register_operand (XEXP (operands[0], 0), SImode)"
3877 [(set (match_dup 4) (match_dup 5))
3878 (parallel [(set (match_dup 0) (const_int 0))
3879 (clobber (match_dup 1))
3880 (clobber (match_dup 4))
3886 operands[5] = XEXP (operands[0], 0);
3887 operands[0] = replace_equiv_address (operands[0], operands[4]);
3891 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3893 (clobber (match_operand:SI 1 "register_operand" ""))
3894 (clobber (match_operand:SI 4 "register_operand" ""))
3895 (use (match_operand:SI 2 "arith_operand" ""))
3896 (use (match_operand:SI 3 "const_int_operand" ""))])]
3898 && GET_CODE (operands[0]) == MEM
3899 && register_operand (XEXP (operands[0], 0), SImode)"
3900 [(parallel [(set (match_dup 0) (const_int 0))
3901 (clobber (match_dup 1))
3902 (clobber (match_dup 4))
3908 rtx addr = XEXP (operands[0], 0);
3909 if (dead_or_set_p (curr_insn, addr))
3913 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3914 operands[0] = replace_equiv_address (operands[0], operands[4]);
3918 (define_insn "clrmemsi_postreload"
3919 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3921 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3922 (clobber (match_dup 0))
3923 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3924 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3926 "!TARGET_64BIT && reload_completed"
3927 "* return output_block_clear (operands, !which_alternative);"
3928 [(set_attr "type" "multi,multi")])
3930 (define_expand "setmemdi"
3931 [(parallel [(set (match_operand:BLK 0 "" "")
3932 (match_operand 2 "const_int_operand" ""))
3933 (clobber (match_dup 4))
3934 (clobber (match_dup 5))
3935 (use (match_operand:DI 1 "arith_operand" ""))
3936 (use (match_operand:DI 3 "const_int_operand" ""))])]
3937 "TARGET_64BIT && optimize > 0"
3942 /* If value to set is not zero, use the library routine. */
3943 if (operands[2] != const0_rtx)
3946 /* Undetermined size, use the library routine. */
3947 if (GET_CODE (operands[1]) != CONST_INT)
3950 size = INTVAL (operands[1]);
3951 align = INTVAL (operands[3]);
3952 align = align > 8 ? 8 : align;
3954 /* If size/alignment is large, then use the library routines. */
3955 if (size / align > 16)
3958 /* This does happen, but not often enough to worry much about. */
3959 if (size / align < MOVE_RATIO)
3962 /* Fall through means we're going to use our block clear pattern. */
3964 = replace_equiv_address (operands[0],
3965 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3966 operands[4] = gen_reg_rtx (DImode);
3967 operands[5] = gen_reg_rtx (DImode);
3970 (define_insn "clrmemdi_prereload"
3971 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3973 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3974 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3975 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3976 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3979 [(set_attr "type" "multi,multi")])
3982 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3984 (clobber (match_operand:DI 1 "register_operand" ""))
3985 (clobber (match_operand:DI 4 "register_operand" ""))
3986 (use (match_operand:DI 2 "arith_operand" ""))
3987 (use (match_operand:DI 3 "const_int_operand" ""))])]
3988 "TARGET_64BIT && reload_completed && !flag_peephole2
3989 && GET_CODE (operands[0]) == MEM
3990 && register_operand (XEXP (operands[0], 0), DImode)"
3991 [(set (match_dup 4) (match_dup 5))
3992 (parallel [(set (match_dup 0) (const_int 0))
3993 (clobber (match_dup 1))
3994 (clobber (match_dup 4))
4000 operands[5] = XEXP (operands[0], 0);
4001 operands[0] = replace_equiv_address (operands[0], operands[4]);
4005 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4007 (clobber (match_operand:DI 1 "register_operand" ""))
4008 (clobber (match_operand:DI 4 "register_operand" ""))
4009 (use (match_operand:DI 2 "arith_operand" ""))
4010 (use (match_operand:DI 3 "const_int_operand" ""))])]
4012 && GET_CODE (operands[0]) == MEM
4013 && register_operand (XEXP (operands[0], 0), DImode)"
4014 [(parallel [(set (match_dup 0) (const_int 0))
4015 (clobber (match_dup 1))
4016 (clobber (match_dup 4))
4022 rtx addr = XEXP (operands[0], 0);
4023 if (dead_or_set_p (curr_insn, addr))
4027 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4028 operands[0] = replace_equiv_address (operands[0], operands[4]);
4032 (define_insn "clrmemdi_postreload"
4033 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
4035 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4036 (clobber (match_dup 0))
4037 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4038 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
4040 "TARGET_64BIT && reload_completed"
4041 "* return output_block_clear (operands, !which_alternative);"
4042 [(set_attr "type" "multi,multi")])
4044 ;; Floating point move insns
4046 ;; This pattern forces (set (reg:DF ...) (const_double ...))
4047 ;; to be reloaded by putting the constant into memory when
4048 ;; reg is a floating point register.
4050 ;; For integer registers we use ldil;ldo to set the appropriate
4053 ;; This must come before the movdf pattern, and it must be present
4054 ;; to handle obscure reloading cases.
4056 [(set (match_operand:DF 0 "register_operand" "=?r,f")
4057 (match_operand:DF 1 "" "?F,m"))]
4058 "GET_CODE (operands[1]) == CONST_DOUBLE
4059 && operands[1] != CONST0_RTX (DFmode)
4061 && !TARGET_SOFT_FLOAT"
4062 "* return (which_alternative == 0 ? output_move_double (operands)
4063 : \"fldd%F1 %1,%0\");"
4064 [(set_attr "type" "move,fpload")
4065 (set_attr "length" "16,4")])
4067 (define_expand "movdf"
4068 [(set (match_operand:DF 0 "general_operand" "")
4069 (match_operand:DF 1 "general_operand" ""))]
4073 if (GET_CODE (operands[1]) == CONST_DOUBLE
4074 && operands[1] != CONST0_RTX (DFmode))
4076 /* Reject CONST_DOUBLE loads to all hard registers when
4077 generating 64-bit code and to floating point registers
4078 when generating 32-bit code. */
4079 if (REG_P (operands[0])
4080 && HARD_REGISTER_P (operands[0])
4081 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
4085 operands[1] = force_const_mem (DFmode, operands[1]);
4088 if (emit_move_sequence (operands, DFmode, 0))
4092 ;; Handle DFmode input reloads requiring a general register as a
4093 ;; scratch register.
4094 (define_expand "reload_indf"
4095 [(set (match_operand:DF 0 "register_operand" "=Z")
4096 (match_operand:DF 1 "non_hard_reg_operand" ""))
4097 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4101 if (emit_move_sequence (operands, DFmode, operands[2]))
4104 /* We don't want the clobber emitted, so handle this ourselves. */
4105 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4109 ;; Handle DFmode output reloads requiring a general register as a
4110 ;; scratch register.
4111 (define_expand "reload_outdf"
4112 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
4113 (match_operand:DF 1 "register_operand" "Z"))
4114 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4118 if (emit_move_sequence (operands, DFmode, operands[2]))
4121 /* We don't want the clobber emitted, so handle this ourselves. */
4122 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4127 [(set (match_operand:DF 0 "move_dest_operand"
4128 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
4129 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4130 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
4131 "(register_operand (operands[0], DFmode)
4132 || reg_or_0_operand (operands[1], DFmode))
4133 && !(GET_CODE (operands[1]) == CONST_DOUBLE
4134 && GET_CODE (operands[0]) == MEM)
4136 && !TARGET_SOFT_FLOAT"
4139 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4140 || operands[1] == CONST0_RTX (DFmode))
4141 && !(REG_P (operands[0]) && REG_P (operands[1])
4142 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4143 return output_fp_move_double (operands);
4144 return output_move_double (operands);
4146 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
4147 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
4150 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
4151 (match_operand:DF 1 "reg_or_0_operand" "f"))]
4153 && !TARGET_DISABLE_INDEXING
4154 && reload_completed"
4156 [(set_attr "type" "fpstore")
4157 (set_attr "pa_combine_type" "addmove")
4158 (set_attr "length" "4")])
4161 [(set (match_operand:SI 0 "register_operand" "")
4162 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4164 (match_operand:SI 2 "register_operand" "")))
4165 (set (mem:DF (match_dup 0))
4166 (match_operand:DF 3 "register_operand" ""))]
4168 && !TARGET_DISABLE_INDEXING
4169 && REG_OK_FOR_BASE_P (operands[2])
4170 && FP_REGNO_P (REGNO (operands[3]))"
4171 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4173 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4178 [(set (match_operand:SI 0 "register_operand" "")
4179 (plus:SI (match_operand:SI 2 "register_operand" "")
4180 (mult:SI (match_operand:SI 1 "register_operand" "")
4182 (set (mem:DF (match_dup 0))
4183 (match_operand:DF 3 "register_operand" ""))]
4185 && !TARGET_DISABLE_INDEXING
4186 && REG_OK_FOR_BASE_P (operands[2])
4187 && FP_REGNO_P (REGNO (operands[3]))"
4188 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4190 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4195 [(set (match_operand:DI 0 "register_operand" "")
4196 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4198 (match_operand:DI 2 "register_operand" "")))
4199 (set (mem:DF (match_dup 0))
4200 (match_operand:DF 3 "register_operand" ""))]
4202 && !TARGET_DISABLE_INDEXING
4204 && REG_OK_FOR_BASE_P (operands[2])
4205 && FP_REGNO_P (REGNO (operands[3]))"
4206 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4208 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4213 [(set (match_operand:DI 0 "register_operand" "")
4214 (plus:DI (match_operand:DI 2 "register_operand" "")
4215 (mult:DI (match_operand:DI 1 "register_operand" "")
4217 (set (mem:DF (match_dup 0))
4218 (match_operand:DF 3 "register_operand" ""))]
4220 && !TARGET_DISABLE_INDEXING
4222 && REG_OK_FOR_BASE_P (operands[2])
4223 && FP_REGNO_P (REGNO (operands[3]))"
4224 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4226 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4231 [(set (match_operand:SI 0 "register_operand" "")
4232 (plus:SI (match_operand:SI 1 "register_operand" "")
4233 (match_operand:SI 2 "register_operand" "")))
4234 (set (mem:DF (match_dup 0))
4235 (match_operand:DF 3 "register_operand" ""))]
4237 && !TARGET_DISABLE_INDEXING
4238 && TARGET_NO_SPACE_REGS
4239 && REG_OK_FOR_INDEX_P (operands[1])
4240 && REG_OK_FOR_BASE_P (operands[2])
4241 && FP_REGNO_P (REGNO (operands[3]))"
4242 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
4244 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4248 [(set (match_operand:SI 0 "register_operand" "")
4249 (plus:SI (match_operand:SI 1 "register_operand" "")
4250 (match_operand:SI 2 "register_operand" "")))
4251 (set (mem:DF (match_dup 0))
4252 (match_operand:DF 3 "register_operand" ""))]
4254 && !TARGET_DISABLE_INDEXING
4255 && TARGET_NO_SPACE_REGS
4256 && REG_OK_FOR_BASE_P (operands[1])
4257 && REG_OK_FOR_INDEX_P (operands[2])
4258 && FP_REGNO_P (REGNO (operands[3]))"
4259 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
4261 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4265 [(set (match_operand:DI 0 "register_operand" "")
4266 (plus:DI (match_operand:DI 1 "register_operand" "")
4267 (match_operand:DI 2 "register_operand" "")))
4268 (set (mem:DF (match_dup 0))
4269 (match_operand:DF 3 "register_operand" ""))]
4271 && !TARGET_DISABLE_INDEXING
4273 && TARGET_NO_SPACE_REGS
4274 && REG_OK_FOR_INDEX_P (operands[1])
4275 && REG_OK_FOR_BASE_P (operands[2])
4276 && FP_REGNO_P (REGNO (operands[3]))"
4277 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4279 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4283 [(set (match_operand:DI 0 "register_operand" "")
4284 (plus:DI (match_operand:DI 1 "register_operand" "")
4285 (match_operand:DI 2 "register_operand" "")))
4286 (set (mem:DF (match_dup 0))
4287 (match_operand:DF 3 "register_operand" ""))]
4289 && !TARGET_DISABLE_INDEXING
4291 && TARGET_NO_SPACE_REGS
4292 && REG_OK_FOR_BASE_P (operands[1])
4293 && REG_OK_FOR_INDEX_P (operands[2])
4294 && FP_REGNO_P (REGNO (operands[3]))"
4295 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4297 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4301 [(set (match_operand:DF 0 "move_dest_operand"
4303 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4305 "(register_operand (operands[0], DFmode)
4306 || reg_or_0_operand (operands[1], DFmode))
4308 && TARGET_SOFT_FLOAT"
4311 return output_move_double (operands);
4313 [(set_attr "type" "move,store,store,load,load")
4314 (set_attr "length" "8,8,16,8,16")])
4317 [(set (match_operand:DF 0 "move_dest_operand"
4318 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4319 (match_operand:DF 1 "move_src_operand"
4320 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4321 "(register_operand (operands[0], DFmode)
4322 || reg_or_0_operand (operands[1], DFmode))
4323 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4334 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4335 (set_attr "pa_combine_type" "addmove")
4336 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4339 (define_expand "movdi"
4340 [(set (match_operand:DI 0 "general_operand" "")
4341 (match_operand:DI 1 "general_operand" ""))]
4345 /* Except for zero, we don't support loading a CONST_INT directly
4346 to a hard floating-point register since a scratch register is
4347 needed for the operation. While the operation could be handled
4348 before register allocation, the simplest solution is to fail. */
4350 && GET_CODE (operands[1]) == CONST_INT
4351 && operands[1] != CONST0_RTX (DImode)
4352 && REG_P (operands[0])
4353 && HARD_REGISTER_P (operands[0])
4354 && REGNO (operands[0]) >= 32)
4357 if (emit_move_sequence (operands, DImode, 0))
4361 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4362 (define_expand "reload_indi_r1"
4363 [(set (match_operand:DI 0 "register_operand" "=Z")
4364 (match_operand:DI 1 "non_hard_reg_operand" ""))
4365 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4369 if (emit_move_sequence (operands, DImode, operands[2]))
4372 /* We don't want the clobber emitted, so handle this ourselves. */
4373 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4377 ;; Handle DImode input reloads requiring a general register as a
4378 ;; scratch register.
4379 (define_expand "reload_indi"
4380 [(set (match_operand:DI 0 "register_operand" "=Z")
4381 (match_operand:DI 1 "non_hard_reg_operand" ""))
4382 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4386 if (emit_move_sequence (operands, DImode, operands[2]))
4389 /* We don't want the clobber emitted, so handle this ourselves. */
4390 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4394 ;; Handle DImode output reloads requiring a general register as a
4395 ;; scratch register.
4396 (define_expand "reload_outdi"
4397 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4398 (match_operand:DI 1 "register_operand" "Z"))
4399 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4403 if (emit_move_sequence (operands, DImode, operands[2]))
4406 /* We don't want the clobber emitted, so handle this ourselves. */
4407 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4412 [(set (match_operand:DI 0 "register_operand" "=r")
4413 (high:DI (match_operand 1 "" "")))]
4417 rtx op0 = operands[0];
4418 rtx op1 = operands[1];
4420 switch (GET_CODE (op1))
4423 #if HOST_BITS_PER_WIDE_INT <= 32
4424 operands[0] = operand_subword (op0, 1, 0, DImode);
4425 output_asm_insn (\"ldil L'%1,%0\", operands);
4427 operands[0] = operand_subword (op0, 0, 0, DImode);
4428 if (INTVAL (op1) < 0)
4429 output_asm_insn (\"ldi -1,%0\", operands);
4431 output_asm_insn (\"ldi 0,%0\", operands);
4433 operands[0] = operand_subword (op0, 1, 0, DImode);
4434 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4435 output_asm_insn (\"ldil L'%1,%0\", operands);
4437 operands[0] = operand_subword (op0, 0, 0, DImode);
4438 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4439 output_asm_insn (singlemove_string (operands), operands);
4444 operands[0] = operand_subword (op0, 1, 0, DImode);
4445 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4446 output_asm_insn (\"ldil L'%1,%0\", operands);
4448 operands[0] = operand_subword (op0, 0, 0, DImode);
4449 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4450 output_asm_insn (singlemove_string (operands), operands);
4458 [(set_attr "type" "move")
4459 (set_attr "length" "12")])
4462 [(set (match_operand:DI 0 "move_dest_operand"
4463 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4464 (match_operand:DI 1 "general_operand"
4465 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4466 "(register_operand (operands[0], DImode)
4467 || reg_or_0_operand (operands[1], DImode))
4469 && !TARGET_SOFT_FLOAT"
4472 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4473 || operands[1] == CONST0_RTX (DFmode))
4474 && !(REG_P (operands[0]) && REG_P (operands[1])
4475 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4476 return output_fp_move_double (operands);
4477 return output_move_double (operands);
4480 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4481 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4484 [(set (match_operand:DI 0 "move_dest_operand"
4485 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4486 (match_operand:DI 1 "move_src_operand"
4487 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4488 "(register_operand (operands[0], DImode)
4489 || reg_or_0_operand (operands[1], DImode))
4490 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4500 {mfctl|mfctl,w} %%sar,%0
4504 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4505 (set_attr "pa_combine_type" "addmove")
4506 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4509 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4510 (match_operand:DI 1 "register_operand" "f"))]
4513 && !TARGET_DISABLE_INDEXING
4514 && reload_completed"
4516 [(set_attr "type" "fpstore")
4517 (set_attr "pa_combine_type" "addmove")
4518 (set_attr "length" "4")])
4521 [(set (match_operand:DI 0 "register_operand" "")
4522 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4524 (match_operand:DI 2 "register_operand" "")))
4525 (set (mem:DI (match_dup 0))
4526 (match_operand:DI 3 "register_operand" ""))]
4528 && !TARGET_DISABLE_INDEXING
4530 && REG_OK_FOR_BASE_P (operands[2])
4531 && FP_REGNO_P (REGNO (operands[3]))"
4532 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4534 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4539 [(set (match_operand:DI 0 "register_operand" "")
4540 (plus:DI (match_operand:DI 2 "register_operand" "")
4541 (mult:DI (match_operand:DI 1 "register_operand" "")
4543 (set (mem:DI (match_dup 0))
4544 (match_operand:DI 3 "register_operand" ""))]
4546 && !TARGET_DISABLE_INDEXING
4548 && REG_OK_FOR_BASE_P (operands[2])
4549 && FP_REGNO_P (REGNO (operands[3]))"
4550 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4552 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4557 [(set (match_operand:DI 0 "register_operand" "")
4558 (plus:DI (match_operand:DI 1 "register_operand" "")
4559 (match_operand:DI 2 "register_operand" "")))
4560 (set (mem:DI (match_dup 0))
4561 (match_operand:DI 3 "register_operand" ""))]
4563 && !TARGET_DISABLE_INDEXING
4565 && TARGET_NO_SPACE_REGS
4566 && REG_OK_FOR_INDEX_P (operands[1])
4567 && REG_OK_FOR_BASE_P (operands[2])
4568 && FP_REGNO_P (REGNO (operands[3]))"
4569 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4571 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4575 [(set (match_operand:DI 0 "register_operand" "")
4576 (plus:DI (match_operand:DI 1 "register_operand" "")
4577 (match_operand:DI 2 "register_operand" "")))
4578 (set (mem:DI (match_dup 0))
4579 (match_operand:DI 3 "register_operand" ""))]
4581 && !TARGET_DISABLE_INDEXING
4583 && TARGET_NO_SPACE_REGS
4584 && REG_OK_FOR_BASE_P (operands[1])
4585 && REG_OK_FOR_INDEX_P (operands[2])
4586 && FP_REGNO_P (REGNO (operands[3]))"
4587 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4589 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4593 [(set (match_operand:DI 0 "move_dest_operand"
4595 (match_operand:DI 1 "general_operand"
4597 "(register_operand (operands[0], DImode)
4598 || reg_or_0_operand (operands[1], DImode))
4600 && TARGET_SOFT_FLOAT"
4603 return output_move_double (operands);
4605 [(set_attr "type" "move,store,store,load,load,multi")
4606 (set_attr "length" "8,8,16,8,16,16")])
4609 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4610 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4611 (match_operand:DI 2 "immediate_operand" "i,i")))]
4615 /* Don't output a 64-bit constant, since we can't trust the assembler to
4616 handle it correctly. */
4617 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4618 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4619 else if (HOST_BITS_PER_WIDE_INT > 32
4620 && GET_CODE (operands[2]) == CONST_INT)
4621 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4622 if (which_alternative == 1)
4623 output_asm_insn (\"copy %1,%0\", operands);
4624 return \"ldo R'%G2(%R1),%R0\";
4626 [(set_attr "type" "move,move")
4627 (set_attr "length" "4,8")])
4629 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4630 ;; to be reloaded by putting the constant into memory when
4631 ;; reg is a floating point register.
4633 ;; For integer registers we use ldil;ldo to set the appropriate
4636 ;; This must come before the movsf pattern, and it must be present
4637 ;; to handle obscure reloading cases.
4639 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4640 (match_operand:SF 1 "" "?F,m"))]
4641 "GET_CODE (operands[1]) == CONST_DOUBLE
4642 && operands[1] != CONST0_RTX (SFmode)
4643 && ! TARGET_SOFT_FLOAT"
4644 "* return (which_alternative == 0 ? singlemove_string (operands)
4645 : \" fldw%F1 %1,%0\");"
4646 [(set_attr "type" "move,fpload")
4647 (set_attr "length" "8,4")])
4649 (define_expand "movsf"
4650 [(set (match_operand:SF 0 "general_operand" "")
4651 (match_operand:SF 1 "general_operand" ""))]
4655 /* Reject CONST_DOUBLE loads to floating point registers. */
4656 if (GET_CODE (operands[1]) == CONST_DOUBLE
4657 && operands[1] != CONST0_RTX (SFmode)
4658 && REG_P (operands[0])
4659 && HARD_REGISTER_P (operands[0])
4660 && REGNO (operands[0]) >= 32)
4663 if (emit_move_sequence (operands, SFmode, 0))
4667 ;; Handle SFmode input reloads requiring a general register as a
4668 ;; scratch register.
4669 (define_expand "reload_insf"
4670 [(set (match_operand:SF 0 "register_operand" "=Z")
4671 (match_operand:SF 1 "non_hard_reg_operand" ""))
4672 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4676 if (emit_move_sequence (operands, SFmode, operands[2]))
4679 /* We don't want the clobber emitted, so handle this ourselves. */
4680 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4684 ;; Handle SFmode output reloads requiring a general register as a
4685 ;; scratch register.
4686 (define_expand "reload_outsf"
4687 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4688 (match_operand:SF 1 "register_operand" "Z"))
4689 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4693 if (emit_move_sequence (operands, SFmode, operands[2]))
4696 /* We don't want the clobber emitted, so handle this ourselves. */
4697 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4702 [(set (match_operand:SF 0 "move_dest_operand"
4703 "=f,!*r,f,*r,Q,Q,?*r,?f")
4704 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4705 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4706 "(register_operand (operands[0], SFmode)
4707 || reg_or_0_operand (operands[1], SFmode))
4708 && !TARGET_SOFT_FLOAT
4717 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4718 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4719 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4720 (set_attr "pa_combine_type" "addmove")
4721 (set_attr "length" "4,4,4,4,4,4,8,8")])
4724 [(set (match_operand:SF 0 "move_dest_operand"
4726 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4727 "fG,!*rG,RQ,RQ,f,*rG"))]
4728 "(register_operand (operands[0], SFmode)
4729 || reg_or_0_operand (operands[1], SFmode))
4730 && !TARGET_SOFT_FLOAT
4739 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4740 (set_attr "pa_combine_type" "addmove")
4741 (set_attr "length" "4,4,4,4,4,4")])
4744 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4745 (match_operand:SF 1 "register_operand" "f"))]
4747 && !TARGET_DISABLE_INDEXING
4748 && reload_completed"
4750 [(set_attr "type" "fpstore")
4751 (set_attr "pa_combine_type" "addmove")
4752 (set_attr "length" "4")])
4755 [(set (match_operand:SI 0 "register_operand" "")
4756 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4758 (match_operand:SI 2 "register_operand" "")))
4759 (set (mem:SF (match_dup 0))
4760 (match_operand:SF 3 "register_operand" ""))]
4762 && !TARGET_DISABLE_INDEXING
4763 && REG_OK_FOR_BASE_P (operands[2])
4764 && FP_REGNO_P (REGNO (operands[3]))"
4765 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4767 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4772 [(set (match_operand:SI 0 "register_operand" "")
4773 (plus:SI (match_operand:SI 2 "register_operand" "")
4774 (mult:SI (match_operand:SI 1 "register_operand" "")
4776 (set (mem:SF (match_dup 0))
4777 (match_operand:SF 3 "register_operand" ""))]
4779 && !TARGET_DISABLE_INDEXING
4780 && REG_OK_FOR_BASE_P (operands[2])
4781 && FP_REGNO_P (REGNO (operands[3]))"
4782 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4784 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4789 [(set (match_operand:DI 0 "register_operand" "")
4790 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4792 (match_operand:DI 2 "register_operand" "")))
4793 (set (mem:SF (match_dup 0))
4794 (match_operand:SF 3 "register_operand" ""))]
4796 && !TARGET_DISABLE_INDEXING
4798 && REG_OK_FOR_BASE_P (operands[2])
4799 && FP_REGNO_P (REGNO (operands[3]))"
4800 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4802 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4807 [(set (match_operand:DI 0 "register_operand" "")
4808 (plus:DI (match_operand:DI 2 "register_operand" "")
4809 (mult:DI (match_operand:DI 1 "register_operand" "")
4811 (set (mem:SF (match_dup 0))
4812 (match_operand:SF 3 "register_operand" ""))]
4814 && !TARGET_DISABLE_INDEXING
4816 && REG_OK_FOR_BASE_P (operands[2])
4817 && FP_REGNO_P (REGNO (operands[3]))"
4818 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4820 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4825 [(set (match_operand:SI 0 "register_operand" "")
4826 (plus:SI (match_operand:SI 1 "register_operand" "")
4827 (match_operand:SI 2 "register_operand" "")))
4828 (set (mem:SF (match_dup 0))
4829 (match_operand:SF 3 "register_operand" ""))]
4831 && !TARGET_DISABLE_INDEXING
4832 && TARGET_NO_SPACE_REGS
4833 && REG_OK_FOR_INDEX_P (operands[1])
4834 && REG_OK_FOR_BASE_P (operands[2])
4835 && FP_REGNO_P (REGNO (operands[3]))"
4836 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4838 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4842 [(set (match_operand:SI 0 "register_operand" "")
4843 (plus:SI (match_operand:SI 1 "register_operand" "")
4844 (match_operand:SI 2 "register_operand" "")))
4845 (set (mem:SF (match_dup 0))
4846 (match_operand:SF 3 "register_operand" ""))]
4848 && !TARGET_DISABLE_INDEXING
4849 && TARGET_NO_SPACE_REGS
4850 && REG_OK_FOR_BASE_P (operands[1])
4851 && REG_OK_FOR_INDEX_P (operands[2])
4852 && FP_REGNO_P (REGNO (operands[3]))"
4853 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4855 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4859 [(set (match_operand:DI 0 "register_operand" "")
4860 (plus:DI (match_operand:DI 1 "register_operand" "")
4861 (match_operand:DI 2 "register_operand" "")))
4862 (set (mem:SF (match_dup 0))
4863 (match_operand:SF 3 "register_operand" ""))]
4865 && !TARGET_DISABLE_INDEXING
4867 && TARGET_NO_SPACE_REGS
4868 && REG_OK_FOR_INDEX_P (operands[1])
4869 && REG_OK_FOR_BASE_P (operands[2])
4870 && FP_REGNO_P (REGNO (operands[3]))"
4871 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4873 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4877 [(set (match_operand:DI 0 "register_operand" "")
4878 (plus:DI (match_operand:DI 1 "register_operand" "")
4879 (match_operand:DI 2 "register_operand" "")))
4880 (set (mem:SF (match_dup 0))
4881 (match_operand:SF 3 "register_operand" ""))]
4883 && !TARGET_DISABLE_INDEXING
4885 && TARGET_NO_SPACE_REGS
4886 && REG_OK_FOR_BASE_P (operands[1])
4887 && REG_OK_FOR_INDEX_P (operands[2])
4888 && FP_REGNO_P (REGNO (operands[3]))"
4889 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4891 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4895 [(set (match_operand:SF 0 "move_dest_operand"
4897 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4899 "(register_operand (operands[0], SFmode)
4900 || reg_or_0_operand (operands[1], SFmode))
4901 && TARGET_SOFT_FLOAT"
4906 [(set_attr "type" "move,load,store")
4907 (set_attr "pa_combine_type" "addmove")
4908 (set_attr "length" "4,4,4")])
4912 ;;- zero extension instructions
4913 ;; We have define_expand for zero extension patterns to make sure the
4914 ;; operands get loaded into registers. The define_insns accept
4915 ;; memory operands. This gives us better overall code than just
4916 ;; having a pattern that does or does not accept memory operands.
4918 (define_expand "zero_extendqihi2"
4919 [(set (match_operand:HI 0 "register_operand" "")
4921 (match_operand:QI 1 "register_operand" "")))]
4926 [(set (match_operand:HI 0 "register_operand" "=r,r")
4928 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4929 "GET_CODE (operands[1]) != CONST_INT"
4931 {extru|extrw,u} %1,31,8,%0
4933 [(set_attr "type" "shift,load")
4934 (set_attr "length" "4,4")])
4936 (define_expand "zero_extendqisi2"
4937 [(set (match_operand:SI 0 "register_operand" "")
4939 (match_operand:QI 1 "register_operand" "")))]
4944 [(set (match_operand:SI 0 "register_operand" "=r,r")
4946 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4947 "GET_CODE (operands[1]) != CONST_INT"
4949 {extru|extrw,u} %1,31,8,%0
4951 [(set_attr "type" "shift,load")
4952 (set_attr "length" "4,4")])
4954 (define_expand "zero_extendhisi2"
4955 [(set (match_operand:SI 0 "register_operand" "")
4957 (match_operand:HI 1 "register_operand" "")))]
4962 [(set (match_operand:SI 0 "register_operand" "=r,r")
4964 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4965 "GET_CODE (operands[1]) != CONST_INT"
4967 {extru|extrw,u} %1,31,16,%0
4969 [(set_attr "type" "shift,load")
4970 (set_attr "length" "4,4")])
4972 (define_expand "zero_extendqidi2"
4973 [(set (match_operand:DI 0 "register_operand" "")
4975 (match_operand:QI 1 "register_operand" "")))]
4980 [(set (match_operand:DI 0 "register_operand" "=r,r")
4982 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4983 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4987 [(set_attr "type" "shift,load")
4988 (set_attr "length" "4,4")])
4990 (define_expand "zero_extendhidi2"
4991 [(set (match_operand:DI 0 "register_operand" "")
4993 (match_operand:HI 1 "register_operand" "")))]
4998 [(set (match_operand:DI 0 "register_operand" "=r,r")
5000 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
5001 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5005 [(set_attr "type" "shift,load")
5006 (set_attr "length" "4,4")])
5008 (define_expand "zero_extendsidi2"
5009 [(set (match_operand:DI 0 "register_operand" "")
5011 (match_operand:SI 1 "register_operand" "")))]
5016 [(set (match_operand:DI 0 "register_operand" "=r,r")
5018 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
5019 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5023 [(set_attr "type" "shift,load")
5024 (set_attr "length" "4,4")])
5026 ;;- sign extension instructions
5028 (define_insn "extendhisi2"
5029 [(set (match_operand:SI 0 "register_operand" "=r")
5030 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
5032 "{extrs|extrw,s} %1,31,16,%0"
5033 [(set_attr "type" "shift")
5034 (set_attr "length" "4")])
5036 (define_insn "extendqihi2"
5037 [(set (match_operand:HI 0 "register_operand" "=r")
5038 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
5040 "{extrs|extrw,s} %1,31,8,%0"
5041 [(set_attr "type" "shift")
5042 (set_attr "length" "4")])
5044 (define_insn "extendqisi2"
5045 [(set (match_operand:SI 0 "register_operand" "=r")
5046 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
5048 "{extrs|extrw,s} %1,31,8,%0"
5049 [(set_attr "type" "shift")
5050 (set_attr "length" "4")])
5052 (define_insn "extendqidi2"
5053 [(set (match_operand:DI 0 "register_operand" "=r")
5054 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
5056 "extrd,s %1,63,8,%0"
5057 [(set_attr "type" "shift")
5058 (set_attr "length" "4")])
5060 (define_insn "extendhidi2"
5061 [(set (match_operand:DI 0 "register_operand" "=r")
5062 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
5064 "extrd,s %1,63,16,%0"
5065 [(set_attr "type" "shift")
5066 (set_attr "length" "4")])
5068 (define_insn "extendsidi2"
5069 [(set (match_operand:DI 0 "register_operand" "=r")
5070 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
5072 "extrd,s %1,63,32,%0"
5073 [(set_attr "type" "shift")
5074 (set_attr "length" "4")])
5077 ;; Conversions between float and double.
5079 (define_insn "extendsfdf2"
5080 [(set (match_operand:DF 0 "register_operand" "=f")
5082 (match_operand:SF 1 "register_operand" "f")))]
5083 "! TARGET_SOFT_FLOAT"
5084 "{fcnvff|fcnv},sgl,dbl %1,%0"
5085 [(set_attr "type" "fpalu")
5086 (set_attr "length" "4")])
5088 (define_insn "truncdfsf2"
5089 [(set (match_operand:SF 0 "register_operand" "=f")
5091 (match_operand:DF 1 "register_operand" "f")))]
5092 "! TARGET_SOFT_FLOAT"
5093 "{fcnvff|fcnv},dbl,sgl %1,%0"
5094 [(set_attr "type" "fpalu")
5095 (set_attr "length" "4")])
5097 ;; Conversion between fixed point and floating point.
5098 ;; Note that among the fix-to-float insns
5099 ;; the ones that start with SImode come first.
5100 ;; That is so that an operand that is a CONST_INT
5101 ;; (and therefore lacks a specific machine mode).
5102 ;; will be recognized as SImode (which is always valid)
5103 ;; rather than as QImode or HImode.
5105 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
5106 ;; to be reloaded by putting the constant into memory.
5107 ;; It must come before the more general floatsisf2 pattern.
5109 [(set (match_operand:SF 0 "register_operand" "=f")
5110 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
5111 "! TARGET_SOFT_FLOAT"
5112 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
5113 [(set_attr "type" "fpalu")
5114 (set_attr "length" "8")])
5116 (define_insn "floatsisf2"
5117 [(set (match_operand:SF 0 "register_operand" "=f")
5118 (float:SF (match_operand:SI 1 "register_operand" "f")))]
5119 "! TARGET_SOFT_FLOAT"
5120 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
5121 [(set_attr "type" "fpalu")
5122 (set_attr "length" "4")])
5124 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
5125 ;; to be reloaded by putting the constant into memory.
5126 ;; It must come before the more general floatsidf2 pattern.
5128 [(set (match_operand:DF 0 "register_operand" "=f")
5129 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
5130 "! TARGET_SOFT_FLOAT"
5131 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
5132 [(set_attr "type" "fpalu")
5133 (set_attr "length" "8")])
5135 (define_insn "floatsidf2"
5136 [(set (match_operand:DF 0 "register_operand" "=f")
5137 (float:DF (match_operand:SI 1 "register_operand" "f")))]
5138 "! TARGET_SOFT_FLOAT"
5139 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
5140 [(set_attr "type" "fpalu")
5141 (set_attr "length" "4")])
5143 (define_expand "floatunssisf2"
5144 [(set (subreg:SI (match_dup 2) 4)
5145 (match_operand:SI 1 "register_operand" ""))
5146 (set (subreg:SI (match_dup 2) 0)
5148 (set (match_operand:SF 0 "register_operand" "")
5149 (float:SF (match_dup 2)))]
5150 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5155 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
5158 operands[2] = gen_reg_rtx (DImode);
5161 (define_expand "floatunssidf2"
5162 [(set (subreg:SI (match_dup 2) 4)
5163 (match_operand:SI 1 "register_operand" ""))
5164 (set (subreg:SI (match_dup 2) 0)
5166 (set (match_operand:DF 0 "register_operand" "")
5167 (float:DF (match_dup 2)))]
5168 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5173 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
5176 operands[2] = gen_reg_rtx (DImode);
5179 (define_insn "floatdisf2"
5180 [(set (match_operand:SF 0 "register_operand" "=f")
5181 (float:SF (match_operand:DI 1 "register_operand" "f")))]
5182 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5183 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
5184 [(set_attr "type" "fpalu")
5185 (set_attr "length" "4")])
5187 (define_insn "floatdidf2"
5188 [(set (match_operand:DF 0 "register_operand" "=f")
5189 (float:DF (match_operand:DI 1 "register_operand" "f")))]
5190 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5191 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
5192 [(set_attr "type" "fpalu")
5193 (set_attr "length" "4")])
5195 ;; Convert a float to an actual integer.
5196 ;; Truncation is performed as part of the conversion.
5198 (define_insn "fix_truncsfsi2"
5199 [(set (match_operand:SI 0 "register_operand" "=f")
5200 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5201 "! TARGET_SOFT_FLOAT"
5202 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
5203 [(set_attr "type" "fpalu")
5204 (set_attr "length" "4")])
5206 (define_insn "fix_truncdfsi2"
5207 [(set (match_operand:SI 0 "register_operand" "=f")
5208 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5209 "! TARGET_SOFT_FLOAT"
5210 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
5211 [(set_attr "type" "fpalu")
5212 (set_attr "length" "4")])
5214 (define_insn "fix_truncsfdi2"
5215 [(set (match_operand:DI 0 "register_operand" "=f")
5216 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5217 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5218 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
5219 [(set_attr "type" "fpalu")
5220 (set_attr "length" "4")])
5222 (define_insn "fix_truncdfdi2"
5223 [(set (match_operand:DI 0 "register_operand" "=f")
5224 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5225 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5226 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
5227 [(set_attr "type" "fpalu")
5228 (set_attr "length" "4")])
5230 (define_insn "floatunssidf2_pa20"
5231 [(set (match_operand:DF 0 "register_operand" "=f")
5232 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
5233 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5235 [(set_attr "type" "fpalu")
5236 (set_attr "length" "4")])
5238 (define_insn "floatunssisf2_pa20"
5239 [(set (match_operand:SF 0 "register_operand" "=f")
5240 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
5241 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5243 [(set_attr "type" "fpalu")
5244 (set_attr "length" "4")])
5246 (define_insn "floatunsdisf2"
5247 [(set (match_operand:SF 0 "register_operand" "=f")
5248 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
5249 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5250 "fcnv,udw,sgl %1,%0"
5251 [(set_attr "type" "fpalu")
5252 (set_attr "length" "4")])
5254 (define_insn "floatunsdidf2"
5255 [(set (match_operand:DF 0 "register_operand" "=f")
5256 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
5257 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5258 "fcnv,udw,dbl %1,%0"
5259 [(set_attr "type" "fpalu")
5260 (set_attr "length" "4")])
5262 (define_insn "fixuns_truncsfsi2"
5263 [(set (match_operand:SI 0 "register_operand" "=f")
5264 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5265 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5266 "fcnv,t,sgl,uw %1,%0"
5267 [(set_attr "type" "fpalu")
5268 (set_attr "length" "4")])
5270 (define_insn "fixuns_truncdfsi2"
5271 [(set (match_operand:SI 0 "register_operand" "=f")
5272 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5273 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5274 "fcnv,t,dbl,uw %1,%0"
5275 [(set_attr "type" "fpalu")
5276 (set_attr "length" "4")])
5278 (define_insn "fixuns_truncsfdi2"
5279 [(set (match_operand:DI 0 "register_operand" "=f")
5280 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5281 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5282 "fcnv,t,sgl,udw %1,%0"
5283 [(set_attr "type" "fpalu")
5284 (set_attr "length" "4")])
5286 (define_insn "fixuns_truncdfdi2"
5287 [(set (match_operand:DI 0 "register_operand" "=f")
5288 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5289 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5290 "fcnv,t,dbl,udw %1,%0"
5291 [(set_attr "type" "fpalu")
5292 (set_attr "length" "4")])
5294 ;;- arithmetic instructions
5296 (define_expand "adddi3"
5297 [(set (match_operand:DI 0 "register_operand" "")
5298 (plus:DI (match_operand:DI 1 "register_operand" "")
5299 (match_operand:DI 2 "adddi3_operand" "")))]
5304 [(set (match_operand:DI 0 "register_operand" "=r")
5305 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5306 (match_operand:DI 2 "arith11_operand" "rI")))]
5310 if (GET_CODE (operands[2]) == CONST_INT)
5312 if (INTVAL (operands[2]) >= 0)
5313 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5315 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5318 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5320 [(set_attr "type" "binary")
5321 (set_attr "length" "8")])
5324 [(set (match_operand:DI 0 "register_operand" "=r,r")
5325 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5326 (match_operand:DI 2 "arith_operand" "r,J")))]
5331 [(set_attr "type" "binary,binary")
5332 (set_attr "pa_combine_type" "addmove")
5333 (set_attr "length" "4,4")])
5336 [(set (match_operand:DI 0 "register_operand" "=r")
5337 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5338 (match_operand:DI 2 "register_operand" "r")))]
5341 [(set_attr "type" "binary")
5342 (set_attr "length" "4")])
5345 [(set (match_operand:SI 0 "register_operand" "=r")
5346 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5347 (match_operand:SI 2 "register_operand" "r")))]
5350 [(set_attr "type" "binary")
5351 (set_attr "length" "4")])
5353 (define_expand "addvdi3"
5354 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5355 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
5356 (match_operand:DI 2 "arith11_operand" "")))
5357 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5358 (sign_extend:TI (match_dup 2)))
5359 (sign_extend:TI (plus:DI (match_dup 1)
5366 [(set (match_operand:DI 0 "register_operand" "=r,r")
5367 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
5368 (match_operand:DI 2 "arith11_operand" "r,I")))
5369 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5370 (sign_extend:TI (match_dup 2)))
5371 (sign_extend:TI (plus:DI (match_dup 1)
5377 addi,tsv,* %2,%1,%0"
5378 [(set_attr "type" "binary,binary")
5379 (set_attr "length" "4,4")])
5382 [(set (match_operand:DI 0 "register_operand" "=r")
5383 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5384 (match_operand:DI 2 "arith11_operand" "rI")))
5385 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5386 (sign_extend:TI (match_dup 2)))
5387 (sign_extend:TI (plus:DI (match_dup 1)
5393 if (GET_CODE (operands[2]) == CONST_INT)
5395 if (INTVAL (operands[2]) >= 0)
5396 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5398 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5401 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5403 [(set_attr "type" "binary")
5404 (set_attr "length" "8")])
5406 ;; define_splits to optimize cases of adding a constant integer
5407 ;; to a register when the constant does not fit in 14 bits. */
5409 [(set (match_operand:SI 0 "register_operand" "")
5410 (plus:SI (match_operand:SI 1 "register_operand" "")
5411 (match_operand:SI 2 "const_int_operand" "")))
5412 (clobber (match_operand:SI 4 "register_operand" ""))]
5413 "! cint_ok_for_move (INTVAL (operands[2]))
5414 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5415 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5416 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5419 int val = INTVAL (operands[2]);
5420 int low = (val < 0) ? -0x2000 : 0x1fff;
5421 int rest = val - low;
5423 operands[2] = GEN_INT (rest);
5424 operands[3] = GEN_INT (low);
5428 [(set (match_operand:SI 0 "register_operand" "")
5429 (plus:SI (match_operand:SI 1 "register_operand" "")
5430 (match_operand:SI 2 "const_int_operand" "")))
5431 (clobber (match_operand:SI 4 "register_operand" ""))]
5432 "! cint_ok_for_move (INTVAL (operands[2]))"
5433 [(set (match_dup 4) (match_dup 2))
5434 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5438 HOST_WIDE_INT intval = INTVAL (operands[2]);
5440 /* Try dividing the constant by 2, then 4, and finally 8 to see
5441 if we can get a constant which can be loaded into a register
5442 in a single instruction (cint_ok_for_move).
5444 If that fails, try to negate the constant and subtract it
5445 from our input operand. */
5446 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5448 operands[2] = GEN_INT (intval / 2);
5449 operands[3] = const2_rtx;
5451 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5453 operands[2] = GEN_INT (intval / 4);
5454 operands[3] = GEN_INT (4);
5456 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5458 operands[2] = GEN_INT (intval / 8);
5459 operands[3] = GEN_INT (8);
5461 else if (cint_ok_for_move (-intval))
5463 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5464 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5471 (define_insn "addsi3"
5472 [(set (match_operand:SI 0 "register_operand" "=r,r")
5473 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5474 (match_operand:SI 2 "arith_operand" "r,J")))]
5477 {addl|add,l} %1,%2,%0
5479 [(set_attr "type" "binary,binary")
5480 (set_attr "pa_combine_type" "addmove")
5481 (set_attr "length" "4,4")])
5483 (define_insn "addvsi3"
5484 [(set (match_operand:SI 0 "register_operand" "=r,r")
5485 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5486 (match_operand:SI 2 "arith11_operand" "r,I")))
5487 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5488 (sign_extend:DI (match_dup 2)))
5489 (sign_extend:DI (plus:SI (match_dup 1)
5494 {addo|add,tsv} %2,%1,%0
5495 {addio|addi,tsv} %2,%1,%0"
5496 [(set_attr "type" "binary,binary")
5497 (set_attr "length" "4,4")])
5499 (define_expand "subdi3"
5500 [(set (match_operand:DI 0 "register_operand" "")
5501 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5502 (match_operand:DI 2 "reg_or_0_operand" "")))]
5507 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5508 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5509 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5515 [(set_attr "type" "binary,binary,move")
5516 (set_attr "length" "4,4,4")])
5519 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5520 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5521 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5525 if (GET_CODE (operands[1]) == CONST_INT)
5527 if (INTVAL (operands[1]) >= 0)
5528 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5530 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5533 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5535 [(set_attr "type" "binary")
5536 (set (attr "length")
5537 (if_then_else (eq_attr "alternative" "0")
5539 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5544 (define_expand "subvdi3"
5545 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5546 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5547 (match_operand:DI 2 "reg_or_0_operand" "")))
5548 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5549 (sign_extend:TI (match_dup 2)))
5550 (sign_extend:TI (minus:DI (match_dup 1)
5557 [(set (match_operand:DI 0 "register_operand" "=r,r")
5558 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5559 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5560 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5561 (sign_extend:TI (match_dup 2)))
5562 (sign_extend:TI (minus:DI (match_dup 1)
5567 {subo|sub,tsv} %1,%2,%0
5568 {subio|subi,tsv} %1,%2,%0"
5569 [(set_attr "type" "binary,binary")
5570 (set_attr "length" "4,4")])
5573 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5574 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5575 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5576 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5577 (sign_extend:TI (match_dup 2)))
5578 (sign_extend:TI (minus:DI (match_dup 1)
5584 if (GET_CODE (operands[1]) == CONST_INT)
5586 if (INTVAL (operands[1]) >= 0)
5587 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5589 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5592 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5594 [(set_attr "type" "binary,binary")
5595 (set (attr "length")
5596 (if_then_else (eq_attr "alternative" "0")
5598 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5603 (define_expand "subsi3"
5604 [(set (match_operand:SI 0 "register_operand" "")
5605 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5606 (match_operand:SI 2 "register_operand" "")))]
5611 [(set (match_operand:SI 0 "register_operand" "=r,r")
5612 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5613 (match_operand:SI 2 "register_operand" "r,r")))]
5618 [(set_attr "type" "binary,binary")
5619 (set_attr "length" "4,4")])
5622 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5623 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5624 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5630 [(set_attr "type" "binary,binary,move")
5631 (set_attr "length" "4,4,4")])
5633 (define_insn "subvsi3"
5634 [(set (match_operand:SI 0 "register_operand" "=r,r")
5635 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5636 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5637 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5638 (sign_extend:DI (match_dup 2)))
5639 (sign_extend:DI (minus:SI (match_dup 1)
5644 {subo|sub,tsv} %1,%2,%0
5645 {subio|subi,tsv} %1,%2,%0"
5646 [(set_attr "type" "binary,binary")
5647 (set_attr "length" "4,4")])
5649 ;; Clobbering a "register_operand" instead of a match_scratch
5650 ;; in operand3 of millicode calls avoids spilling %r1 and
5651 ;; produces better code.
5653 ;; The mulsi3 insns set up registers for the millicode call.
5654 (define_expand "mulsi3"
5655 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5656 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5657 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5658 (clobber (match_dup 3))
5659 (clobber (reg:SI 26))
5660 (clobber (reg:SI 25))
5661 (clobber (match_dup 4))])
5662 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5666 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5667 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5669 rtx scratch = gen_reg_rtx (DImode);
5670 operands[1] = force_reg (SImode, operands[1]);
5671 operands[2] = force_reg (SImode, operands[2]);
5672 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5673 emit_insn (gen_movsi (operands[0],
5674 gen_rtx_SUBREG (SImode, scratch,
5675 GET_MODE_SIZE (SImode))));
5678 operands[3] = gen_reg_rtx (SImode);
5681 (define_insn "umulsidi3"
5682 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5683 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5684 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5685 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5687 [(set_attr "type" "fpmuldbl")
5688 (set_attr "length" "4")])
5691 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5692 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5693 (match_operand:DI 2 "uint32_operand" "f")))]
5694 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5696 [(set_attr "type" "fpmuldbl")
5697 (set_attr "length" "4")])
5700 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5701 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5702 (match_operand:DI 2 "uint32_operand" "f")))]
5703 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5705 [(set_attr "type" "fpmuldbl")
5706 (set_attr "length" "4")])
5709 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5710 (clobber (match_operand:SI 0 "register_operand" "=a"))
5711 (clobber (reg:SI 26))
5712 (clobber (reg:SI 25))
5713 (clobber (reg:SI 31))]
5715 "* return output_mul_insn (0, insn);"
5716 [(set_attr "type" "milli")
5717 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5720 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5721 (clobber (match_operand:SI 0 "register_operand" "=a"))
5722 (clobber (reg:SI 26))
5723 (clobber (reg:SI 25))
5724 (clobber (reg:SI 2))]
5726 "* return output_mul_insn (0, insn);"
5727 [(set_attr "type" "milli")
5728 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5730 (define_expand "muldi3"
5731 [(set (match_operand:DI 0 "register_operand" "")
5732 (mult:DI (match_operand:DI 1 "register_operand" "")
5733 (match_operand:DI 2 "register_operand" "")))]
5734 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5737 rtx low_product = gen_reg_rtx (DImode);
5738 rtx cross_product1 = gen_reg_rtx (DImode);
5739 rtx cross_product2 = gen_reg_rtx (DImode);
5740 rtx cross_scratch = gen_reg_rtx (DImode);
5741 rtx cross_product = gen_reg_rtx (DImode);
5742 rtx op1l, op1r, op2l, op2r;
5743 rtx op1shifted, op2shifted;
5745 op1shifted = gen_reg_rtx (DImode);
5746 op2shifted = gen_reg_rtx (DImode);
5747 op1l = gen_reg_rtx (SImode);
5748 op1r = gen_reg_rtx (SImode);
5749 op2l = gen_reg_rtx (SImode);
5750 op2r = gen_reg_rtx (SImode);
5752 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5754 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5756 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5757 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5758 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5759 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5761 /* Emit multiplies for the cross products. */
5762 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5763 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5765 /* Emit a multiply for the low sub-word. */
5766 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5768 /* Sum the cross products and shift them into proper position. */
5769 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5770 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5772 /* Add the cross product to the low product and store the result
5773 into the output operand . */
5774 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5778 ;;; Division and mod.
5779 (define_expand "divsi3"
5780 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5781 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5782 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5783 (clobber (match_dup 3))
5784 (clobber (match_dup 4))
5785 (clobber (reg:SI 26))
5786 (clobber (reg:SI 25))
5787 (clobber (match_dup 5))])
5788 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5792 operands[3] = gen_reg_rtx (SImode);
5795 operands[5] = gen_rtx_REG (SImode, 2);
5796 operands[4] = operands[5];
5800 operands[5] = gen_rtx_REG (SImode, 31);
5801 operands[4] = gen_reg_rtx (SImode);
5803 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5809 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5810 (clobber (match_operand:SI 1 "register_operand" "=a"))
5811 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5812 (clobber (reg:SI 26))
5813 (clobber (reg:SI 25))
5814 (clobber (reg:SI 31))]
5817 return output_div_insn (operands, 0, insn);"
5818 [(set_attr "type" "milli")
5819 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5823 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5824 (clobber (match_operand:SI 1 "register_operand" "=a"))
5825 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5826 (clobber (reg:SI 26))
5827 (clobber (reg:SI 25))
5828 (clobber (reg:SI 2))]
5831 return output_div_insn (operands, 0, insn);"
5832 [(set_attr "type" "milli")
5833 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5835 (define_expand "udivsi3"
5836 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5837 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5838 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5839 (clobber (match_dup 3))
5840 (clobber (match_dup 4))
5841 (clobber (reg:SI 26))
5842 (clobber (reg:SI 25))
5843 (clobber (match_dup 5))])
5844 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5848 operands[3] = gen_reg_rtx (SImode);
5852 operands[5] = gen_rtx_REG (SImode, 2);
5853 operands[4] = operands[5];
5857 operands[5] = gen_rtx_REG (SImode, 31);
5858 operands[4] = gen_reg_rtx (SImode);
5860 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5866 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5867 (clobber (match_operand:SI 1 "register_operand" "=a"))
5868 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5869 (clobber (reg:SI 26))
5870 (clobber (reg:SI 25))
5871 (clobber (reg:SI 31))]
5874 return output_div_insn (operands, 1, insn);"
5875 [(set_attr "type" "milli")
5876 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5880 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5881 (clobber (match_operand:SI 1 "register_operand" "=a"))
5882 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5883 (clobber (reg:SI 26))
5884 (clobber (reg:SI 25))
5885 (clobber (reg:SI 2))]
5888 return output_div_insn (operands, 1, insn);"
5889 [(set_attr "type" "milli")
5890 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5892 (define_expand "modsi3"
5893 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5894 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5895 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5896 (clobber (match_dup 3))
5897 (clobber (match_dup 4))
5898 (clobber (reg:SI 26))
5899 (clobber (reg:SI 25))
5900 (clobber (match_dup 5))])
5901 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5907 operands[5] = gen_rtx_REG (SImode, 2);
5908 operands[4] = operands[5];
5912 operands[5] = gen_rtx_REG (SImode, 31);
5913 operands[4] = gen_reg_rtx (SImode);
5915 operands[3] = gen_reg_rtx (SImode);
5919 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5920 (clobber (match_operand:SI 0 "register_operand" "=a"))
5921 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5922 (clobber (reg:SI 26))
5923 (clobber (reg:SI 25))
5924 (clobber (reg:SI 31))]
5927 return output_mod_insn (0, insn);"
5928 [(set_attr "type" "milli")
5929 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5932 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5933 (clobber (match_operand:SI 0 "register_operand" "=a"))
5934 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5935 (clobber (reg:SI 26))
5936 (clobber (reg:SI 25))
5937 (clobber (reg:SI 2))]
5940 return output_mod_insn (0, insn);"
5941 [(set_attr "type" "milli")
5942 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5944 (define_expand "umodsi3"
5945 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5946 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5947 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5948 (clobber (match_dup 3))
5949 (clobber (match_dup 4))
5950 (clobber (reg:SI 26))
5951 (clobber (reg:SI 25))
5952 (clobber (match_dup 5))])
5953 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5959 operands[5] = gen_rtx_REG (SImode, 2);
5960 operands[4] = operands[5];
5964 operands[5] = gen_rtx_REG (SImode, 31);
5965 operands[4] = gen_reg_rtx (SImode);
5967 operands[3] = gen_reg_rtx (SImode);
5971 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5972 (clobber (match_operand:SI 0 "register_operand" "=a"))
5973 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5974 (clobber (reg:SI 26))
5975 (clobber (reg:SI 25))
5976 (clobber (reg:SI 31))]
5979 return output_mod_insn (1, insn);"
5980 [(set_attr "type" "milli")
5981 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5984 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5985 (clobber (match_operand:SI 0 "register_operand" "=a"))
5986 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5987 (clobber (reg:SI 26))
5988 (clobber (reg:SI 25))
5989 (clobber (reg:SI 2))]
5992 return output_mod_insn (1, insn);"
5993 [(set_attr "type" "milli")
5994 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5996 ;;- and instructions
5997 ;; We define DImode `and` so with DImode `not` we can get
5998 ;; DImode `andn`. Other combinations are possible.
6000 (define_expand "anddi3"
6001 [(set (match_operand:DI 0 "register_operand" "")
6002 (and:DI (match_operand:DI 1 "register_operand" "")
6003 (match_operand:DI 2 "and_operand" "")))]
6007 /* Both operands must be register operands. */
6008 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6013 [(set (match_operand:DI 0 "register_operand" "=r")
6014 (and:DI (match_operand:DI 1 "register_operand" "%r")
6015 (match_operand:DI 2 "register_operand" "r")))]
6017 "and %1,%2,%0\;and %R1,%R2,%R0"
6018 [(set_attr "type" "binary")
6019 (set_attr "length" "8")])
6022 [(set (match_operand:DI 0 "register_operand" "=r,r")
6023 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
6024 (match_operand:DI 2 "and_operand" "rO,P")))]
6026 "* return output_64bit_and (operands); "
6027 [(set_attr "type" "binary")
6028 (set_attr "length" "4")])
6030 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
6031 ; constant with ldil;ldo.
6032 (define_insn "andsi3"
6033 [(set (match_operand:SI 0 "register_operand" "=r,r")
6034 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
6035 (match_operand:SI 2 "and_operand" "rO,P")))]
6037 "* return output_and (operands); "
6038 [(set_attr "type" "binary,shift")
6039 (set_attr "length" "4,4")])
6042 [(set (match_operand:DI 0 "register_operand" "=r")
6043 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6044 (match_operand:DI 2 "register_operand" "r")))]
6046 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
6047 [(set_attr "type" "binary")
6048 (set_attr "length" "8")])
6051 [(set (match_operand:DI 0 "register_operand" "=r")
6052 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6053 (match_operand:DI 2 "register_operand" "r")))]
6056 [(set_attr "type" "binary")
6057 (set_attr "length" "4")])
6060 [(set (match_operand:SI 0 "register_operand" "=r")
6061 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
6062 (match_operand:SI 2 "register_operand" "r")))]
6065 [(set_attr "type" "binary")
6066 (set_attr "length" "4")])
6068 (define_expand "iordi3"
6069 [(set (match_operand:DI 0 "register_operand" "")
6070 (ior:DI (match_operand:DI 1 "register_operand" "")
6071 (match_operand:DI 2 "ior_operand" "")))]
6075 /* Both operands must be register operands. */
6076 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6081 [(set (match_operand:DI 0 "register_operand" "=r")
6082 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6083 (match_operand:DI 2 "register_operand" "r")))]
6085 "or %1,%2,%0\;or %R1,%R2,%R0"
6086 [(set_attr "type" "binary")
6087 (set_attr "length" "8")])
6090 [(set (match_operand:DI 0 "register_operand" "=r,r")
6091 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
6092 (match_operand:DI 2 "ior_operand" "M,i")))]
6094 "* return output_64bit_ior (operands); "
6095 [(set_attr "type" "binary,shift")
6096 (set_attr "length" "4,4")])
6099 [(set (match_operand:DI 0 "register_operand" "=r")
6100 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6101 (match_operand:DI 2 "register_operand" "r")))]
6104 [(set_attr "type" "binary")
6105 (set_attr "length" "4")])
6107 ;; Need a define_expand because we've run out of CONST_OK... characters.
6108 (define_expand "iorsi3"
6109 [(set (match_operand:SI 0 "register_operand" "")
6110 (ior:SI (match_operand:SI 1 "register_operand" "")
6111 (match_operand:SI 2 "arith32_operand" "")))]
6115 if (! (ior_operand (operands[2], SImode)
6116 || register_operand (operands[2], SImode)))
6117 operands[2] = force_reg (SImode, operands[2]);
6121 [(set (match_operand:SI 0 "register_operand" "=r,r")
6122 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
6123 (match_operand:SI 2 "ior_operand" "M,i")))]
6125 "* return output_ior (operands); "
6126 [(set_attr "type" "binary,shift")
6127 (set_attr "length" "4,4")])
6130 [(set (match_operand:SI 0 "register_operand" "=r")
6131 (ior:SI (match_operand:SI 1 "register_operand" "%r")
6132 (match_operand:SI 2 "register_operand" "r")))]
6135 [(set_attr "type" "binary")
6136 (set_attr "length" "4")])
6138 (define_expand "xordi3"
6139 [(set (match_operand:DI 0 "register_operand" "")
6140 (xor:DI (match_operand:DI 1 "register_operand" "")
6141 (match_operand:DI 2 "register_operand" "")))]
6148 [(set (match_operand:DI 0 "register_operand" "=r")
6149 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6150 (match_operand:DI 2 "register_operand" "r")))]
6152 "xor %1,%2,%0\;xor %R1,%R2,%R0"
6153 [(set_attr "type" "binary")
6154 (set_attr "length" "8")])
6157 [(set (match_operand:DI 0 "register_operand" "=r")
6158 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6159 (match_operand:DI 2 "register_operand" "r")))]
6162 [(set_attr "type" "binary")
6163 (set_attr "length" "4")])
6165 (define_insn "xorsi3"
6166 [(set (match_operand:SI 0 "register_operand" "=r")
6167 (xor:SI (match_operand:SI 1 "register_operand" "%r")
6168 (match_operand:SI 2 "register_operand" "r")))]
6171 [(set_attr "type" "binary")
6172 (set_attr "length" "4")])
6174 (define_expand "negdi2"
6175 [(set (match_operand:DI 0 "register_operand" "")
6176 (neg:DI (match_operand:DI 1 "register_operand" "")))]
6181 [(set (match_operand:DI 0 "register_operand" "=r")
6182 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6184 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
6185 [(set_attr "type" "unary")
6186 (set_attr "length" "8")])
6189 [(set (match_operand:DI 0 "register_operand" "=r")
6190 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6193 [(set_attr "type" "unary")
6194 (set_attr "length" "4")])
6196 (define_expand "negvdi2"
6197 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6198 (neg:DI (match_operand:DI 1 "register_operand" "")))
6199 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6200 (sign_extend:TI (neg:DI (match_dup 1))))
6206 [(set (match_operand:DI 0 "register_operand" "=r")
6207 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6208 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6209 (sign_extend:TI (neg:DI (match_dup 1))))
6212 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
6213 [(set_attr "type" "unary")
6214 (set_attr "length" "8")])
6217 [(set (match_operand:DI 0 "register_operand" "=r")
6218 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6219 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6220 (sign_extend:TI (neg:DI (match_dup 1))))
6223 "sub,tsv %%r0,%1,%0"
6224 [(set_attr "type" "unary")
6225 (set_attr "length" "4")])
6227 (define_insn "negsi2"
6228 [(set (match_operand:SI 0 "register_operand" "=r")
6229 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
6232 [(set_attr "type" "unary")
6233 (set_attr "length" "4")])
6235 (define_insn "negvsi2"
6236 [(set (match_operand:SI 0 "register_operand" "=r")
6237 (neg:SI (match_operand:SI 1 "register_operand" "r")))
6238 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
6239 (sign_extend:DI (neg:SI (match_dup 1))))
6242 "{subo|sub,tsv} %%r0,%1,%0"
6243 [(set_attr "type" "unary")
6244 (set_attr "length" "4")])
6246 (define_expand "one_cmpldi2"
6247 [(set (match_operand:DI 0 "register_operand" "")
6248 (not:DI (match_operand:DI 1 "register_operand" "")))]
6255 [(set (match_operand:DI 0 "register_operand" "=r")
6256 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6258 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
6259 [(set_attr "type" "unary")
6260 (set_attr "length" "8")])
6263 [(set (match_operand:DI 0 "register_operand" "=r")
6264 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6267 [(set_attr "type" "unary")
6268 (set_attr "length" "4")])
6270 (define_insn "one_cmplsi2"
6271 [(set (match_operand:SI 0 "register_operand" "=r")
6272 (not:SI (match_operand:SI 1 "register_operand" "r")))]
6275 [(set_attr "type" "unary")
6276 (set_attr "length" "4")])
6278 ;; Floating point arithmetic instructions.
6280 (define_insn "adddf3"
6281 [(set (match_operand:DF 0 "register_operand" "=f")
6282 (plus:DF (match_operand:DF 1 "register_operand" "f")
6283 (match_operand:DF 2 "register_operand" "f")))]
6284 "! TARGET_SOFT_FLOAT"
6286 [(set_attr "type" "fpalu")
6287 (set_attr "pa_combine_type" "faddsub")
6288 (set_attr "length" "4")])
6290 (define_insn "addsf3"
6291 [(set (match_operand:SF 0 "register_operand" "=f")
6292 (plus:SF (match_operand:SF 1 "register_operand" "f")
6293 (match_operand:SF 2 "register_operand" "f")))]
6294 "! TARGET_SOFT_FLOAT"
6296 [(set_attr "type" "fpalu")
6297 (set_attr "pa_combine_type" "faddsub")
6298 (set_attr "length" "4")])
6300 (define_insn "subdf3"
6301 [(set (match_operand:DF 0 "register_operand" "=f")
6302 (minus:DF (match_operand:DF 1 "register_operand" "f")
6303 (match_operand:DF 2 "register_operand" "f")))]
6304 "! TARGET_SOFT_FLOAT"
6306 [(set_attr "type" "fpalu")
6307 (set_attr "pa_combine_type" "faddsub")
6308 (set_attr "length" "4")])
6310 (define_insn "subsf3"
6311 [(set (match_operand:SF 0 "register_operand" "=f")
6312 (minus:SF (match_operand:SF 1 "register_operand" "f")
6313 (match_operand:SF 2 "register_operand" "f")))]
6314 "! TARGET_SOFT_FLOAT"
6316 [(set_attr "type" "fpalu")
6317 (set_attr "pa_combine_type" "faddsub")
6318 (set_attr "length" "4")])
6320 (define_insn "muldf3"
6321 [(set (match_operand:DF 0 "register_operand" "=f")
6322 (mult:DF (match_operand:DF 1 "register_operand" "f")
6323 (match_operand:DF 2 "register_operand" "f")))]
6324 "! TARGET_SOFT_FLOAT"
6326 [(set_attr "type" "fpmuldbl")
6327 (set_attr "pa_combine_type" "fmpy")
6328 (set_attr "length" "4")])
6330 (define_insn "mulsf3"
6331 [(set (match_operand:SF 0 "register_operand" "=f")
6332 (mult:SF (match_operand:SF 1 "register_operand" "f")
6333 (match_operand:SF 2 "register_operand" "f")))]
6334 "! TARGET_SOFT_FLOAT"
6336 [(set_attr "type" "fpmulsgl")
6337 (set_attr "pa_combine_type" "fmpy")
6338 (set_attr "length" "4")])
6340 (define_insn "divdf3"
6341 [(set (match_operand:DF 0 "register_operand" "=f")
6342 (div:DF (match_operand:DF 1 "register_operand" "f")
6343 (match_operand:DF 2 "register_operand" "f")))]
6344 "! TARGET_SOFT_FLOAT"
6346 [(set_attr "type" "fpdivdbl")
6347 (set_attr "length" "4")])
6349 (define_insn "divsf3"
6350 [(set (match_operand:SF 0 "register_operand" "=f")
6351 (div:SF (match_operand:SF 1 "register_operand" "f")
6352 (match_operand:SF 2 "register_operand" "f")))]
6353 "! TARGET_SOFT_FLOAT"
6355 [(set_attr "type" "fpdivsgl")
6356 (set_attr "length" "4")])
6358 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6359 ;; negation can be done by subtracting from plus zero. However, this
6360 ;; violates the IEEE standard when negating plus and minus zero.
6361 (define_expand "negdf2"
6362 [(parallel [(set (match_operand:DF 0 "register_operand" "")
6363 (neg:DF (match_operand:DF 1 "register_operand" "")))
6364 (use (match_dup 2))])]
6365 "! TARGET_SOFT_FLOAT"
6367 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6368 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6371 operands[2] = force_reg (DFmode,
6372 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
6373 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
6378 (define_insn "negdf2_fast"
6379 [(set (match_operand:DF 0 "register_operand" "=f")
6380 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6381 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6385 return \"fneg,dbl %1,%0\";
6387 return \"fsub,dbl %%fr0,%1,%0\";
6389 [(set_attr "type" "fpalu")
6390 (set_attr "length" "4")])
6392 (define_expand "negsf2"
6393 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6394 (neg:SF (match_operand:SF 1 "register_operand" "")))
6395 (use (match_dup 2))])]
6396 "! TARGET_SOFT_FLOAT"
6398 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6399 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6402 operands[2] = force_reg (SFmode,
6403 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6404 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6409 (define_insn "negsf2_fast"
6410 [(set (match_operand:SF 0 "register_operand" "=f")
6411 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6412 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6416 return \"fneg,sgl %1,%0\";
6418 return \"fsub,sgl %%fr0,%1,%0\";
6420 [(set_attr "type" "fpalu")
6421 (set_attr "length" "4")])
6423 (define_insn "absdf2"
6424 [(set (match_operand:DF 0 "register_operand" "=f")
6425 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6426 "! TARGET_SOFT_FLOAT"
6428 [(set_attr "type" "fpalu")
6429 (set_attr "length" "4")])
6431 (define_insn "abssf2"
6432 [(set (match_operand:SF 0 "register_operand" "=f")
6433 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6434 "! TARGET_SOFT_FLOAT"
6436 [(set_attr "type" "fpalu")
6437 (set_attr "length" "4")])
6439 (define_insn "sqrtdf2"
6440 [(set (match_operand:DF 0 "register_operand" "=f")
6441 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6442 "! TARGET_SOFT_FLOAT"
6444 [(set_attr "type" "fpsqrtdbl")
6445 (set_attr "length" "4")])
6447 (define_insn "sqrtsf2"
6448 [(set (match_operand:SF 0 "register_operand" "=f")
6449 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6450 "! TARGET_SOFT_FLOAT"
6452 [(set_attr "type" "fpsqrtsgl")
6453 (set_attr "length" "4")])
6455 ;; PA 2.0 floating point instructions
6459 [(set (match_operand:DF 0 "register_operand" "=f")
6460 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6461 (match_operand:DF 2 "register_operand" "f"))
6462 (match_operand:DF 3 "register_operand" "f")))]
6463 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6464 "fmpyfadd,dbl %1,%2,%3,%0"
6465 [(set_attr "type" "fpmuldbl")
6466 (set_attr "length" "4")])
6469 [(set (match_operand:DF 0 "register_operand" "=f")
6470 (plus:DF (match_operand:DF 1 "register_operand" "f")
6471 (mult:DF (match_operand:DF 2 "register_operand" "f")
6472 (match_operand:DF 3 "register_operand" "f"))))]
6473 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6474 "fmpyfadd,dbl %2,%3,%1,%0"
6475 [(set_attr "type" "fpmuldbl")
6476 (set_attr "length" "4")])
6479 [(set (match_operand:SF 0 "register_operand" "=f")
6480 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6481 (match_operand:SF 2 "register_operand" "f"))
6482 (match_operand:SF 3 "register_operand" "f")))]
6483 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6484 "fmpyfadd,sgl %1,%2,%3,%0"
6485 [(set_attr "type" "fpmulsgl")
6486 (set_attr "length" "4")])
6489 [(set (match_operand:SF 0 "register_operand" "=f")
6490 (plus:SF (match_operand:SF 1 "register_operand" "f")
6491 (mult:SF (match_operand:SF 2 "register_operand" "f")
6492 (match_operand:SF 3 "register_operand" "f"))))]
6493 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6494 "fmpyfadd,sgl %2,%3,%1,%0"
6495 [(set_attr "type" "fpmulsgl")
6496 (set_attr "length" "4")])
6498 ; fmpynfadd patterns
6500 [(set (match_operand:DF 0 "register_operand" "=f")
6501 (minus:DF (match_operand:DF 1 "register_operand" "f")
6502 (mult:DF (match_operand:DF 2 "register_operand" "f")
6503 (match_operand:DF 3 "register_operand" "f"))))]
6504 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6505 "fmpynfadd,dbl %2,%3,%1,%0"
6506 [(set_attr "type" "fpmuldbl")
6507 (set_attr "length" "4")])
6510 [(set (match_operand:SF 0 "register_operand" "=f")
6511 (minus:SF (match_operand:SF 1 "register_operand" "f")
6512 (mult:SF (match_operand:SF 2 "register_operand" "f")
6513 (match_operand:SF 3 "register_operand" "f"))))]
6514 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6515 "fmpynfadd,sgl %2,%3,%1,%0"
6516 [(set_attr "type" "fpmulsgl")
6517 (set_attr "length" "4")])
6521 [(set (match_operand:DF 0 "register_operand" "=f")
6522 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6523 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6525 [(set_attr "type" "fpalu")
6526 (set_attr "length" "4")])
6529 [(set (match_operand:SF 0 "register_operand" "=f")
6530 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6531 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6533 [(set_attr "type" "fpalu")
6534 (set_attr "length" "4")])
6536 ;; Generating a fused multiply sequence is a win for this case as it will
6537 ;; reduce the latency for the fused case without impacting the plain
6540 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6541 ;; perform two operations with the result of the first feeding the second.
6543 [(set (match_operand:DF 0 "register_operand" "=f")
6544 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6545 (match_operand:DF 2 "register_operand" "f"))
6546 (match_operand:DF 3 "register_operand" "f")))
6547 (set (match_operand:DF 4 "register_operand" "=&f")
6548 (mult:DF (match_dup 1) (match_dup 2)))]
6549 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6550 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6551 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6553 [(set_attr "type" "fpmuldbl")
6554 (set_attr "length" "8")])
6556 ;; We want to split this up during scheduling since we want both insns
6557 ;; to schedule independently.
6559 [(set (match_operand:DF 0 "register_operand" "")
6560 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6561 (match_operand:DF 2 "register_operand" ""))
6562 (match_operand:DF 3 "register_operand" "")))
6563 (set (match_operand:DF 4 "register_operand" "")
6564 (mult:DF (match_dup 1) (match_dup 2)))]
6565 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6566 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6567 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6572 [(set (match_operand:SF 0 "register_operand" "=f")
6573 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6574 (match_operand:SF 2 "register_operand" "f"))
6575 (match_operand:SF 3 "register_operand" "f")))
6576 (set (match_operand:SF 4 "register_operand" "=&f")
6577 (mult:SF (match_dup 1) (match_dup 2)))]
6578 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6579 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6580 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6582 [(set_attr "type" "fpmuldbl")
6583 (set_attr "length" "8")])
6585 ;; We want to split this up during scheduling since we want both insns
6586 ;; to schedule independently.
6588 [(set (match_operand:SF 0 "register_operand" "")
6589 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6590 (match_operand:SF 2 "register_operand" ""))
6591 (match_operand:SF 3 "register_operand" "")))
6592 (set (match_operand:SF 4 "register_operand" "")
6593 (mult:SF (match_dup 1) (match_dup 2)))]
6594 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6595 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6596 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6600 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6603 [(set (match_operand:DF 0 "register_operand" "=f")
6604 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6605 (match_operand:DF 2 "register_operand" "f"))))]
6606 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6607 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6608 [(set_attr "type" "fpmuldbl")
6609 (set_attr "length" "4")])
6612 [(set (match_operand:SF 0 "register_operand" "=f")
6613 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6614 (match_operand:SF 2 "register_operand" "f"))))]
6615 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6616 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6617 [(set_attr "type" "fpmuldbl")
6618 (set_attr "length" "4")])
6621 [(set (match_operand:DF 0 "register_operand" "=f")
6622 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6623 (match_operand:DF 2 "register_operand" "f"))))
6624 (set (match_operand:DF 3 "register_operand" "=&f")
6625 (mult:DF (match_dup 1) (match_dup 2)))]
6626 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6627 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6628 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6630 [(set_attr "type" "fpmuldbl")
6631 (set_attr "length" "8")])
6634 [(set (match_operand:DF 0 "register_operand" "")
6635 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6636 (match_operand:DF 2 "register_operand" ""))))
6637 (set (match_operand:DF 3 "register_operand" "")
6638 (mult:DF (match_dup 1) (match_dup 2)))]
6639 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6640 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6641 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6645 [(set (match_operand:SF 0 "register_operand" "=f")
6646 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6647 (match_operand:SF 2 "register_operand" "f"))))
6648 (set (match_operand:SF 3 "register_operand" "=&f")
6649 (mult:SF (match_dup 1) (match_dup 2)))]
6650 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6651 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6652 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6654 [(set_attr "type" "fpmuldbl")
6655 (set_attr "length" "8")])
6658 [(set (match_operand:SF 0 "register_operand" "")
6659 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6660 (match_operand:SF 2 "register_operand" ""))))
6661 (set (match_operand:SF 3 "register_operand" "")
6662 (mult:SF (match_dup 1) (match_dup 2)))]
6663 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6664 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6665 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6668 ;; Now fused multiplies with the result of the multiply negated.
6670 [(set (match_operand:DF 0 "register_operand" "=f")
6671 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6672 (match_operand:DF 2 "register_operand" "f")))
6673 (match_operand:DF 3 "register_operand" "f")))]
6674 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6675 "fmpynfadd,dbl %1,%2,%3,%0"
6676 [(set_attr "type" "fpmuldbl")
6677 (set_attr "length" "4")])
6680 [(set (match_operand:SF 0 "register_operand" "=f")
6681 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6682 (match_operand:SF 2 "register_operand" "f")))
6683 (match_operand:SF 3 "register_operand" "f")))]
6684 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6685 "fmpynfadd,sgl %1,%2,%3,%0"
6686 [(set_attr "type" "fpmuldbl")
6687 (set_attr "length" "4")])
6690 [(set (match_operand:DF 0 "register_operand" "=f")
6691 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6692 (match_operand:DF 2 "register_operand" "f")))
6693 (match_operand:DF 3 "register_operand" "f")))
6694 (set (match_operand:DF 4 "register_operand" "=&f")
6695 (mult:DF (match_dup 1) (match_dup 2)))]
6696 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6697 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6698 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6700 [(set_attr "type" "fpmuldbl")
6701 (set_attr "length" "8")])
6704 [(set (match_operand:DF 0 "register_operand" "")
6705 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6706 (match_operand:DF 2 "register_operand" "")))
6707 (match_operand:DF 3 "register_operand" "")))
6708 (set (match_operand:DF 4 "register_operand" "")
6709 (mult:DF (match_dup 1) (match_dup 2)))]
6710 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6711 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6712 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6717 [(set (match_operand:SF 0 "register_operand" "=f")
6718 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6719 (match_operand:SF 2 "register_operand" "f")))
6720 (match_operand:SF 3 "register_operand" "f")))
6721 (set (match_operand:SF 4 "register_operand" "=&f")
6722 (mult:SF (match_dup 1) (match_dup 2)))]
6723 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6724 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6725 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6727 [(set_attr "type" "fpmuldbl")
6728 (set_attr "length" "8")])
6731 [(set (match_operand:SF 0 "register_operand" "")
6732 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6733 (match_operand:SF 2 "register_operand" "")))
6734 (match_operand:SF 3 "register_operand" "")))
6735 (set (match_operand:SF 4 "register_operand" "")
6736 (mult:SF (match_dup 1) (match_dup 2)))]
6737 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6738 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6739 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6744 [(set (match_operand:DF 0 "register_operand" "=f")
6745 (minus:DF (match_operand:DF 3 "register_operand" "f")
6746 (mult:DF (match_operand:DF 1 "register_operand" "f")
6747 (match_operand:DF 2 "register_operand" "f"))))
6748 (set (match_operand:DF 4 "register_operand" "=&f")
6749 (mult:DF (match_dup 1) (match_dup 2)))]
6750 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6751 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6752 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6754 [(set_attr "type" "fpmuldbl")
6755 (set_attr "length" "8")])
6758 [(set (match_operand:DF 0 "register_operand" "")
6759 (minus:DF (match_operand:DF 3 "register_operand" "")
6760 (mult:DF (match_operand:DF 1 "register_operand" "")
6761 (match_operand:DF 2 "register_operand" ""))))
6762 (set (match_operand:DF 4 "register_operand" "")
6763 (mult:DF (match_dup 1) (match_dup 2)))]
6764 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6765 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6766 (set (match_dup 0) (minus:DF (match_dup 3)
6767 (mult:DF (match_dup 1) (match_dup 2))))]
6771 [(set (match_operand:SF 0 "register_operand" "=f")
6772 (minus:SF (match_operand:SF 3 "register_operand" "f")
6773 (mult:SF (match_operand:SF 1 "register_operand" "f")
6774 (match_operand:SF 2 "register_operand" "f"))))
6775 (set (match_operand:SF 4 "register_operand" "=&f")
6776 (mult:SF (match_dup 1) (match_dup 2)))]
6777 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6778 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6779 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6781 [(set_attr "type" "fpmuldbl")
6782 (set_attr "length" "8")])
6785 [(set (match_operand:SF 0 "register_operand" "")
6786 (minus:SF (match_operand:SF 3 "register_operand" "")
6787 (mult:SF (match_operand:SF 1 "register_operand" "")
6788 (match_operand:SF 2 "register_operand" ""))))
6789 (set (match_operand:SF 4 "register_operand" "")
6790 (mult:SF (match_dup 1) (match_dup 2)))]
6791 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6792 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6793 (set (match_dup 0) (minus:SF (match_dup 3)
6794 (mult:SF (match_dup 1) (match_dup 2))))]
6798 [(set (match_operand:DF 0 "register_operand" "=f")
6799 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6800 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6801 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6802 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6804 [(set_attr "type" "fpalu")
6805 (set_attr "length" "8")])
6808 [(set (match_operand:DF 0 "register_operand" "")
6809 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6810 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6811 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6812 [(set (match_dup 2) (abs:DF (match_dup 1)))
6813 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6817 [(set (match_operand:SF 0 "register_operand" "=f")
6818 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6819 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6820 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6821 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6823 [(set_attr "type" "fpalu")
6824 (set_attr "length" "8")])
6827 [(set (match_operand:SF 0 "register_operand" "")
6828 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6829 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6830 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6831 [(set (match_dup 2) (abs:SF (match_dup 1)))
6832 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6835 ;;- Shift instructions
6837 ;; Optimized special case of shifting.
6840 [(set (match_operand:SI 0 "register_operand" "=r")
6841 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6845 [(set_attr "type" "load")
6846 (set_attr "length" "4")])
6849 [(set (match_operand:SI 0 "register_operand" "=r")
6850 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6854 [(set_attr "type" "load")
6855 (set_attr "length" "4")])
6858 [(set (match_operand:SI 0 "register_operand" "=r")
6859 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6860 (match_operand:SI 3 "shadd_operand" ""))
6861 (match_operand:SI 1 "register_operand" "r")))]
6863 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6864 [(set_attr "type" "binary")
6865 (set_attr "length" "4")])
6868 [(set (match_operand:DI 0 "register_operand" "=r")
6869 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6870 (match_operand:DI 3 "shadd_operand" ""))
6871 (match_operand:DI 1 "register_operand" "r")))]
6873 "shladd,l %2,%O3,%1,%0"
6874 [(set_attr "type" "binary")
6875 (set_attr "length" "4")])
6877 (define_expand "ashlsi3"
6878 [(set (match_operand:SI 0 "register_operand" "")
6879 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6880 (match_operand:SI 2 "arith32_operand" "")))]
6884 if (GET_CODE (operands[2]) != CONST_INT)
6886 rtx temp = gen_reg_rtx (SImode);
6887 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6888 if (GET_CODE (operands[1]) == CONST_INT)
6889 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6891 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6894 /* Make sure both inputs are not constants,
6895 there are no patterns for that. */
6896 operands[1] = force_reg (SImode, operands[1]);
6900 [(set (match_operand:SI 0 "register_operand" "=r")
6901 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6902 (match_operand:SI 2 "const_int_operand" "n")))]
6904 "{zdep|depw,z} %1,%P2,%L2,%0"
6905 [(set_attr "type" "shift")
6906 (set_attr "length" "4")])
6908 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6909 ; Doing it like this makes slightly better code since reload can
6910 ; replace a register with a known value in range -16..15 with a
6911 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6912 ; but since we have no more CONST_OK... characters, that is not
6914 (define_insn "zvdep32"
6915 [(set (match_operand:SI 0 "register_operand" "=r,r")
6916 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6917 (minus:SI (const_int 31)
6918 (match_operand:SI 2 "register_operand" "q,q"))))]
6921 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6922 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6923 [(set_attr "type" "shift,shift")
6924 (set_attr "length" "4,4")])
6926 (define_insn "zvdep_imm32"
6927 [(set (match_operand:SI 0 "register_operand" "=r")
6928 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6929 (minus:SI (const_int 31)
6930 (match_operand:SI 2 "register_operand" "q"))))]
6934 int x = INTVAL (operands[1]);
6935 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6936 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6937 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6939 [(set_attr "type" "shift")
6940 (set_attr "length" "4")])
6942 (define_insn "vdepi_ior"
6943 [(set (match_operand:SI 0 "register_operand" "=r")
6944 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6945 (minus:SI (const_int 31)
6946 (match_operand:SI 2 "register_operand" "q")))
6947 (match_operand:SI 3 "register_operand" "0")))]
6948 ; accept ...0001...1, can this be generalized?
6949 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6952 int x = INTVAL (operands[1]);
6953 operands[2] = GEN_INT (exact_log2 (x + 1));
6954 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6956 [(set_attr "type" "shift")
6957 (set_attr "length" "4")])
6959 (define_insn "vdepi_and"
6960 [(set (match_operand:SI 0 "register_operand" "=r")
6961 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6962 (minus:SI (const_int 31)
6963 (match_operand:SI 2 "register_operand" "q")))
6964 (match_operand:SI 3 "register_operand" "0")))]
6965 ; this can be generalized...!
6966 "INTVAL (operands[1]) == -2"
6969 int x = INTVAL (operands[1]);
6970 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6971 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6973 [(set_attr "type" "shift")
6974 (set_attr "length" "4")])
6976 (define_expand "ashldi3"
6977 [(set (match_operand:DI 0 "register_operand" "")
6978 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6979 (match_operand:DI 2 "arith32_operand" "")))]
6983 if (GET_CODE (operands[2]) != CONST_INT)
6985 rtx temp = gen_reg_rtx (DImode);
6986 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6987 if (GET_CODE (operands[1]) == CONST_INT)
6988 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6990 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6993 /* Make sure both inputs are not constants,
6994 there are no patterns for that. */
6995 operands[1] = force_reg (DImode, operands[1]);
6999 [(set (match_operand:DI 0 "register_operand" "=r")
7000 (ashift:DI (match_operand:DI 1 "register_operand" "r")
7001 (match_operand:DI 2 "const_int_operand" "n")))]
7003 "depd,z %1,%p2,%Q2,%0"
7004 [(set_attr "type" "shift")
7005 (set_attr "length" "4")])
7007 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
7008 ; Doing it like this makes slightly better code since reload can
7009 ; replace a register with a known value in range -16..15 with a
7010 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
7011 ; but since we have no more CONST_OK... characters, that is not
7013 (define_insn "zvdep64"
7014 [(set (match_operand:DI 0 "register_operand" "=r,r")
7015 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
7016 (minus:DI (const_int 63)
7017 (match_operand:DI 2 "register_operand" "q,q"))))]
7020 depd,z %1,%%sar,64,%0
7021 depdi,z %1,%%sar,64,%0"
7022 [(set_attr "type" "shift,shift")
7023 (set_attr "length" "4,4")])
7025 (define_insn "zvdep_imm64"
7026 [(set (match_operand:DI 0 "register_operand" "=r")
7027 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
7028 (minus:DI (const_int 63)
7029 (match_operand:DI 2 "register_operand" "q"))))]
7033 int x = INTVAL (operands[1]);
7034 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
7035 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
7036 return \"depdi,z %1,%%sar,%2,%0\";
7038 [(set_attr "type" "shift")
7039 (set_attr "length" "4")])
7042 [(set (match_operand:DI 0 "register_operand" "=r")
7043 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
7044 (minus:DI (const_int 63)
7045 (match_operand:DI 2 "register_operand" "q")))
7046 (match_operand:DI 3 "register_operand" "0")))]
7047 ; accept ...0001...1, can this be generalized?
7048 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
7051 int x = INTVAL (operands[1]);
7052 operands[2] = GEN_INT (exact_log2 (x + 1));
7053 return \"depdi -1,%%sar,%2,%0\";
7055 [(set_attr "type" "shift")
7056 (set_attr "length" "4")])
7059 [(set (match_operand:DI 0 "register_operand" "=r")
7060 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
7061 (minus:DI (const_int 63)
7062 (match_operand:DI 2 "register_operand" "q")))
7063 (match_operand:DI 3 "register_operand" "0")))]
7064 ; this can be generalized...!
7065 "TARGET_64BIT && INTVAL (operands[1]) == -2"
7068 int x = INTVAL (operands[1]);
7069 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7070 return \"depdi 0,%%sar,%2,%0\";
7072 [(set_attr "type" "shift")
7073 (set_attr "length" "4")])
7075 (define_expand "ashrsi3"
7076 [(set (match_operand:SI 0 "register_operand" "")
7077 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
7078 (match_operand:SI 2 "arith32_operand" "")))]
7082 if (GET_CODE (operands[2]) != CONST_INT)
7084 rtx temp = gen_reg_rtx (SImode);
7085 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
7086 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
7092 [(set (match_operand:SI 0 "register_operand" "=r")
7093 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7094 (match_operand:SI 2 "const_int_operand" "n")))]
7096 "{extrs|extrw,s} %1,%P2,%L2,%0"
7097 [(set_attr "type" "shift")
7098 (set_attr "length" "4")])
7100 (define_insn "vextrs32"
7101 [(set (match_operand:SI 0 "register_operand" "=r")
7102 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7103 (minus:SI (const_int 31)
7104 (match_operand:SI 2 "register_operand" "q"))))]
7106 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
7107 [(set_attr "type" "shift")
7108 (set_attr "length" "4")])
7110 (define_expand "ashrdi3"
7111 [(set (match_operand:DI 0 "register_operand" "")
7112 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7113 (match_operand:DI 2 "arith32_operand" "")))]
7117 if (GET_CODE (operands[2]) != CONST_INT)
7119 rtx temp = gen_reg_rtx (DImode);
7120 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7121 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
7127 [(set (match_operand:DI 0 "register_operand" "=r")
7128 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7129 (match_operand:DI 2 "const_int_operand" "n")))]
7131 "extrd,s %1,%p2,%Q2,%0"
7132 [(set_attr "type" "shift")
7133 (set_attr "length" "4")])
7135 (define_insn "vextrs64"
7136 [(set (match_operand:DI 0 "register_operand" "=r")
7137 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7138 (minus:DI (const_int 63)
7139 (match_operand:DI 2 "register_operand" "q"))))]
7141 "extrd,s %1,%%sar,64,%0"
7142 [(set_attr "type" "shift")
7143 (set_attr "length" "4")])
7145 (define_insn "lshrsi3"
7146 [(set (match_operand:SI 0 "register_operand" "=r,r")
7147 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
7148 (match_operand:SI 2 "arith32_operand" "q,n")))]
7151 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
7152 {extru|extrw,u} %1,%P2,%L2,%0"
7153 [(set_attr "type" "shift")
7154 (set_attr "length" "4")])
7156 (define_insn "lshrdi3"
7157 [(set (match_operand:DI 0 "register_operand" "=r,r")
7158 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
7159 (match_operand:DI 2 "arith32_operand" "q,n")))]
7162 shrpd %%r0,%1,%%sar,%0
7163 extrd,u %1,%p2,%Q2,%0"
7164 [(set_attr "type" "shift")
7165 (set_attr "length" "4")])
7167 (define_insn "rotrsi3"
7168 [(set (match_operand:SI 0 "register_operand" "=r,r")
7169 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
7170 (match_operand:SI 2 "arith32_operand" "q,n")))]
7174 if (GET_CODE (operands[2]) == CONST_INT)
7176 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
7177 return \"{shd|shrpw} %1,%1,%2,%0\";
7180 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
7182 [(set_attr "type" "shift")
7183 (set_attr "length" "4")])
7185 (define_expand "rotlsi3"
7186 [(set (match_operand:SI 0 "register_operand" "")
7187 (rotate:SI (match_operand:SI 1 "register_operand" "")
7188 (match_operand:SI 2 "arith32_operand" "")))]
7192 if (GET_CODE (operands[2]) != CONST_INT)
7194 rtx temp = gen_reg_rtx (SImode);
7195 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
7196 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
7199 /* Else expand normally. */
7203 [(set (match_operand:SI 0 "register_operand" "=r")
7204 (rotate:SI (match_operand:SI 1 "register_operand" "r")
7205 (match_operand:SI 2 "const_int_operand" "n")))]
7209 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
7210 return \"{shd|shrpw} %1,%1,%2,%0\";
7212 [(set_attr "type" "shift")
7213 (set_attr "length" "4")])
7216 [(set (match_operand:SI 0 "register_operand" "=r")
7217 (match_operator:SI 5 "plus_xor_ior_operator"
7218 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
7219 (match_operand:SI 3 "const_int_operand" "n"))
7220 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7221 (match_operand:SI 4 "const_int_operand" "n"))]))]
7222 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7223 "{shd|shrpw} %1,%2,%4,%0"
7224 [(set_attr "type" "shift")
7225 (set_attr "length" "4")])
7228 [(set (match_operand:SI 0 "register_operand" "=r")
7229 (match_operator:SI 5 "plus_xor_ior_operator"
7230 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7231 (match_operand:SI 4 "const_int_operand" "n"))
7232 (ashift:SI (match_operand:SI 1 "register_operand" "r")
7233 (match_operand:SI 3 "const_int_operand" "n"))]))]
7234 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7235 "{shd|shrpw} %1,%2,%4,%0"
7236 [(set_attr "type" "shift")
7237 (set_attr "length" "4")])
7240 [(set (match_operand:SI 0 "register_operand" "=r")
7241 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
7242 (match_operand:SI 2 "const_int_operand" ""))
7243 (match_operand:SI 3 "const_int_operand" "")))]
7244 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
7247 int cnt = INTVAL (operands[2]) & 31;
7248 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
7249 operands[2] = GEN_INT (31 - cnt);
7250 return \"{zdep|depw,z} %1,%2,%3,%0\";
7252 [(set_attr "type" "shift")
7253 (set_attr "length" "4")])
7255 ;; Unconditional and other jump instructions.
7257 ;; This is used for most returns.
7258 (define_insn "return_internal"
7265 return \"bve%* (%%r2)\";
7266 return \"bv%* %%r0(%%r2)\";
7268 [(set_attr "type" "branch")
7269 (set_attr "length" "4")])
7271 ;; This is used for eh returns which bypass the return stub.
7272 (define_insn "return_external_pic"
7274 (clobber (reg:SI 1))
7276 "!TARGET_NO_SPACE_REGS
7278 && flag_pic && crtl->calls_eh_return"
7279 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
7280 [(set_attr "type" "branch")
7281 (set_attr "length" "12")])
7283 (define_expand "prologue"
7286 "hppa_expand_prologue ();DONE;")
7288 (define_expand "sibcall_epilogue"
7293 hppa_expand_epilogue ();
7297 (define_expand "epilogue"
7304 /* Try to use the trivial return first. Else use the full epilogue. */
7305 if (reload_completed
7306 && !frame_pointer_needed
7307 && !df_regs_ever_live_p (2)
7308 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1))
7309 x = gen_return_internal ();
7312 hppa_expand_epilogue ();
7314 /* EH returns bypass the normal return stub. Thus, we must do an
7315 interspace branch to return from functions that call eh_return.
7316 This is only a problem for returns from shared code on ports
7317 using space registers. */
7318 if (!TARGET_NO_SPACE_REGS
7320 && flag_pic && crtl->calls_eh_return)
7321 x = gen_return_external_pic ();
7323 x = gen_return_internal ();
7329 ; Used by hppa_profile_hook to load the starting address of the current
7330 ; function; operand 1 contains the address of the label in operand 3
7331 (define_insn "load_offset_label_address"
7332 [(set (match_operand:SI 0 "register_operand" "=r")
7333 (plus:SI (match_operand:SI 1 "register_operand" "r")
7334 (minus:SI (match_operand:SI 2 "" "")
7335 (label_ref:SI (match_operand 3 "" "")))))]
7338 [(set_attr "type" "multi")
7339 (set_attr "length" "4")])
7341 ; Output a code label and load its address.
7342 (define_insn "lcla1"
7343 [(set (match_operand:SI 0 "register_operand" "=r")
7344 (label_ref:SI (match_operand 1 "" "")))
7349 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
7350 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7351 CODE_LABEL_NUMBER (operands[1]));
7354 [(set_attr "type" "multi")
7355 (set_attr "length" "8")])
7357 (define_insn "lcla2"
7358 [(set (match_operand:SI 0 "register_operand" "=r")
7359 (label_ref:SI (match_operand 1 "" "")))
7364 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7365 CODE_LABEL_NUMBER (operands[1]));
7368 [(set_attr "type" "move")
7369 (set_attr "length" "4")])
7371 (define_insn "blockage"
7372 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
7375 [(set_attr "length" "0")])
7378 [(set (pc) (label_ref (match_operand 0 "" "")))]
7382 /* An unconditional branch which can reach its target. */
7383 if (get_attr_length (insn) < 16)
7386 return output_lbranch (operands[0], insn, 1);
7388 [(set_attr "type" "uncond_branch")
7389 (set_attr "pa_combine_type" "uncond_branch")
7390 (set (attr "length")
7391 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7392 (if_then_else (lt (abs (minus (match_dup 0)
7393 (plus (pc) (const_int 8))))
7394 (const_int MAX_12BIT_OFFSET))
7397 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7398 (const_int MAX_17BIT_OFFSET))
7400 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7402 (eq (symbol_ref "flag_pic") (const_int 0))
7406 ;;; Hope this is only within a function...
7407 (define_insn "indirect_jump"
7408 [(set (pc) (match_operand 0 "register_operand" "r"))]
7409 "GET_MODE (operands[0]) == word_mode"
7411 [(set_attr "type" "branch")
7412 (set_attr "length" "4")])
7414 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7415 ;;; SOM target doesn't allow branching to a label inside a function.
7416 ;;; We also don't correctly compute branch distances for labels
7417 ;;; outside the current function. Thus, we use an indirect jump can't
7418 ;;; be optimized to a direct jump for all targets. We assume that
7419 ;;; the branch target is in the same space (i.e., nested function
7420 ;;; jumping to a label in an outer function in the same translation
7422 (define_expand "nonlocal_goto"
7423 [(use (match_operand 0 "general_operand" ""))
7424 (use (match_operand 1 "general_operand" ""))
7425 (use (match_operand 2 "general_operand" ""))
7426 (use (match_operand 3 "general_operand" ""))]
7429 rtx lab = operands[1];
7430 rtx stack = operands[2];
7431 rtx fp = operands[3];
7433 lab = copy_to_reg (lab);
7435 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7436 gen_rtx_MEM (BLKmode,
7437 gen_rtx_SCRATCH (VOIDmode))));
7438 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7439 gen_rtx_MEM (BLKmode,
7440 hard_frame_pointer_rtx)));
7442 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7443 instead of the hard_frame_pointer_rtx in the save area. As a
7444 result, an extra instruction is needed to adjust for the offset
7445 of the virtual stack variables and the frame pointer. */
7446 if (GET_CODE (fp) != REG)
7447 fp = force_reg (Pmode, fp);
7448 emit_move_insn (virtual_stack_vars_rtx, fp);
7450 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7452 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7453 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7455 /* Nonlocal goto jumps are only used between functions in the same
7456 translation unit. Thus, we can avoid the extra overhead of an
7458 emit_jump_insn (gen_indirect_goto (lab));
7463 (define_insn "indirect_goto"
7464 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7465 "GET_MODE (operands[0]) == word_mode"
7467 [(set_attr "type" "branch")
7468 (set_attr "length" "4")])
7470 ;;; This jump is used in branch tables where the insn length is fixed.
7471 ;;; The length of this insn is adjusted if the delay slot is not filled.
7472 (define_insn "short_jump"
7473 [(set (pc) (label_ref (match_operand 0 "" "")))
7477 [(set_attr "type" "btable_branch")
7478 (set_attr "length" "4")])
7480 ;; Subroutines of "casesi".
7481 ;; operand 0 is index
7482 ;; operand 1 is the minimum bound
7483 ;; operand 2 is the maximum bound - minimum bound + 1
7484 ;; operand 3 is CODE_LABEL for the table;
7485 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7487 (define_expand "casesi"
7488 [(match_operand:SI 0 "general_operand" "")
7489 (match_operand:SI 1 "const_int_operand" "")
7490 (match_operand:SI 2 "const_int_operand" "")
7491 (match_operand 3 "" "")
7492 (match_operand 4 "" "")]
7496 if (GET_CODE (operands[0]) != REG)
7497 operands[0] = force_reg (SImode, operands[0]);
7499 if (operands[1] != const0_rtx)
7501 rtx index = gen_reg_rtx (SImode);
7503 operands[1] = GEN_INT (-INTVAL (operands[1]));
7504 if (!INT_14_BITS (operands[1]))
7505 operands[1] = force_reg (SImode, operands[1]);
7506 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7507 operands[0] = index;
7510 /* In 64bit mode we must make sure to wipe the upper bits of the register
7511 just in case the addition overflowed or we had random bits in the
7512 high part of the register. */
7515 rtx index = gen_reg_rtx (DImode);
7517 emit_insn (gen_extendsidi2 (index, operands[0]));
7518 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
7521 if (!INT_5_BITS (operands[2]))
7522 operands[2] = force_reg (SImode, operands[2]);
7524 /* This branch prevents us finding an insn for the delay slot of the
7525 following vectored branch. It might be possible to use the delay
7526 slot if an index value of -1 was used to transfer to the out-of-range
7527 label. In order to do this, we would have to output the -1 vector
7528 element after the delay insn. The casesi output code would have to
7529 check if the casesi insn is in a delay branch sequence and output
7530 the delay insn if one is found. If this was done, then it might
7531 then be worthwhile to split the casesi patterns to improve scheduling.
7532 However, it's not clear that all this extra complexity is worth
7534 emit_insn (gen_cmpsi (operands[0], operands[2]));
7535 emit_jump_insn (gen_bgtu (operands[4]));
7537 if (TARGET_BIG_SWITCH)
7540 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7542 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7544 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7547 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7551 ;;; The rtl for this pattern doesn't accurately describe what the insn
7552 ;;; actually does, particularly when case-vector elements are exploded
7553 ;;; in pa_reorg. However, the initial SET in these patterns must show
7554 ;;; the connection of the insn to the following jump table.
7555 (define_insn "casesi0"
7556 [(set (pc) (mem:SI (plus:SI
7557 (mult:SI (match_operand:SI 0 "register_operand" "r")
7559 (label_ref (match_operand 1 "" "")))))]
7561 "blr,n %0,%%r0\;nop"
7562 [(set_attr "type" "multi")
7563 (set_attr "length" "8")])
7565 ;;; 32-bit code, absolute branch table.
7566 (define_insn "casesi32"
7567 [(set (pc) (mem:SI (plus:SI
7568 (mult:SI (match_operand:SI 0 "register_operand" "r")
7570 (label_ref (match_operand 1 "" "")))))
7571 (clobber (match_scratch:SI 2 "=&r"))]
7573 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7574 [(set_attr "type" "multi")
7575 (set_attr "length" "16")])
7577 ;;; 32-bit code, relative branch table.
7578 (define_insn "casesi32p"
7579 [(set (pc) (mem:SI (plus:SI
7580 (mult:SI (match_operand:SI 0 "register_operand" "r")
7582 (label_ref (match_operand 1 "" "")))))
7583 (clobber (match_scratch:SI 2 "=&r"))
7584 (clobber (match_scratch:SI 3 "=&r"))]
7586 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7587 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7588 [(set_attr "type" "multi")
7589 (set (attr "length")
7590 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7594 ;;; 64-bit code, 32-bit relative branch table.
7595 (define_insn "casesi64p"
7596 [(set (pc) (mem:DI (plus:DI
7597 (mult:DI (sign_extend:DI
7598 (match_operand:SI 0 "register_operand" "r"))
7600 (label_ref (match_operand 1 "" "")))))
7601 (clobber (match_scratch:DI 2 "=&r"))
7602 (clobber (match_scratch:DI 3 "=&r"))]
7604 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7605 add,l %2,%3,%3\;bv,n %%r0(%3)"
7606 [(set_attr "type" "multi")
7607 (set_attr "length" "24")])
7611 ;;- jump to subroutine
7613 (define_expand "call"
7614 [(parallel [(call (match_operand:SI 0 "" "")
7615 (match_operand 1 "" ""))
7616 (clobber (reg:SI 2))])]
7621 rtx nb = operands[1];
7623 if (TARGET_PORTABLE_RUNTIME)
7624 op = force_reg (SImode, XEXP (operands[0], 0));
7626 op = XEXP (operands[0], 0);
7630 if (!virtuals_instantiated)
7631 emit_move_insn (arg_pointer_rtx,
7632 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7636 /* The loop pass can generate new libcalls after the virtual
7637 registers are instantiated when fpregs are disabled because
7638 the only method that we have for doing DImode multiplication
7639 is with a libcall. This could be trouble if we haven't
7640 allocated enough space for the outgoing arguments. */
7641 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7643 emit_move_insn (arg_pointer_rtx,
7644 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7645 GEN_INT (STACK_POINTER_OFFSET + 64)));
7649 /* Use two different patterns for calls to explicitly named functions
7650 and calls through function pointers. This is necessary as these two
7651 types of calls use different calling conventions, and CSE might try
7652 to change the named call into an indirect call in some cases (using
7653 two patterns keeps CSE from performing this optimization).
7655 We now use even more call patterns as there was a subtle bug in
7656 attempting to restore the pic register after a call using a simple
7657 move insn. During reload, a instruction involving a pseudo register
7658 with no explicit dependence on the PIC register can be converted
7659 to an equivalent load from memory using the PIC register. If we
7660 emit a simple move to restore the PIC register in the initial rtl
7661 generation, then it can potentially be repositioned during scheduling.
7662 and an instruction that eventually uses the PIC register may end up
7663 between the call and the PIC register restore.
7665 This only worked because there is a post call group of instructions
7666 that are scheduled with the call. These instructions are included
7667 in the same basic block as the call. However, calls can throw in
7668 C++ code and a basic block has to terminate at the call if the call
7669 can throw. This results in the PIC register restore being scheduled
7670 independently from the call. So, we now hide the save and restore
7671 of the PIC register in the call pattern until after reload. Then,
7672 we split the moves out. A small side benefit is that we now don't
7673 need to have a use of the PIC register in the return pattern and
7674 the final save/restore operation is not needed.
7676 I elected to just clobber %r4 in the PIC patterns and use it instead
7677 of trying to force hppa_pic_save_rtx () to a callee saved register.
7678 This might have required a new register class and constraint. It
7679 was also simpler to just handle the restore from a register than a
7683 if (GET_CODE (op) == SYMBOL_REF)
7684 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7687 op = force_reg (word_mode, op);
7688 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7693 if (GET_CODE (op) == SYMBOL_REF)
7696 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7698 call_insn = emit_call_insn (gen_call_symref (op, nb));
7702 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7704 emit_move_insn (tmpreg, force_reg (word_mode, op));
7706 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7708 call_insn = emit_call_insn (gen_call_reg (nb));
7715 ;; We use function calls to set the attribute length of calls and millicode
7716 ;; calls. This is necessary because of the large variety of call sequences.
7717 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7718 ;; we need the same calculation in several places, maintenance becomes a
7721 ;; However, this has a subtle impact on branch shortening. When the
7722 ;; expression used to set the length attribute of an instruction depends
7723 ;; on a relative address (e.g., pc or a branch address), genattrtab
7724 ;; notes that the insn's length is variable, and attempts to determine a
7725 ;; worst-case default length and code to compute an insn's current length.
7727 ;; The use of a function call hides the variable dependence of our calls
7728 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7729 ;; as variable and it only generates code for the default case using our
7730 ;; function call. Because of this, calls and millicode calls have a fixed
7731 ;; length in the branch shortening pass, and some branches will use a longer
7732 ;; code sequence than necessary. However, the length of any given call
7733 ;; will still reflect its final code location and it may be shorter than
7734 ;; the initial length estimate.
7736 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7737 ;; in the set. However, when genattrtab hits a function call in its attempt
7738 ;; to compute the default length, it marks the result as unknown and sets
7739 ;; the default result to MAX_INT ;-( One possible fix that would allow
7740 ;; calls to participate in branch shortening would be to make the call to
7741 ;; insn_default_length a target option. Then, we could massage unknown
7742 ;; results. Another fix might be to change genattrtab so that it just does
7743 ;; the call in the variable case as it already does for the fixed case.
7745 (define_insn "call_symref"
7746 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7747 (match_operand 1 "" "i"))
7748 (clobber (reg:SI 1))
7749 (clobber (reg:SI 2))
7750 (use (const_int 0))]
7751 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7754 output_arg_descriptor (insn);
7755 return output_call (insn, operands[0], 0);
7757 [(set_attr "type" "call")
7758 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7760 (define_insn "call_symref_pic"
7761 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7762 (match_operand 1 "" "i"))
7763 (clobber (reg:SI 1))
7764 (clobber (reg:SI 2))
7765 (clobber (reg:SI 4))
7767 (use (const_int 0))]
7768 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7771 output_arg_descriptor (insn);
7772 return output_call (insn, operands[0], 0);
7774 [(set_attr "type" "call")
7775 (set (attr "length")
7776 (plus (symbol_ref "attr_length_call (insn, 0)")
7777 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7779 ;; Split out the PIC register save and restore after reload. This is
7780 ;; done only if the function returns. As the split is done after reload,
7781 ;; there are some situations in which we unnecessarily save and restore
7782 ;; %r4. This happens when there is a single call and the PIC register
7783 ;; is "dead" after the call. This isn't easy to fix as the usage of
7784 ;; the PIC register isn't completely determined until the reload pass.
7786 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7787 (match_operand 1 "" ""))
7788 (clobber (reg:SI 1))
7789 (clobber (reg:SI 2))
7790 (clobber (reg:SI 4))
7792 (use (const_int 0))])]
7793 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7795 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7796 [(set (reg:SI 4) (reg:SI 19))
7797 (parallel [(call (mem:SI (match_dup 0))
7799 (clobber (reg:SI 1))
7800 (clobber (reg:SI 2))
7802 (use (const_int 0))])
7803 (set (reg:SI 19) (reg:SI 4))]
7806 ;; Remove the clobber of register 4 when optimizing. This has to be
7807 ;; done with a peephole optimization rather than a split because the
7808 ;; split sequence for a call must be longer than one instruction.
7810 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7811 (match_operand 1 "" ""))
7812 (clobber (reg:SI 1))
7813 (clobber (reg:SI 2))
7814 (clobber (reg:SI 4))
7816 (use (const_int 0))])]
7817 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7818 [(parallel [(call (mem:SI (match_dup 0))
7820 (clobber (reg:SI 1))
7821 (clobber (reg:SI 2))
7823 (use (const_int 0))])]
7826 (define_insn "*call_symref_pic_post_reload"
7827 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7828 (match_operand 1 "" "i"))
7829 (clobber (reg:SI 1))
7830 (clobber (reg:SI 2))
7832 (use (const_int 0))]
7833 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7836 output_arg_descriptor (insn);
7837 return output_call (insn, operands[0], 0);
7839 [(set_attr "type" "call")
7840 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7842 ;; This pattern is split if it is necessary to save and restore the
7844 (define_insn "call_symref_64bit"
7845 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7846 (match_operand 1 "" "i"))
7847 (clobber (reg:DI 1))
7848 (clobber (reg:DI 2))
7849 (clobber (reg:DI 4))
7852 (use (const_int 0))]
7856 output_arg_descriptor (insn);
7857 return output_call (insn, operands[0], 0);
7859 [(set_attr "type" "call")
7860 (set (attr "length")
7861 (plus (symbol_ref "attr_length_call (insn, 0)")
7862 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7864 ;; Split out the PIC register save and restore after reload. This is
7865 ;; done only if the function returns. As the split is done after reload,
7866 ;; there are some situations in which we unnecessarily save and restore
7867 ;; %r4. This happens when there is a single call and the PIC register
7868 ;; is "dead" after the call. This isn't easy to fix as the usage of
7869 ;; the PIC register isn't completely determined until the reload pass.
7871 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7872 (match_operand 1 "" ""))
7873 (clobber (reg:DI 1))
7874 (clobber (reg:DI 2))
7875 (clobber (reg:DI 4))
7878 (use (const_int 0))])]
7881 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7882 [(set (reg:DI 4) (reg:DI 27))
7883 (parallel [(call (mem:SI (match_dup 0))
7885 (clobber (reg:DI 1))
7886 (clobber (reg:DI 2))
7889 (use (const_int 0))])
7890 (set (reg:DI 27) (reg:DI 4))]
7893 ;; Remove the clobber of register 4 when optimizing. This has to be
7894 ;; done with a peephole optimization rather than a split because the
7895 ;; split sequence for a call must be longer than one instruction.
7897 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7898 (match_operand 1 "" ""))
7899 (clobber (reg:DI 1))
7900 (clobber (reg:DI 2))
7901 (clobber (reg:DI 4))
7904 (use (const_int 0))])]
7905 "TARGET_64BIT && reload_completed"
7906 [(parallel [(call (mem:SI (match_dup 0))
7908 (clobber (reg:DI 1))
7909 (clobber (reg:DI 2))
7912 (use (const_int 0))])]
7915 (define_insn "*call_symref_64bit_post_reload"
7916 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7917 (match_operand 1 "" "i"))
7918 (clobber (reg:DI 1))
7919 (clobber (reg:DI 2))
7922 (use (const_int 0))]
7926 output_arg_descriptor (insn);
7927 return output_call (insn, operands[0], 0);
7929 [(set_attr "type" "call")
7930 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7932 (define_insn "call_reg"
7933 [(call (mem:SI (reg:SI 22))
7934 (match_operand 0 "" "i"))
7935 (clobber (reg:SI 1))
7936 (clobber (reg:SI 2))
7937 (use (const_int 1))]
7941 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7943 [(set_attr "type" "dyncall")
7944 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7946 ;; This pattern is split if it is necessary to save and restore the
7948 (define_insn "call_reg_pic"
7949 [(call (mem:SI (reg:SI 22))
7950 (match_operand 0 "" "i"))
7951 (clobber (reg:SI 1))
7952 (clobber (reg:SI 2))
7953 (clobber (reg:SI 4))
7955 (use (const_int 1))]
7959 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7961 [(set_attr "type" "dyncall")
7962 (set (attr "length")
7963 (plus (symbol_ref "attr_length_indirect_call (insn)")
7964 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7966 ;; Split out the PIC register save and restore after reload. This is
7967 ;; done only if the function returns. As the split is done after reload,
7968 ;; there are some situations in which we unnecessarily save and restore
7969 ;; %r4. This happens when there is a single call and the PIC register
7970 ;; is "dead" after the call. This isn't easy to fix as the usage of
7971 ;; the PIC register isn't completely determined until the reload pass.
7973 [(parallel [(call (mem:SI (reg:SI 22))
7974 (match_operand 0 "" ""))
7975 (clobber (reg:SI 1))
7976 (clobber (reg:SI 2))
7977 (clobber (reg:SI 4))
7979 (use (const_int 1))])]
7982 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7983 [(set (reg:SI 4) (reg:SI 19))
7984 (parallel [(call (mem:SI (reg:SI 22))
7986 (clobber (reg:SI 1))
7987 (clobber (reg:SI 2))
7989 (use (const_int 1))])
7990 (set (reg:SI 19) (reg:SI 4))]
7993 ;; Remove the clobber of register 4 when optimizing. This has to be
7994 ;; done with a peephole optimization rather than a split because the
7995 ;; split sequence for a call must be longer than one instruction.
7997 [(parallel [(call (mem:SI (reg:SI 22))
7998 (match_operand 0 "" ""))
7999 (clobber (reg:SI 1))
8000 (clobber (reg:SI 2))
8001 (clobber (reg:SI 4))
8003 (use (const_int 1))])]
8004 "!TARGET_64BIT && reload_completed"
8005 [(parallel [(call (mem:SI (reg:SI 22))
8007 (clobber (reg:SI 1))
8008 (clobber (reg:SI 2))
8010 (use (const_int 1))])]
8013 (define_insn "*call_reg_pic_post_reload"
8014 [(call (mem:SI (reg:SI 22))
8015 (match_operand 0 "" "i"))
8016 (clobber (reg:SI 1))
8017 (clobber (reg:SI 2))
8019 (use (const_int 1))]
8023 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8025 [(set_attr "type" "dyncall")
8026 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8028 ;; This pattern is split if it is necessary to save and restore the
8030 (define_insn "call_reg_64bit"
8031 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8032 (match_operand 1 "" "i"))
8033 (clobber (reg:DI 2))
8034 (clobber (reg:DI 4))
8037 (use (const_int 1))]
8041 return output_indirect_call (insn, operands[0]);
8043 [(set_attr "type" "dyncall")
8044 (set (attr "length")
8045 (plus (symbol_ref "attr_length_indirect_call (insn)")
8046 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8048 ;; Split out the PIC register save and restore after reload. This is
8049 ;; done only if the function returns. As the split is done after reload,
8050 ;; there are some situations in which we unnecessarily save and restore
8051 ;; %r4. This happens when there is a single call and the PIC register
8052 ;; is "dead" after the call. This isn't easy to fix as the usage of
8053 ;; the PIC register isn't completely determined until the reload pass.
8055 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8056 (match_operand 1 "" ""))
8057 (clobber (reg:DI 2))
8058 (clobber (reg:DI 4))
8061 (use (const_int 1))])]
8064 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8065 [(set (reg:DI 4) (reg:DI 27))
8066 (parallel [(call (mem:SI (match_dup 0))
8068 (clobber (reg:DI 2))
8071 (use (const_int 1))])
8072 (set (reg:DI 27) (reg:DI 4))]
8075 ;; Remove the clobber of register 4 when optimizing. This has to be
8076 ;; done with a peephole optimization rather than a split because the
8077 ;; split sequence for a call must be longer than one instruction.
8079 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8080 (match_operand 1 "" ""))
8081 (clobber (reg:DI 2))
8082 (clobber (reg:DI 4))
8085 (use (const_int 1))])]
8086 "TARGET_64BIT && reload_completed"
8087 [(parallel [(call (mem:SI (match_dup 0))
8089 (clobber (reg:DI 2))
8092 (use (const_int 1))])]
8095 (define_insn "*call_reg_64bit_post_reload"
8096 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8097 (match_operand 1 "" "i"))
8098 (clobber (reg:DI 2))
8101 (use (const_int 1))]
8105 return output_indirect_call (insn, operands[0]);
8107 [(set_attr "type" "dyncall")
8108 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8110 (define_expand "call_value"
8111 [(parallel [(set (match_operand 0 "" "")
8112 (call (match_operand:SI 1 "" "")
8113 (match_operand 2 "" "")))
8114 (clobber (reg:SI 2))])]
8119 rtx dst = operands[0];
8120 rtx nb = operands[2];
8122 if (TARGET_PORTABLE_RUNTIME)
8123 op = force_reg (SImode, XEXP (operands[1], 0));
8125 op = XEXP (operands[1], 0);
8129 if (!virtuals_instantiated)
8130 emit_move_insn (arg_pointer_rtx,
8131 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8135 /* The loop pass can generate new libcalls after the virtual
8136 registers are instantiated when fpregs are disabled because
8137 the only method that we have for doing DImode multiplication
8138 is with a libcall. This could be trouble if we haven't
8139 allocated enough space for the outgoing arguments. */
8140 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8142 emit_move_insn (arg_pointer_rtx,
8143 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8144 GEN_INT (STACK_POINTER_OFFSET + 64)));
8148 /* Use two different patterns for calls to explicitly named functions
8149 and calls through function pointers. This is necessary as these two
8150 types of calls use different calling conventions, and CSE might try
8151 to change the named call into an indirect call in some cases (using
8152 two patterns keeps CSE from performing this optimization).
8154 We now use even more call patterns as there was a subtle bug in
8155 attempting to restore the pic register after a call using a simple
8156 move insn. During reload, a instruction involving a pseudo register
8157 with no explicit dependence on the PIC register can be converted
8158 to an equivalent load from memory using the PIC register. If we
8159 emit a simple move to restore the PIC register in the initial rtl
8160 generation, then it can potentially be repositioned during scheduling.
8161 and an instruction that eventually uses the PIC register may end up
8162 between the call and the PIC register restore.
8164 This only worked because there is a post call group of instructions
8165 that are scheduled with the call. These instructions are included
8166 in the same basic block as the call. However, calls can throw in
8167 C++ code and a basic block has to terminate at the call if the call
8168 can throw. This results in the PIC register restore being scheduled
8169 independently from the call. So, we now hide the save and restore
8170 of the PIC register in the call pattern until after reload. Then,
8171 we split the moves out. A small side benefit is that we now don't
8172 need to have a use of the PIC register in the return pattern and
8173 the final save/restore operation is not needed.
8175 I elected to just clobber %r4 in the PIC patterns and use it instead
8176 of trying to force hppa_pic_save_rtx () to a callee saved register.
8177 This might have required a new register class and constraint. It
8178 was also simpler to just handle the restore from a register than a
8182 if (GET_CODE (op) == SYMBOL_REF)
8183 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
8186 op = force_reg (word_mode, op);
8187 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
8192 if (GET_CODE (op) == SYMBOL_REF)
8195 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
8197 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
8201 rtx tmpreg = gen_rtx_REG (word_mode, 22);
8203 emit_move_insn (tmpreg, force_reg (word_mode, op));
8205 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
8207 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
8214 (define_insn "call_val_symref"
8215 [(set (match_operand 0 "" "")
8216 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8217 (match_operand 2 "" "i")))
8218 (clobber (reg:SI 1))
8219 (clobber (reg:SI 2))
8220 (use (const_int 0))]
8221 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8224 output_arg_descriptor (insn);
8225 return output_call (insn, operands[1], 0);
8227 [(set_attr "type" "call")
8228 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8230 (define_insn "call_val_symref_pic"
8231 [(set (match_operand 0 "" "")
8232 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8233 (match_operand 2 "" "i")))
8234 (clobber (reg:SI 1))
8235 (clobber (reg:SI 2))
8236 (clobber (reg:SI 4))
8238 (use (const_int 0))]
8239 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8242 output_arg_descriptor (insn);
8243 return output_call (insn, operands[1], 0);
8245 [(set_attr "type" "call")
8246 (set (attr "length")
8247 (plus (symbol_ref "attr_length_call (insn, 0)")
8248 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8250 ;; Split out the PIC register save and restore after reload. This is
8251 ;; done only if the function returns. As the split is done after reload,
8252 ;; there are some situations in which we unnecessarily save and restore
8253 ;; %r4. This happens when there is a single call and the PIC register
8254 ;; is "dead" after the call. This isn't easy to fix as the usage of
8255 ;; the PIC register isn't completely determined until the reload pass.
8257 [(parallel [(set (match_operand 0 "" "")
8258 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8259 (match_operand 2 "" "")))
8260 (clobber (reg:SI 1))
8261 (clobber (reg:SI 2))
8262 (clobber (reg:SI 4))
8264 (use (const_int 0))])]
8265 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
8267 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8268 [(set (reg:SI 4) (reg:SI 19))
8269 (parallel [(set (match_dup 0)
8270 (call (mem:SI (match_dup 1))
8272 (clobber (reg:SI 1))
8273 (clobber (reg:SI 2))
8275 (use (const_int 0))])
8276 (set (reg:SI 19) (reg:SI 4))]
8279 ;; Remove the clobber of register 4 when optimizing. This has to be
8280 ;; done with a peephole optimization rather than a split because the
8281 ;; split sequence for a call must be longer than one instruction.
8283 [(parallel [(set (match_operand 0 "" "")
8284 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8285 (match_operand 2 "" "")))
8286 (clobber (reg:SI 1))
8287 (clobber (reg:SI 2))
8288 (clobber (reg:SI 4))
8290 (use (const_int 0))])]
8291 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8292 [(parallel [(set (match_dup 0)
8293 (call (mem:SI (match_dup 1))
8295 (clobber (reg:SI 1))
8296 (clobber (reg:SI 2))
8298 (use (const_int 0))])]
8301 (define_insn "*call_val_symref_pic_post_reload"
8302 [(set (match_operand 0 "" "")
8303 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8304 (match_operand 2 "" "i")))
8305 (clobber (reg:SI 1))
8306 (clobber (reg:SI 2))
8308 (use (const_int 0))]
8309 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8312 output_arg_descriptor (insn);
8313 return output_call (insn, operands[1], 0);
8315 [(set_attr "type" "call")
8316 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8318 ;; This pattern is split if it is necessary to save and restore the
8320 (define_insn "call_val_symref_64bit"
8321 [(set (match_operand 0 "" "")
8322 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8323 (match_operand 2 "" "i")))
8324 (clobber (reg:DI 1))
8325 (clobber (reg:DI 2))
8326 (clobber (reg:DI 4))
8329 (use (const_int 0))]
8333 output_arg_descriptor (insn);
8334 return output_call (insn, operands[1], 0);
8336 [(set_attr "type" "call")
8337 (set (attr "length")
8338 (plus (symbol_ref "attr_length_call (insn, 0)")
8339 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8341 ;; Split out the PIC register save and restore after reload. This is
8342 ;; done only if the function returns. As the split is done after reload,
8343 ;; there are some situations in which we unnecessarily save and restore
8344 ;; %r4. This happens when there is a single call and the PIC register
8345 ;; is "dead" after the call. This isn't easy to fix as the usage of
8346 ;; the PIC register isn't completely determined until the reload pass.
8348 [(parallel [(set (match_operand 0 "" "")
8349 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8350 (match_operand 2 "" "")))
8351 (clobber (reg:DI 1))
8352 (clobber (reg:DI 2))
8353 (clobber (reg:DI 4))
8356 (use (const_int 0))])]
8359 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8360 [(set (reg:DI 4) (reg:DI 27))
8361 (parallel [(set (match_dup 0)
8362 (call (mem:SI (match_dup 1))
8364 (clobber (reg:DI 1))
8365 (clobber (reg:DI 2))
8368 (use (const_int 0))])
8369 (set (reg:DI 27) (reg:DI 4))]
8372 ;; Remove the clobber of register 4 when optimizing. This has to be
8373 ;; done with a peephole optimization rather than a split because the
8374 ;; split sequence for a call must be longer than one instruction.
8376 [(parallel [(set (match_operand 0 "" "")
8377 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8378 (match_operand 2 "" "")))
8379 (clobber (reg:DI 1))
8380 (clobber (reg:DI 2))
8381 (clobber (reg:DI 4))
8384 (use (const_int 0))])]
8385 "TARGET_64BIT && reload_completed"
8386 [(parallel [(set (match_dup 0)
8387 (call (mem:SI (match_dup 1))
8389 (clobber (reg:DI 1))
8390 (clobber (reg:DI 2))
8393 (use (const_int 0))])]
8396 (define_insn "*call_val_symref_64bit_post_reload"
8397 [(set (match_operand 0 "" "")
8398 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8399 (match_operand 2 "" "i")))
8400 (clobber (reg:DI 1))
8401 (clobber (reg:DI 2))
8404 (use (const_int 0))]
8408 output_arg_descriptor (insn);
8409 return output_call (insn, operands[1], 0);
8411 [(set_attr "type" "call")
8412 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8414 (define_insn "call_val_reg"
8415 [(set (match_operand 0 "" "")
8416 (call (mem:SI (reg:SI 22))
8417 (match_operand 1 "" "i")))
8418 (clobber (reg:SI 1))
8419 (clobber (reg:SI 2))
8420 (use (const_int 1))]
8424 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8426 [(set_attr "type" "dyncall")
8427 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8429 ;; This pattern is split if it is necessary to save and restore the
8431 (define_insn "call_val_reg_pic"
8432 [(set (match_operand 0 "" "")
8433 (call (mem:SI (reg:SI 22))
8434 (match_operand 1 "" "i")))
8435 (clobber (reg:SI 1))
8436 (clobber (reg:SI 2))
8437 (clobber (reg:SI 4))
8439 (use (const_int 1))]
8443 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8445 [(set_attr "type" "dyncall")
8446 (set (attr "length")
8447 (plus (symbol_ref "attr_length_indirect_call (insn)")
8448 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8450 ;; Split out the PIC register save and restore after reload. This is
8451 ;; done only if the function returns. As the split is done after reload,
8452 ;; there are some situations in which we unnecessarily save and restore
8453 ;; %r4. This happens when there is a single call and the PIC register
8454 ;; is "dead" after the call. This isn't easy to fix as the usage of
8455 ;; the PIC register isn't completely determined until the reload pass.
8457 [(parallel [(set (match_operand 0 "" "")
8458 (call (mem:SI (reg:SI 22))
8459 (match_operand 1 "" "")))
8460 (clobber (reg:SI 1))
8461 (clobber (reg:SI 2))
8462 (clobber (reg:SI 4))
8464 (use (const_int 1))])]
8467 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8468 [(set (reg:SI 4) (reg:SI 19))
8469 (parallel [(set (match_dup 0)
8470 (call (mem:SI (reg:SI 22))
8472 (clobber (reg:SI 1))
8473 (clobber (reg:SI 2))
8475 (use (const_int 1))])
8476 (set (reg:SI 19) (reg:SI 4))]
8479 ;; Remove the clobber of register 4 when optimizing. This has to be
8480 ;; done with a peephole optimization rather than a split because the
8481 ;; split sequence for a call must be longer than one instruction.
8483 [(parallel [(set (match_operand 0 "" "")
8484 (call (mem:SI (reg:SI 22))
8485 (match_operand 1 "" "")))
8486 (clobber (reg:SI 1))
8487 (clobber (reg:SI 2))
8488 (clobber (reg:SI 4))
8490 (use (const_int 1))])]
8491 "!TARGET_64BIT && reload_completed"
8492 [(parallel [(set (match_dup 0)
8493 (call (mem:SI (reg:SI 22))
8495 (clobber (reg:SI 1))
8496 (clobber (reg:SI 2))
8498 (use (const_int 1))])]
8501 (define_insn "*call_val_reg_pic_post_reload"
8502 [(set (match_operand 0 "" "")
8503 (call (mem:SI (reg:SI 22))
8504 (match_operand 1 "" "i")))
8505 (clobber (reg:SI 1))
8506 (clobber (reg:SI 2))
8508 (use (const_int 1))]
8512 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8514 [(set_attr "type" "dyncall")
8515 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8517 ;; This pattern is split if it is necessary to save and restore the
8519 (define_insn "call_val_reg_64bit"
8520 [(set (match_operand 0 "" "")
8521 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8522 (match_operand 2 "" "i")))
8523 (clobber (reg:DI 2))
8524 (clobber (reg:DI 4))
8527 (use (const_int 1))]
8531 return output_indirect_call (insn, operands[1]);
8533 [(set_attr "type" "dyncall")
8534 (set (attr "length")
8535 (plus (symbol_ref "attr_length_indirect_call (insn)")
8536 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8538 ;; Split out the PIC register save and restore after reload. This is
8539 ;; done only if the function returns. As the split is done after reload,
8540 ;; there are some situations in which we unnecessarily save and restore
8541 ;; %r4. This happens when there is a single call and the PIC register
8542 ;; is "dead" after the call. This isn't easy to fix as the usage of
8543 ;; the PIC register isn't completely determined until the reload pass.
8545 [(parallel [(set (match_operand 0 "" "")
8546 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8547 (match_operand 2 "" "")))
8548 (clobber (reg:DI 2))
8549 (clobber (reg:DI 4))
8552 (use (const_int 1))])]
8555 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8556 [(set (reg:DI 4) (reg:DI 27))
8557 (parallel [(set (match_dup 0)
8558 (call (mem:SI (match_dup 1))
8560 (clobber (reg:DI 2))
8563 (use (const_int 1))])
8564 (set (reg:DI 27) (reg:DI 4))]
8567 ;; Remove the clobber of register 4 when optimizing. This has to be
8568 ;; done with a peephole optimization rather than a split because the
8569 ;; split sequence for a call must be longer than one instruction.
8571 [(parallel [(set (match_operand 0 "" "")
8572 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8573 (match_operand 2 "" "")))
8574 (clobber (reg:DI 2))
8575 (clobber (reg:DI 4))
8578 (use (const_int 1))])]
8579 "TARGET_64BIT && reload_completed"
8580 [(parallel [(set (match_dup 0)
8581 (call (mem:SI (match_dup 1))
8583 (clobber (reg:DI 2))
8586 (use (const_int 1))])]
8589 (define_insn "*call_val_reg_64bit_post_reload"
8590 [(set (match_operand 0 "" "")
8591 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8592 (match_operand 2 "" "i")))
8593 (clobber (reg:DI 2))
8596 (use (const_int 1))]
8600 return output_indirect_call (insn, operands[1]);
8602 [(set_attr "type" "dyncall")
8603 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8605 ;; Call subroutine returning any type.
8607 (define_expand "untyped_call"
8608 [(parallel [(call (match_operand 0 "" "")
8610 (match_operand 1 "" "")
8611 (match_operand 2 "" "")])]
8617 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8619 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8621 rtx set = XVECEXP (operands[2], 0, i);
8622 emit_move_insn (SET_DEST (set), SET_SRC (set));
8625 /* The optimizer does not know that the call sets the function value
8626 registers we stored in the result block. We avoid problems by
8627 claiming that all hard registers are used and clobbered at this
8629 emit_insn (gen_blockage ());
8634 (define_expand "sibcall"
8635 [(call (match_operand:SI 0 "" "")
8636 (match_operand 1 "" ""))]
8637 "!TARGET_PORTABLE_RUNTIME"
8641 rtx nb = operands[1];
8643 op = XEXP (operands[0], 0);
8647 if (!virtuals_instantiated)
8648 emit_move_insn (arg_pointer_rtx,
8649 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8653 /* The loop pass can generate new libcalls after the virtual
8654 registers are instantiated when fpregs are disabled because
8655 the only method that we have for doing DImode multiplication
8656 is with a libcall. This could be trouble if we haven't
8657 allocated enough space for the outgoing arguments. */
8658 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8660 emit_move_insn (arg_pointer_rtx,
8661 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8662 GEN_INT (STACK_POINTER_OFFSET + 64)));
8666 /* Indirect sibling calls are not allowed. */
8668 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8670 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8672 call_insn = emit_call_insn (call_insn);
8675 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8677 /* We don't have to restore the PIC register. */
8679 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8684 (define_insn "sibcall_internal_symref"
8685 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8686 (match_operand 1 "" "i"))
8687 (clobber (reg:SI 1))
8689 (use (const_int 0))]
8690 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8693 output_arg_descriptor (insn);
8694 return output_call (insn, operands[0], 1);
8696 [(set_attr "type" "call")
8697 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8699 (define_insn "sibcall_internal_symref_64bit"
8700 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8701 (match_operand 1 "" "i"))
8702 (clobber (reg:DI 1))
8704 (use (const_int 0))]
8708 output_arg_descriptor (insn);
8709 return output_call (insn, operands[0], 1);
8711 [(set_attr "type" "call")
8712 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8714 (define_expand "sibcall_value"
8715 [(set (match_operand 0 "" "")
8716 (call (match_operand:SI 1 "" "")
8717 (match_operand 2 "" "")))]
8718 "!TARGET_PORTABLE_RUNTIME"
8722 rtx nb = operands[1];
8724 op = XEXP (operands[1], 0);
8728 if (!virtuals_instantiated)
8729 emit_move_insn (arg_pointer_rtx,
8730 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8734 /* The loop pass can generate new libcalls after the virtual
8735 registers are instantiated when fpregs are disabled because
8736 the only method that we have for doing DImode multiplication
8737 is with a libcall. This could be trouble if we haven't
8738 allocated enough space for the outgoing arguments. */
8739 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8741 emit_move_insn (arg_pointer_rtx,
8742 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8743 GEN_INT (STACK_POINTER_OFFSET + 64)));
8747 /* Indirect sibling calls are not allowed. */
8750 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8753 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8755 call_insn = emit_call_insn (call_insn);
8758 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8760 /* We don't have to restore the PIC register. */
8762 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8767 (define_insn "sibcall_value_internal_symref"
8768 [(set (match_operand 0 "" "")
8769 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8770 (match_operand 2 "" "i")))
8771 (clobber (reg:SI 1))
8773 (use (const_int 0))]
8774 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8777 output_arg_descriptor (insn);
8778 return output_call (insn, operands[1], 1);
8780 [(set_attr "type" "call")
8781 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8783 (define_insn "sibcall_value_internal_symref_64bit"
8784 [(set (match_operand 0 "" "")
8785 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8786 (match_operand 2 "" "i")))
8787 (clobber (reg:DI 1))
8789 (use (const_int 0))]
8793 output_arg_descriptor (insn);
8794 return output_call (insn, operands[1], 1);
8796 [(set_attr "type" "call")
8797 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8803 [(set_attr "type" "move")
8804 (set_attr "length" "4")])
8806 ;; These are just placeholders so we know where branch tables
8808 (define_insn "begin_brtab"
8813 /* Only GAS actually supports this pseudo-op. */
8815 return \".begin_brtab\";
8819 [(set_attr "type" "move")
8820 (set_attr "length" "0")])
8822 (define_insn "end_brtab"
8827 /* Only GAS actually supports this pseudo-op. */
8829 return \".end_brtab\";
8833 [(set_attr "type" "move")
8834 (set_attr "length" "0")])
8836 ;;; EH does longjmp's from and within the data section. Thus,
8837 ;;; an interspace branch is required for the longjmp implementation.
8838 ;;; Registers r1 and r2 are used as scratch registers for the jump
8840 (define_expand "interspace_jump"
8842 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8843 (clobber (match_dup 1))])]
8847 operands[1] = gen_rtx_REG (word_mode, 2);
8851 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8852 (clobber (reg:SI 2))]
8853 "TARGET_PA_20 && !TARGET_64BIT"
8855 [(set_attr "type" "branch")
8856 (set_attr "length" "4")])
8859 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8860 (clobber (reg:SI 2))]
8861 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8863 [(set_attr "type" "branch")
8864 (set_attr "length" "4")])
8867 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8868 (clobber (reg:SI 2))]
8870 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8871 [(set_attr "type" "branch")
8872 (set_attr "length" "12")])
8875 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8876 (clobber (reg:DI 2))]
8879 [(set_attr "type" "branch")
8880 (set_attr "length" "4")])
8882 (define_expand "builtin_longjmp"
8883 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8887 /* The elements of the buffer are, in order: */
8888 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8889 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8890 POINTER_SIZE / BITS_PER_UNIT));
8891 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8892 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8893 rtx pv = gen_rtx_REG (Pmode, 1);
8895 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8896 gen_rtx_MEM (BLKmode,
8897 gen_rtx_SCRATCH (VOIDmode))));
8898 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8899 gen_rtx_MEM (BLKmode,
8900 hard_frame_pointer_rtx)));
8902 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8903 instead of the hard_frame_pointer_rtx in the save area. We need
8904 to adjust for the offset between these two values when we have
8905 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8906 pattern, the receiver performs the adjustment. */
8907 #ifdef HAVE_nonlocal_goto
8908 if (HAVE_nonlocal_goto)
8909 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8912 emit_move_insn (hard_frame_pointer_rtx, fp);
8914 /* This bit is the same as expand_builtin_longjmp. */
8915 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8916 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8917 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8919 /* Load the label we are jumping through into r1 so that we know
8920 where to look for it when we get back to setjmp's function for
8921 restoring the gp. */
8922 emit_move_insn (pv, lab);
8924 /* Prevent the insns above from being scheduled into the delay slot
8925 of the interspace jump because the space register could change. */
8926 emit_insn (gen_blockage ());
8928 emit_jump_insn (gen_interspace_jump (pv));
8933 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8934 (define_expand "extzv"
8935 [(set (match_operand 0 "register_operand" "")
8936 (zero_extract (match_operand 1 "register_operand" "")
8937 (match_operand 2 "uint32_operand" "")
8938 (match_operand 3 "uint32_operand" "")))]
8942 HOST_WIDE_INT len = INTVAL (operands[2]);
8943 HOST_WIDE_INT pos = INTVAL (operands[3]);
8945 /* PA extraction insns don't support zero length bitfields or fields
8946 extending beyond the left or right-most bits. Also, we reject lengths
8947 equal to a word as they are better handled by the move patterns. */
8948 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8951 /* From mips.md: extract_bit_field doesn't verify that our source
8952 matches the predicate, so check it again here. */
8953 if (!register_operand (operands[1], VOIDmode))
8957 emit_insn (gen_extzv_64 (operands[0], operands[1],
8958 operands[2], operands[3]));
8960 emit_insn (gen_extzv_32 (operands[0], operands[1],
8961 operands[2], operands[3]));
8965 (define_insn "extzv_32"
8966 [(set (match_operand:SI 0 "register_operand" "=r")
8967 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8968 (match_operand:SI 2 "uint5_operand" "")
8969 (match_operand:SI 3 "uint5_operand" "")))]
8971 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8972 [(set_attr "type" "shift")
8973 (set_attr "length" "4")])
8976 [(set (match_operand:SI 0 "register_operand" "=r")
8977 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8979 (match_operand:SI 2 "register_operand" "q")))]
8981 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8982 [(set_attr "type" "shift")
8983 (set_attr "length" "4")])
8985 (define_insn "extzv_64"
8986 [(set (match_operand:DI 0 "register_operand" "=r")
8987 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8988 (match_operand:DI 2 "uint32_operand" "")
8989 (match_operand:DI 3 "uint32_operand" "")))]
8991 "extrd,u %1,%3+%2-1,%2,%0"
8992 [(set_attr "type" "shift")
8993 (set_attr "length" "4")])
8996 [(set (match_operand:DI 0 "register_operand" "=r")
8997 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8999 (match_operand:DI 2 "register_operand" "q")))]
9001 "extrd,u %1,%%sar,1,%0"
9002 [(set_attr "type" "shift")
9003 (set_attr "length" "4")])
9005 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
9006 (define_expand "extv"
9007 [(set (match_operand 0 "register_operand" "")
9008 (sign_extract (match_operand 1 "register_operand" "")
9009 (match_operand 2 "uint32_operand" "")
9010 (match_operand 3 "uint32_operand" "")))]
9014 HOST_WIDE_INT len = INTVAL (operands[2]);
9015 HOST_WIDE_INT pos = INTVAL (operands[3]);
9017 /* PA extraction insns don't support zero length bitfields or fields
9018 extending beyond the left or right-most bits. Also, we reject lengths
9019 equal to a word as they are better handled by the move patterns. */
9020 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9023 /* From mips.md: extract_bit_field doesn't verify that our source
9024 matches the predicate, so check it again here. */
9025 if (!register_operand (operands[1], VOIDmode))
9029 emit_insn (gen_extv_64 (operands[0], operands[1],
9030 operands[2], operands[3]));
9032 emit_insn (gen_extv_32 (operands[0], operands[1],
9033 operands[2], operands[3]));
9037 (define_insn "extv_32"
9038 [(set (match_operand:SI 0 "register_operand" "=r")
9039 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9040 (match_operand:SI 2 "uint5_operand" "")
9041 (match_operand:SI 3 "uint5_operand" "")))]
9043 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
9044 [(set_attr "type" "shift")
9045 (set_attr "length" "4")])
9048 [(set (match_operand:SI 0 "register_operand" "=r")
9049 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9051 (match_operand:SI 2 "register_operand" "q")))]
9053 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
9054 [(set_attr "type" "shift")
9055 (set_attr "length" "4")])
9057 (define_insn "extv_64"
9058 [(set (match_operand:DI 0 "register_operand" "=r")
9059 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9060 (match_operand:DI 2 "uint32_operand" "")
9061 (match_operand:DI 3 "uint32_operand" "")))]
9063 "extrd,s %1,%3+%2-1,%2,%0"
9064 [(set_attr "type" "shift")
9065 (set_attr "length" "4")])
9068 [(set (match_operand:DI 0 "register_operand" "=r")
9069 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9071 (match_operand:DI 2 "register_operand" "q")))]
9073 "extrd,s %1,%%sar,1,%0"
9074 [(set_attr "type" "shift")
9075 (set_attr "length" "4")])
9077 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
9078 (define_expand "insv"
9079 [(set (zero_extract (match_operand 0 "register_operand" "")
9080 (match_operand 1 "uint32_operand" "")
9081 (match_operand 2 "uint32_operand" ""))
9082 (match_operand 3 "arith5_operand" ""))]
9086 HOST_WIDE_INT len = INTVAL (operands[1]);
9087 HOST_WIDE_INT pos = INTVAL (operands[2]);
9089 /* PA insertion insns don't support zero length bitfields or fields
9090 extending beyond the left or right-most bits. Also, we reject lengths
9091 equal to a word as they are better handled by the move patterns. */
9092 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9095 /* From mips.md: insert_bit_field doesn't verify that our destination
9096 matches the predicate, so check it again here. */
9097 if (!register_operand (operands[0], VOIDmode))
9101 emit_insn (gen_insv_64 (operands[0], operands[1],
9102 operands[2], operands[3]));
9104 emit_insn (gen_insv_32 (operands[0], operands[1],
9105 operands[2], operands[3]));
9109 (define_insn "insv_32"
9110 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
9111 (match_operand:SI 1 "uint5_operand" "")
9112 (match_operand:SI 2 "uint5_operand" ""))
9113 (match_operand:SI 3 "arith5_operand" "r,L"))]
9116 {dep|depw} %3,%2+%1-1,%1,%0
9117 {depi|depwi} %3,%2+%1-1,%1,%0"
9118 [(set_attr "type" "shift,shift")
9119 (set_attr "length" "4,4")])
9121 ;; Optimize insertion of const_int values of type 1...1xxxx.
9123 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
9124 (match_operand:SI 1 "uint5_operand" "")
9125 (match_operand:SI 2 "uint5_operand" ""))
9126 (match_operand:SI 3 "const_int_operand" ""))]
9127 "(INTVAL (operands[3]) & 0x10) != 0 &&
9128 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9131 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9132 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
9134 [(set_attr "type" "shift")
9135 (set_attr "length" "4")])
9137 (define_insn "insv_64"
9138 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
9139 (match_operand:DI 1 "uint32_operand" "")
9140 (match_operand:DI 2 "uint32_operand" ""))
9141 (match_operand:DI 3 "arith32_operand" "r,L"))]
9144 depd %3,%2+%1-1,%1,%0
9145 depdi %3,%2+%1-1,%1,%0"
9146 [(set_attr "type" "shift,shift")
9147 (set_attr "length" "4,4")])
9149 ;; Optimize insertion of const_int values of type 1...1xxxx.
9151 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9152 (match_operand:DI 1 "uint32_operand" "")
9153 (match_operand:DI 2 "uint32_operand" ""))
9154 (match_operand:DI 3 "const_int_operand" ""))]
9155 "(INTVAL (operands[3]) & 0x10) != 0
9157 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9160 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9161 return \"depdi %3,%2+%1-1,%1,%0\";
9163 [(set_attr "type" "shift")
9164 (set_attr "length" "4")])
9167 [(set (match_operand:DI 0 "register_operand" "=r")
9168 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9171 "depd,z %1,31,32,%0"
9172 [(set_attr "type" "shift")
9173 (set_attr "length" "4")])
9175 ;; This insn is used for some loop tests, typically loops reversed when
9176 ;; strength reduction is used. It is actually created when the instruction
9177 ;; combination phase combines the special loop test. Since this insn
9178 ;; is both a jump insn and has an output, it must deal with its own
9179 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
9180 ;; to not choose the register alternatives in the event a reload is needed.
9181 (define_insn "decrement_and_branch_until_zero"
9184 (match_operator 2 "comparison_operator"
9186 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
9187 (match_operand:SI 1 "int5_operand" "L,L,L"))
9189 (label_ref (match_operand 3 "" ""))
9192 (plus:SI (match_dup 0) (match_dup 1)))
9193 (clobber (match_scratch:SI 4 "=X,r,r"))]
9195 "* return output_dbra (operands, insn, which_alternative); "
9196 ;; Do not expect to understand this the first time through.
9197 [(set_attr "type" "cbranch,multi,multi")
9198 (set (attr "length")
9199 (if_then_else (eq_attr "alternative" "0")
9200 ;; Loop counter in register case
9201 ;; Short branch has length of 4
9202 ;; Long branch has length of 8, 20, 24 or 28
9203 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9204 (const_int MAX_12BIT_OFFSET))
9206 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9207 (const_int MAX_17BIT_OFFSET))
9209 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9211 (eq (symbol_ref "flag_pic") (const_int 0))
9215 ;; Loop counter in FP reg case.
9216 ;; Extra goo to deal with additional reload insns.
9217 (if_then_else (eq_attr "alternative" "1")
9218 (if_then_else (lt (match_dup 3) (pc))
9219 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9220 (const_int MAX_12BIT_OFFSET))
9222 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9223 (const_int MAX_17BIT_OFFSET))
9225 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9227 (eq (symbol_ref "flag_pic") (const_int 0))
9230 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9231 (const_int MAX_12BIT_OFFSET))
9233 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9234 (const_int MAX_17BIT_OFFSET))
9236 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9238 (eq (symbol_ref "flag_pic") (const_int 0))
9242 ;; Loop counter in memory case.
9243 ;; Extra goo to deal with additional reload insns.
9244 (if_then_else (lt (match_dup 3) (pc))
9245 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9246 (const_int MAX_12BIT_OFFSET))
9248 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9249 (const_int MAX_17BIT_OFFSET))
9251 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9253 (eq (symbol_ref "flag_pic") (const_int 0))
9256 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9257 (const_int MAX_12BIT_OFFSET))
9259 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9260 (const_int MAX_17BIT_OFFSET))
9262 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9264 (eq (symbol_ref "flag_pic") (const_int 0))
9266 (const_int 36))))))])
9271 (match_operator 2 "movb_comparison_operator"
9272 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9273 (label_ref (match_operand 3 "" ""))
9275 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9278 "* return output_movb (operands, insn, which_alternative, 0); "
9279 ;; Do not expect to understand this the first time through.
9280 [(set_attr "type" "cbranch,multi,multi,multi")
9281 (set (attr "length")
9282 (if_then_else (eq_attr "alternative" "0")
9283 ;; Loop counter in register case
9284 ;; Short branch has length of 4
9285 ;; Long branch has length of 8, 20, 24 or 28
9286 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9287 (const_int MAX_12BIT_OFFSET))
9289 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9290 (const_int MAX_17BIT_OFFSET))
9292 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9294 (eq (symbol_ref "flag_pic") (const_int 0))
9298 ;; Loop counter in FP reg case.
9299 ;; Extra goo to deal with additional reload insns.
9300 (if_then_else (eq_attr "alternative" "1")
9301 (if_then_else (lt (match_dup 3) (pc))
9302 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9303 (const_int MAX_12BIT_OFFSET))
9305 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9306 (const_int MAX_17BIT_OFFSET))
9308 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9310 (eq (symbol_ref "flag_pic") (const_int 0))
9313 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9314 (const_int MAX_12BIT_OFFSET))
9316 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9317 (const_int MAX_17BIT_OFFSET))
9319 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9321 (eq (symbol_ref "flag_pic") (const_int 0))
9325 ;; Loop counter in memory or sar case.
9326 ;; Extra goo to deal with additional reload insns.
9327 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9328 (const_int MAX_12BIT_OFFSET))
9330 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9331 (const_int MAX_17BIT_OFFSET))
9333 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9335 (eq (symbol_ref "flag_pic") (const_int 0))
9337 (const_int 32)))))])
9339 ;; Handle negated branch.
9343 (match_operator 2 "movb_comparison_operator"
9344 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9346 (label_ref (match_operand 3 "" ""))))
9347 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9350 "* return output_movb (operands, insn, which_alternative, 1); "
9351 ;; Do not expect to understand this the first time through.
9352 [(set_attr "type" "cbranch,multi,multi,multi")
9353 (set (attr "length")
9354 (if_then_else (eq_attr "alternative" "0")
9355 ;; Loop counter in register case
9356 ;; Short branch has length of 4
9357 ;; Long branch has length of 8
9358 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9359 (const_int MAX_12BIT_OFFSET))
9361 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9362 (const_int MAX_17BIT_OFFSET))
9364 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9366 (eq (symbol_ref "flag_pic") (const_int 0))
9370 ;; Loop counter in FP reg case.
9371 ;; Extra goo to deal with additional reload insns.
9372 (if_then_else (eq_attr "alternative" "1")
9373 (if_then_else (lt (match_dup 3) (pc))
9374 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9375 (const_int MAX_12BIT_OFFSET))
9377 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9378 (const_int MAX_17BIT_OFFSET))
9380 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9382 (eq (symbol_ref "flag_pic") (const_int 0))
9385 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9386 (const_int MAX_12BIT_OFFSET))
9388 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9389 (const_int MAX_17BIT_OFFSET))
9391 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9393 (eq (symbol_ref "flag_pic") (const_int 0))
9397 ;; Loop counter in memory or SAR case.
9398 ;; Extra goo to deal with additional reload insns.
9399 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9400 (const_int MAX_12BIT_OFFSET))
9402 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9403 (const_int MAX_17BIT_OFFSET))
9405 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9407 (eq (symbol_ref "flag_pic") (const_int 0))
9409 (const_int 32)))))])
9412 [(set (pc) (label_ref (match_operand 3 "" "" )))
9413 (set (match_operand:SI 0 "ireg_operand" "=r")
9414 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9415 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9416 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9419 return output_parallel_addb (operands, insn);
9421 [(set_attr "type" "parallel_branch")
9422 (set (attr "length")
9423 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9424 (const_int MAX_12BIT_OFFSET))
9426 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9427 (const_int MAX_17BIT_OFFSET))
9429 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9431 (eq (symbol_ref "flag_pic") (const_int 0))
9436 [(set (pc) (label_ref (match_operand 2 "" "" )))
9437 (set (match_operand:SF 0 "ireg_operand" "=r")
9438 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9442 return output_parallel_movb (operands, insn);
9444 [(set_attr "type" "parallel_branch")
9445 (set (attr "length")
9446 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9447 (const_int MAX_12BIT_OFFSET))
9449 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9450 (const_int MAX_17BIT_OFFSET))
9452 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9454 (eq (symbol_ref "flag_pic") (const_int 0))
9459 [(set (pc) (label_ref (match_operand 2 "" "" )))
9460 (set (match_operand:SI 0 "ireg_operand" "=r")
9461 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9465 return output_parallel_movb (operands, insn);
9467 [(set_attr "type" "parallel_branch")
9468 (set (attr "length")
9469 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9470 (const_int MAX_12BIT_OFFSET))
9472 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9473 (const_int MAX_17BIT_OFFSET))
9475 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9477 (eq (symbol_ref "flag_pic") (const_int 0))
9482 [(set (pc) (label_ref (match_operand 2 "" "" )))
9483 (set (match_operand:HI 0 "ireg_operand" "=r")
9484 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9488 return output_parallel_movb (operands, insn);
9490 [(set_attr "type" "parallel_branch")
9491 (set (attr "length")
9492 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9493 (const_int MAX_12BIT_OFFSET))
9495 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9496 (const_int MAX_17BIT_OFFSET))
9498 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9500 (eq (symbol_ref "flag_pic") (const_int 0))
9505 [(set (pc) (label_ref (match_operand 2 "" "" )))
9506 (set (match_operand:QI 0 "ireg_operand" "=r")
9507 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9511 return output_parallel_movb (operands, insn);
9513 [(set_attr "type" "parallel_branch")
9514 (set (attr "length")
9515 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9516 (const_int MAX_12BIT_OFFSET))
9518 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9519 (const_int MAX_17BIT_OFFSET))
9521 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9523 (eq (symbol_ref "flag_pic") (const_int 0))
9528 [(set (match_operand 0 "register_operand" "=f")
9529 (mult (match_operand 1 "register_operand" "f")
9530 (match_operand 2 "register_operand" "f")))
9531 (set (match_operand 3 "register_operand" "+f")
9532 (plus (match_operand 4 "register_operand" "f")
9533 (match_operand 5 "register_operand" "f")))]
9534 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9535 && reload_completed && fmpyaddoperands (operands)"
9538 if (GET_MODE (operands[0]) == DFmode)
9540 if (rtx_equal_p (operands[3], operands[5]))
9541 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9543 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9547 if (rtx_equal_p (operands[3], operands[5]))
9548 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9550 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9553 [(set_attr "type" "fpalu")
9554 (set_attr "length" "4")])
9557 [(set (match_operand 3 "register_operand" "+f")
9558 (plus (match_operand 4 "register_operand" "f")
9559 (match_operand 5 "register_operand" "f")))
9560 (set (match_operand 0 "register_operand" "=f")
9561 (mult (match_operand 1 "register_operand" "f")
9562 (match_operand 2 "register_operand" "f")))]
9563 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9564 && reload_completed && fmpyaddoperands (operands)"
9567 if (GET_MODE (operands[0]) == DFmode)
9569 if (rtx_equal_p (operands[3], operands[5]))
9570 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9572 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9576 if (rtx_equal_p (operands[3], operands[5]))
9577 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9579 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9582 [(set_attr "type" "fpalu")
9583 (set_attr "length" "4")])
9586 [(set (match_operand 0 "register_operand" "=f")
9587 (mult (match_operand 1 "register_operand" "f")
9588 (match_operand 2 "register_operand" "f")))
9589 (set (match_operand 3 "register_operand" "+f")
9590 (minus (match_operand 4 "register_operand" "f")
9591 (match_operand 5 "register_operand" "f")))]
9592 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9593 && reload_completed && fmpysuboperands (operands)"
9596 if (GET_MODE (operands[0]) == DFmode)
9597 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9599 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9601 [(set_attr "type" "fpalu")
9602 (set_attr "length" "4")])
9605 [(set (match_operand 3 "register_operand" "+f")
9606 (minus (match_operand 4 "register_operand" "f")
9607 (match_operand 5 "register_operand" "f")))
9608 (set (match_operand 0 "register_operand" "=f")
9609 (mult (match_operand 1 "register_operand" "f")
9610 (match_operand 2 "register_operand" "f")))]
9611 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9612 && reload_completed && fmpysuboperands (operands)"
9615 if (GET_MODE (operands[0]) == DFmode)
9616 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9618 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9620 [(set_attr "type" "fpalu")
9621 (set_attr "length" "4")])
9623 ;; The following two patterns are used by the trampoline code for nested
9624 ;; functions. They flush the I and D cache lines from the start address
9625 ;; (operand0) to the end address (operand1). No lines are flushed if the
9626 ;; end address is less than the start address (unsigned).
9628 ;; Because the range of memory flushed is variable and the size of a MEM
9629 ;; can only be a CONST_INT, the patterns specify that they perform an
9630 ;; unspecified volatile operation on all memory.
9632 ;; The address range for an icache flush must lie within a single
9633 ;; space on targets with non-equivalent space registers.
9635 ;; Operand 0 contains the start address.
9636 ;; Operand 1 contains the end address.
9637 ;; Operand 2 contains the line length to use.
9638 (define_insn "dcacheflush<P:mode>"
9640 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9641 (use (match_operand 0 "pmode_register_operand" "r"))
9642 (use (match_operand 1 "pmode_register_operand" "r"))
9643 (use (match_operand 2 "pmode_register_operand" "r"))
9644 (clobber (match_scratch:P 3 "=&0"))]
9646 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9647 [(set_attr "type" "multi")
9648 (set_attr "length" "12")])
9650 (define_insn "icacheflush<P:mode>"
9652 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9653 (use (match_operand 0 "pmode_register_operand" "r"))
9654 (use (match_operand 1 "pmode_register_operand" "r"))
9655 (use (match_operand 2 "pmode_register_operand" "r"))
9656 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9657 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9658 (clobber (match_scratch:P 5 "=&0"))]
9660 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9661 [(set_attr "type" "multi")
9662 (set_attr "length" "52")])
9664 ;; An out-of-line prologue.
9665 (define_insn "outline_prologue_call"
9666 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9667 (clobber (reg:SI 31))
9668 (clobber (reg:SI 22))
9669 (clobber (reg:SI 21))
9670 (clobber (reg:SI 20))
9671 (clobber (reg:SI 19))
9672 (clobber (reg:SI 1))]
9676 extern int frame_pointer_needed;
9678 /* We need two different versions depending on whether or not we
9679 need a frame pointer. Also note that we return to the instruction
9680 immediately after the branch rather than two instructions after the
9681 break as normally is the case. */
9682 if (frame_pointer_needed)
9684 /* Must import the magic millicode routine(s). */
9685 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9687 if (TARGET_PORTABLE_RUNTIME)
9689 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9690 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9694 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9698 /* Must import the magic millicode routine(s). */
9699 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9701 if (TARGET_PORTABLE_RUNTIME)
9703 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9704 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9707 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9711 [(set_attr "type" "multi")
9712 (set_attr "length" "8")])
9714 ;; An out-of-line epilogue.
9715 (define_insn "outline_epilogue_call"
9716 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9719 (clobber (reg:SI 31))
9720 (clobber (reg:SI 22))
9721 (clobber (reg:SI 21))
9722 (clobber (reg:SI 20))
9723 (clobber (reg:SI 19))
9724 (clobber (reg:SI 2))
9725 (clobber (reg:SI 1))]
9729 extern int frame_pointer_needed;
9731 /* We need two different versions depending on whether or not we
9732 need a frame pointer. Also note that we return to the instruction
9733 immediately after the branch rather than two instructions after the
9734 break as normally is the case. */
9735 if (frame_pointer_needed)
9737 /* Must import the magic millicode routine. */
9738 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9740 /* The out-of-line prologue will make sure we return to the right
9742 if (TARGET_PORTABLE_RUNTIME)
9744 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9745 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9749 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9753 /* Must import the magic millicode routine. */
9754 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9756 /* The out-of-line prologue will make sure we return to the right
9758 if (TARGET_PORTABLE_RUNTIME)
9760 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9761 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9764 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9768 [(set_attr "type" "multi")
9769 (set_attr "length" "8")])
9771 ;; Given a function pointer, canonicalize it so it can be
9772 ;; reliably compared to another function pointer. */
9773 (define_expand "canonicalize_funcptr_for_compare"
9774 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9775 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9776 (clobber (match_dup 2))
9777 (clobber (reg:SI 26))
9778 (clobber (reg:SI 22))
9779 (clobber (reg:SI 31))])
9780 (set (match_operand:SI 0 "register_operand" "")
9782 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9787 rtx canonicalize_funcptr_for_compare_libfunc
9788 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9790 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9791 operands[0], LCT_NORMAL, Pmode,
9792 1, operands[1], Pmode);
9796 operands[2] = gen_reg_rtx (SImode);
9797 if (GET_CODE (operands[1]) != REG)
9799 rtx tmp = gen_reg_rtx (Pmode);
9800 emit_move_insn (tmp, operands[1]);
9805 (define_insn "*$$sh_func_adrs"
9806 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9807 (clobber (match_operand:SI 0 "register_operand" "=a"))
9808 (clobber (reg:SI 26))
9809 (clobber (reg:SI 22))
9810 (clobber (reg:SI 31))]
9814 int length = get_attr_length (insn);
9817 xoperands[0] = GEN_INT (length - 8);
9818 xoperands[1] = GEN_INT (length - 16);
9820 /* Must import the magic millicode routine. */
9821 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9823 /* This is absolutely amazing.
9825 First, copy our input parameter into %r29 just in case we don't
9826 need to call $$sh_func_adrs. */
9827 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9828 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9830 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9831 we use %r26 unchanged. */
9832 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9833 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9835 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9836 4096, then again we use %r26 unchanged. */
9837 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9839 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9840 return output_millicode_call (insn,
9841 gen_rtx_SYMBOL_REF (SImode,
9842 \"$$sh_func_adrs\"));
9844 [(set_attr "type" "multi")
9845 (set (attr "length")
9846 (plus (symbol_ref "attr_length_millicode_call (insn)")
9849 ;; On the PA, the PIC register is call clobbered, so it must
9850 ;; be saved & restored around calls by the caller. If the call
9851 ;; doesn't return normally (nonlocal goto, or an exception is
9852 ;; thrown), then the code at the exception handler label must
9853 ;; restore the PIC register.
9854 (define_expand "exception_receiver"
9859 /* On the 64-bit port, we need a blockage because there is
9860 confusion regarding the dependence of the restore on the
9861 frame pointer. As a result, the frame pointer and pic
9862 register restores sometimes are interchanged erroneously. */
9864 emit_insn (gen_blockage ());
9865 /* Restore the PIC register using hppa_pic_save_rtx (). The
9866 PIC register is not saved in the frame in 64-bit ABI. */
9867 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9868 emit_insn (gen_blockage ());
9872 (define_expand "builtin_setjmp_receiver"
9873 [(label_ref (match_operand 0 "" ""))]
9878 emit_insn (gen_blockage ());
9879 /* Restore the PIC register. Hopefully, this will always be from
9880 a stack slot. The only registers that are valid after a
9881 builtin_longjmp are the stack and frame pointers. */
9882 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9883 emit_insn (gen_blockage ());
9887 ;; Allocate new stack space and update the saved stack pointer in the
9888 ;; frame marker. The HP C compilers also copy additional words in the
9889 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9890 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9891 ;; currently don't copy these values.
9893 ;; Since the copy of the frame marker can't be done atomically, I
9894 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9895 ;; The HP compilers appear to raise the stack and copy the frame
9896 ;; marker in a strict instruction sequence. This suggests that the
9897 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9898 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9899 ;; as GAS doesn't support it, or try to keep the instructions emitted
9900 ;; here in strict sequence.
9901 (define_expand "allocate_stack"
9902 [(match_operand 0 "" "")
9903 (match_operand 1 "" "")]
9909 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9910 in operand 0 before adjusting the stack. */
9911 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9912 anti_adjust_stack (operands[1]);
9913 if (TARGET_HPUX_UNWIND_LIBRARY)
9915 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9916 GEN_INT (TARGET_64BIT ? -8 : -4));
9917 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9919 if (!TARGET_64BIT && flag_pic)
9921 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9922 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9927 (define_expand "prefetch"
9928 [(match_operand 0 "address_operand" "")
9929 (match_operand 1 "const_int_operand" "")
9930 (match_operand 2 "const_int_operand" "")]
9933 int locality = INTVAL (operands[2]);
9935 gcc_assert (locality >= 0 && locality <= 3);
9937 /* Change operand[0] to a MEM as we don't have the infrastructure
9938 to output all the supported address modes for ldw/ldd when we use
9939 the address directly. However, we do have it for MEMs. */
9940 operands[0] = gen_rtx_MEM (QImode, operands[0]);
9942 /* If the address isn't valid for the prefetch, replace it. */
9945 if (!prefetch_nocc_operand (operands[0], QImode))
9947 = replace_equiv_address (operands[0],
9948 copy_to_mode_reg (Pmode,
9949 XEXP (operands[0], 0)));
9950 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
9954 if (!prefetch_cc_operand (operands[0], QImode))
9956 = replace_equiv_address (operands[0],
9957 copy_to_mode_reg (Pmode,
9958 XEXP (operands[0], 0)));
9959 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
9964 (define_insn "prefetch_cc"
9965 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
9966 (match_operand:SI 1 "const_int_operand" "n")
9967 (match_operand:SI 2 "const_int_operand" "n"))]
9968 "TARGET_PA_20 && operands[2] == const0_rtx"
9970 /* The SL cache-control completor indicates good spatial locality but
9971 poor temporal locality. The ldw instruction with a target of general
9972 register 0 prefetches a cache line for a read. The ldd instruction
9973 prefetches a cache line for a write. */
9974 static const char * const instr[2] = {
9975 "ldw%M0,sl %0,%%r0",
9978 int read_or_write = INTVAL (operands[1]);
9980 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9982 return instr [read_or_write];
9984 [(set_attr "type" "load")
9985 (set_attr "length" "4")])
9987 (define_insn "prefetch_nocc"
9988 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
9989 (match_operand:SI 1 "const_int_operand" "n,n")
9990 (match_operand:SI 2 "const_int_operand" "n,n"))]
9991 "TARGET_PA_20 && operands[2] != const0_rtx"
9993 /* The ldw instruction with a target of general register 0 prefetches
9994 a cache line for a read. The ldd instruction prefetches a cache line
9996 static const char * const instr[2][2] = {
10006 int read_or_write = INTVAL (operands[1]);
10008 gcc_assert (which_alternative == 0 || which_alternative == 1);
10009 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10011 return instr [which_alternative][read_or_write];
10013 [(set_attr "type" "load")
10014 (set_attr "length" "4")])
10018 (define_insn "tgd_load"
10019 [(set (match_operand:SI 0 "register_operand" "=r")
10020 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
10021 (clobber (reg:SI 1))
10026 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
10028 [(set_attr "type" "multi")
10029 (set_attr "length" "8")])
10031 (define_insn "tgd_load_pic"
10032 [(set (match_operand:SI 0 "register_operand" "=r")
10033 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
10034 (clobber (reg:SI 1))
10039 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
10041 [(set_attr "type" "multi")
10042 (set_attr "length" "8")])
10044 (define_insn "tld_load"
10045 [(set (match_operand:SI 0 "register_operand" "=r")
10046 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
10047 (clobber (reg:SI 1))
10052 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
10054 [(set_attr "type" "multi")
10055 (set_attr "length" "8")])
10057 (define_insn "tld_load_pic"
10058 [(set (match_operand:SI 0 "register_operand" "=r")
10059 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
10060 (clobber (reg:SI 1))
10065 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
10067 [(set_attr "type" "multi")
10068 (set_attr "length" "8")])
10070 (define_insn "tld_offset_load"
10071 [(set (match_operand:SI 0 "register_operand" "=r")
10072 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
10074 (match_operand:SI 2 "register_operand" "r")))
10075 (clobber (reg:SI 1))]
10079 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
10081 [(set_attr "type" "multi")
10082 (set_attr "length" "8")])
10084 (define_insn "tp_load"
10085 [(set (match_operand:SI 0 "register_operand" "=r")
10086 (unspec:SI [(const_int 0)] UNSPEC_TP))]
10089 [(set_attr "type" "multi")
10090 (set_attr "length" "4")])
10092 (define_insn "tie_load"
10093 [(set (match_operand:SI 0 "register_operand" "=r")
10094 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
10095 (clobber (reg:SI 1))
10100 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
10102 [(set_attr "type" "multi")
10103 (set_attr "length" "8")])
10105 (define_insn "tie_load_pic"
10106 [(set (match_operand:SI 0 "register_operand" "=r")
10107 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
10108 (clobber (reg:SI 1))
10113 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
10115 [(set_attr "type" "multi")
10116 (set_attr "length" "8")])
10118 (define_insn "tle_load"
10119 [(set (match_operand:SI 0 "register_operand" "=r")
10120 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
10122 (match_operand:SI 2 "register_operand" "r")))
10123 (clobber (reg:SI 1))]
10125 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
10126 [(set_attr "type" "multi")
10127 (set_attr "length" "8")])