gcc/config/pa/predicates.md

   1 ;; Predicate definitions for HP PA-RISC.
   2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  19 ;; Boston, MA 02111-1307, USA.
  20
  21 ;; Return nonzero only if OP is a register of mode MODE, or
  22 ;; CONST0_RTX.
  23
  24 (define_predicate "reg_or_0_operand"
  25   (match_code "subreg,reg,const_int,const_double")
  26 {
  27   return (op == CONST0_RTX (mode) || register_operand (op, mode));
  28 })
  29
  30 ;; Return nonzero if OP is suitable for use in a call to a named
  31 ;; function.
  32 ;;
  33 ;; For 2.5 try to eliminate either call_operand_address or
  34 ;; function_label_operand, they perform very similar functions.
  35
  36 (define_predicate "call_operand_address"
  37   (match_code "label_ref,symbol_ref,const_int,const_double,const,high")
  38 {
  39   return (GET_MODE (op) == word_mode
  40           && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
  41 })
  42
  43 ;; Return 1 iff OP is an indexed memory operand.
  44
  45 (define_predicate "indexed_memory_operand"
  46   (match_code "subreg,mem")
  47 {
  48   if (GET_MODE (op) != mode)
  49     return 0;
  50
  51   /* Before reload, a (SUBREG (MEM...)) forces reloading into a register.  */
  52   if (reload_completed && GET_CODE (op) == SUBREG)
  53     op = SUBREG_REG (op);
  54
  55   if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
  56     return 0;
  57
  58   op = XEXP (op, 0);
  59
  60   return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
  61 })
  62
  63 ;; TODO: Add a comment.
  64
  65 (define_predicate "symbolic_operand"
  66   (match_code "symbol_ref,label_ref,const")
  67 {
  68   switch (GET_CODE (op))
  69     {
  70     case SYMBOL_REF:
  71     case LABEL_REF:
  72       return 1;
  73     case CONST:
  74       op = XEXP (op, 0);
  75       return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
  76                || GET_CODE (XEXP (op, 0)) == LABEL_REF)
  77               && GET_CODE (XEXP (op, 1)) == CONST_INT);
  78     default:
  79       return 0;
  80     }
  81 })
  82
  83 ;; Return truth value of statement that OP is a symbolic memory
  84 ;; operand of mode MODE.
  85
  86 (define_predicate "symbolic_memory_operand"
  87   (match_code "subreg,mem")
  88 {
  89   if (GET_CODE (op) == SUBREG)
  90     op = SUBREG_REG (op);
  91   if (GET_CODE (op) != MEM)
  92     return 0;
  93   op = XEXP (op, 0);
  94   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
  95           || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
  96 })
  97
  98 ;; Return 1 if the operand is a register operand or a non-symbolic
  99 ;; memory operand after reload.  This predicate is used for branch
 100 ;; patterns that internally handle register reloading.  We need to
 101 ;; accept non-symbolic memory operands after reload to ensure that the
 102 ;; pattern is still valid if reload didn't find a hard register for
 103 ;; the operand.
 104
 105 (define_predicate "reg_before_reload_operand"
 106   (match_code "reg,mem")
 107 {
 108   /* Don't accept a SUBREG since it will need a reload.  */
 109   if (GET_CODE (op) == SUBREG)
 110     return 0;
 111
 112   if (register_operand (op, mode))
 113     return 1;
 114
 115   if (reload_completed
 116       && memory_operand (op, mode)
 117       && !symbolic_memory_operand (op, mode))
 118     return 1;
 119
 120   return 0;
 121 })
 122
 123 ;; Return 1 if the operand is either a register, zero, or a memory
 124 ;; operand that is not symbolic.
 125
 126 (define_predicate "reg_or_0_or_nonsymb_mem_operand"
 127   (match_code "subreg,reg,mem,const_int,const_double")
 128 {
 129   if (register_operand (op, mode))
 130     return 1;
 131
 132   if (op == CONST0_RTX (mode))
 133     return 1;
 134
 135   if (GET_CODE (op) == SUBREG)
 136     op = SUBREG_REG (op);
 137
 138   if (GET_CODE (op) != MEM)
 139     return 0;
 140
 141   /* Until problems with management of the REG_POINTER flag are resolved,
 142      we need to delay creating move insns with unscaled indexed addresses
 143      until CSE is not expected.  */
 144   if (!TARGET_NO_SPACE_REGS
 145       && !cse_not_expected
 146       && GET_CODE (XEXP (op, 0)) == PLUS
 147       && REG_P (XEXP (XEXP (op, 0), 0))
 148       && REG_P (XEXP (XEXP (op, 0), 1)))
 149     return 0;
 150
 151   return (!symbolic_memory_operand (op, mode)
 152           && memory_address_p (mode, XEXP (op, 0)));
 153 })
 154
 155 ;; Accept anything that can be used as a destination operand for a
 156 ;; move instruction.  We don't accept indexed memory operands since
 157 ;; they are supported only for floating point stores.
 158
 159 (define_predicate "move_dest_operand"
 160   (match_code "subreg,reg,mem")
 161 {
 162   if (register_operand (op, mode))
 163     return 1;
 164
 165   if (GET_MODE (op) != mode)
 166     return 0;
 167
 168   if (GET_CODE (op) == SUBREG)
 169     op = SUBREG_REG (op);
 170
 171   if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
 172     return 0;
 173
 174   op = XEXP (op, 0);
 175
 176   return (memory_address_p (mode, op)
 177           && !IS_INDEX_ADDR_P (op)
 178           && !IS_LO_SUM_DLT_ADDR_P (op));
 179 })
 180
 181 ;; Accept anything that can be used as a source operand for a move
 182 ;; instruction.
 183
 184 (define_predicate "move_src_operand"
 185   (match_code "subreg,reg,const_int,mem")
 186 {
 187   if (register_operand (op, mode))
 188     return 1;
 189
 190   if (GET_CODE (op) == CONST_INT)
 191     return cint_ok_for_move (INTVAL (op));
 192
 193   if (GET_MODE (op) != mode)
 194     return 0;
 195
 196   if (GET_CODE (op) == SUBREG)
 197     op = SUBREG_REG (op);
 198
 199   if (GET_CODE (op) != MEM)
 200     return 0;
 201
 202   /* Until problems with management of the REG_POINTER flag are resolved,
 203      we need to delay creating move insns with unscaled indexed addresses
 204      until CSE is not expected.  */
 205   if (!TARGET_NO_SPACE_REGS
 206       && !cse_not_expected
 207       && GET_CODE (XEXP (op, 0)) == PLUS
 208       && REG_P (XEXP (XEXP (op, 0), 0))
 209       && REG_P (XEXP (XEXP (op, 0), 1)))
 210     return 0;
 211
 212   return memory_address_p (mode, XEXP (op, 0));
 213 })
 214
 215 ;; Accept anything that can be used as the source operand for a
 216 ;; prefetch instruction with a cache-control completer.
 217
 218 (define_predicate "prefetch_cc_operand"
 219   (match_code "mem")
 220 {
 221   if (GET_CODE (op) != MEM)
 222     return 0;
 223
 224   op = XEXP (op, 0);
 225
 226   /* We must reject virtual registers as we don't allow REG+D.  */
 227   if (op == virtual_incoming_args_rtx
 228       || op == virtual_stack_vars_rtx
 229       || op == virtual_stack_dynamic_rtx
 230       || op == virtual_outgoing_args_rtx
 231       || op == virtual_cfa_rtx)
 232     return 0;
 233
 234   if (!REG_P (op) && !IS_INDEX_ADDR_P (op))
 235     return 0;
 236
 237   /* Until problems with management of the REG_POINTER flag are resolved,
 238      we need to delay creating prefetch insns with unscaled indexed addresses
 239      until CSE is not expected.  */
 240   if (!TARGET_NO_SPACE_REGS
 241       && !cse_not_expected
 242       && GET_CODE (op) == PLUS
 243       && REG_P (XEXP (op, 0)))
 244     return 0;
 245
 246   return memory_address_p (mode, op);
 247 })
 248
 249 ;; Accept anything that can be used as the source operand for a
 250 ;; prefetch instruction with no cache-control completer.
 251
 252 (define_predicate "prefetch_nocc_operand"
 253   (match_code "mem")
 254 {
 255   if (GET_CODE (op) != MEM)
 256     return 0;
 257
 258   op = XEXP (op, 0);
 259
 260   /* Until problems with management of the REG_POINTER flag are resolved,
 261      we need to delay creating prefetch insns with unscaled indexed addresses
 262      until CSE is not expected.  */
 263   if (!TARGET_NO_SPACE_REGS
 264       && !cse_not_expected
 265       && GET_CODE (op) == PLUS
 266       && REG_P (XEXP (op, 0))
 267       && REG_P (XEXP (op, 1)))
 268     return 0;
 269
 270   return memory_address_p (mode, op);
 271 })
 272
 273 ;; Accept REG and any CONST_INT that can be moved in one instruction
 274 ;; into a general register.
 275
 276 (define_predicate "reg_or_cint_move_operand"
 277   (match_code "subreg,reg,const_int")
 278 {
 279   if (register_operand (op, mode))
 280     return 1;
 281
 282   return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
 283 })
 284
 285 ;; TODO: Add a comment here.
 286
 287 (define_predicate "pic_label_operand"
 288   (match_code "label_ref,const")
 289 {
 290   if (!flag_pic)
 291     return 0;
 292
 293   switch (GET_CODE (op))
 294     {
 295     case LABEL_REF:
 296       return 1;
 297     case CONST:
 298       op = XEXP (op, 0);
 299       return (GET_CODE (XEXP (op, 0)) == LABEL_REF
 300               && GET_CODE (XEXP (op, 1)) == CONST_INT);
 301     default:
 302       return 0;
 303     }
 304 })
 305
 306 ;; TODO: Add a comment here.
 307
 308 (define_predicate "fp_reg_operand"
 309   (match_code "reg")
 310 {
 311   return reg_renumber && FP_REG_P (op);
 312 })
 313
 314 ;; Return truth value of whether OP can be used as an operand in a
 315 ;; three operand arithmetic insn that accepts registers of mode MODE
 316 ;; or 14-bit signed integers.
 317
 318 (define_predicate "arith_operand"
 319   (match_code "subreg,reg,const_int")
 320 {
 321   return (register_operand (op, mode)
 322           || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
 323 })
 324
 325 ;; Return truth value of whether OP can be used as an operand in a
 326 ;; three operand arithmetic insn that accepts registers of mode MODE
 327 ;; or 11-bit signed integers.
 328
 329 (define_predicate "arith11_operand"
 330   (match_code "subreg,reg,const_int")
 331 {
 332   return (register_operand (op, mode)
 333           || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
 334 })
 335
 336 ;; A constant integer suitable for use in a PRE_MODIFY memory
 337 ;; reference.
 338
 339 (define_predicate "pre_cint_operand"
 340   (match_code "const_int")
 341 {
 342   return (GET_CODE (op) == CONST_INT
 343           && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
 344 })
 345
 346 ;; A constant integer suitable for use in a POST_MODIFY memory
 347 ;; reference.
 348
 349 (define_predicate "post_cint_operand"
 350   (match_code "const_int")
 351 {
 352   return (GET_CODE (op) == CONST_INT
 353           && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
 354 })
 355
 356 ;; TODO: Add a comment here.
 357
 358 (define_predicate "arith_double_operand"
 359   (match_code "subreg,reg,const_double")
 360 {
 361   return (register_operand (op, mode)
 362           || (GET_CODE (op) == CONST_DOUBLE
 363               && GET_MODE (op) == mode
 364               && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
 365               && ((CONST_DOUBLE_HIGH (op) >= 0)
 366                   == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
 367 })
 368
 369 ;; Return truth value of whether OP is an integer which fits the range
 370 ;; constraining immediate operands in three-address insns, or is an
 371 ;; integer register.
 372
 373 (define_predicate "ireg_or_int5_operand"
 374   (match_code "const_int,reg")
 375 {
 376   return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
 377           || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
 378 })
 379
 380 ;; Return truth value of whether OP is an integer which fits the range
 381 ;; constraining immediate operands in three-address insns.
 382
 383 (define_predicate "int5_operand"
 384   (match_code "const_int")
 385 {
 386   return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
 387 })
 388
 389 ;; Return truth value of whether OP is an integer which fits the range
 390 ;; constraining immediate operands in three-address insns.
 391
 392 (define_predicate "uint5_operand"
 393   (match_code "const_int")
 394 {
 395   return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
 396 })
 397
 398 ;; Return truth value of whether OP is an integer which fits the range
 399 ;; constraining immediate operands in three-address insns.
 400
 401 (define_predicate "int11_operand"
 402   (match_code "const_int")
 403 {
 404   return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
 405 })
 406
 407 ;; Return truth value of whether OP is an integer which fits the range
 408 ;; constraining immediate operands in three-address insns.
 409
 410 (define_predicate "uint32_operand"
 411   (match_code "const_int,const_double")
 412 {
 413 #if HOST_BITS_PER_WIDE_INT > 32
 414   /* All allowed constants will fit a CONST_INT.  */
 415   return (GET_CODE (op) == CONST_INT
 416           && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
 417 #else
 418   return (GET_CODE (op) == CONST_INT
 419           || (GET_CODE (op) == CONST_DOUBLE
 420               && CONST_DOUBLE_HIGH (op) == 0));
 421 #endif
 422 })
 423
 424 ;; Return truth value of whether OP is an integer which fits the range
 425 ;; constraining immediate operands in three-address insns.
 426
 427 (define_predicate "arith5_operand"
 428   (match_code "subreg,reg,const_int")
 429 {
 430   return register_operand (op, mode) || int5_operand (op, mode);
 431 })
 432
 433 ;; True iff depi or extru can be used to compute (reg & OP).
 434
 435 (define_predicate "and_operand"
 436   (match_code "subreg,reg,const_int")
 437 {
 438   return (register_operand (op, mode)
 439           || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
 440 })
 441
 442 ;; True iff depi can be used to compute (reg | OP).
 443
 444 (define_predicate "ior_operand"
 445   (match_code "const_int")
 446 {
 447   return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
 448 })
 449
 450 ;; True iff OP is a CONST_INT of the forms 0...0xxxx or
 451 ;; 0...01...1xxxx. Such values can be the left hand side x in (x <<
 452 ;; r), using the zvdepi instruction.
 453
 454 (define_predicate "lhs_lshift_cint_operand"
 455   (match_code "const_int")
 456 {
 457   unsigned HOST_WIDE_INT x;
 458   if (GET_CODE (op) != CONST_INT)
 459     return 0;
 460   x = INTVAL (op) >> 4;
 461   return (x & (x + 1)) == 0;
 462 })
 463
 464 ;; TODO: Add a comment here.
 465
 466 (define_predicate "lhs_lshift_operand"
 467   (match_code "subreg,reg,const_int")
 468 {
 469   return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
 470 })
 471
 472 ;; TODO: Add a comment here.
 473
 474 (define_predicate "arith32_operand"
 475   (match_code "subreg,reg,const_int")
 476 {
 477   return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
 478 })
 479
 480 ;; TODO: Add a comment here.
 481
 482 (define_predicate "pc_or_label_operand"
 483   (match_code "pc,label_ref")
 484 {
 485   return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
 486 })
 487
 488 ;; TODO: Add a comment here.
 489
 490 (define_predicate "plus_xor_ior_operator"
 491   (match_code "plus,xor,ior")
 492 {
 493   return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
 494           || GET_CODE (op) == IOR);
 495 })
 496
 497 ;; Return 1 if OP is a CONST_INT with the value 2, 4, or 8.  These are
 498 ;; the valid constant for shadd instructions.
 499
 500 (define_predicate "shadd_operand"
 501   (match_code "const_int")
 502 {
 503   return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
 504 })
 505
 506 ;; TODO: Add a comment here.
 507
 508 (define_predicate "div_operand"
 509   (match_code "reg,const_int")
 510 {
 511   return (mode == SImode
 512           && ((GET_CODE (op) == REG && REGNO (op) == 25)
 513               || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
 514                   && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
 515 })
 516
 517 ;; Return nonzero if OP is an integer register, else return zero.
 518
 519 (define_predicate "ireg_operand"
 520   (match_code "reg")
 521 {
 522   return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
 523 })
 524
 525 ;; Return 1 if this is a comparison operator.  This allows the use of
 526 ;; MATCH_OPERATOR to recognize all the branch insns.
 527
 528 (define_predicate "cmpib_comparison_operator"
 529   (match_code "eq,ne,lt,le,leu,gt,gtu,ge")
 530 {
 531   return ((mode == VOIDmode || GET_MODE (op) == mode)
 532           && (GET_CODE (op) == EQ
 533               || GET_CODE (op) == NE
 534               || GET_CODE (op) == GT
 535               || GET_CODE (op) == GTU
 536               || GET_CODE (op) == GE
 537               || GET_CODE (op) == LT
 538               || GET_CODE (op) == LE
 539               || GET_CODE (op) == LEU));
 540 })
 541
 542 ;; Return 1 if OP is an operator suitable for use in a movb
 543 ;; instruction.
 544
 545 (define_predicate "movb_comparison_operator"
 546   (match_code "eq,ne,lt,ge")
 547 {
 548   return (GET_CODE (op) == EQ || GET_CODE (op) == NE
 549           || GET_CODE (op) == LT || GET_CODE (op) == GE);
 550 })