1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
35 #include "conditions.h"
37 #include "stor-layout.h"
43 /* This file should be included last. */
44 #include "target-def.h"
46 /* this is the current value returned by the macro FIRST_PARM_OFFSET
48 int current_first_parm_offset
;
50 /* Routines to encode/decode pdp11 floats */
51 static void encode_pdp11_f (const struct real_format
*fmt
,
52 long *, const REAL_VALUE_TYPE
*);
53 static void decode_pdp11_f (const struct real_format
*,
54 REAL_VALUE_TYPE
*, const long *);
55 static void encode_pdp11_d (const struct real_format
*fmt
,
56 long *, const REAL_VALUE_TYPE
*);
57 static void decode_pdp11_d (const struct real_format
*,
58 REAL_VALUE_TYPE
*, const long *);
60 /* These two are taken from the corresponding vax descriptors
61 in real.c, changing only the encode/decode routine pointers. */
62 const struct real_format pdp11_f_format
=
85 const struct real_format pdp11_d_format
=
109 encode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
110 const REAL_VALUE_TYPE
*r
)
112 (*vax_f_format
.encode
) (fmt
, buf
, r
);
113 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
117 decode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
118 REAL_VALUE_TYPE
*r
, const long *buf
)
121 tbuf
= ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
122 (*vax_f_format
.decode
) (fmt
, r
, &tbuf
);
126 encode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
127 const REAL_VALUE_TYPE
*r
)
129 (*vax_d_format
.encode
) (fmt
, buf
, r
);
130 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
131 buf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
135 decode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
136 REAL_VALUE_TYPE
*r
, const long *buf
)
139 tbuf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
140 tbuf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
141 (*vax_d_format
.decode
) (fmt
, r
, tbuf
);
144 /* This is where the condition code register lives. */
145 /* rtx cc0_reg_rtx; - no longer needed? */
147 static const char *singlemove_string (rtx
*);
148 static bool pdp11_assemble_integer (rtx
, unsigned int, int);
149 static bool pdp11_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
150 static bool pdp11_return_in_memory (const_tree
, const_tree
);
151 static rtx
pdp11_function_value (const_tree
, const_tree
, bool);
152 static rtx
pdp11_libcall_value (machine_mode
, const_rtx
);
153 static bool pdp11_function_value_regno_p (const unsigned int);
154 static void pdp11_trampoline_init (rtx
, tree
, rtx
);
155 static rtx
pdp11_function_arg (cumulative_args_t
, machine_mode
,
157 static void pdp11_function_arg_advance (cumulative_args_t
,
158 machine_mode
, const_tree
, bool);
159 static void pdp11_conditional_register_usage (void);
160 static bool pdp11_legitimate_constant_p (machine_mode
, rtx
);
162 static bool pdp11_scalar_mode_supported_p (machine_mode
);
164 /* Initialize the GCC target structure. */
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP NULL
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP NULL
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP NULL
171 #undef TARGET_ASM_INTEGER
172 #define TARGET_ASM_INTEGER pdp11_assemble_integer
174 #undef TARGET_ASM_OPEN_PAREN
175 #define TARGET_ASM_OPEN_PAREN "["
176 #undef TARGET_ASM_CLOSE_PAREN
177 #define TARGET_ASM_CLOSE_PAREN "]"
179 #undef TARGET_RTX_COSTS
180 #define TARGET_RTX_COSTS pdp11_rtx_costs
182 #undef TARGET_FUNCTION_ARG
183 #define TARGET_FUNCTION_ARG pdp11_function_arg
184 #undef TARGET_FUNCTION_ARG_ADVANCE
185 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance
187 #undef TARGET_RETURN_IN_MEMORY
188 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
190 #undef TARGET_FUNCTION_VALUE
191 #define TARGET_FUNCTION_VALUE pdp11_function_value
192 #undef TARGET_LIBCALL_VALUE
193 #define TARGET_LIBCALL_VALUE pdp11_libcall_value
194 #undef TARGET_FUNCTION_VALUE_REGNO_P
195 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p
197 #undef TARGET_TRAMPOLINE_INIT
198 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
200 #undef TARGET_SECONDARY_RELOAD
201 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
203 #undef TARGET_REGISTER_MOVE_COST
204 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
206 #undef TARGET_PREFERRED_RELOAD_CLASS
207 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
209 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
210 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
213 #define TARGET_LRA_P hook_bool_void_false
215 #undef TARGET_LEGITIMATE_ADDRESS_P
216 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p
218 #undef TARGET_CONDITIONAL_REGISTER_USAGE
219 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage
221 #undef TARGET_ASM_FUNCTION_SECTION
222 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section
224 #undef TARGET_PRINT_OPERAND
225 #define TARGET_PRINT_OPERAND pdp11_asm_print_operand
227 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
228 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p
230 #undef TARGET_LEGITIMATE_CONSTANT_P
231 #define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p
233 #undef TARGET_SCALAR_MODE_SUPPORTED_P
234 #define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p
236 /* A helper function to determine if REGNO should be saved in the
237 current function's stack frame. */
240 pdp11_saved_regno (unsigned regno
)
242 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
245 /* Expand the function prologue. */
248 pdp11_expand_prologue (void)
250 HOST_WIDE_INT fsize
= get_frame_size ();
252 rtx x
, via_ac
= NULL
;
254 /* If we are outputting code for main, the switch FPU to the
255 right mode if TARGET_FPU. */
256 if (MAIN_NAME_P (DECL_NAME (current_function_decl
)) && TARGET_FPU
)
258 emit_insn (gen_setd ());
259 emit_insn (gen_seti ());
262 if (frame_pointer_needed
)
264 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
265 x
= gen_frame_mem (Pmode
, x
);
266 emit_move_insn (x
, hard_frame_pointer_rtx
);
268 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
274 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
277 /* Prevent frame references via the frame pointer from being
278 scheduled before the frame is allocated. */
279 if (frame_pointer_needed
)
280 emit_insn (gen_blockage ());
283 /* Save CPU registers. */
284 for (regno
= R0_REGNUM
; regno
<= PC_REGNUM
; regno
++)
285 if (pdp11_saved_regno (regno
)
286 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
288 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
289 x
= gen_frame_mem (Pmode
, x
);
290 emit_move_insn (x
, gen_rtx_REG (Pmode
, regno
));
293 /* Save FPU registers. */
294 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
295 if (pdp11_saved_regno (regno
))
297 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
298 x
= gen_frame_mem (DFmode
, x
);
299 via_ac
= gen_rtx_REG (DFmode
, regno
);
300 emit_move_insn (x
, via_ac
);
303 /* ??? Maybe make ac4, ac5 call used regs?? */
304 for (regno
= AC4_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
305 if (pdp11_saved_regno (regno
))
307 gcc_assert (via_ac
!= NULL
);
308 emit_move_insn (via_ac
, gen_rtx_REG (DFmode
, regno
));
310 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
311 x
= gen_frame_mem (DFmode
, x
);
312 emit_move_insn (x
, via_ac
);
316 /* The function epilogue should not depend on the current stack pointer!
317 It should use the frame pointer only. This is mandatory because
318 of alloca; we also take advantage of it to omit stack adjustments
321 /* Maybe we can make leaf functions faster by switching to the
322 second register file - this way we don't have to save regs!
323 leaf functions are ~ 50% of all functions (dynamically!)
325 set/clear bit 11 (dec. 2048) of status word for switching register files -
326 but how can we do this? the pdp11/45 manual says bit may only
327 be set (p.24), but not cleared!
329 switching to kernel is probably more expensive, so we'll leave it
330 like this and not use the second set of registers...
332 maybe as option if you want to generate code for kernel mode? */
335 pdp11_expand_epilogue (void)
337 HOST_WIDE_INT fsize
= get_frame_size ();
339 rtx x
, reg
, via_ac
= NULL
;
341 if (pdp11_saved_regno (AC4_REGNUM
) || pdp11_saved_regno (AC5_REGNUM
))
343 /* Find a temporary with which to restore AC4/5. */
344 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
345 if (pdp11_saved_regno (regno
))
347 via_ac
= gen_rtx_REG (DFmode
, regno
);
352 /* If possible, restore registers via pops. */
353 if (!frame_pointer_needed
|| crtl
->sp_is_unchanging
)
355 /* Restore registers via pops. */
357 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
358 if (pdp11_saved_regno (regno
))
360 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
361 x
= gen_frame_mem (DFmode
, x
);
362 reg
= gen_rtx_REG (DFmode
, regno
);
364 if (LOAD_FPU_REG_P (regno
))
365 emit_move_insn (reg
, x
);
368 emit_move_insn (via_ac
, x
);
369 emit_move_insn (reg
, via_ac
);
373 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
374 if (pdp11_saved_regno (regno
)
375 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
377 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
378 x
= gen_frame_mem (Pmode
, x
);
379 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
384 /* Restore registers via moves. */
385 /* ??? If more than a few registers need to be restored, it's smaller
386 to generate a pointer through which we can emit pops. Consider
387 that moves cost 2*NREG words and pops cost NREG+3 words. This
388 means that the crossover is NREG=3.
390 Possible registers to use are:
391 (1) The first call-saved general register. This register will
392 be restored with the last pop.
393 (2) R1, if it's not used as a return register.
394 (3) FP itself. This option may result in +4 words, since we
395 may need two add imm,rn instructions instead of just one.
396 This also has the downside that we're not representing
397 the unwind info in any way, so during the epilogue the
398 debugger may get lost. */
400 HOST_WIDE_INT ofs
= -pdp11_sp_frame_offset ();
402 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
403 if (pdp11_saved_regno (regno
))
405 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
406 x
= gen_frame_mem (DFmode
, x
);
407 reg
= gen_rtx_REG (DFmode
, regno
);
409 if (LOAD_FPU_REG_P (regno
))
410 emit_move_insn (reg
, x
);
413 emit_move_insn (via_ac
, x
);
414 emit_move_insn (reg
, via_ac
);
419 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
420 if (pdp11_saved_regno (regno
)
421 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
423 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
424 x
= gen_frame_mem (Pmode
, x
);
425 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
430 /* Deallocate the stack frame. */
433 /* Prevent frame references via any pointer from being
434 scheduled after the frame is deallocated. */
435 emit_insn (gen_blockage ());
437 if (frame_pointer_needed
)
439 /* We can deallocate the frame with a single move. */
440 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
443 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
447 if (frame_pointer_needed
)
449 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
450 x
= gen_frame_mem (Pmode
, x
);
451 emit_move_insn (hard_frame_pointer_rtx
, x
);
454 emit_jump_insn (gen_return ());
457 /* Return the best assembler insn template
458 for moving operands[1] into operands[0] as a fullword. */
460 singlemove_string (rtx
*operands
)
462 if (operands
[1] != const0_rtx
)
469 /* Expand multi-word operands (SImode or DImode) into the 2 or 4
470 corresponding HImode operands. The number of operands is given
471 as the third argument, and the required order of the parts as
472 the fourth argument. */
474 pdp11_expand_operands (rtx
*operands
, rtx exops
[][2], int opcount
,
475 pdp11_action
*action
, pdp11_partorder order
)
477 int words
, op
, w
, i
, sh
;
478 pdp11_partorder useorder
;
479 bool sameoff
= false;
480 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype
;
483 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
485 /* If either piece order is accepted and one is pre-decrement
486 while the other is post-increment, set order to be high order
487 word first. That will force the pre-decrement to be turned
488 into a pointer adjust, then offset addressing.
489 Otherwise, if either operand uses pre-decrement, that means
490 the order is low order first.
491 Otherwise, if both operands are registers and destination is
492 higher than source and they overlap, do low order word (highest
493 register number) first. */
497 if (!REG_P (operands
[0]) && !REG_P (operands
[1]) &&
498 !(CONSTANT_P (operands
[1]) ||
499 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
500 ((GET_CODE (XEXP (operands
[0], 0)) == POST_INC
&&
501 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
) ||
502 (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
&&
503 GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)))
505 else if ((!REG_P (operands
[0]) &&
506 GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
) ||
507 (!REG_P (operands
[1]) &&
508 !(CONSTANT_P (operands
[1]) ||
509 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
510 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
))
512 else if (REG_P (operands
[0]) && REG_P (operands
[1]) &&
513 REGNO (operands
[0]) > REGNO (operands
[1]) &&
514 REGNO (operands
[0]) < REGNO (operands
[1]) + words
)
517 /* Check for source == offset from register and dest == push of
518 the same register. In that case, we have to use the same
519 offset (the one for the low order word) for all words, because
520 the push increases the offset to each source word.
521 In theory there are other cases like this, for example dest == pop,
522 but those don't occur in real life so ignore those. */
523 if (GET_CODE (operands
[0]) == MEM
524 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
525 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
526 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
530 /* If the caller didn't specify order, use the one we computed,
531 or high word first if we don't care either. If the caller did
532 specify, verify we don't have a problem with that order.
533 (If it matters to the caller, constraints need to be used to
534 ensure this case doesn't occur). */
536 order
= (useorder
== either
) ? big
: useorder
;
538 gcc_assert (useorder
== either
|| useorder
== order
);
541 for (op
= 0; op
< opcount
; op
++)
543 /* First classify the operand. */
544 if (REG_P (operands
[op
]))
546 else if (CONSTANT_P (operands
[op
])
547 || GET_CODE (operands
[op
]) == CONST_DOUBLE
)
549 else if (GET_CODE (XEXP (operands
[op
], 0)) == POST_INC
)
551 else if (GET_CODE (XEXP (operands
[op
], 0)) == PRE_DEC
)
553 else if (!reload_in_progress
|| offsettable_memref_p (operands
[op
]))
555 else if (GET_CODE (operands
[op
]) == MEM
)
560 /* Check for the cases that the operand constraints are not
561 supposed to allow to happen. Return failure for such cases. */
566 action
[op
] = no_action
;
568 /* If the operand uses pre-decrement addressing but we
569 want to get the parts high order first,
570 decrement the former register explicitly
571 and change the operand into ordinary indexing. */
572 if (optype
== PUSHOP
&& order
== big
)
574 gcc_assert (action
!= NULL
);
575 action
[op
] = dec_before
;
576 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
577 XEXP (XEXP (operands
[op
], 0), 0));
580 /* If the operand uses post-increment mode but we want
581 to get the parts low order first, change the operand
582 into ordinary indexing and remember to increment
583 the register explicitly when we're done. */
584 else if (optype
== POPOP
&& order
== little
)
586 gcc_assert (action
!= NULL
);
587 action
[op
] = inc_after
;
588 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
589 XEXP (XEXP (operands
[op
], 0), 0));
593 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
594 REAL_VALUE_TO_TARGET_DOUBLE
595 (*CONST_DOUBLE_REAL_VALUE (operands
[op
]), sval
);
597 for (i
= 0; i
< words
; i
++)
606 /* Set the output operand to be word "w" of the input. */
608 exops
[i
][op
] = gen_rtx_REG (HImode
, REGNO (operands
[op
]) + w
);
609 else if (optype
== OFFSOP
)
610 exops
[i
][op
] = adjust_address (operands
[op
], HImode
, w
* 2);
611 else if (optype
== CNSTOP
)
613 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
615 sh
= 16 - (w
& 1) * 16;
616 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, (sval
[w
/ 2] >> sh
) & 0xffff);
620 sh
= ((words
- 1 - w
) * 16);
621 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, trunc_int_for_mode (INTVAL(operands
[op
]) >> sh
, HImode
));
625 exops
[i
][op
] = operands
[op
];
631 /* Output assembler code to perform a multiple-word move insn
632 with operands OPERANDS. This moves 2 or 4 words depending
633 on the machine mode of the operands. */
636 output_move_multiple (rtx
*operands
)
639 pdp11_action action
[2];
642 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
644 pdp11_expand_operands (operands
, exops
, 2, action
, either
);
646 /* Check for explicit decrement before. */
647 if (action
[0] == dec_before
)
649 operands
[0] = XEXP (operands
[0], 0);
650 output_asm_insn ("sub $4,%0", operands
);
652 if (action
[1] == dec_before
)
654 operands
[1] = XEXP (operands
[1], 0);
655 output_asm_insn ("sub $4,%1", operands
);
659 for (i
= 0; i
< words
; i
++)
660 output_asm_insn (singlemove_string (exops
[i
]), exops
[i
]);
662 /* Check for increment after. */
663 if (action
[0] == inc_after
)
665 operands
[0] = XEXP (operands
[0], 0);
666 output_asm_insn ("add $4,%0", operands
);
668 if (action
[1] == inc_after
)
670 operands
[1] = XEXP (operands
[1], 0);
671 output_asm_insn ("add $4,%1", operands
);
677 /* Output an ascii string. */
679 output_ascii (FILE *file
, const char *p
, int size
)
683 /* This used to output .byte "string", which doesn't work with the UNIX
684 assembler and I think not with DEC ones either. */
685 fprintf (file
, "\t.byte ");
687 for (i
= 0; i
< size
; i
++)
689 register int c
= p
[i
];
692 fprintf (file
, "%#o", c
);
701 pdp11_asm_output_var (FILE *file
, const char *name
, int size
,
702 int align
, bool global
)
705 fprintf (file
, "\n\t.even\n");
708 fprintf (file
, ".globl ");
709 assemble_name (file
, name
);
711 fprintf (file
, "\n");
712 assemble_name (file
, name
);
713 fprintf (file
, ": .=.+ %#ho\n", (unsigned short)size
);
717 pdp11_asm_print_operand (FILE *file
, rtx x
, int code
)
723 else if (code
== '@')
730 else if (GET_CODE (x
) == REG
)
731 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
732 else if (GET_CODE (x
) == MEM
)
733 output_address (GET_MODE (x
), XEXP (x
, 0));
734 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != SImode
)
736 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), sval
);
737 fprintf (file
, "$%#lo", sval
[0] >> 16);
742 output_addr_const_pdp11 (file
, x
);
747 pdp11_asm_print_operand_punct_valid_p (unsigned char c
)
749 return (c
== '#' || c
== '@');
753 print_operand_address (FILE *file
, register rtx addr
)
761 switch (GET_CODE (addr
))
768 addr
= XEXP (addr
, 0);
773 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
778 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
783 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
789 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
790 || GET_CODE (XEXP (addr
, 0)) == MEM
)
792 offset
= XEXP (addr
, 0);
793 addr
= XEXP (addr
, 1);
795 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
796 || GET_CODE (XEXP (addr
, 1)) == MEM
)
798 offset
= XEXP (addr
, 1);
799 addr
= XEXP (addr
, 0);
801 if (GET_CODE (addr
) != PLUS
)
803 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
805 breg
= XEXP (addr
, 0);
806 addr
= XEXP (addr
, 1);
808 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
810 breg
= XEXP (addr
, 1);
811 addr
= XEXP (addr
, 0);
813 if (GET_CODE (addr
) == REG
)
815 gcc_assert (breg
== 0);
821 gcc_assert (addr
== 0);
825 output_addr_const_pdp11 (file
, addr
);
828 gcc_assert (GET_CODE (breg
) == REG
);
829 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
834 if (!again
&& GET_CODE (addr
) == CONST_INT
)
836 /* Absolute (integer number) address. */
837 if (!TARGET_UNIX_ASM
)
838 fprintf (file
, "@$");
840 output_addr_const_pdp11 (file
, addr
);
844 /* Target hook to assemble integer objects. We need to use the
845 pdp-specific version of output_addr_const. */
848 pdp11_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
854 fprintf (asm_out_file
, "\t.byte\t");
855 output_addr_const_pdp11 (asm_out_file
, GEN_INT (INTVAL (x
) & 0xff));
857 fprintf (asm_out_file
, " /* char */\n");
861 fprintf (asm_out_file
, TARGET_UNIX_ASM
? "\t" : "\t.word\t");
862 output_addr_const_pdp11 (asm_out_file
, x
);
863 fprintf (asm_out_file
, " /* short */\n");
866 return default_assemble_integer (x
, size
, aligned_p
);
870 /* register move costs, indexed by regs */
872 static const int move_costs
[N_REG_CLASSES
][N_REG_CLASSES
] =
874 /* NO MUL GEN LFPU NLFPU FPU ALL */
876 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
877 /* MUL */ { 0, 2, 2, 22, 22, 22, 22},
878 /* GEN */ { 0, 2, 2, 22, 22, 22, 22},
879 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22},
880 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22},
881 /* FPU */ { 0, 22, 22, 2, 10, 10, 22},
882 /* ALL */ { 0, 22, 22, 22, 22, 22, 22}
886 /* -- note that some moves are tremendously expensive,
887 because they require lots of tricks! do we have to
888 charge the costs incurred by secondary reload class
889 -- as we do here with 10 -- or not ? */
892 pdp11_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
893 reg_class_t c1
, reg_class_t c2
)
895 return move_costs
[(int)c1
][(int)c2
];
899 pdp11_rtx_costs (rtx x
, machine_mode mode
, int outer_code ATTRIBUTE_UNUSED
,
900 int opno ATTRIBUTE_UNUSED
, int *total
,
901 bool speed ATTRIBUTE_UNUSED
)
903 int code
= GET_CODE (x
);
908 if (INTVAL (x
) == 0 || INTVAL (x
) == -1 || INTVAL (x
) == 1)
918 /* Twice as expensive as REG. */
923 /* Twice (or 4 times) as expensive as 16 bit. */
928 /* ??? There is something wrong in MULT because MULT is not
929 as cheap as total = 2 even if we can shift! */
930 /* If optimizing for size make mult etc cheap, but not 1, so when
931 in doubt the faster insn is chosen. */
933 *total
= COSTS_N_INSNS (2);
935 *total
= COSTS_N_INSNS (11);
940 *total
= COSTS_N_INSNS (2);
942 *total
= COSTS_N_INSNS (25);
947 *total
= COSTS_N_INSNS (2);
949 *total
= COSTS_N_INSNS (26);
953 /* Equivalent to length, so same for optimize_size. */
954 *total
= COSTS_N_INSNS (3);
958 /* Only used for qi->hi. */
959 *total
= COSTS_N_INSNS (1);
964 *total
= COSTS_N_INSNS (1);
965 else if (mode
== SImode
)
966 *total
= COSTS_N_INSNS (6);
968 *total
= COSTS_N_INSNS (2);
975 *total
= COSTS_N_INSNS (1);
976 else if (mode
== QImode
)
978 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
979 *total
= COSTS_N_INSNS (8); /* worst case */
981 *total
= COSTS_N_INSNS (INTVAL (XEXP (x
, 1)));
983 else if (mode
== HImode
)
985 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
987 if (abs (INTVAL (XEXP (x
, 1))) == 1)
988 *total
= COSTS_N_INSNS (1);
990 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
993 *total
= COSTS_N_INSNS (10); /* worst case */
995 else if (mode
== SImode
)
997 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
998 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
999 else /* worst case */
1000 *total
= COSTS_N_INSNS (18);
1010 output_jump (enum rtx_code code
, int inv
, int length
)
1014 static char buf
[1000];
1015 const char *pos
, *neg
;
1017 if (cc_prev_status
.flags
& CC_NO_OVERFLOW
)
1021 case GTU
: code
= GT
; break;
1022 case LTU
: code
= LT
; break;
1023 case GEU
: code
= GE
; break;
1024 case LEU
: code
= LE
; break;
1030 case EQ
: pos
= "beq", neg
= "bne"; break;
1031 case NE
: pos
= "bne", neg
= "beq"; break;
1032 case GT
: pos
= "bgt", neg
= "ble"; break;
1033 case GTU
: pos
= "bhi", neg
= "blos"; break;
1034 case LT
: pos
= "blt", neg
= "bge"; break;
1035 case LTU
: pos
= "blo", neg
= "bhis"; break;
1036 case GE
: pos
= "bge", neg
= "blt"; break;
1037 case GEU
: pos
= "bhis", neg
= "blo"; break;
1038 case LE
: pos
= "ble", neg
= "bgt"; break;
1039 case LEU
: pos
= "blos", neg
= "bhi"; break;
1040 default: gcc_unreachable ();
1044 /* currently we don't need this, because the tstdf and cmpdf
1045 copy the condition code immediately, and other float operations are not
1046 yet recognized as changing the FCC - if so, then the length-cost of all
1047 jump insns increases by one, because we have to potentially copy the
1049 if (cc_status
.flags
& CC_IN_FPU
)
1050 output_asm_insn("cfcc", NULL
);
1057 sprintf(buf
, "%s %%l1", inv
? neg
: pos
);
1063 sprintf(buf
, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv
? pos
: neg
, x
, x
);
1077 notice_update_cc_on_set(rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
1079 if (GET_CODE (SET_DEST (exp
)) == CC0
)
1081 cc_status
.flags
= 0;
1082 cc_status
.value1
= SET_DEST (exp
);
1083 cc_status
.value2
= SET_SRC (exp
);
1085 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1089 else if (SET_DEST(exp
) == pc_rtx
)
1093 else if (GET_MODE (SET_DEST(exp
)) == HImode
1094 || GET_MODE (SET_DEST(exp
)) == QImode
)
1096 cc_status
.flags
= GET_CODE (SET_SRC(exp
)) == MINUS
? 0 : CC_NO_OVERFLOW
;
1097 cc_status
.value1
= SET_SRC (exp
);
1098 cc_status
.value2
= SET_DEST (exp
);
1100 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1102 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1103 cc_status
.value2
= 0;
1104 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
1106 && GET_CODE (cc_status
.value2
) == MEM
)
1107 cc_status
.value2
= 0;
1117 simple_memory_operand(rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1121 /* Eliminate non-memory operations */
1122 if (GET_CODE (op
) != MEM
)
1126 /* dword operations really put out 2 instructions, so eliminate them. */
1127 if (GET_MODE_SIZE (GET_MODE (op
)) > (HAVE_64BIT_P () ? 8 : 4))
1131 /* Decode the address now. */
1135 addr
= XEXP (op
, 0);
1137 switch (GET_CODE (addr
))
1140 /* (R0) - no extra cost */
1145 /* -(R0), (R0)+ - cheap! */
1149 /* cheap - is encoded in addressing mode info!
1151 -- except for @(R0), which has to be @0(R0) !!! */
1153 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1163 /* @#address - extra cost */
1167 /* X(R0) - extra cost */
1179 * output a block move:
1181 * operands[0] ... to
1182 * operands[1] ... from
1183 * operands[2] ... length
1184 * operands[3] ... alignment
1185 * operands[4] ... scratch register
1190 output_block_move(rtx
*operands
)
1192 static int count
= 0;
1197 /* Move of zero bytes is a NOP. */
1198 if (operands
[2] == const0_rtx
)
1201 /* Look for moves by small constant byte counts, those we'll
1202 expand to straight line code. */
1203 if (CONSTANT_P (operands
[2]))
1205 if (INTVAL (operands
[2]) < 16
1206 && (!optimize_size
|| INTVAL (operands
[2]) < 5)
1207 && INTVAL (operands
[3]) == 1)
1211 for (i
= 1; i
<= INTVAL (operands
[2]); i
++)
1212 output_asm_insn("movb (%1)+, (%0)+", operands
);
1216 else if (INTVAL(operands
[2]) < 32
1217 && (!optimize_size
|| INTVAL (operands
[2]) < 9)
1218 && INTVAL (operands
[3]) >= 2)
1222 for (i
= 1; i
<= INTVAL (operands
[2]) / 2; i
++)
1223 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1224 if (INTVAL (operands
[2]) & 1)
1225 output_asm_insn ("movb (%1), (%0)", operands
);
1231 /* Ideally we'd look for moves that are multiples of 4 or 8
1232 bytes and handle those by unrolling the move loop. That
1233 makes for a lot of code if done at run time, but it's ok
1234 for constant counts. Also, for variable counts we have
1235 to worry about odd byte count with even aligned pointers.
1236 On 11/40 and up we handle that case; on older machines
1237 we don't and just use byte-wise moves all the time. */
1239 if (CONSTANT_P (operands
[2]) )
1241 if (INTVAL (operands
[3]) < 2)
1245 lastbyte
= INTVAL (operands
[2]) & 1;
1247 if (optimize_size
|| INTVAL (operands
[2]) & 2)
1249 else if (INTVAL (operands
[2]) & 4)
1255 /* Loop count is byte count scaled by unroll. */
1256 operands
[2] = GEN_INT (INTVAL (operands
[2]) >> unroll
);
1257 output_asm_insn ("mov %2, %4", operands
);
1261 /* Variable byte count; use the input register
1263 operands
[4] = operands
[2];
1265 /* Decide whether to move by words, and check
1266 the byte count for zero. */
1267 if (TARGET_40_PLUS
&& INTVAL (operands
[3]) > 1)
1270 output_asm_insn ("asr %4", operands
);
1275 output_asm_insn ("tst %4", operands
);
1277 sprintf (buf
, "beq movestrhi%d", count
+ 1);
1278 output_asm_insn (buf
, NULL
);
1281 /* Output the loop label. */
1282 sprintf (buf
, "\nmovestrhi%d:", count
);
1283 output_asm_insn (buf
, NULL
);
1285 /* Output the appropriate move instructions. */
1289 output_asm_insn ("movb (%1)+, (%0)+", operands
);
1293 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1297 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1298 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1302 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1303 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1304 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1305 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1309 /* Output the decrement and test. */
1312 sprintf (buf
, "sob %%4, movestrhi%d", count
);
1313 output_asm_insn (buf
, operands
);
1317 output_asm_insn ("dec %4", operands
);
1318 sprintf (buf
, "bgt movestrhi%d", count
);
1319 output_asm_insn (buf
, NULL
);
1323 /* If constant odd byte count, move the last byte. */
1325 output_asm_insn ("movb (%1), (%0)", operands
);
1326 else if (!CONSTANT_P (operands
[2]))
1328 /* Output the destination label for the zero byte count check. */
1329 sprintf (buf
, "\nmovestrhi%d:", count
);
1330 output_asm_insn (buf
, NULL
);
1333 /* If we did word moves, check for trailing last byte. */
1336 sprintf (buf
, "bcc movestrhi%d", count
);
1337 output_asm_insn (buf
, NULL
);
1338 output_asm_insn ("movb (%1), (%0)", operands
);
1339 sprintf (buf
, "\nmovestrhi%d:", count
);
1340 output_asm_insn (buf
, NULL
);
1348 /* This function checks whether a real value can be encoded as
1349 a literal, i.e., addressing mode 27. In that mode, real values
1350 are one word values, so the remaining 48 bits have to be zero. */
1352 legitimate_const_double_p (rtx address
)
1355 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (address
), sval
);
1356 if ((sval
[0] & 0xffff) == 0 && sval
[1] == 0)
1361 /* Implement CANNOT_CHANGE_MODE_CLASS. */
1363 pdp11_cannot_change_mode_class (machine_mode from
,
1365 enum reg_class rclass
)
1367 /* Also, FPU registers contain a whole float value and the parts of
1368 it are not separately accessible.
1370 So we disallow all mode changes involving FPRs. */
1371 if (FLOAT_MODE_P (from
) != FLOAT_MODE_P (to
))
1374 return reg_classes_intersect_p (FPU_REGS
, rclass
);
1377 /* TARGET_PREFERRED_RELOAD_CLASS
1379 Given an rtx X being reloaded into a reg required to be
1380 in class CLASS, return the class of reg to actually use.
1381 In general this is just CLASS; but on some machines
1382 in some cases it is preferable to use a more restrictive class.
1384 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1387 pdp11_preferred_reload_class (rtx x
, reg_class_t rclass
)
1389 if (rclass
== FPU_REGS
)
1390 return LOAD_FPU_REGS
;
1391 if (rclass
== ALL_REGS
)
1393 if (FLOAT_MODE_P (GET_MODE (x
)))
1394 return LOAD_FPU_REGS
;
1396 return GENERAL_REGS
;
1401 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
1403 Given an rtx X being reloaded into a reg required to be
1404 in class CLASS, return the class of reg to actually use.
1405 In general this is just CLASS; but on some machines
1406 in some cases it is preferable to use a more restrictive class.
1408 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1411 pdp11_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
1413 if (rclass
== FPU_REGS
)
1414 return LOAD_FPU_REGS
;
1415 if (rclass
== ALL_REGS
)
1417 if (FLOAT_MODE_P (GET_MODE (x
)))
1418 return LOAD_FPU_REGS
;
1420 return GENERAL_REGS
;
1426 /* TARGET_SECONDARY_RELOAD.
1428 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
1429 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
1430 can be loade/stored directly. */
1432 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED
,
1434 reg_class_t reload_class
,
1435 machine_mode reload_mode ATTRIBUTE_UNUSED
,
1436 secondary_reload_info
*sri ATTRIBUTE_UNUSED
)
1438 if (reload_class
!= NO_LOAD_FPU_REGS
|| GET_CODE (x
) != REG
||
1439 REGNO_REG_CLASS (REGNO (x
)) == LOAD_FPU_REGS
)
1442 return LOAD_FPU_REGS
;
1445 /* Target routine to check if register to register move requires memory.
1447 The answer is yes if we're going between general register and FPU
1448 registers. The mode doesn't matter in making this check.
1451 pdp11_secondary_memory_needed (reg_class_t c1
, reg_class_t c2
,
1452 machine_mode mode ATTRIBUTE_UNUSED
)
1454 int fromfloat
= (c1
== LOAD_FPU_REGS
|| c1
== NO_LOAD_FPU_REGS
||
1456 int tofloat
= (c2
== LOAD_FPU_REGS
|| c2
== NO_LOAD_FPU_REGS
||
1459 return (fromfloat
!= tofloat
);
1462 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1463 that is a valid memory address for an instruction.
1464 The MODE argument is the machine mode for the MEM expression
1465 that wants to use this address.
1470 pdp11_legitimate_address_p (machine_mode mode
,
1471 rtx operand
, bool strict
)
1475 /* accept @#address */
1476 if (CONSTANT_ADDRESS_P (operand
))
1479 switch (GET_CODE (operand
))
1483 return !strict
|| REGNO_OK_FOR_BASE_P (REGNO (operand
));
1487 return GET_CODE (XEXP (operand
, 0)) == REG
1488 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))))
1489 && CONSTANT_ADDRESS_P (XEXP (operand
, 1));
1493 return GET_CODE (XEXP (operand
, 0)) == REG
1494 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1498 return GET_CODE (XEXP (operand
, 0)) == REG
1499 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1502 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */
1503 return GET_CODE (XEXP (operand
, 0)) == REG
1504 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1505 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1506 && GET_CODE (XEXP (xfoob
, 0)) == REG
1507 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1508 && CONSTANT_P (XEXP (xfoob
, 1))
1509 && INTVAL (XEXP (xfoob
,1)) == -2;
1512 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */
1513 return GET_CODE (XEXP (operand
, 0)) == REG
1514 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1515 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1516 && GET_CODE (XEXP (xfoob
, 0)) == REG
1517 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1518 && CONSTANT_P (XEXP (xfoob
, 1))
1519 && INTVAL (XEXP (xfoob
,1)) == 2;
1522 /* handle another level of indirection ! */
1523 xfoob
= XEXP (operand
, 0);
1525 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently
1526 also forbidden for float, because we have to handle this
1527 in output_move_double and/or output_move_quad() - we could
1528 do it, but currently it's not worth it!!!
1529 now that DFmode cannot go into CPU register file,
1530 maybe I should allow float ...
1531 but then I have to handle memory-to-memory moves in movdf ?? */
1532 if (GET_MODE_BITSIZE(mode
) > 16)
1535 /* accept @address */
1536 if (CONSTANT_ADDRESS_P (xfoob
))
1539 switch (GET_CODE (xfoob
))
1542 /* accept @(R0) - which is @0(R0) */
1543 return !strict
|| REGNO_OK_FOR_BASE_P(REGNO (xfoob
));
1547 return GET_CODE (XEXP (xfoob
, 0)) == REG
1548 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))))
1549 && CONSTANT_ADDRESS_P (XEXP (xfoob
, 1));
1553 return GET_CODE (XEXP (xfoob
, 0)) == REG
1554 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1558 return GET_CODE (XEXP (xfoob
, 0)) == REG
1559 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1562 /* anything else is invalid */
1567 /* anything else is invalid */
1572 /* Return the class number of the smallest class containing
1573 reg number REGNO. */
1575 pdp11_regno_reg_class (int regno
)
1577 if (regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1578 return GENERAL_REGS
;
1579 else if (regno
> AC3_REGNUM
)
1580 return NO_LOAD_FPU_REGS
;
1581 else if (regno
>= AC0_REGNUM
)
1582 return LOAD_FPU_REGS
;
1586 return GENERAL_REGS
;
1591 pdp11_sp_frame_offset (void)
1593 int offset
= 0, regno
;
1594 offset
= get_frame_size();
1595 for (regno
= 0; regno
<= PC_REGNUM
; regno
++)
1596 if (pdp11_saved_regno (regno
))
1598 for (regno
= AC0_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
1599 if (pdp11_saved_regno (regno
))
1605 /* Return the offset between two registers, one to be eliminated, and the other
1606 its replacement, at the start of a routine. */
1609 pdp11_initial_elimination_offset (int from
, int to
)
1613 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1615 else if (from
== FRAME_POINTER_REGNUM
1616 && to
== HARD_FRAME_POINTER_REGNUM
)
1620 gcc_assert (to
== STACK_POINTER_REGNUM
);
1622 /* Get the size of the register save area. */
1623 spoff
= pdp11_sp_frame_offset ();
1624 if (from
== FRAME_POINTER_REGNUM
)
1627 gcc_assert (from
== ARG_POINTER_REGNUM
);
1629 /* If there is a frame pointer, that is saved too. */
1630 if (frame_pointer_needed
)
1633 /* Account for the saved PC in the function call. */
1638 /* A copy of output_addr_const modified for pdp11 expression syntax.
1639 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1640 use, and for debugging output, which we don't support with this port either.
1641 So this copy should get called whenever needed.
1644 output_addr_const_pdp11 (FILE *file
, rtx x
)
1650 switch (GET_CODE (x
))
1653 gcc_assert (flag_pic
);
1658 assemble_name (file
, XSTR (x
, 0));
1662 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
1663 assemble_name (file
, buf
);
1667 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
1668 assemble_name (file
, buf
);
1676 fprintf (file
, "-");
1678 fprintf (file
, "%#o", i
& 0xffff);
1682 /* This used to output parentheses around the expression,
1683 but that does not work on the 386 (either ATT or BSD assembler). */
1684 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1688 if (GET_MODE (x
) == VOIDmode
)
1690 /* We can use %o if the number is one word and positive. */
1691 gcc_assert (!CONST_DOUBLE_HIGH (x
));
1692 fprintf (file
, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x
));
1695 /* We can't handle floating point constants;
1696 PRINT_OPERAND must handle them. */
1697 output_operand_lossage ("floating constant misused");
1701 /* Some assemblers need integer constants to appear last (e.g. masm). */
1702 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
1704 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1705 if (INTVAL (XEXP (x
, 0)) >= 0)
1706 fprintf (file
, "+");
1707 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1711 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1712 if (INTVAL (XEXP (x
, 1)) >= 0)
1713 fprintf (file
, "+");
1714 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1719 /* Avoid outputting things like x-x or x+5-x,
1720 since some assemblers can't handle that. */
1721 x
= simplify_subtraction (x
);
1722 if (GET_CODE (x
) != MINUS
)
1725 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1726 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
1727 || INTVAL (XEXP (x
, 1)) >= 0)
1728 fprintf (file
, "-");
1729 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1734 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1738 output_operand_lossage ("invalid expression as operand");
1742 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1745 pdp11_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1747 /* Integers 32 bits and under, and scalar floats (if FPU), are returned
1748 in registers. The rest go into memory. */
1749 return (TYPE_MODE (type
) == DImode
1750 || (FLOAT_MODE_P (TYPE_MODE (type
)) && ! TARGET_AC0
)
1751 || TREE_CODE (type
) == VECTOR_TYPE
1752 || COMPLEX_MODE_P (TYPE_MODE (type
)));
1755 /* Worker function for TARGET_FUNCTION_VALUE.
1757 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */
1760 pdp11_function_value (const_tree valtype
,
1761 const_tree fntype_or_decl ATTRIBUTE_UNUSED
,
1762 bool outgoing ATTRIBUTE_UNUSED
)
1764 return gen_rtx_REG (TYPE_MODE (valtype
),
1765 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype
)));
1768 /* Worker function for TARGET_LIBCALL_VALUE. */
1771 pdp11_libcall_value (machine_mode mode
,
1772 const_rtx fun ATTRIBUTE_UNUSED
)
1774 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG(mode
));
1777 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1779 On the pdp, the first "output" reg is the only register thus used.
1781 maybe ac0 ? - as option someday! */
1784 pdp11_function_value_regno_p (const unsigned int regno
)
1786 return (regno
== RETVAL_REGNUM
) || (TARGET_AC0
&& (regno
== AC0_REGNUM
));
1789 /* Worker function for TARGET_TRAMPOLINE_INIT.
1791 trampoline - how should i do it in separate i+d ?
1792 have some allocate_trampoline magic???
1794 the following should work for shared I/D:
1796 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
1797 JMP @#FUNCTION 000137 0x0000 <- FUNCTION
1801 pdp11_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
1803 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
1806 gcc_assert (!TARGET_SPLIT
);
1808 mem
= adjust_address (m_tramp
, HImode
, 0);
1809 emit_move_insn (mem
, GEN_INT (012700+STATIC_CHAIN_REGNUM
));
1810 mem
= adjust_address (m_tramp
, HImode
, 2);
1811 emit_move_insn (mem
, chain_value
);
1812 mem
= adjust_address (m_tramp
, HImode
, 4);
1813 emit_move_insn (mem
, GEN_INT (000137));
1814 emit_move_insn (mem
, fnaddr
);
1817 /* Worker function for TARGET_FUNCTION_ARG.
1819 Determine where to put an argument to a function.
1820 Value is zero to push the argument on the stack,
1821 or a hard register in which to store the argument.
1823 MODE is the argument's machine mode.
1824 TYPE is the data type of the argument (as a tree).
1825 This is null for libcalls where that information may
1827 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1828 the preceding args and about the function being called.
1829 NAMED is nonzero if this argument is a named parameter
1830 (otherwise it is an extra parameter matching an ellipsis). */
1833 pdp11_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1834 machine_mode mode ATTRIBUTE_UNUSED
,
1835 const_tree type ATTRIBUTE_UNUSED
,
1836 bool named ATTRIBUTE_UNUSED
)
1841 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE.
1843 Update the data in CUM to advance over an argument of mode MODE and
1844 data type TYPE. (TYPE is null for libcalls where that information
1845 may not be available.) */
1848 pdp11_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1849 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1851 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1853 *cum
+= (mode
!= BLKmode
1854 ? GET_MODE_SIZE (mode
)
1855 : int_size_in_bytes (type
));
1858 /* Make sure everything's fine if we *don't* have an FPU.
1859 This assumes that putting a register in fixed_regs will keep the
1860 compiler's mitts completely off it. We don't bother to zero it out
1861 of register classes. Also fix incompatible register naming with
1862 the UNIX assembler. */
1865 pdp11_conditional_register_usage (void)
1871 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FPU_REGS
]);
1872 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++ )
1873 if (TEST_HARD_REG_BIT (x
, i
))
1874 fixed_regs
[i
] = call_used_regs
[i
] = 1;
1878 call_used_regs
[AC0_REGNUM
] = 1;
1879 if (TARGET_UNIX_ASM
)
1881 /* Change names of FPU registers for the UNIX assembler. */
1882 reg_names
[8] = "fr0";
1883 reg_names
[9] = "fr1";
1884 reg_names
[10] = "fr2";
1885 reg_names
[11] = "fr3";
1886 reg_names
[12] = "fr4";
1887 reg_names
[13] = "fr5";
1892 pdp11_function_section (tree decl ATTRIBUTE_UNUSED
,
1893 enum node_frequency freq ATTRIBUTE_UNUSED
,
1894 bool startup ATTRIBUTE_UNUSED
,
1895 bool exit ATTRIBUTE_UNUSED
)
1900 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1903 pdp11_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1905 return GET_CODE (x
) != CONST_DOUBLE
|| legitimate_const_double_p (x
);
1908 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
1911 pdp11_scalar_mode_supported_p (machine_mode mode
)
1913 /* Support SFmode even with -mfloat64. */
1916 return default_scalar_mode_supported_p (mode
);
1920 pdp11_branch_cost ()
1922 return (TARGET_BRANCH_CHEAP
? 0 : 1);
1925 struct gcc_target targetm
= TARGET_INITIALIZER
;