1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994-2014 Free Software Foundation, Inc.
3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
32 #include "insn-attr.h"
36 #include "stor-layout.h"
40 #include "diagnostic-core.h"
43 #include "target-def.h"
49 /* this is the current value returned by the macro FIRST_PARM_OFFSET
51 int current_first_parm_offset
;
53 /* Routines to encode/decode pdp11 floats */
54 static void encode_pdp11_f (const struct real_format
*fmt
,
55 long *, const REAL_VALUE_TYPE
*);
56 static void decode_pdp11_f (const struct real_format
*,
57 REAL_VALUE_TYPE
*, const long *);
58 static void encode_pdp11_d (const struct real_format
*fmt
,
59 long *, const REAL_VALUE_TYPE
*);
60 static void decode_pdp11_d (const struct real_format
*,
61 REAL_VALUE_TYPE
*, const long *);
63 /* These two are taken from the corresponding vax descriptors
64 in real.c, changing only the encode/decode routine pointers. */
65 const struct real_format pdp11_f_format
=
86 const struct real_format pdp11_d_format
=
108 encode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
109 const REAL_VALUE_TYPE
*r
)
111 (*vax_f_format
.encode
) (fmt
, buf
, r
);
112 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
116 decode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
117 REAL_VALUE_TYPE
*r
, const long *buf
)
120 tbuf
= ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
121 (*vax_f_format
.decode
) (fmt
, r
, &tbuf
);
125 encode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
126 const REAL_VALUE_TYPE
*r
)
128 (*vax_d_format
.encode
) (fmt
, buf
, r
);
129 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
130 buf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
134 decode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
135 REAL_VALUE_TYPE
*r
, const long *buf
)
138 tbuf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
139 tbuf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
140 (*vax_d_format
.decode
) (fmt
, r
, tbuf
);
143 /* This is where the condition code register lives. */
144 /* rtx cc0_reg_rtx; - no longer needed? */
146 static const char *singlemove_string (rtx
*);
147 static bool pdp11_assemble_integer (rtx
, unsigned int, int);
148 static bool pdp11_rtx_costs (rtx
, int, int, int, int *, bool);
149 static bool pdp11_return_in_memory (const_tree
, const_tree
);
150 static rtx
pdp11_function_value (const_tree
, const_tree
, bool);
151 static rtx
pdp11_libcall_value (enum machine_mode
, const_rtx
);
152 static bool pdp11_function_value_regno_p (const unsigned int);
153 static void pdp11_trampoline_init (rtx
, tree
, rtx
);
154 static rtx
pdp11_function_arg (cumulative_args_t
, enum machine_mode
,
156 static void pdp11_function_arg_advance (cumulative_args_t
,
157 enum machine_mode
, const_tree
, bool);
158 static void pdp11_conditional_register_usage (void);
159 static bool pdp11_legitimate_constant_p (enum machine_mode
, rtx
);
161 static bool pdp11_scalar_mode_supported_p (enum machine_mode
);
163 /* Initialize the GCC target structure. */
164 #undef TARGET_ASM_BYTE_OP
165 #define TARGET_ASM_BYTE_OP NULL
166 #undef TARGET_ASM_ALIGNED_HI_OP
167 #define TARGET_ASM_ALIGNED_HI_OP NULL
168 #undef TARGET_ASM_ALIGNED_SI_OP
169 #define TARGET_ASM_ALIGNED_SI_OP NULL
170 #undef TARGET_ASM_INTEGER
171 #define TARGET_ASM_INTEGER pdp11_assemble_integer
173 #undef TARGET_ASM_OPEN_PAREN
174 #define TARGET_ASM_OPEN_PAREN "["
175 #undef TARGET_ASM_CLOSE_PAREN
176 #define TARGET_ASM_CLOSE_PAREN "]"
178 #undef TARGET_RTX_COSTS
179 #define TARGET_RTX_COSTS pdp11_rtx_costs
181 #undef TARGET_FUNCTION_ARG
182 #define TARGET_FUNCTION_ARG pdp11_function_arg
183 #undef TARGET_FUNCTION_ARG_ADVANCE
184 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance
186 #undef TARGET_RETURN_IN_MEMORY
187 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
189 #undef TARGET_FUNCTION_VALUE
190 #define TARGET_FUNCTION_VALUE pdp11_function_value
191 #undef TARGET_LIBCALL_VALUE
192 #define TARGET_LIBCALL_VALUE pdp11_libcall_value
193 #undef TARGET_FUNCTION_VALUE_REGNO_P
194 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p
196 #undef TARGET_TRAMPOLINE_INIT
197 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
199 #undef TARGET_SECONDARY_RELOAD
200 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
202 #undef TARGET_REGISTER_MOVE_COST
203 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
205 #undef TARGET_PREFERRED_RELOAD_CLASS
206 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
208 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
209 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
211 #undef TARGET_LEGITIMATE_ADDRESS_P
212 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p
214 #undef TARGET_CONDITIONAL_REGISTER_USAGE
215 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage
217 #undef TARGET_ASM_FUNCTION_SECTION
218 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section
220 #undef TARGET_PRINT_OPERAND
221 #define TARGET_PRINT_OPERAND pdp11_asm_print_operand
223 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
224 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p
226 #undef TARGET_LEGITIMATE_CONSTANT_P
227 #define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p
229 #undef TARGET_SCALAR_MODE_SUPPORTED_P
230 #define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p
232 /* A helper function to determine if REGNO should be saved in the
233 current function's stack frame. */
236 pdp11_saved_regno (unsigned regno
)
238 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
241 /* Expand the function prologue. */
244 pdp11_expand_prologue (void)
246 HOST_WIDE_INT fsize
= get_frame_size ();
248 rtx x
, via_ac
= NULL
;
250 /* If we are outputting code for main, the switch FPU to the
251 right mode if TARGET_FPU. */
252 if (MAIN_NAME_P (DECL_NAME (current_function_decl
)) && TARGET_FPU
)
254 emit_insn (gen_setd ());
255 emit_insn (gen_seti ());
258 if (frame_pointer_needed
)
260 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
261 x
= gen_frame_mem (Pmode
, x
);
262 emit_move_insn (x
, hard_frame_pointer_rtx
);
264 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
270 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
273 /* Prevent frame references via the frame pointer from being
274 scheduled before the frame is allocated. */
275 if (frame_pointer_needed
)
276 emit_insn (gen_blockage ());
279 /* Save CPU registers. */
280 for (regno
= R0_REGNUM
; regno
<= PC_REGNUM
; regno
++)
281 if (pdp11_saved_regno (regno
)
282 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
284 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
285 x
= gen_frame_mem (Pmode
, x
);
286 emit_move_insn (x
, gen_rtx_REG (Pmode
, regno
));
289 /* Save FPU registers. */
290 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
291 if (pdp11_saved_regno (regno
))
293 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
294 x
= gen_frame_mem (DFmode
, x
);
295 via_ac
= gen_rtx_REG (DFmode
, regno
);
296 emit_move_insn (x
, via_ac
);
299 /* ??? Maybe make ac4, ac5 call used regs?? */
300 for (regno
= AC4_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
301 if (pdp11_saved_regno (regno
))
303 gcc_assert (via_ac
!= NULL
);
304 emit_move_insn (via_ac
, gen_rtx_REG (DFmode
, regno
));
306 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
307 x
= gen_frame_mem (DFmode
, x
);
308 emit_move_insn (x
, via_ac
);
312 /* The function epilogue should not depend on the current stack pointer!
313 It should use the frame pointer only. This is mandatory because
314 of alloca; we also take advantage of it to omit stack adjustments
317 /* Maybe we can make leaf functions faster by switching to the
318 second register file - this way we don't have to save regs!
319 leaf functions are ~ 50% of all functions (dynamically!)
321 set/clear bit 11 (dec. 2048) of status word for switching register files -
322 but how can we do this? the pdp11/45 manual says bit may only
323 be set (p.24), but not cleared!
325 switching to kernel is probably more expensive, so we'll leave it
326 like this and not use the second set of registers...
328 maybe as option if you want to generate code for kernel mode? */
331 pdp11_expand_epilogue (void)
333 HOST_WIDE_INT fsize
= get_frame_size ();
335 rtx x
, reg
, via_ac
= NULL
;
337 if (pdp11_saved_regno (AC4_REGNUM
) || pdp11_saved_regno (AC5_REGNUM
))
339 /* Find a temporary with which to restore AC4/5. */
340 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
341 if (pdp11_saved_regno (regno
))
343 via_ac
= gen_rtx_REG (DFmode
, regno
);
348 /* If possible, restore registers via pops. */
349 if (!frame_pointer_needed
|| crtl
->sp_is_unchanging
)
351 /* Restore registers via pops. */
353 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
354 if (pdp11_saved_regno (regno
))
356 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
357 x
= gen_frame_mem (DFmode
, x
);
358 reg
= gen_rtx_REG (DFmode
, regno
);
360 if (LOAD_FPU_REG_P (regno
))
361 emit_move_insn (reg
, x
);
364 emit_move_insn (via_ac
, x
);
365 emit_move_insn (reg
, via_ac
);
369 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
370 if (pdp11_saved_regno (regno
)
371 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
373 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
374 x
= gen_frame_mem (Pmode
, x
);
375 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
380 /* Restore registers via moves. */
381 /* ??? If more than a few registers need to be restored, it's smaller
382 to generate a pointer through which we can emit pops. Consider
383 that moves cost 2*NREG words and pops cost NREG+3 words. This
384 means that the crossover is NREG=3.
386 Possible registers to use are:
387 (1) The first call-saved general register. This register will
388 be restored with the last pop.
389 (2) R1, if it's not used as a return register.
390 (3) FP itself. This option may result in +4 words, since we
391 may need two add imm,rn instructions instead of just one.
392 This also has the downside that we're not representing
393 the unwind info in any way, so during the epilogue the
394 debugger may get lost. */
396 HOST_WIDE_INT ofs
= -pdp11_sp_frame_offset ();
398 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
399 if (pdp11_saved_regno (regno
))
401 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
402 x
= gen_frame_mem (DFmode
, x
);
403 reg
= gen_rtx_REG (DFmode
, regno
);
405 if (LOAD_FPU_REG_P (regno
))
406 emit_move_insn (reg
, x
);
409 emit_move_insn (via_ac
, x
);
410 emit_move_insn (reg
, via_ac
);
415 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
416 if (pdp11_saved_regno (regno
)
417 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
419 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
420 x
= gen_frame_mem (Pmode
, x
);
421 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
426 /* Deallocate the stack frame. */
429 /* Prevent frame references via any pointer from being
430 scheduled after the frame is deallocated. */
431 emit_insn (gen_blockage ());
433 if (frame_pointer_needed
)
435 /* We can deallocate the frame with a single move. */
436 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
439 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
443 if (frame_pointer_needed
)
445 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
446 x
= gen_frame_mem (Pmode
, x
);
447 emit_move_insn (hard_frame_pointer_rtx
, x
);
450 emit_jump_insn (gen_return ());
453 /* Return the best assembler insn template
454 for moving operands[1] into operands[0] as a fullword. */
456 singlemove_string (rtx
*operands
)
458 if (operands
[1] != const0_rtx
)
465 /* Expand multi-word operands (SImode or DImode) into the 2 or 4
466 corresponding HImode operands. The number of operands is given
467 as the third argument, and the required order of the parts as
468 the fourth argument. */
470 pdp11_expand_operands (rtx
*operands
, rtx exops
[][2], int opcount
,
471 pdp11_action
*action
, pdp11_partorder order
)
473 int words
, op
, w
, i
, sh
;
474 pdp11_partorder useorder
;
475 bool sameoff
= false;
476 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype
;
480 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
482 /* If either piece order is accepted and one is pre-decrement
483 while the other is post-increment, set order to be high order
484 word first. That will force the pre-decrement to be turned
485 into a pointer adjust, then offset addressing.
486 Otherwise, if either operand uses pre-decrement, that means
487 the order is low order first.
488 Otherwise, if both operands are registers and destination is
489 higher than source and they overlap, do low order word (highest
490 register number) first. */
494 if (!REG_P (operands
[0]) && !REG_P (operands
[1]) &&
495 !(CONSTANT_P (operands
[1]) ||
496 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
497 ((GET_CODE (XEXP (operands
[0], 0)) == POST_INC
&&
498 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
) ||
499 (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
&&
500 GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)))
502 else if ((!REG_P (operands
[0]) &&
503 GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
) ||
504 (!REG_P (operands
[1]) &&
505 !(CONSTANT_P (operands
[1]) ||
506 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
507 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
))
509 else if (REG_P (operands
[0]) && REG_P (operands
[1]) &&
510 REGNO (operands
[0]) > REGNO (operands
[1]) &&
511 REGNO (operands
[0]) < REGNO (operands
[1]) + words
)
514 /* Check for source == offset from register and dest == push of
515 the same register. In that case, we have to use the same
516 offset (the one for the low order word) for all words, because
517 the push increases the offset to each source word.
518 In theory there are other cases like this, for example dest == pop,
519 but those don't occur in real life so ignore those. */
520 if (GET_CODE (operands
[0]) == MEM
521 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
522 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
523 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
527 /* If the caller didn't specify order, use the one we computed,
528 or high word first if we don't care either. If the caller did
529 specify, verify we don't have a problem with that order.
530 (If it matters to the caller, constraints need to be used to
531 ensure this case doesn't occur). */
533 order
= (useorder
== either
) ? big
: useorder
;
535 gcc_assert (useorder
== either
|| useorder
== order
);
538 for (op
= 0; op
< opcount
; op
++)
540 /* First classify the operand. */
541 if (REG_P (operands
[op
]))
543 else if (CONSTANT_P (operands
[op
])
544 || GET_CODE (operands
[op
]) == CONST_DOUBLE
)
546 else if (GET_CODE (XEXP (operands
[op
], 0)) == POST_INC
)
548 else if (GET_CODE (XEXP (operands
[op
], 0)) == PRE_DEC
)
550 else if (!reload_in_progress
|| offsettable_memref_p (operands
[op
]))
552 else if (GET_CODE (operands
[op
]) == MEM
)
557 /* Check for the cases that the operand constraints are not
558 supposed to allow to happen. Return failure for such cases. */
563 action
[op
] = no_action
;
565 /* If the operand uses pre-decrement addressing but we
566 want to get the parts high order first,
567 decrement the former register explicitly
568 and change the operand into ordinary indexing. */
569 if (optype
== PUSHOP
&& order
== big
)
571 gcc_assert (action
!= NULL
);
572 action
[op
] = dec_before
;
573 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
574 XEXP (XEXP (operands
[op
], 0), 0));
577 /* If the operand uses post-increment mode but we want
578 to get the parts low order first, change the operand
579 into ordinary indexing and remember to increment
580 the register explicitly when we're done. */
581 else if (optype
== POPOP
&& order
== little
)
583 gcc_assert (action
!= NULL
);
584 action
[op
] = inc_after
;
585 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
586 XEXP (XEXP (operands
[op
], 0), 0));
590 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
592 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[op
]);
593 REAL_VALUE_TO_TARGET_DOUBLE (r
, sval
);
596 for (i
= 0; i
< words
; i
++)
605 /* Set the output operand to be word "w" of the input. */
607 exops
[i
][op
] = gen_rtx_REG (HImode
, REGNO (operands
[op
]) + w
);
608 else if (optype
== OFFSOP
)
609 exops
[i
][op
] = adjust_address (operands
[op
], HImode
, w
* 2);
610 else if (optype
== CNSTOP
)
612 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
614 sh
= 16 - (w
& 1) * 16;
615 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, (sval
[w
/ 2] >> sh
) & 0xffff);
619 sh
= ((words
- 1 - w
) * 16);
620 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, trunc_int_for_mode (INTVAL(operands
[op
]) >> sh
, HImode
));
624 exops
[i
][op
] = operands
[op
];
630 /* Output assembler code to perform a multiple-word move insn
631 with operands OPERANDS. This moves 2 or 4 words depending
632 on the machine mode of the operands. */
635 output_move_multiple (rtx
*operands
)
638 pdp11_action action
[2];
641 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
643 pdp11_expand_operands (operands
, exops
, 2, action
, either
);
645 /* Check for explicit decrement before. */
646 if (action
[0] == dec_before
)
648 operands
[0] = XEXP (operands
[0], 0);
649 output_asm_insn ("sub $4,%0", operands
);
651 if (action
[1] == dec_before
)
653 operands
[1] = XEXP (operands
[1], 0);
654 output_asm_insn ("sub $4,%1", operands
);
658 for (i
= 0; i
< words
; i
++)
659 output_asm_insn (singlemove_string (exops
[i
]), exops
[i
]);
661 /* Check for increment after. */
662 if (action
[0] == inc_after
)
664 operands
[0] = XEXP (operands
[0], 0);
665 output_asm_insn ("add $4,%0", operands
);
667 if (action
[1] == inc_after
)
669 operands
[1] = XEXP (operands
[1], 0);
670 output_asm_insn ("add $4,%1", operands
);
676 /* Output an ascii string. */
678 output_ascii (FILE *file
, const char *p
, int size
)
682 /* This used to output .byte "string", which doesn't work with the UNIX
683 assembler and I think not with DEC ones either. */
684 fprintf (file
, "\t.byte ");
686 for (i
= 0; i
< size
; i
++)
688 register int c
= p
[i
];
691 fprintf (file
, "%#o", c
);
700 pdp11_asm_output_var (FILE *file
, const char *name
, int size
,
701 int align
, bool global
)
704 fprintf (file
, "\n\t.even\n");
707 fprintf (file
, ".globl ");
708 assemble_name (file
, name
);
710 fprintf (file
, "\n");
711 assemble_name (file
, name
);
712 fprintf (file
, ": .=.+ %#ho\n", (unsigned short)size
);
716 pdp11_asm_print_operand (FILE *file
, rtx x
, int code
)
723 else if (code
== '@')
730 else if (GET_CODE (x
) == REG
)
731 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
732 else if (GET_CODE (x
) == MEM
)
733 output_address (XEXP (x
, 0));
734 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != SImode
)
736 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
737 REAL_VALUE_TO_TARGET_DOUBLE (r
, sval
);
738 fprintf (file
, "$%#lo", sval
[0] >> 16);
743 output_addr_const_pdp11 (file
, x
);
748 pdp11_asm_print_operand_punct_valid_p (unsigned char c
)
750 return (c
== '#' || c
== '@');
754 print_operand_address (FILE *file
, register rtx addr
)
762 switch (GET_CODE (addr
))
769 addr
= XEXP (addr
, 0);
774 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
779 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
784 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
790 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
791 || GET_CODE (XEXP (addr
, 0)) == MEM
)
793 offset
= XEXP (addr
, 0);
794 addr
= XEXP (addr
, 1);
796 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
797 || GET_CODE (XEXP (addr
, 1)) == MEM
)
799 offset
= XEXP (addr
, 1);
800 addr
= XEXP (addr
, 0);
802 if (GET_CODE (addr
) != PLUS
)
804 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
806 breg
= XEXP (addr
, 0);
807 addr
= XEXP (addr
, 1);
809 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
811 breg
= XEXP (addr
, 1);
812 addr
= XEXP (addr
, 0);
814 if (GET_CODE (addr
) == REG
)
816 gcc_assert (breg
== 0);
822 gcc_assert (addr
== 0);
826 output_addr_const_pdp11 (file
, addr
);
829 gcc_assert (GET_CODE (breg
) == REG
);
830 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
835 if (!again
&& GET_CODE (addr
) == CONST_INT
)
837 /* Absolute (integer number) address. */
838 if (!TARGET_UNIX_ASM
)
839 fprintf (file
, "@$");
841 output_addr_const_pdp11 (file
, addr
);
845 /* Target hook to assemble integer objects. We need to use the
846 pdp-specific version of output_addr_const. */
849 pdp11_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
855 fprintf (asm_out_file
, "\t.byte\t");
856 output_addr_const_pdp11 (asm_out_file
, GEN_INT (INTVAL (x
) & 0xff));
858 fprintf (asm_out_file
, " /* char */\n");
862 fprintf (asm_out_file
, TARGET_UNIX_ASM
? "\t" : "\t.word\t");
863 output_addr_const_pdp11 (asm_out_file
, x
);
864 fprintf (asm_out_file
, " /* short */\n");
867 return default_assemble_integer (x
, size
, aligned_p
);
871 /* register move costs, indexed by regs */
873 static const int move_costs
[N_REG_CLASSES
][N_REG_CLASSES
] =
875 /* NO MUL GEN LFPU NLFPU FPU ALL */
877 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
878 /* MUL */ { 0, 2, 2, 22, 22, 22, 22},
879 /* GEN */ { 0, 2, 2, 22, 22, 22, 22},
880 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22},
881 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22},
882 /* FPU */ { 0, 22, 22, 2, 10, 10, 22},
883 /* ALL */ { 0, 22, 22, 22, 22, 22, 22}
887 /* -- note that some moves are tremendously expensive,
888 because they require lots of tricks! do we have to
889 charge the costs incurred by secondary reload class
890 -- as we do here with 10 -- or not ? */
893 pdp11_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
894 reg_class_t c1
, reg_class_t c2
)
896 return move_costs
[(int)c1
][(int)c2
];
900 pdp11_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
901 int opno ATTRIBUTE_UNUSED
, int *total
,
902 bool speed ATTRIBUTE_UNUSED
)
907 if (INTVAL (x
) == 0 || INTVAL (x
) == -1 || INTVAL (x
) == 1)
917 /* Twice as expensive as REG. */
922 /* Twice (or 4 times) as expensive as 16 bit. */
927 /* ??? There is something wrong in MULT because MULT is not
928 as cheap as total = 2 even if we can shift! */
929 /* If optimizing for size make mult etc cheap, but not 1, so when
930 in doubt the faster insn is chosen. */
932 *total
= COSTS_N_INSNS (2);
934 *total
= COSTS_N_INSNS (11);
939 *total
= COSTS_N_INSNS (2);
941 *total
= COSTS_N_INSNS (25);
946 *total
= COSTS_N_INSNS (2);
948 *total
= COSTS_N_INSNS (26);
952 /* Equivalent to length, so same for optimize_size. */
953 *total
= COSTS_N_INSNS (3);
957 /* Only used for qi->hi. */
958 *total
= COSTS_N_INSNS (1);
962 if (GET_MODE (x
) == HImode
)
963 *total
= COSTS_N_INSNS (1);
964 else if (GET_MODE (x
) == SImode
)
965 *total
= COSTS_N_INSNS (6);
967 *total
= COSTS_N_INSNS (2);
974 *total
= COSTS_N_INSNS (1);
975 else if (GET_MODE (x
) == QImode
)
977 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
978 *total
= COSTS_N_INSNS (8); /* worst case */
980 *total
= COSTS_N_INSNS (INTVAL (XEXP (x
, 1)));
982 else if (GET_MODE (x
) == HImode
)
984 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
986 if (abs (INTVAL (XEXP (x
, 1))) == 1)
987 *total
= COSTS_N_INSNS (1);
989 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
992 *total
= COSTS_N_INSNS (10); /* worst case */
994 else if (GET_MODE (x
) == SImode
)
996 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
997 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
998 else /* worst case */
999 *total
= COSTS_N_INSNS (18);
1009 output_jump (enum rtx_code code
, int inv
, int length
)
1013 static char buf
[1000];
1014 const char *pos
, *neg
;
1016 if (cc_prev_status
.flags
& CC_NO_OVERFLOW
)
1020 case GTU
: code
= GT
; break;
1021 case LTU
: code
= LT
; break;
1022 case GEU
: code
= GE
; break;
1023 case LEU
: code
= LE
; break;
1029 case EQ
: pos
= "beq", neg
= "bne"; break;
1030 case NE
: pos
= "bne", neg
= "beq"; break;
1031 case GT
: pos
= "bgt", neg
= "ble"; break;
1032 case GTU
: pos
= "bhi", neg
= "blos"; break;
1033 case LT
: pos
= "blt", neg
= "bge"; break;
1034 case LTU
: pos
= "blo", neg
= "bhis"; break;
1035 case GE
: pos
= "bge", neg
= "blt"; break;
1036 case GEU
: pos
= "bhis", neg
= "blo"; break;
1037 case LE
: pos
= "ble", neg
= "bgt"; break;
1038 case LEU
: pos
= "blos", neg
= "bhi"; break;
1039 default: gcc_unreachable ();
1043 /* currently we don't need this, because the tstdf and cmpdf
1044 copy the condition code immediately, and other float operations are not
1045 yet recognized as changing the FCC - if so, then the length-cost of all
1046 jump insns increases by one, because we have to potentially copy the
1048 if (cc_status
.flags
& CC_IN_FPU
)
1049 output_asm_insn("cfcc", NULL
);
1056 sprintf(buf
, "%s %%l1", inv
? neg
: pos
);
1062 sprintf(buf
, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv
? pos
: neg
, x
, x
);
1076 notice_update_cc_on_set(rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
1078 if (GET_CODE (SET_DEST (exp
)) == CC0
)
1080 cc_status
.flags
= 0;
1081 cc_status
.value1
= SET_DEST (exp
);
1082 cc_status
.value2
= SET_SRC (exp
);
1084 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1088 else if (SET_DEST(exp
) == pc_rtx
)
1092 else if (GET_MODE (SET_DEST(exp
)) == HImode
1093 || GET_MODE (SET_DEST(exp
)) == QImode
)
1095 cc_status
.flags
= GET_CODE (SET_SRC(exp
)) == MINUS
? 0 : CC_NO_OVERFLOW
;
1096 cc_status
.value1
= SET_SRC (exp
);
1097 cc_status
.value2
= SET_DEST (exp
);
1099 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1101 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1102 cc_status
.value2
= 0;
1103 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
1105 && GET_CODE (cc_status
.value2
) == MEM
)
1106 cc_status
.value2
= 0;
1116 simple_memory_operand(rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1120 /* Eliminate non-memory operations */
1121 if (GET_CODE (op
) != MEM
)
1125 /* dword operations really put out 2 instructions, so eliminate them. */
1126 if (GET_MODE_SIZE (GET_MODE (op
)) > (HAVE_64BIT_P () ? 8 : 4))
1130 /* Decode the address now. */
1134 addr
= XEXP (op
, 0);
1136 switch (GET_CODE (addr
))
1139 /* (R0) - no extra cost */
1144 /* -(R0), (R0)+ - cheap! */
1148 /* cheap - is encoded in addressing mode info!
1150 -- except for @(R0), which has to be @0(R0) !!! */
1152 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1162 /* @#address - extra cost */
1166 /* X(R0) - extra cost */
1178 * output a block move:
1180 * operands[0] ... to
1181 * operands[1] ... from
1182 * operands[2] ... length
1183 * operands[3] ... alignment
1184 * operands[4] ... scratch register
1189 output_block_move(rtx
*operands
)
1191 static int count
= 0;
1196 /* Move of zero bytes is a NOP. */
1197 if (operands
[2] == const0_rtx
)
1200 /* Look for moves by small constant byte counts, those we'll
1201 expand to straight line code. */
1202 if (CONSTANT_P (operands
[2]))
1204 if (INTVAL (operands
[2]) < 16
1205 && (!optimize_size
|| INTVAL (operands
[2]) < 5)
1206 && INTVAL (operands
[3]) == 1)
1210 for (i
= 1; i
<= INTVAL (operands
[2]); i
++)
1211 output_asm_insn("movb (%1)+, (%0)+", operands
);
1215 else if (INTVAL(operands
[2]) < 32
1216 && (!optimize_size
|| INTVAL (operands
[2]) < 9)
1217 && INTVAL (operands
[3]) >= 2)
1221 for (i
= 1; i
<= INTVAL (operands
[2]) / 2; i
++)
1222 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1223 if (INTVAL (operands
[2]) & 1)
1224 output_asm_insn ("movb (%1), (%0)", operands
);
1230 /* Ideally we'd look for moves that are multiples of 4 or 8
1231 bytes and handle those by unrolling the move loop. That
1232 makes for a lot of code if done at run time, but it's ok
1233 for constant counts. Also, for variable counts we have
1234 to worry about odd byte count with even aligned pointers.
1235 On 11/40 and up we handle that case; on older machines
1236 we don't and just use byte-wise moves all the time. */
1238 if (CONSTANT_P (operands
[2]) )
1240 if (INTVAL (operands
[3]) < 2)
1244 lastbyte
= INTVAL (operands
[2]) & 1;
1246 if (optimize_size
|| INTVAL (operands
[2]) & 2)
1248 else if (INTVAL (operands
[2]) & 4)
1254 /* Loop count is byte count scaled by unroll. */
1255 operands
[2] = GEN_INT (INTVAL (operands
[2]) >> unroll
);
1256 output_asm_insn ("mov %2, %4", operands
);
1260 /* Variable byte count; use the input register
1262 operands
[4] = operands
[2];
1264 /* Decide whether to move by words, and check
1265 the byte count for zero. */
1266 if (TARGET_40_PLUS
&& INTVAL (operands
[3]) > 1)
1269 output_asm_insn ("asr %4", operands
);
1274 output_asm_insn ("tst %4", operands
);
1276 sprintf (buf
, "beq movestrhi%d", count
+ 1);
1277 output_asm_insn (buf
, NULL
);
1280 /* Output the loop label. */
1281 sprintf (buf
, "\nmovestrhi%d:", count
);
1282 output_asm_insn (buf
, NULL
);
1284 /* Output the appropriate move instructions. */
1288 output_asm_insn ("movb (%1)+, (%0)+", operands
);
1292 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1296 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1297 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1301 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1302 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1303 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1304 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1308 /* Output the decrement and test. */
1311 sprintf (buf
, "sob %%4, movestrhi%d", count
);
1312 output_asm_insn (buf
, operands
);
1316 output_asm_insn ("dec %4", operands
);
1317 sprintf (buf
, "bgt movestrhi%d", count
);
1318 output_asm_insn (buf
, NULL
);
1322 /* If constant odd byte count, move the last byte. */
1324 output_asm_insn ("movb (%1), (%0)", operands
);
1325 else if (!CONSTANT_P (operands
[2]))
1327 /* Output the destination label for the zero byte count check. */
1328 sprintf (buf
, "\nmovestrhi%d:", count
);
1329 output_asm_insn (buf
, NULL
);
1332 /* If we did word moves, check for trailing last byte. */
1335 sprintf (buf
, "bcc movestrhi%d", count
);
1336 output_asm_insn (buf
, NULL
);
1337 output_asm_insn ("movb (%1), (%0)", operands
);
1338 sprintf (buf
, "\nmovestrhi%d:", count
);
1339 output_asm_insn (buf
, NULL
);
1347 /* This function checks whether a real value can be encoded as
1348 a literal, i.e., addressing mode 27. In that mode, real values
1349 are one word values, so the remaining 48 bits have to be zero. */
1351 legitimate_const_double_p (rtx address
)
1355 REAL_VALUE_FROM_CONST_DOUBLE (r
, address
);
1356 REAL_VALUE_TO_TARGET_DOUBLE (r
, sval
);
1357 if ((sval
[0] & 0xffff) == 0 && sval
[1] == 0)
1362 /* Implement CANNOT_CHANGE_MODE_CLASS. */
1364 pdp11_cannot_change_mode_class (enum machine_mode from
,
1365 enum machine_mode to
,
1366 enum reg_class rclass
)
1368 /* Also, FPU registers contain a whole float value and the parts of
1369 it are not separately accessible.
1371 So we disallow all mode changes involving FPRs. */
1372 if (FLOAT_MODE_P (from
) != FLOAT_MODE_P (to
))
1375 return reg_classes_intersect_p (FPU_REGS
, rclass
);
1378 /* TARGET_PREFERRED_RELOAD_CLASS
1380 Given an rtx X being reloaded into a reg required to be
1381 in class CLASS, return the class of reg to actually use.
1382 In general this is just CLASS; but on some machines
1383 in some cases it is preferable to use a more restrictive class.
1385 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1388 pdp11_preferred_reload_class (rtx x
, reg_class_t rclass
)
1390 if (rclass
== FPU_REGS
)
1391 return LOAD_FPU_REGS
;
1392 if (rclass
== ALL_REGS
)
1394 if (FLOAT_MODE_P (GET_MODE (x
)))
1395 return LOAD_FPU_REGS
;
1397 return GENERAL_REGS
;
1402 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
1404 Given an rtx X being reloaded into a reg required to be
1405 in class CLASS, return the class of reg to actually use.
1406 In general this is just CLASS; but on some machines
1407 in some cases it is preferable to use a more restrictive class.
1409 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1412 pdp11_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
1414 if (rclass
== FPU_REGS
)
1415 return LOAD_FPU_REGS
;
1416 if (rclass
== ALL_REGS
)
1418 if (FLOAT_MODE_P (GET_MODE (x
)))
1419 return LOAD_FPU_REGS
;
1421 return GENERAL_REGS
;
1427 /* TARGET_SECONDARY_RELOAD.
1429 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
1430 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
1431 can be loade/stored directly. */
1433 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED
,
1435 reg_class_t reload_class
,
1436 enum machine_mode reload_mode ATTRIBUTE_UNUSED
,
1437 secondary_reload_info
*sri ATTRIBUTE_UNUSED
)
1439 if (reload_class
!= NO_LOAD_FPU_REGS
|| GET_CODE (x
) != REG
||
1440 REGNO_REG_CLASS (REGNO (x
)) == LOAD_FPU_REGS
)
1443 return LOAD_FPU_REGS
;
1446 /* Target routine to check if register to register move requires memory.
1448 The answer is yes if we're going between general register and FPU
1449 registers. The mode doesn't matter in making this check.
1452 pdp11_secondary_memory_needed (reg_class_t c1
, reg_class_t c2
,
1453 enum machine_mode mode ATTRIBUTE_UNUSED
)
1455 int fromfloat
= (c1
== LOAD_FPU_REGS
|| c1
== NO_LOAD_FPU_REGS
||
1457 int tofloat
= (c2
== LOAD_FPU_REGS
|| c2
== NO_LOAD_FPU_REGS
||
1460 return (fromfloat
!= tofloat
);
1463 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1464 that is a valid memory address for an instruction.
1465 The MODE argument is the machine mode for the MEM expression
1466 that wants to use this address.
1471 pdp11_legitimate_address_p (enum machine_mode mode
,
1472 rtx operand
, bool strict
)
1476 /* accept @#address */
1477 if (CONSTANT_ADDRESS_P (operand
))
1480 switch (GET_CODE (operand
))
1484 return !strict
|| REGNO_OK_FOR_BASE_P (REGNO (operand
));
1488 return GET_CODE (XEXP (operand
, 0)) == REG
1489 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))))
1490 && CONSTANT_ADDRESS_P (XEXP (operand
, 1));
1494 return GET_CODE (XEXP (operand
, 0)) == REG
1495 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1499 return GET_CODE (XEXP (operand
, 0)) == REG
1500 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1503 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */
1504 return GET_CODE (XEXP (operand
, 0)) == REG
1505 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1506 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1507 && GET_CODE (XEXP (xfoob
, 0)) == REG
1508 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1509 && CONSTANT_P (XEXP (xfoob
, 1))
1510 && INTVAL (XEXP (xfoob
,1)) == -2;
1513 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */
1514 return GET_CODE (XEXP (operand
, 0)) == REG
1515 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1516 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1517 && GET_CODE (XEXP (xfoob
, 0)) == REG
1518 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1519 && CONSTANT_P (XEXP (xfoob
, 1))
1520 && INTVAL (XEXP (xfoob
,1)) == 2;
1523 /* handle another level of indirection ! */
1524 xfoob
= XEXP (operand
, 0);
1526 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently
1527 also forbidden for float, because we have to handle this
1528 in output_move_double and/or output_move_quad() - we could
1529 do it, but currently it's not worth it!!!
1530 now that DFmode cannot go into CPU register file,
1531 maybe I should allow float ...
1532 but then I have to handle memory-to-memory moves in movdf ?? */
1533 if (GET_MODE_BITSIZE(mode
) > 16)
1536 /* accept @address */
1537 if (CONSTANT_ADDRESS_P (xfoob
))
1540 switch (GET_CODE (xfoob
))
1543 /* accept @(R0) - which is @0(R0) */
1544 return !strict
|| REGNO_OK_FOR_BASE_P(REGNO (xfoob
));
1548 return GET_CODE (XEXP (xfoob
, 0)) == REG
1549 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))))
1550 && CONSTANT_ADDRESS_P (XEXP (xfoob
, 1));
1554 return GET_CODE (XEXP (xfoob
, 0)) == REG
1555 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1559 return GET_CODE (XEXP (xfoob
, 0)) == REG
1560 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1563 /* anything else is invalid */
1568 /* anything else is invalid */
1573 /* Return the class number of the smallest class containing
1574 reg number REGNO. */
1576 pdp11_regno_reg_class (int regno
)
1578 if (regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1579 return GENERAL_REGS
;
1580 else if (regno
> AC3_REGNUM
)
1581 return NO_LOAD_FPU_REGS
;
1582 else if (regno
>= AC0_REGNUM
)
1583 return LOAD_FPU_REGS
;
1587 return GENERAL_REGS
;
1592 pdp11_sp_frame_offset (void)
1594 int offset
= 0, regno
;
1595 offset
= get_frame_size();
1596 for (regno
= 0; regno
<= PC_REGNUM
; regno
++)
1597 if (pdp11_saved_regno (regno
))
1599 for (regno
= AC0_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
1600 if (pdp11_saved_regno (regno
))
1606 /* Return the offset between two registers, one to be eliminated, and the other
1607 its replacement, at the start of a routine. */
1610 pdp11_initial_elimination_offset (int from
, int to
)
1614 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1616 else if (from
== FRAME_POINTER_REGNUM
1617 && to
== HARD_FRAME_POINTER_REGNUM
)
1621 gcc_assert (to
== STACK_POINTER_REGNUM
);
1623 /* Get the size of the register save area. */
1624 spoff
= pdp11_sp_frame_offset ();
1625 if (from
== FRAME_POINTER_REGNUM
)
1628 gcc_assert (from
== ARG_POINTER_REGNUM
);
1630 /* If there is a frame pointer, that is saved too. */
1631 if (frame_pointer_needed
)
1634 /* Account for the saved PC in the function call. */
1639 /* A copy of output_addr_const modified for pdp11 expression syntax.
1640 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1641 use, and for debugging output, which we don't support with this port either.
1642 So this copy should get called whenever needed.
1645 output_addr_const_pdp11 (FILE *file
, rtx x
)
1651 switch (GET_CODE (x
))
1654 gcc_assert (flag_pic
);
1659 assemble_name (file
, XSTR (x
, 0));
1663 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
1664 assemble_name (file
, buf
);
1668 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
1669 assemble_name (file
, buf
);
1677 fprintf (file
, "-");
1679 fprintf (file
, "%#o", i
& 0xffff);
1683 /* This used to output parentheses around the expression,
1684 but that does not work on the 386 (either ATT or BSD assembler). */
1685 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1689 if (GET_MODE (x
) == VOIDmode
)
1691 /* We can use %o if the number is one word and positive. */
1692 gcc_assert (!CONST_DOUBLE_HIGH (x
));
1693 fprintf (file
, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x
));
1696 /* We can't handle floating point constants;
1697 PRINT_OPERAND must handle them. */
1698 output_operand_lossage ("floating constant misused");
1702 /* Some assemblers need integer constants to appear last (e.g. masm). */
1703 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
1705 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1706 if (INTVAL (XEXP (x
, 0)) >= 0)
1707 fprintf (file
, "+");
1708 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1712 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1713 if (INTVAL (XEXP (x
, 1)) >= 0)
1714 fprintf (file
, "+");
1715 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1720 /* Avoid outputting things like x-x or x+5-x,
1721 since some assemblers can't handle that. */
1722 x
= simplify_subtraction (x
);
1723 if (GET_CODE (x
) != MINUS
)
1726 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1727 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
1728 || INTVAL (XEXP (x
, 1)) >= 0)
1729 fprintf (file
, "-");
1730 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1735 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1739 output_operand_lossage ("invalid expression as operand");
1743 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1746 pdp11_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1748 /* Integers 32 bits and under, and scalar floats (if FPU), are returned
1749 in registers. The rest go into memory. */
1750 return (TYPE_MODE (type
) == DImode
1751 || (FLOAT_MODE_P (TYPE_MODE (type
)) && ! TARGET_AC0
)
1752 || TREE_CODE (type
) == VECTOR_TYPE
1753 || COMPLEX_MODE_P (TYPE_MODE (type
)));
1756 /* Worker function for TARGET_FUNCTION_VALUE.
1758 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */
1761 pdp11_function_value (const_tree valtype
,
1762 const_tree fntype_or_decl ATTRIBUTE_UNUSED
,
1763 bool outgoing ATTRIBUTE_UNUSED
)
1765 return gen_rtx_REG (TYPE_MODE (valtype
),
1766 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype
)));
1769 /* Worker function for TARGET_LIBCALL_VALUE. */
1772 pdp11_libcall_value (enum machine_mode mode
,
1773 const_rtx fun ATTRIBUTE_UNUSED
)
1775 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG(mode
));
1778 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1780 On the pdp, the first "output" reg is the only register thus used.
1782 maybe ac0 ? - as option someday! */
1785 pdp11_function_value_regno_p (const unsigned int regno
)
1787 return (regno
== RETVAL_REGNUM
) || (TARGET_AC0
&& (regno
== AC0_REGNUM
));
1790 /* Worker function for TARGET_TRAMPOLINE_INIT.
1792 trampoline - how should i do it in separate i+d ?
1793 have some allocate_trampoline magic???
1795 the following should work for shared I/D:
1797 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
1798 JMP @#FUNCTION 000137 0x0000 <- FUNCTION
1802 pdp11_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
1804 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
1807 gcc_assert (!TARGET_SPLIT
);
1809 mem
= adjust_address (m_tramp
, HImode
, 0);
1810 emit_move_insn (mem
, GEN_INT (012700+STATIC_CHAIN_REGNUM
));
1811 mem
= adjust_address (m_tramp
, HImode
, 2);
1812 emit_move_insn (mem
, chain_value
);
1813 mem
= adjust_address (m_tramp
, HImode
, 4);
1814 emit_move_insn (mem
, GEN_INT (000137));
1815 emit_move_insn (mem
, fnaddr
);
1818 /* Worker function for TARGET_FUNCTION_ARG.
1820 Determine where to put an argument to a function.
1821 Value is zero to push the argument on the stack,
1822 or a hard register in which to store the argument.
1824 MODE is the argument's machine mode.
1825 TYPE is the data type of the argument (as a tree).
1826 This is null for libcalls where that information may
1828 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1829 the preceding args and about the function being called.
1830 NAMED is nonzero if this argument is a named parameter
1831 (otherwise it is an extra parameter matching an ellipsis). */
1834 pdp11_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1835 enum machine_mode mode ATTRIBUTE_UNUSED
,
1836 const_tree type ATTRIBUTE_UNUSED
,
1837 bool named ATTRIBUTE_UNUSED
)
1842 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE.
1844 Update the data in CUM to advance over an argument of mode MODE and
1845 data type TYPE. (TYPE is null for libcalls where that information
1846 may not be available.) */
1849 pdp11_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1850 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1852 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1854 *cum
+= (mode
!= BLKmode
1855 ? GET_MODE_SIZE (mode
)
1856 : int_size_in_bytes (type
));
1859 /* Make sure everything's fine if we *don't* have an FPU.
1860 This assumes that putting a register in fixed_regs will keep the
1861 compiler's mitts completely off it. We don't bother to zero it out
1862 of register classes. Also fix incompatible register naming with
1863 the UNIX assembler. */
1866 pdp11_conditional_register_usage (void)
1872 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FPU_REGS
]);
1873 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++ )
1874 if (TEST_HARD_REG_BIT (x
, i
))
1875 fixed_regs
[i
] = call_used_regs
[i
] = 1;
1879 call_used_regs
[AC0_REGNUM
] = 1;
1880 if (TARGET_UNIX_ASM
)
1882 /* Change names of FPU registers for the UNIX assembler. */
1883 reg_names
[8] = "fr0";
1884 reg_names
[9] = "fr1";
1885 reg_names
[10] = "fr2";
1886 reg_names
[11] = "fr3";
1887 reg_names
[12] = "fr4";
1888 reg_names
[13] = "fr5";
1893 pdp11_function_section (tree decl ATTRIBUTE_UNUSED
,
1894 enum node_frequency freq ATTRIBUTE_UNUSED
,
1895 bool startup ATTRIBUTE_UNUSED
,
1896 bool exit ATTRIBUTE_UNUSED
)
1901 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1904 pdp11_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1906 return GET_CODE (x
) != CONST_DOUBLE
|| legitimate_const_double_p (x
);
1909 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
1912 pdp11_scalar_mode_supported_p (enum machine_mode mode
)
1914 /* Support SFmode even with -mfloat64. */
1917 return default_scalar_mode_supported_p (mode
);
1920 struct gcc_target targetm
= TARGET_INITIALIZER
;