1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2004, 2005,
3 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
34 #include "insn-attr.h"
42 #include "target-def.h"
45 #define FPU_REG_P(X) ((X)>=8 && (X)<14)
46 #define CPU_REG_P(X) ((X)>=0 && (X)<8)
49 /* this is the current value returned by the macro FIRST_PARM_OFFSET
51 int current_first_parm_offset
;
53 /* Routines to encode/decode pdp11 floats */
54 static void encode_pdp11_f (const struct real_format
*fmt
,
55 long *, const REAL_VALUE_TYPE
*);
56 static void decode_pdp11_f (const struct real_format
*,
57 REAL_VALUE_TYPE
*, const long *);
58 static void encode_pdp11_d (const struct real_format
*fmt
,
59 long *, const REAL_VALUE_TYPE
*);
60 static void decode_pdp11_d (const struct real_format
*,
61 REAL_VALUE_TYPE
*, const long *);
63 /* These two are taken from the corresponding vax descriptors
64 in real.c, changing only the encode/decode routine pointers. */
65 const struct real_format pdp11_f_format
=
84 const struct real_format pdp11_d_format
=
104 encode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
105 const REAL_VALUE_TYPE
*r
)
107 (*vax_f_format
.encode
) (fmt
, buf
, r
);
108 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
112 decode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
113 REAL_VALUE_TYPE
*r
, const long *buf
)
116 tbuf
= ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
117 (*vax_f_format
.decode
) (fmt
, r
, &tbuf
);
121 encode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
122 const REAL_VALUE_TYPE
*r
)
124 (*vax_d_format
.encode
) (fmt
, buf
, r
);
125 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
126 buf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
130 decode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
131 REAL_VALUE_TYPE
*r
, const long *buf
)
134 tbuf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
135 tbuf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
136 (*vax_d_format
.decode
) (fmt
, r
, tbuf
);
139 /* This is where the condition code register lives. */
140 /* rtx cc0_reg_rtx; - no longer needed? */
142 static bool pdp11_handle_option (size_t, const char *, int);
143 static rtx
find_addr_reg (rtx
);
144 static const char *singlemove_string (rtx
*);
145 static bool pdp11_assemble_integer (rtx
, unsigned int, int);
146 static void pdp11_output_function_prologue (FILE *, HOST_WIDE_INT
);
147 static void pdp11_output_function_epilogue (FILE *, HOST_WIDE_INT
);
148 static bool pdp11_rtx_costs (rtx
, int, int, int *);
149 static bool pdp11_return_in_memory (const_tree
, const_tree
);
151 /* Initialize the GCC target structure. */
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP NULL
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP NULL
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP NULL
158 #undef TARGET_ASM_INTEGER
159 #define TARGET_ASM_INTEGER pdp11_assemble_integer
161 #undef TARGET_ASM_FUNCTION_PROLOGUE
162 #define TARGET_ASM_FUNCTION_PROLOGUE pdp11_output_function_prologue
163 #undef TARGET_ASM_FUNCTION_EPILOGUE
164 #define TARGET_ASM_FUNCTION_EPILOGUE pdp11_output_function_epilogue
166 #undef TARGET_ASM_OPEN_PAREN
167 #define TARGET_ASM_OPEN_PAREN "["
168 #undef TARGET_ASM_CLOSE_PAREN
169 #define TARGET_ASM_CLOSE_PAREN "]"
171 #undef TARGET_DEFAULT_TARGET_FLAGS
172 #define TARGET_DEFAULT_TARGET_FLAGS \
173 (MASK_FPU | MASK_45 | MASK_ABSHI_BUILTIN | TARGET_UNIX_ASM_DEFAULT)
174 #undef TARGET_HANDLE_OPTION
175 #define TARGET_HANDLE_OPTION pdp11_handle_option
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS pdp11_rtx_costs
180 #undef TARGET_RETURN_IN_MEMORY
181 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
183 struct gcc_target targetm
= TARGET_INITIALIZER
;
185 /* Implement TARGET_HANDLE_OPTION. */
188 pdp11_handle_option (size_t code
, const char *arg ATTRIBUTE_UNUSED
,
189 int value ATTRIBUTE_UNUSED
)
194 target_flags
&= ~(MASK_40
| MASK_45
);
202 /* Nonzero if OP is a valid second operand for an arithmetic insn. */
205 arith_operand (rtx op
, enum machine_mode mode
)
207 return (register_operand (op
, mode
) || GET_CODE (op
) == CONST_INT
);
211 const_immediate_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
213 return (GET_CODE (op
) == CONST_INT
);
217 immediate15_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
219 return (GET_CODE (op
) == CONST_INT
&& ((INTVAL (op
) & 0x8000) == 0x0000));
223 expand_shift_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
225 return (GET_CODE (op
) == CONST_INT
226 && abs (INTVAL(op
)) > 1
227 && abs (INTVAL(op
)) <= 4);
231 stream is a stdio stream to output the code to.
232 size is an int: how many units of temporary storage to allocate.
233 Refer to the array `regs_ever_live' to determine which registers
234 to save; `regs_ever_live[I]' is nonzero if register number I
235 is ever used in the function. This macro is responsible for
236 knowing which registers should not be saved even if used.
242 pdp11_output_function_prologue (FILE *stream
, HOST_WIDE_INT size
)
244 fprintf (stream
, "\tjsr r5, csv\n");
247 fprintf (stream
, "\t/*abuse empty parameter slot for locals!*/\n");
249 asm_fprintf (stream
, "\tsub $%#wo, sp\n", size
- 2);
257 pdp11_output_function_prologue (FILE *stream
, HOST_WIDE_INT size
)
259 HOST_WIDE_INT fsize
= ((size
) + 1) & ~1;
264 "\n\t; /* function prologue %s*/\n",
265 current_function_name ());
267 /* if we are outputting code for main,
268 the switch FPU to right mode if TARGET_FPU */
269 if (MAIN_NAME_P (DECL_NAME (current_function_decl
)) && TARGET_FPU
)
272 "\t;/* switch cpu to double float, single integer */\n");
273 fprintf(stream
, "\tsetd\n");
274 fprintf(stream
, "\tseti\n\n");
277 if (frame_pointer_needed
)
279 fprintf(stream
, "\tmov r5, -(sp)\n");
280 fprintf(stream
, "\tmov sp, r5\n");
289 asm_fprintf (stream
, "\tsub $%#wo, sp\n", fsize
);
291 /* save CPU registers */
292 for (regno
= 0; regno
< 8; regno
++)
293 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
294 if (! ((regno
== FRAME_POINTER_REGNUM
)
295 && frame_pointer_needed
))
296 fprintf (stream
, "\tmov %s, -(sp)\n", reg_names
[regno
]);
297 /* fpu regs saving */
299 /* via_ac specifies the ac to use for saving ac4, ac5 */
302 for (regno
= 8; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
305 if (LOAD_FPU_REG_P(regno
)
306 && df_regs_ever_live_p (regno
)
307 && ! call_used_regs
[regno
])
309 fprintf (stream
, "\tstd %s, -(sp)\n", reg_names
[regno
]);
313 /* maybe make ac4, ac5 call used regs?? */
315 if (NO_LOAD_FPU_REG_P(regno
)
316 && df_regs_ever_live_p (regno
)
317 && ! call_used_regs
[regno
])
319 gcc_assert (via_ac
!= -1);
320 fprintf (stream
, "\tldd %s, %s\n",
321 reg_names
[regno
], reg_names
[via_ac
]);
322 fprintf (stream
, "\tstd %s, -(sp)\n", reg_names
[via_ac
]);
326 fprintf (stream
, "\t;/* end of prologue */\n\n");
329 #endif /* !TWO_BSD */
332 The function epilogue should not depend on the current stack pointer!
333 It should use the frame pointer only. This is mandatory because
334 of alloca; we also take advantage of it to omit stack adjustments
337 /* maybe we can make leaf functions faster by switching to the
338 second register file - this way we don't have to save regs!
339 leaf functions are ~ 50% of all functions (dynamically!)
341 set/clear bit 11 (dec. 2048) of status word for switching register files -
342 but how can we do this? the pdp11/45 manual says bit may only
343 be set (p.24), but not cleared!
345 switching to kernel is probably more expensive, so we'll leave it
346 like this and not use the second set of registers...
348 maybe as option if you want to generate code for kernel mode? */
353 pdp11_output_function_epilogue (FILE *stream
,
354 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
356 fprintf (stream
, "\t/* SP ignored by cret? */\n");
357 fprintf (stream
, "\tjmp cret\n");
363 pdp11_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size
)
365 HOST_WIDE_INT fsize
= ((size
) + 1) & ~1;
370 fprintf (stream
, "\n\t; /*function epilogue */\n");
372 if (frame_pointer_needed
)
374 /* hope this is safe - m68k does it also .... */
375 df_regs_ever_live_p (FRAME_POINTER_REGNUM
) = 0;
377 for (i
=7, j
= 0 ; i
>= 0 ; i
--)
378 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
381 /* remember # of pushed bytes for CPU regs */
384 /* change fp -> r5 due to the compile error on libgcc2.c */
385 for (i
=7 ; i
>= 0 ; i
--)
386 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
387 fprintf(stream
, "\tmov %#" HOST_WIDE_INT_PRINT
"o(r5), %s\n",
388 (-fsize
-2*j
--)&0xffff, reg_names
[i
]);
391 via_ac
= FIRST_PSEUDO_REGISTER
-1;
393 for (i
= FIRST_PSEUDO_REGISTER
; i
> 7; i
--)
394 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
400 for (i
= FIRST_PSEUDO_REGISTER
; i
> 7; i
--)
402 if (LOAD_FPU_REG_P(i
)
403 && df_regs_ever_live_p (i
)
404 && ! call_used_regs
[i
])
406 fprintf(stream
, "\tldd %#" HOST_WIDE_INT_PRINT
"o(r5), %s\n",
407 (-fsize
-k
)&0xffff, reg_names
[i
]);
411 if (NO_LOAD_FPU_REG_P(i
)
412 && df_regs_ever_live_p (i
)
413 && ! call_used_regs
[i
])
415 gcc_assert (LOAD_FPU_REG_P(via_ac
));
417 fprintf(stream
, "\tldd %#" HOST_WIDE_INT_PRINT
"o(r5), %s\n",
418 (-fsize
-k
)&0xffff, reg_names
[via_ac
]);
419 fprintf(stream
, "\tstd %s, %s\n", reg_names
[via_ac
], reg_names
[i
]);
424 fprintf(stream
, "\tmov r5, sp\n");
425 fprintf (stream
, "\tmov (sp)+, r5\n");
429 via_ac
= FIRST_PSEUDO_REGISTER
-1;
432 for (i
= FIRST_PSEUDO_REGISTER
; i
> 7; i
--)
433 if (df_regs_ever_live_p (i
) && call_used_regs
[i
])
436 for (i
= FIRST_PSEUDO_REGISTER
; i
> 7; i
--)
438 if (LOAD_FPU_REG_P(i
)
439 && df_regs_ever_live_p (i
)
440 && ! call_used_regs
[i
])
441 fprintf(stream
, "\tldd (sp)+, %s\n", reg_names
[i
]);
443 if (NO_LOAD_FPU_REG_P(i
)
444 && df_regs_ever_live_p (i
)
445 && ! call_used_regs
[i
])
447 gcc_assert (LOAD_FPU_REG_P(via_ac
));
449 fprintf(stream
, "\tldd (sp)+, %s\n", reg_names
[via_ac
]);
450 fprintf(stream
, "\tstd %s, %s\n", reg_names
[via_ac
], reg_names
[i
]);
454 for (i
=7; i
>= 0; i
--)
455 if (df_regs_ever_live_p (i
) && !call_used_regs
[i
])
456 fprintf(stream
, "\tmov (sp)+, %s\n", reg_names
[i
]);
459 fprintf((stream
), "\tadd $%#" HOST_WIDE_INT_PRINT
"o, sp\n",
463 fprintf (stream
, "\trts pc\n");
464 fprintf (stream
, "\t;/* end of epilogue*/\n\n\n");
467 #endif /* !TWO_BSD */
469 /* Return the best assembler insn template
470 for moving operands[1] into operands[0] as a fullword. */
472 singlemove_string (rtx
*operands
)
474 if (operands
[1] != const0_rtx
)
481 /* Output assembler code to perform a doubleword move insn
482 with operands OPERANDS. */
485 output_move_double (rtx
*operands
)
487 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
489 rtx addreg0
= 0, addreg1
= 0;
491 /* First classify both operands. */
493 if (REG_P (operands
[0]))
495 else if (offsettable_memref_p (operands
[0]))
497 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
499 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
501 else if (GET_CODE (operands
[0]) == MEM
)
506 if (REG_P (operands
[1]))
508 else if (CONSTANT_P (operands
[1])
510 || GET_CODE (operands
[1]) == CONST_DOUBLE
514 else if (offsettable_memref_p (operands
[1]))
516 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
518 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
520 else if (GET_CODE (operands
[1]) == MEM
)
525 /* Check for the cases that the operand constraints are not
526 supposed to allow to happen. Abort if we get one,
527 because generating code for these cases is painful. */
529 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
531 /* If one operand is decrementing and one is incrementing
532 decrement the former register explicitly
533 and change that operand into ordinary indexing. */
535 if (optype0
== PUSHOP
&& optype1
== POPOP
)
537 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
538 output_asm_insn ("sub $4,%0", operands
);
539 operands
[0] = gen_rtx_MEM (SImode
, operands
[0]);
542 if (optype0
== POPOP
&& optype1
== PUSHOP
)
544 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
545 output_asm_insn ("sub $4,%1", operands
);
546 operands
[1] = gen_rtx_MEM (SImode
, operands
[1]);
550 /* If an operand is an unoffsettable memory ref, find a register
551 we can increment temporarily to make it refer to the second word. */
553 if (optype0
== MEMOP
)
554 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
556 if (optype1
== MEMOP
)
557 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
559 /* Ok, we can do one word at a time.
560 Normally we do the low-numbered word first,
561 but if either operand is autodecrementing then we
562 do the high-numbered word first.
564 In either case, set up in LATEHALF the operands to use
565 for the high-numbered word and in some cases alter the
566 operands in OPERANDS to be suitable for the low-numbered word. */
568 if (optype0
== REGOP
)
569 latehalf
[0] = gen_rtx_REG (HImode
, REGNO (operands
[0]) + 1);
570 else if (optype0
== OFFSOP
)
571 latehalf
[0] = adjust_address (operands
[0], HImode
, 2);
573 latehalf
[0] = operands
[0];
575 if (optype1
== REGOP
)
576 latehalf
[1] = gen_rtx_REG (HImode
, REGNO (operands
[1]) + 1);
577 else if (optype1
== OFFSOP
)
578 latehalf
[1] = adjust_address (operands
[1], HImode
, 2);
579 else if (optype1
== CNSTOP
)
581 if (CONSTANT_P (operands
[1]))
583 /* now the mess begins, high word is in lower word???
585 that's what ashc makes me think, but I don't remember :-( */
586 latehalf
[1] = GEN_INT (INTVAL(operands
[1]) >> 16);
587 operands
[1] = GEN_INT (INTVAL(operands
[1]) & 0xff);
590 /* immediate 32-bit values not allowed */
591 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
);
594 latehalf
[1] = operands
[1];
596 /* If insn is effectively movd N(sp),-(sp) then we will do the
597 high word first. We should use the adjusted operand 1 (which is N+4(sp))
598 for the low word as well, to compensate for the first decrement of sp. */
599 if (optype0
== PUSHOP
600 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
601 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
602 operands
[1] = latehalf
[1];
604 /* If one or both operands autodecrementing,
605 do the two words, high-numbered first. */
607 /* Likewise, the first move would clobber the source of the second one,
608 do them in the other order. This happens only for registers;
609 such overlap can't happen in memory unless the user explicitly
610 sets it up, and that is an undefined circumstance. */
612 if (optype0
== PUSHOP
|| optype1
== PUSHOP
613 || (optype0
== REGOP
&& optype1
== REGOP
614 && REGNO (operands
[0]) == REGNO (latehalf
[1])))
616 /* Make any unoffsettable addresses point at high-numbered word. */
618 output_asm_insn ("add $2,%0", &addreg0
);
620 output_asm_insn ("add $2,%0", &addreg1
);
623 output_asm_insn (singlemove_string (latehalf
), latehalf
);
625 /* Undo the adds we just did. */
627 output_asm_insn ("sub $2,%0", &addreg0
);
629 output_asm_insn ("sub $2,%0", &addreg1
);
631 /* Do low-numbered word. */
632 return singlemove_string (operands
);
635 /* Normal case: do the two words, low-numbered first. */
637 output_asm_insn (singlemove_string (operands
), operands
);
639 /* Make any unoffsettable addresses point at high-numbered word. */
641 output_asm_insn ("add $2,%0", &addreg0
);
643 output_asm_insn ("add $2,%0", &addreg1
);
646 output_asm_insn (singlemove_string (latehalf
), latehalf
);
648 /* Undo the adds we just did. */
650 output_asm_insn ("sub $2,%0", &addreg0
);
652 output_asm_insn ("sub $2,%0", &addreg1
);
656 /* Output assembler code to perform a quadword move insn
657 with operands OPERANDS. */
660 output_move_quad (rtx
*operands
)
662 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
664 rtx addreg0
= 0, addreg1
= 0;
666 output_asm_insn(";/* movdi/df: %1 -> %0 */", operands
);
668 if (REG_P (operands
[0]))
670 else if (offsettable_memref_p (operands
[0]))
672 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
674 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
676 else if (GET_CODE (operands
[0]) == MEM
)
681 if (REG_P (operands
[1]))
683 else if (CONSTANT_P (operands
[1])
684 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
686 else if (offsettable_memref_p (operands
[1]))
688 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
690 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
692 else if (GET_CODE (operands
[1]) == MEM
)
697 /* Check for the cases that the operand constraints are not
698 supposed to allow to happen. Abort if we get one,
699 because generating code for these cases is painful. */
701 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
703 /* check if we move a CPU reg to an FPU reg, or vice versa! */
704 if (optype0
== REGOP
&& optype1
== REGOP
)
705 /* bogus - 64 bit cannot reside in CPU! */
706 gcc_assert (!CPU_REG_P(REGNO(operands
[0]))
707 && !CPU_REG_P (REGNO(operands
[1])));
709 if (optype0
== REGOP
|| optype1
== REGOP
)
711 /* check for use of clrd????
712 if you ever allow ac4 and ac5 (now we require secondary load)
713 you must check whether
714 you want to load into them or store from them -
715 then dump ac0 into $help$ movce ac4/5 to ac0, do the
716 store from ac0, and restore ac0 - if you can find
717 an unused ac[0-3], use that and you save a store and a load!*/
719 if (FPU_REG_P(REGNO(operands
[0])))
721 if (GET_CODE(operands
[1]) == CONST_DOUBLE
)
724 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
726 if (REAL_VALUES_EQUAL (r
, dconst0
))
727 return "{clrd|clrf} %0";
730 return "{ldd|movf} %1, %0";
733 if (FPU_REG_P(REGNO(operands
[1])))
734 return "{std|movf} %1, %0";
737 /* If one operand is decrementing and one is incrementing
738 decrement the former register explicitly
739 and change that operand into ordinary indexing. */
741 if (optype0
== PUSHOP
&& optype1
== POPOP
)
743 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
744 output_asm_insn ("sub $8,%0", operands
);
745 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
748 if (optype0
== POPOP
&& optype1
== PUSHOP
)
750 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
751 output_asm_insn ("sub $8,%1", operands
);
752 operands
[1] = gen_rtx_MEM (SImode
, operands
[1]);
756 /* If an operand is an unoffsettable memory ref, find a register
757 we can increment temporarily to make it refer to the second word. */
759 if (optype0
== MEMOP
)
760 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
762 if (optype1
== MEMOP
)
763 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
765 /* Ok, we can do one word at a time.
766 Normally we do the low-numbered word first,
767 but if either operand is autodecrementing then we
768 do the high-numbered word first.
770 In either case, set up in LATEHALF the operands to use
771 for the high-numbered word and in some cases alter the
772 operands in OPERANDS to be suitable for the low-numbered word. */
774 if (optype0
== REGOP
)
775 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
776 else if (optype0
== OFFSOP
)
777 latehalf
[0] = adjust_address (operands
[0], SImode
, 4);
779 latehalf
[0] = operands
[0];
781 if (optype1
== REGOP
)
782 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
783 else if (optype1
== OFFSOP
)
784 latehalf
[1] = adjust_address (operands
[1], SImode
, 4);
785 else if (optype1
== CNSTOP
)
787 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
791 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
792 REAL_VALUE_TO_TARGET_DOUBLE (r
, dval
);
793 latehalf
[1] = GEN_INT (dval
[1]);
794 operands
[1] = GEN_INT (dval
[0]);
796 else if (GET_CODE(operands
[1]) == CONST_INT
)
798 latehalf
[1] = const0_rtx
;
804 latehalf
[1] = operands
[1];
806 /* If insn is effectively movd N(sp),-(sp) then we will do the
807 high word first. We should use the adjusted operand 1 (which is N+4(sp))
808 for the low word as well, to compensate for the first decrement of sp. */
809 if (optype0
== PUSHOP
810 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
811 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
812 operands
[1] = latehalf
[1];
814 /* If one or both operands autodecrementing,
815 do the two words, high-numbered first. */
817 /* Likewise, the first move would clobber the source of the second one,
818 do them in the other order. This happens only for registers;
819 such overlap can't happen in memory unless the user explicitly
820 sets it up, and that is an undefined circumstance. */
822 if (optype0
== PUSHOP
|| optype1
== PUSHOP
823 || (optype0
== REGOP
&& optype1
== REGOP
824 && REGNO (operands
[0]) == REGNO (latehalf
[1])))
826 /* Make any unoffsettable addresses point at high-numbered word. */
828 output_asm_insn ("add $4,%0", &addreg0
);
830 output_asm_insn ("add $4,%0", &addreg1
);
833 output_asm_insn(output_move_double(latehalf
), latehalf
);
835 /* Undo the adds we just did. */
837 output_asm_insn ("sub $4,%0", &addreg0
);
839 output_asm_insn ("sub $4,%0", &addreg1
);
841 /* Do low-numbered word. */
842 return output_move_double (operands
);
845 /* Normal case: do the two words, low-numbered first. */
847 output_asm_insn (output_move_double (operands
), operands
);
849 /* Make any unoffsettable addresses point at high-numbered word. */
851 output_asm_insn ("add $4,%0", &addreg0
);
853 output_asm_insn ("add $4,%0", &addreg1
);
856 output_asm_insn (output_move_double (latehalf
), latehalf
);
858 /* Undo the adds we just did. */
860 output_asm_insn ("sub $4,%0", &addreg0
);
862 output_asm_insn ("sub $4,%0", &addreg1
);
868 /* Return a REG that occurs in ADDR with coefficient 1.
869 ADDR can be effectively incremented by incrementing REG. */
872 find_addr_reg (rtx addr
)
874 while (GET_CODE (addr
) == PLUS
)
876 if (GET_CODE (XEXP (addr
, 0)) == REG
)
877 addr
= XEXP (addr
, 0);
878 if (GET_CODE (XEXP (addr
, 1)) == REG
)
879 addr
= XEXP (addr
, 1);
880 if (CONSTANT_P (XEXP (addr
, 0)))
881 addr
= XEXP (addr
, 1);
882 if (CONSTANT_P (XEXP (addr
, 1)))
883 addr
= XEXP (addr
, 0);
885 if (GET_CODE (addr
) == REG
)
890 /* Output an ascii string. */
892 output_ascii (FILE *file
, const char *p
, int size
)
896 /* This used to output .byte "string", which doesn't work with the UNIX
897 assembler and I think not with DEC ones either. */
898 fprintf (file
, "\t.byte ");
900 for (i
= 0; i
< size
; i
++)
902 register int c
= p
[i
];
905 fprintf (file
, "%#o", c
);
913 /* --- stole from out-vax, needs changes */
916 print_operand_address (FILE *file
, register rtx addr
)
918 register rtx reg1
, reg2
, breg
, ireg
;
923 switch (GET_CODE (addr
))
930 addr
= XEXP (addr
, 0);
934 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
939 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
944 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
951 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
952 || GET_CODE (XEXP (addr
, 0)) == MEM
)
954 offset
= XEXP (addr
, 0);
955 addr
= XEXP (addr
, 1);
957 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
958 || GET_CODE (XEXP (addr
, 1)) == MEM
)
960 offset
= XEXP (addr
, 1);
961 addr
= XEXP (addr
, 0);
963 if (GET_CODE (addr
) != PLUS
)
965 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
967 reg1
= XEXP (addr
, 0);
968 addr
= XEXP (addr
, 1);
970 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
972 reg1
= XEXP (addr
, 1);
973 addr
= XEXP (addr
, 0);
975 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
977 reg1
= XEXP (addr
, 0);
978 addr
= XEXP (addr
, 1);
980 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
982 reg1
= XEXP (addr
, 1);
983 addr
= XEXP (addr
, 0);
985 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
)
995 gcc_assert (addr
== 0);
998 if (reg1
!= 0 && GET_CODE (reg1
) == MULT
)
1003 else if (reg2
!= 0 && GET_CODE (reg2
) == MULT
)
1008 else if (reg2
!= 0 || GET_CODE (addr
) == MEM
)
1019 output_address (addr
);
1022 gcc_assert (GET_CODE (breg
) == REG
);
1023 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1027 if (GET_CODE (ireg
) == MULT
)
1028 ireg
= XEXP (ireg
, 0);
1029 gcc_assert (GET_CODE (ireg
) == REG
);
1030 gcc_unreachable(); /* ??? */
1031 fprintf (file
, "[%s]", reg_names
[REGNO (ireg
)]);
1036 output_addr_const_pdp11 (file
, addr
);
1040 /* Target hook to assemble integer objects. We need to use the
1041 pdp-specific version of output_addr_const. */
1044 pdp11_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
1050 fprintf (asm_out_file
, "\t.byte\t");
1051 output_addr_const_pdp11 (asm_out_file
, x
);
1052 fprintf (asm_out_file
, " /* char */\n");
1056 fprintf (asm_out_file
, TARGET_UNIX_ASM
? "\t" : "\t.word\t");
1057 output_addr_const_pdp11 (asm_out_file
, x
);
1058 fprintf (asm_out_file
, " /* short */\n");
1061 return default_assemble_integer (x
, size
, aligned_p
);
1065 /* register move costs, indexed by regs */
1067 static const int move_costs
[N_REG_CLASSES
][N_REG_CLASSES
] =
1069 /* NO MUL GEN LFPU NLFPU FPU ALL */
1071 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
1072 /* MUL */ { 0, 2, 2, 10, 22, 22, 22},
1073 /* GEN */ { 0, 2, 2, 10, 22, 22, 22},
1074 /* LFPU */ { 0, 10, 10, 2, 2, 2, 10},
1075 /* NLFPU */ { 0, 22, 22, 2, 2, 2, 22},
1076 /* FPU */ { 0, 22, 22, 2, 2, 2, 22},
1077 /* ALL */ { 0, 22, 22, 10, 22, 22, 22}
1081 /* -- note that some moves are tremendously expensive,
1082 because they require lots of tricks! do we have to
1083 charge the costs incurred by secondary reload class
1084 -- as we do here with 22 -- or not ? */
1087 register_move_cost(enum reg_class c1
, enum reg_class c2
)
1089 return move_costs
[(int)c1
][(int)c2
];
1093 pdp11_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int *total
)
1098 if (INTVAL (x
) == 0 || INTVAL (x
) == -1 || INTVAL (x
) == 1)
1108 /* Twice as expensive as REG. */
1113 /* Twice (or 4 times) as expensive as 16 bit. */
1118 /* ??? There is something wrong in MULT because MULT is not
1119 as cheap as total = 2 even if we can shift! */
1120 /* If optimizing for size make mult etc cheap, but not 1, so when
1121 in doubt the faster insn is chosen. */
1123 *total
= COSTS_N_INSNS (2);
1125 *total
= COSTS_N_INSNS (11);
1130 *total
= COSTS_N_INSNS (2);
1132 *total
= COSTS_N_INSNS (25);
1137 *total
= COSTS_N_INSNS (2);
1139 *total
= COSTS_N_INSNS (26);
1143 /* Equivalent to length, so same for optimize_size. */
1144 *total
= COSTS_N_INSNS (3);
1148 /* Only used for qi->hi. */
1149 *total
= COSTS_N_INSNS (1);
1153 if (GET_MODE (x
) == HImode
)
1154 *total
= COSTS_N_INSNS (1);
1155 else if (GET_MODE (x
) == SImode
)
1156 *total
= COSTS_N_INSNS (6);
1158 *total
= COSTS_N_INSNS (2);
1165 *total
= COSTS_N_INSNS (1);
1166 else if (GET_MODE (x
) == QImode
)
1168 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1169 *total
= COSTS_N_INSNS (8); /* worst case */
1171 *total
= COSTS_N_INSNS (INTVAL (XEXP (x
, 1)));
1173 else if (GET_MODE (x
) == HImode
)
1175 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1177 if (abs (INTVAL (XEXP (x
, 1))) == 1)
1178 *total
= COSTS_N_INSNS (1);
1180 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1183 *total
= COSTS_N_INSNS (10); /* worst case */
1185 else if (GET_MODE (x
) == SImode
)
1187 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1188 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1189 else /* worst case */
1190 *total
= COSTS_N_INSNS (18);
1200 output_jump (const char *pos
, const char *neg
, int length
)
1204 static char buf
[1000];
1207 /* currently we don't need this, because the tstdf and cmpdf
1208 copy the condition code immediately, and other float operations are not
1209 yet recognized as changing the FCC - if so, then the length-cost of all
1210 jump insns increases by one, because we have to potentially copy the
1212 if (cc_status
.flags
& CC_IN_FPU
)
1213 output_asm_insn("cfcc", NULL
);
1221 strcat(buf
, " %l0");
1227 sprintf(buf
, "%s JMP_%d\n\tjmp %%l0\nJMP_%d:", neg
, x
, x
);
1241 notice_update_cc_on_set(rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
1243 if (GET_CODE (SET_DEST (exp
)) == CC0
)
1245 cc_status
.flags
= 0;
1246 cc_status
.value1
= SET_DEST (exp
);
1247 cc_status
.value2
= SET_SRC (exp
);
1250 if (GET_MODE(SET_SRC(exp)) == DFmode)
1251 cc_status.flags |= CC_IN_FPU;
1254 else if ((GET_CODE (SET_DEST (exp
)) == REG
1255 || GET_CODE (SET_DEST (exp
)) == MEM
)
1256 && GET_CODE (SET_SRC (exp
)) != PC
1257 && (GET_MODE (SET_DEST(exp
)) == HImode
1258 || GET_MODE (SET_DEST(exp
)) == QImode
)
1259 && (GET_CODE (SET_SRC(exp
)) == PLUS
1260 || GET_CODE (SET_SRC(exp
)) == MINUS
1261 || GET_CODE (SET_SRC(exp
)) == AND
1262 || GET_CODE (SET_SRC(exp
)) == IOR
1263 || GET_CODE (SET_SRC(exp
)) == XOR
1264 || GET_CODE (SET_SRC(exp
)) == NOT
1265 || GET_CODE (SET_SRC(exp
)) == NEG
1266 || GET_CODE (SET_SRC(exp
)) == REG
1267 || GET_CODE (SET_SRC(exp
)) == MEM
))
1269 cc_status
.flags
= 0;
1270 cc_status
.value1
= SET_SRC (exp
);
1271 cc_status
.value2
= SET_DEST (exp
);
1273 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1275 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1276 cc_status
.value2
= 0;
1277 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
1279 && GET_CODE (cc_status
.value2
) == MEM
)
1280 cc_status
.value2
= 0;
1282 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1286 else if (GET_CODE (SET_DEST (exp
)) == REG
)
1289 if ((cc_status
.value1
1290 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
)))
1291 cc_status
.value1
= 0;
1292 if ((cc_status
.value2
1293 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
)))
1294 cc_status
.value2
= 0;
1296 else if (SET_DEST(exp
) == pc_rtx
)
1300 else /* if (GET_CODE (SET_DEST (exp)) == MEM) */
1302 /* the last else is a bit paranoiac, but since nearly all instructions
1303 play with condition codes, it's reasonable! */
1305 CC_STATUS_INIT
; /* paranoia*/
1311 simple_memory_operand(rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1315 /* Eliminate non-memory operations */
1316 if (GET_CODE (op
) != MEM
)
1320 /* dword operations really put out 2 instructions, so eliminate them. */
1321 if (GET_MODE_SIZE (GET_MODE (op
)) > (HAVE_64BIT_P () ? 8 : 4))
1325 /* Decode the address now. */
1329 addr
= XEXP (op
, 0);
1331 switch (GET_CODE (addr
))
1334 /* (R0) - no extra cost */
1339 /* -(R0), (R0)+ - cheap! */
1343 /* cheap - is encoded in addressing mode info!
1345 -- except for @(R0), which has to be @0(R0) !!! */
1347 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1357 /* @#address - extra cost */
1361 /* X(R0) - extra cost */
1373 * output a block move:
1375 * operands[0] ... to
1376 * operands[1] ... from
1377 * operands[2] ... length
1378 * operands[3] ... alignment
1379 * operands[4] ... scratch register
1384 output_block_move(rtx
*operands
)
1386 static int count
= 0;
1389 if (GET_CODE(operands
[2]) == CONST_INT
1392 if (INTVAL(operands
[2]) < 16
1393 && INTVAL(operands
[3]) == 1)
1397 for (i
= 1; i
<= INTVAL(operands
[2]); i
++)
1398 output_asm_insn("movb (%1)+, (%0)+", operands
);
1402 else if (INTVAL(operands
[2]) < 32)
1406 for (i
= 1; i
<= INTVAL(operands
[2])/2; i
++)
1407 output_asm_insn("mov (%1)+, (%0)+", operands
);
1409 /* may I assume that moved quantity is
1410 multiple of alignment ???
1419 /* can do other clever things, maybe... */
1422 if (CONSTANT_P(operands
[2]) )
1424 /* just move count to scratch */
1425 output_asm_insn("mov %2, %4", operands
);
1429 /* just clobber the register */
1430 operands
[4] = operands
[2];
1434 /* switch over alignment */
1435 switch (INTVAL(operands
[3]))
1451 sprintf(buf
, "\nmovestrhi%d:", count
);
1452 output_asm_insn(buf
, NULL
);
1454 output_asm_insn("movb (%1)+, (%0)+", operands
);
1458 sprintf(buf
, "sob %%4, movestrhi%d", count
);
1459 output_asm_insn(buf
, operands
);
1463 output_asm_insn("dec %4", operands
);
1465 sprintf(buf
, "bgt movestrhi%d", count
);
1466 output_asm_insn(buf
, NULL
);
1488 generate_compact_code
:
1490 output_asm_insn("asr %4", operands
);
1492 sprintf(buf
, "\nmovestrhi%d:", count
);
1493 output_asm_insn(buf
, NULL
);
1495 output_asm_insn("mov (%1)+, (%0)+", operands
);
1499 sprintf(buf
, "sob %%4, movestrhi%d", count
);
1500 output_asm_insn(buf
, operands
);
1504 output_asm_insn("dec %4", operands
);
1506 sprintf(buf
, "bgt movestrhi%d", count
);
1507 output_asm_insn(buf
, NULL
);
1533 goto generate_compact_code
;
1535 output_asm_insn("asr %4", operands
);
1536 output_asm_insn("asr %4", operands
);
1538 sprintf(buf
, "\nmovestrhi%d:", count
);
1539 output_asm_insn(buf
, NULL
);
1541 output_asm_insn("mov (%1)+, (%0)+", operands
);
1542 output_asm_insn("mov (%1)+, (%0)+", operands
);
1546 sprintf(buf
, "sob %%4, movestrhi%d", count
);
1547 output_asm_insn(buf
, operands
);
1551 output_asm_insn("dec %4", operands
);
1553 sprintf(buf
, "bgt movestrhi%d", count
);
1554 output_asm_insn(buf
, NULL
);
1584 goto generate_compact_code
;
1586 output_asm_insn("asr %4", operands
);
1587 output_asm_insn("asr %4", operands
);
1588 output_asm_insn("asr %4", operands
);
1590 sprintf(buf
, "\nmovestrhi%d:", count
);
1591 output_asm_insn(buf
, NULL
);
1593 output_asm_insn("mov (%1)+, (%0)+", operands
);
1594 output_asm_insn("mov (%1)+, (%0)+", operands
);
1595 output_asm_insn("mov (%1)+, (%0)+", operands
);
1596 output_asm_insn("mov (%1)+, (%0)+", operands
);
1600 sprintf(buf
, "sob %%4, movestrhi%d", count
);
1601 output_asm_insn(buf
, operands
);
1605 output_asm_insn("dec %4", operands
);
1607 sprintf(buf
, "bgt movestrhi%d", count
);
1608 output_asm_insn(buf
, NULL
);
1622 legitimate_address_p (enum machine_mode mode
, rtx address
)
1624 /* #define REG_OK_STRICT */
1625 GO_IF_LEGITIMATE_ADDRESS(mode
, address
, win
);
1632 /* #undef REG_OK_STRICT */
1635 /* This function checks whether a real value can be encoded as
1636 a literal, i.e., addressing mode 27. In that mode, real values
1637 are one word values, so the remaining 48 bits have to be zero. */
1639 legitimate_const_double_p (rtx address
)
1643 REAL_VALUE_FROM_CONST_DOUBLE (r
, address
);
1644 REAL_VALUE_TO_TARGET_DOUBLE (r
, sval
);
1645 if ((sval
[0] & 0xffff) == 0 && sval
[1] == 0)
1650 /* A copy of output_addr_const modified for pdp11 expression syntax.
1651 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1652 use, and for debugging output, which we don't support with this port either.
1653 So this copy should get called whenever needed.
1656 output_addr_const_pdp11 (FILE *file
, rtx x
)
1661 switch (GET_CODE (x
))
1664 gcc_assert (flag_pic
);
1669 assemble_name (file
, XSTR (x
, 0));
1673 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
1674 assemble_name (file
, buf
);
1678 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
1679 assemble_name (file
, buf
);
1683 /* Should we check for constants which are too big? Maybe cutting
1684 them off to 16 bits is OK? */
1685 fprintf (file
, "%#ho", (unsigned short) INTVAL (x
));
1689 /* This used to output parentheses around the expression,
1690 but that does not work on the 386 (either ATT or BSD assembler). */
1691 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1695 if (GET_MODE (x
) == VOIDmode
)
1697 /* We can use %o if the number is one word and positive. */
1698 gcc_assert (!CONST_DOUBLE_HIGH (x
));
1699 fprintf (file
, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x
));
1702 /* We can't handle floating point constants;
1703 PRINT_OPERAND must handle them. */
1704 output_operand_lossage ("floating constant misused");
1708 /* Some assemblers need integer constants to appear last (e.g. masm). */
1709 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
1711 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1712 if (INTVAL (XEXP (x
, 0)) >= 0)
1713 fprintf (file
, "+");
1714 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1718 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1719 if (INTVAL (XEXP (x
, 1)) >= 0)
1720 fprintf (file
, "+");
1721 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1726 /* Avoid outputting things like x-x or x+5-x,
1727 since some assemblers can't handle that. */
1728 x
= simplify_subtraction (x
);
1729 if (GET_CODE (x
) != MINUS
)
1732 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1733 fprintf (file
, "-");
1734 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1735 && INTVAL (XEXP (x
, 1)) < 0)
1737 fprintf (file
, targetm
.asm_out
.open_paren
);
1738 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1739 fprintf (file
, targetm
.asm_out
.close_paren
);
1742 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1747 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1751 output_operand_lossage ("invalid expression as operand");
1755 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1758 pdp11_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1760 /* Should probably return DImode and DFmode in memory, lest
1761 we fill up all regs!
1763 have to, else we crash - exception: maybe return result in
1764 ac0 if DFmode and FPU present - compatibility problem with
1765 libraries for non-floating point.... */
1766 return (TYPE_MODE (type
) == DImode
1767 || (TYPE_MODE (type
) == DFmode
&& ! TARGET_AC0
));