1 /* Definitions of target machine for GNU compiler, for the pdp-11
2 Copyright (C) 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2004, 2005,
3 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define CONSTANT_POOL_BEFORE_FUNCTION 0
24 /* check whether load_fpu_reg or not */
25 #define LOAD_FPU_REG_P(x) ((x) >= AC0_REGNUM && (x) <= AC3_REGNUM)
26 #define NO_LOAD_FPU_REG_P(x) ((x) == AC4_REGNUM || (x) == AC5_REGNUM)
27 #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x))
28 #define CPU_REG_P(x) ((x) <= PC_REGNUM)
30 /* Names to predefine in the preprocessor for this target machine. */
32 #define TARGET_CPU_CPP_BUILTINS() \
35 builtin_define_std ("pdp11"); \
39 /* Print subsidiary information on the compiler version in use. */
40 #define TARGET_VERSION fprintf (stderr, " (pdp11)");
43 /* Generate DBX debugging information. */
45 #define DBX_DEBUGGING_INFO
47 #define TARGET_40_PLUS (TARGET_40 || TARGET_45)
48 #define TARGET_10 (! TARGET_40_PLUS)
50 #define TARGET_UNIX_ASM_DEFAULT 0
52 #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0)
57 #define SHORT_TYPE_SIZE 16
58 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32)
59 #define LONG_TYPE_SIZE 32
60 #define LONG_LONG_TYPE_SIZE 64
62 /* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit
63 of saving core for huge arrays - the definitions are
64 already in md - but floats can never reside in
65 an FPU register - we keep the FPU in double float mode
67 #define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64)
68 #define DOUBLE_TYPE_SIZE 64
69 #define LONG_DOUBLE_TYPE_SIZE 64
71 /* machine types from ansi */
72 #define SIZE_TYPE "unsigned int" /* definition of size_t */
73 #define WCHAR_TYPE "int" /* or long int???? */
74 #define WCHAR_TYPE_SIZE 16
76 #define PTRDIFF_TYPE "int"
78 /* target machine storage layout */
80 /* Define this if most significant bit is lowest numbered
81 in instructions that operate on numbered bit-fields. */
82 #define BITS_BIG_ENDIAN 0
84 /* Define this if most significant byte of a word is the lowest numbered. */
85 #define BYTES_BIG_ENDIAN 0
87 /* Define this if most significant word of a multiword number is first. */
88 #define WORDS_BIG_ENDIAN 1
90 /* Define that floats are in VAX order, not high word first as for ints. */
91 #define FLOAT_WORDS_BIG_ENDIAN 0
93 /* Width of a word, in units (bytes).
95 UNITS OR BYTES - seems like units */
96 #define UNITS_PER_WORD 2
98 /* This machine doesn't use IEEE floats. */
99 /* Because the pdp11 (at least Unix) convention for 32-bit ints is
100 big endian, opposite for what you need for float, the vax float
101 conversion routines aren't actually used directly. But the underlying
102 format is indeed the vax/pdp11 float format. */
103 extern const struct real_format pdp11_f_format
;
104 extern const struct real_format pdp11_d_format
;
106 /* Maximum sized of reasonable data type
107 DImode or Dfmode ...*/
108 #define MAX_FIXED_MODE_SIZE 64
110 /* Allocation boundary (in *bits*) for storing pointers in memory. */
111 #define POINTER_BOUNDARY 16
113 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
114 #define PARM_BOUNDARY 16
116 /* Boundary (in *bits*) on which stack pointer should be aligned. */
117 #define STACK_BOUNDARY 16
119 /* Allocation boundary (in *bits*) for the code of a function. */
120 #define FUNCTION_BOUNDARY 16
122 /* Alignment of field after `int : 0' in a structure. */
123 #define EMPTY_FIELD_BOUNDARY 16
125 /* No data type wants to be aligned rounder than this. */
126 #define BIGGEST_ALIGNMENT 16
128 /* Define this if move instructions will actually fail to work
129 when given unaligned data. */
130 #define STRICT_ALIGNMENT 1
132 /* Standard register usage. */
134 /* Number of actual hardware registers.
135 The hardware registers are assigned numbers for the compiler
136 from 0 to just below FIRST_PSEUDO_REGISTER.
137 All registers that the compiler knows about must be given numbers,
138 even those that are not normally considered general registers.
140 we have 8 integer registers, plus 6 float
141 (don't use scratch float !) */
143 /* 1 for registers that have pervasive standard uses
144 and are not available for the register allocator.
146 On the pdp, these are:
149 reg 5 = fp; not necessarily!
152 /* don't let them touch fp regs for the time being !*/
154 #define FIXED_REGISTERS \
155 {0, 0, 0, 0, 0, 0, 1, 1, \
160 /* 1 for registers not available across function calls.
161 These must include the FIXED_REGISTERS and also any
162 registers that can be used without being saved.
163 The latter must include the registers where values are returned
164 and the register where structure-value addresses are passed.
165 Aside from that, you can include as many other registers as you like. */
167 /* don't know about fp */
168 #define CALL_USED_REGISTERS \
169 {1, 1, 0, 0, 0, 0, 1, 1, \
173 /* Make sure everything's fine if we *don't* have an FPU.
174 This assumes that putting a register in fixed_regs will keep the
175 compiler's mitts completely off it. We don't bother to zero it out
176 of register classes. Also fix incompatible register naming with
179 #define CONDITIONAL_REGISTER_USAGE \
185 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \
186 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
187 if (TEST_HARD_REG_BIT (x, i)) \
188 fixed_regs[i] = call_used_regs[i] = 1; \
192 call_used_regs[AC0_REGNUM] = 1; \
193 if (TARGET_UNIX_ASM) \
195 /* Change names of FPU registers for the UNIX assembler. */ \
196 reg_names[8] = "fr0"; \
197 reg_names[9] = "fr1"; \
198 reg_names[10] = "fr2"; \
199 reg_names[11] = "fr3"; \
200 reg_names[12] = "fr4"; \
201 reg_names[13] = "fr5"; \
205 /* Return number of consecutive hard regs needed starting at reg REGNO
206 to hold something of mode MODE.
207 This is ordinarily the length in words of a value of mode MODE
208 but can be less for certain modes in special long registers.
211 #define HARD_REGNO_NREGS(REGNO, MODE) \
212 ((REGNO <= PC_REGNUM)? \
213 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
217 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
218 On the pdp, the cpu registers can hold any mode - check alignment
220 FPU can only hold DF - simplifies life!
222 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
223 (((REGNO) <= PC_REGNUM)? \
224 ((GET_MODE_BITSIZE(MODE) <= 16) \
225 || (GET_MODE_BITSIZE(MODE) >= 32 && !((REGNO) & 1))) \
229 /* Value is 1 if it is a good idea to tie two pseudo registers
230 when one has mode MODE1 and one has mode MODE2.
231 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
232 for any hard reg, then this must be 0 for correct output. */
233 #define MODES_TIEABLE_P(MODE1, MODE2) 0
235 /* Specify the registers used for certain standard purposes.
236 The values of these macros are register numbers. */
238 /* Base register for access to arguments of the function. */
239 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
241 /* Register in which static-chain is passed to a function. */
242 /* ??? - i don't want to give up a reg for this! */
243 #define STATIC_CHAIN_REGNUM 4
245 /* Define the classes of registers for register constraints in the
246 machine description. Also define ranges of constants.
248 One of the classes must always be named ALL_REGS and include all hard regs.
249 If there is more than one class, another class must be named NO_REGS
250 and contain no registers.
252 The name GENERAL_REGS must be the name of a class (or an alias for
253 another name such as ALL_REGS). This is the class of registers
254 that is allowed by "g" or "r" in a register constraint.
255 Also, registers outside this class are allocated only when
256 instructions express preferences for them.
258 The classes must be numbered in nondecreasing order; that is,
259 a larger-numbered class must never be contained completely
260 in a smaller-numbered class.
262 For any two classes, it is very desirable that there be another
263 class that represents their union. */
265 /* The pdp has a couple of classes:
267 MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication
268 (even numbered do 32-bit multiply)
269 LMUL_REGS long multiply registers (even numbered regs )
270 (don't need them, all 32-bit regs are even numbered!)
271 GENERAL_REGS is all cpu
272 LOAD_FPU_REGS is the first four cpu regs, they are easier to load
273 NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them
274 FPU_REGS is all fpu regs
277 enum reg_class
{ NO_REGS
, MUL_REGS
, GENERAL_REGS
, LOAD_FPU_REGS
, NO_LOAD_FPU_REGS
, FPU_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
279 #define N_REG_CLASSES (int) LIM_REG_CLASSES
281 /* have to allow this till cmpsi/tstsi are fixed in a better way !! */
282 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
284 /* Since GENERAL_REGS is the same class as ALL_REGS,
285 don't give it a different class number; just make it an alias. */
287 /* #define GENERAL_REGS ALL_REGS */
289 /* Give names of register classes as strings for dump file. */
291 #define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" }
293 /* Define which registers fit in which classes.
294 This is an initializer for a vector of HARD_REG_SET
295 of length N_REG_CLASSES. */
297 #define REG_CLASS_CONTENTS {{0}, {0x00aa}, {0x00ff}, {0x0f00}, {0x3000}, {0x3f00}, {0x3fff}}
299 /* The same information, inverted:
300 Return the class number of the smallest class containing
301 reg number REGNO. This could be a conditional expression
302 or could index an array. */
304 #define REGNO_REG_CLASS(REGNO) \
305 ((REGNO) >= AC0_REGNUM ? \
306 ((REGNO) <= AC3_REGNUM ? LOAD_FPU_REGS : \
307 NO_LOAD_FPU_REGS) : \
308 (((REGNO) & 1) ? MUL_REGS : GENERAL_REGS))
311 /* The class value for index registers, and the one for base regs. */
312 #define INDEX_REG_CLASS GENERAL_REGS
313 #define BASE_REG_CLASS GENERAL_REGS
315 /* The following macro defines cover classes for Integrated Register
316 Allocator. Cover classes is a set of non-intersected register
317 classes covering all hard registers used for register allocation
318 purpose. Any move between two registers of a cover class should be
319 cheaper than load or store of the registers. The macro value is
320 array of register classes with LIM_REG_CLASSES used as the end
323 #define IRA_COVER_CLASSES { GENERAL_REGS, FPU_REGS, LIM_REG_CLASSES }
325 /* Given an rtx X being reloaded into a reg required to be
326 in class CLASS, return the class of reg to actually use.
327 In general this is just CLASS; but on some machines
328 in some cases it is preferable to use a more restrictive class.
330 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
332 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
333 (((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS)
335 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \
336 (((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS)
338 /* Return the maximum number of consecutive registers
339 needed to represent mode MODE in a register of class CLASS. */
340 #define CLASS_MAX_NREGS(CLASS, MODE) \
341 ((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \
342 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \
347 /* Stack layout; function entry, exit and calling. */
349 /* Define this if pushing a word on the stack
350 makes the stack pointer a smaller address. */
351 #define STACK_GROWS_DOWNWARD
353 /* Define this to nonzero if the nominal address of the stack frame
354 is at the high-address end of the local variables;
355 that is, each additional local variable allocated
356 goes at a more negative offset in the frame.
358 #define FRAME_GROWS_DOWNWARD 1
360 /* Offset within stack frame to start allocating local variables at.
361 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
362 first local allocated. Otherwise, it is the offset to the BEGINNING
363 of the first local allocated. */
364 #define STARTING_FRAME_OFFSET 0
366 /* If we generate an insn to push BYTES bytes,
367 this says how many the stack pointer really advances by.
368 On the pdp11, the stack is on an even boundary */
369 #define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1)
371 /* current_first_parm_offset stores the # of registers pushed on the
373 extern int current_first_parm_offset
;
375 /* Offset of first parameter from the argument pointer register value.
376 For the pdp11, this is nonzero to account for the return address.
378 2 - frame pointer (always saved, even when not used!!!!)
379 -- change some day !!!:q!
382 #define FIRST_PARM_OFFSET(FNDECL) 4
384 /* Define how to find the value returned by a function.
385 VALTYPE is the data type of the value (as a tree).
386 If the precise function being called is known, FUNC is its FUNCTION_DECL;
387 otherwise, FUNC is 0. */
388 #define BASE_RETURN_VALUE_REG(MODE) \
389 ((MODE) == DFmode ? 8 : 0)
391 /* 1 if N is a possible register number for function argument passing.
394 #define FUNCTION_ARG_REGNO_P(N) 0
396 /* Define a data type for recording info about an argument list
397 during the scan of that argument list. This data type should
398 hold all necessary information about the function itself
399 and about the args processed so far, enough to enable macros
400 such as FUNCTION_ARG to determine where the next arg should go.
404 #define CUMULATIVE_ARGS int
406 /* Initialize a variable CUM of type CUMULATIVE_ARGS
407 for a call to a function whose data type is FNTYPE.
408 For a library call, FNTYPE is 0.
410 ...., the offset normally starts at 0, but starts at 1 word
411 when the function gets a structure-value-address as an
412 invisible first argument. */
414 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
417 /* Output assembler code to FILE to increment profiler label # LABELNO
418 for profiling a function entry. */
420 #define FUNCTION_PROFILER(FILE, LABELNO) \
423 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
424 the stack pointer does not matter. The value is tested only in
425 functions that have frame pointers.
426 No definition is equivalent to always zero. */
428 extern int may_call_alloca
;
430 #define EXIT_IGNORE_STACK 1
432 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \
435 offset = get_frame_size(); \
436 for (regno = 0; regno <= PC_REGNUM; regno++) \
437 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) \
439 for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++) \
440 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) \
442 /* offset -= 2; no fp on stack frame */ \
443 (DEPTH_VAR) = offset; \
447 /* Addressing modes, and classification of registers for them. */
449 #define HAVE_POST_INCREMENT 1
451 #define HAVE_PRE_DECREMENT 1
453 /* Macros to check register numbers against specific register classes. */
455 /* These assume that REGNO is a hard or pseudo reg number.
456 They give nonzero only if REGNO is a hard reg of the suitable class
457 or a pseudo reg currently allocated to a suitable hard reg.
458 Since they use reg_renumber, they are safe only once reg_renumber
459 has been allocated, which happens in local-alloc.c. */
461 #define REGNO_OK_FOR_INDEX_P(REGNO) \
462 ((REGNO) <= PC_REGNUM || (unsigned) reg_renumber[REGNO] <= PC_REGNUM)
463 #define REGNO_OK_FOR_BASE_P(REGNO) \
464 ((REGNO) <= PC_REGNUM || (unsigned) reg_renumber[REGNO] <= PC_REGNUM)
466 /* Now macros that check whether X is a register and also,
467 strictly, whether it is in a specified class.
472 /* Maximum number of registers that can appear in a valid memory address. */
474 #define MAX_REGS_PER_ADDRESS 1
476 /* Nonzero if the constant value X is a legitimate general operand.
477 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
479 #define LEGITIMATE_CONSTANT_P(X) \
480 (GET_CODE (X) != CONST_DOUBLE || legitimate_const_double_p (X))
482 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
483 and check its validity for a certain class.
484 We have two alternate definitions for each of them.
485 The usual definition accepts all pseudo regs; the other rejects
486 them unless they have been allocated suitable hard regs.
487 The symbol REG_OK_STRICT causes the latter definition to be used.
489 Most source files want to accept pseudo regs in the hope that
490 they will get allocated to the class that the insn wants them to be in.
491 Source files for reload pass need to be strict.
492 After reload, it makes no difference, since pseudo regs have
493 been eliminated by then. */
495 #ifndef REG_OK_STRICT
497 /* Nonzero if X is a hard reg that can be used as an index
498 or if it is a pseudo reg. */
499 #define REG_OK_FOR_INDEX_P(X) (1)
500 /* Nonzero if X is a hard reg that can be used as a base reg
501 or if it is a pseudo reg. */
502 #define REG_OK_FOR_BASE_P(X) (1)
506 /* Nonzero if X is a hard reg that can be used as an index. */
507 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
508 /* Nonzero if X is a hard reg that can be used as a base reg. */
509 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
513 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
514 that is a valid memory address for an instruction.
515 The MODE argument is the machine mode for the MEM expression
516 that wants to use this address.
520 #define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \
525 if (GET_CODE (operand) == REG \
526 && REG_OK_FOR_BASE_P(operand)) \
529 /* accept @#address */ \
530 if (CONSTANT_ADDRESS_P (operand)) \
534 if (GET_CODE (operand) == PLUS \
535 && GET_CODE (XEXP (operand, 0)) == REG \
536 && REG_OK_FOR_BASE_P (XEXP (operand, 0)) \
537 && CONSTANT_ADDRESS_P (XEXP (operand, 1))) \
541 if (GET_CODE (operand) == PRE_DEC \
542 && GET_CODE (XEXP (operand, 0)) == REG \
543 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \
547 if (GET_CODE (operand) == POST_INC \
548 && GET_CODE (XEXP (operand, 0)) == REG \
549 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \
552 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ \
553 if (GET_CODE (operand) == PRE_MODIFY \
554 && GET_CODE (XEXP (operand, 0)) == REG \
555 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM \
556 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \
557 && GET_CODE (XEXP (xfoob, 0)) == REG \
558 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM \
559 && CONSTANT_P (XEXP (xfoob, 1)) \
560 && INTVAL (XEXP (xfoob,1)) == -2) \
563 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ \
564 if (GET_CODE (operand) == POST_MODIFY \
565 && GET_CODE (XEXP (operand, 0)) == REG \
566 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM \
567 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \
568 && GET_CODE (XEXP (xfoob, 0)) == REG \
569 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM \
570 && CONSTANT_P (XEXP (xfoob, 1)) \
571 && INTVAL (XEXP (xfoob,1)) == 2) \
575 /* handle another level of indirection ! */ \
576 if (GET_CODE(operand) != MEM) \
579 xfoob = XEXP (operand, 0); \
581 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */ \
582 /* also forbidden for float, because we have to handle this */ \
583 /* in output_move_double and/or output_move_quad() - we could */ \
584 /* do it, but currently it's not worth it!!! */ \
585 /* now that DFmode cannot go into CPU register file, */ \
586 /* maybe I should allow float ... */ \
587 /* but then I have to handle memory-to-memory moves in movdf ?? */ \
589 if (GET_MODE_BITSIZE(mode) > 16) \
592 /* accept @(R0) - which is @0(R0) */ \
593 if (GET_CODE (xfoob) == REG \
594 && REG_OK_FOR_BASE_P(xfoob)) \
597 /* accept @address */ \
598 if (CONSTANT_ADDRESS_P (xfoob)) \
601 /* accept @X(R0) */ \
602 if (GET_CODE (xfoob) == PLUS \
603 && GET_CODE (XEXP (xfoob, 0)) == REG \
604 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0)) \
605 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1))) \
608 /* accept @-(R0) */ \
609 if (GET_CODE (xfoob) == PRE_DEC \
610 && GET_CODE (XEXP (xfoob, 0)) == REG \
611 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \
614 /* accept @(R0)+ */ \
615 if (GET_CODE (xfoob) == POST_INC \
616 && GET_CODE (XEXP (xfoob, 0)) == REG \
617 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \
620 /* anything else is invalid */ \
625 /* Specify the machine mode that this machine uses
626 for the index in the tablejump instruction. */
627 #define CASE_VECTOR_MODE HImode
629 /* Define this if a raw index is all that is needed for a
631 #define CASE_TAKES_INDEX_RAW
633 /* Define this as 1 if `char' should by default be signed; else as 0. */
634 #define DEFAULT_SIGNED_CHAR 1
636 /* Max number of bytes we can move from memory to memory
637 in one reasonably fast instruction.
642 /* Nonzero if access to memory by byte is slow and undesirable. -
644 #define SLOW_BYTE_ACCESS 0
646 /* Do not break .stabs pseudos into continuations. */
647 #define DBX_CONTIN_LENGTH 0
649 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
650 is done just by pretending it is already truncated. */
651 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
653 /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE,
654 return the mode to be used for the comparison. For floating-point, CCFPmode
657 #define SELECT_CC_MODE(OP,X,Y) \
658 (GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode)
660 /* Specify the machine mode that pointers have.
661 After generation of rtl, the compiler makes no further distinction
662 between pointers and any other objects of this machine mode. */
665 /* A function address in a call instruction
666 is a word address (for indexing purposes)
667 so give the MEM rtx a word's mode. */
668 #define FUNCTION_MODE HImode
670 /* Define this if addresses of constant functions
671 shouldn't be put through pseudo regs where they can be cse'd.
672 Desirable on machines where ordinary constants are expensive
673 but a CALL with constant address is cheap. */
674 /* #define NO_FUNCTION_CSE */
677 /* cost of moving one register class to another */
678 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
679 pdp11_register_move_cost (CLASS1, CLASS2)
681 /* Tell emit-rtl.c how to initialize special values on a per-function base. */
682 extern struct rtx_def
*cc0_reg_rtx
;
684 #define CC_STATUS_MDEP rtx
686 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
688 /* Tell final.c how to eliminate redundant test instructions. */
690 /* Here we define machine-dependent flags and fields in cc_status
691 (see `conditions.h'). */
693 #define CC_IN_FPU 04000
695 /* Do UPDATE_CC if EXP is a set, used in
698 floats only do compare correctly, else nullify ...
703 /* Store in cc_status the expressions
704 that the condition codes will describe
705 after execution of an instruction whose pattern is EXP.
706 Do not alter them if the instruction would not alter the cc's. */
708 #define NOTICE_UPDATE_CC(EXP, INSN) \
709 { if (GET_CODE (EXP) == SET) \
711 notice_update_cc_on_set(EXP, INSN); \
713 else if (GET_CODE (EXP) == PARALLEL \
714 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \
716 notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \
718 else if (GET_CODE (EXP) == CALL) \
719 { /* all bets are off */ CC_STATUS_INIT; } \
720 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
721 && cc_status.value2 \
722 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
724 printf ("here!\n"); \
725 cc_status.value2 = 0; \
729 /* Control the assembler format that we output. */
731 /* Output to assembler file text saying following lines
732 may contain character constants, extra white space, comments, etc. */
734 #define ASM_APP_ON ""
736 /* Output to assembler file text saying following lines
737 no longer contain unusual constructs. */
739 #define ASM_APP_OFF ""
741 /* Output before read-only data. */
743 #define TEXT_SECTION_ASM_OP "\t.text\n"
745 /* Output before writable data. */
747 #define DATA_SECTION_ASM_OP "\t.data\n"
749 /* How to refer to registers in assembler output.
750 This sequence is indexed by compiler's hard-register-number (see above). */
752 #define REGISTER_NAMES \
753 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \
754 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" }
756 /* Globalizing directive for a label. */
757 #define GLOBAL_ASM_OP "\t.globl "
759 /* The prefix to add to user-visible assembler symbols. */
761 #define USER_LABEL_PREFIX "_"
763 /* This is how to store into the string LABEL
764 the symbol_ref name of an internal numbered label where
765 PREFIX is the class of label and NUM is the number within the class.
766 This is suitable for output with `assemble_name'. */
768 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
769 sprintf (LABEL, "*%s_%lu", PREFIX, (unsigned long)(NUM))
771 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
772 output_ascii (FILE, P, SIZE)
774 /* This is how to output an element of a case-vector that is absolute. */
776 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
777 fprintf (FILE, "\t%sL_%d\n", TARGET_UNIX_ASM ? "" : ".word ", VALUE)
779 /* This is how to output an element of a case-vector that is relative.
780 Don't define this if it is not supported. */
782 /* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
784 /* This is how to output an assembler line
785 that says to advance the location counter
786 to a multiple of 2**LOG bytes.
791 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
797 fprintf (FILE, "\t.even\n"); \
800 gcc_unreachable (); \
803 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
804 fprintf (FILE, "\t.=.+ %#ho\n", (unsigned short)(SIZE))
806 /* This says how to output an assembler line
807 to define a global common symbol. */
809 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
810 ( fprintf ((FILE), ".globl "), \
811 assemble_name ((FILE), (NAME)), \
812 fprintf ((FILE), "\n"), \
813 assemble_name ((FILE), (NAME)), \
814 fprintf ((FILE), ": .=.+ %#ho\n", (unsigned short)(ROUNDED)) \
817 /* This says how to output an assembler line
818 to define a local common symbol. */
820 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
821 ( assemble_name ((FILE), (NAME)), \
822 fprintf ((FILE), ":\t.=.+ %#ho\n", (unsigned short)(ROUNDED)))
824 /* Print operand X (an rtx) in assembler syntax to file FILE.
825 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
826 For `%' followed by punctuation, CODE is the punctuation and X is null.
831 #define PRINT_OPERAND(FILE, X, CODE) \
832 { if (CODE == '#') fprintf (FILE, "#"); \
833 else if (GET_CODE (X) == REG) \
834 fprintf (FILE, "%s", reg_names[REGNO (X)]); \
835 else if (GET_CODE (X) == MEM) \
836 output_address (XEXP (X, 0)); \
837 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode) \
838 { REAL_VALUE_TYPE r; \
840 REAL_VALUE_FROM_CONST_DOUBLE (r, X); \
841 REAL_VALUE_TO_TARGET_DOUBLE (r, sval); \
842 fprintf (FILE, "$%#lo", sval[0] >> 16); } \
843 else { putc ('$', FILE); output_addr_const_pdp11 (FILE, X); }}
845 /* Print a memory address as an operand to reference that memory location. */
847 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
848 print_operand_address (FILE, ADDR)
850 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
852 fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \
855 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
857 fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \
860 #define TRAMPOLINE_SIZE 8
861 #define TRAMPOLINE_ALIGNMENT 16
863 /* there is no point in avoiding branches on a pdp,
864 since branches are really cheap - I just want to find out
865 how much difference the BRANCH_COST macro makes in code */
866 #define BRANCH_COST(speed_p, predictable_p) (TARGET_BRANCH_CHEAP ? 0 : 1)
869 #define COMPARE_FLAG_MODE HImode