1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001-2014 Free Software Foundation, Inc.
3 Contributed by Picochip Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
38 #include "stor-layout.h"
39 #include "stringpool.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
52 #include "target-def.h"
53 #include "langhooks.h"
57 #include "picochip-protos.h"
59 #include "insn-attr.h" /* For DFA state_t. */
60 #include "insn-config.h" /* Required by recog.h */
61 #include "insn-codes.h" /* For CODE_FOR_? */
62 #include "optabs.h" /* For GEN_FCN */
63 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
64 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
65 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
66 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
71 /* Target AE ISA information. */
72 enum picochip_dfa_type picochip_schedule_type
;
74 bool picochip_has_mul_unit
= false;
75 bool picochip_has_mac_unit
= false;
77 /* targetm hook function prototypes. */
79 void picochip_asm_file_start (void);
80 void picochip_asm_file_end (void);
82 void picochip_init_libfuncs (void);
83 void picochip_reorg (void);
85 int picochip_arg_partial_bytes (cumulative_args_t p_cum
,
86 enum machine_mode mode
,
87 tree type
, bool named
);
88 rtx
picochip_function_arg (cumulative_args_t p_cum
,
89 enum machine_mode mode
,
90 const_tree type
, bool named
);
91 rtx
picochip_incoming_function_arg (cumulative_args_t p_cum
,
92 enum machine_mode mode
,
93 const_tree type
, bool named
);
94 void picochip_arg_advance (cumulative_args_t p_cum
, enum machine_mode mode
,
95 const_tree type
, bool named
);
96 unsigned int picochip_function_arg_boundary (enum machine_mode mode
,
99 int picochip_sched_lookahead (void);
100 int picochip_sched_issue_rate (void);
101 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
102 rtx dep_insn
, int cost
);
103 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
104 int *n_readyp
, int clock
);
106 void picochip_init_builtins (void);
107 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
109 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int opno
,
110 int* total
, bool speed
);
111 bool picochip_return_in_memory(const_tree type
,
112 const_tree fntype ATTRIBUTE_UNUSED
);
113 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
114 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
115 enum machine_mode mode
);
116 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
117 int opnum
, int type
, int ind_levels
);
119 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
120 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
121 bool outgoing ATTRIBUTE_UNUSED
);
123 picochip_secondary_reload (bool in_p
,
124 rtx x ATTRIBUTE_UNUSED
,
125 reg_class_t cla ATTRIBUTE_UNUSED
,
126 enum machine_mode mode
,
127 secondary_reload_info
*sri
);
129 picochip_asm_named_section (const char *name
,
130 unsigned int flags ATTRIBUTE_UNUSED
,
131 tree decl ATTRIBUTE_UNUSED
);
133 static rtx
picochip_static_chain (const_tree
, bool);
135 static void picochip_option_override (void);
137 /* Lookup table mapping a register number to the earliest containing
138 class. Used by REGNO_REG_CLASS. */
139 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
141 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
142 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
143 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
144 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
145 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
148 /* picoChip register names. */
149 const char *picochip_regnames
[] = REGISTER_NAMES
;
151 /* Define the maximum number of registers which may be used to pass
152 * parameters to functions. */
153 #define MAX_CALL_PARAMETER_REGS 6
156 /* Target scheduling information. */
158 /* This flag indicates whether the next instruction to be output is a
159 VLIW continuation instruction. It is used to communicate between
160 final_prescan_insn and asm_output_opcode. */
161 static int picochip_vliw_continuation
= 0;
163 /* This variable is used to communicate the current instruction
164 between final_prescan_insn and functions such as asm_output_opcode,
165 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
166 current instruction. */
167 static rtx picochip_current_prescan_insn
;
169 static bool picochip_is_delay_slot_pending
= 0;
171 /* When final_prescan_insn is called, it computes information about
172 the current VLIW packet, and stores it in this structure. When
173 instructions are output, this state is used to make sure that the
174 instructions are output in the correct way (e.g., which ALU to use,
175 whether a macro branch was ever previously a real branch, etc.). */
178 int contains_pico_alu_insn
;
179 int contains_non_cc_alu_insn
;
180 int num_alu_insns_so_far
;
182 /* Record how many instructions are contained in the packet. */
183 int num_insns_in_packet
;
185 /* There was a case for this to be more than 1 */
186 int num_cfi_labels_deferred
;
187 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
188 emitted inside a VLIW packet. */
189 char lm_label_name
[256]; /* Used to record the name of an LM label. */
192 struct vliw_state picochip_current_vliw_state
;
194 /* Save/restore recog_data. */
195 static int picochip_saved_which_alternative
;
196 static struct recog_data_d picochip_saved_recog_data
;
198 /* Determine which ALU to use for the instruction in
199 picochip_current_prescan_insn. */
200 static char picochip_get_vliw_alu_id (void);
202 /* Initialize the GCC target structure. */
204 #undef TARGET_ASM_FUNCTION_PROLOGUE
205 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
207 #undef TARGET_ASM_FUNCTION_EPILOGUE
208 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
210 #undef TARGET_ASM_INTERNAL_LABEL
211 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
213 #undef TARGET_ASM_GLOBALIZE_LABEL
214 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
216 #undef TARGET_ASM_BYTE_OP
217 #define TARGET_ASM_BYTE_OP ".initByte "
218 #undef TARGET_ASM_ALIGNED_HI_OP
219 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
220 #undef TARGET_ASM_UNALIGNED_HI_OP
221 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
224 #undef TARGET_ASM_UNALIGNED_SI_OP
225 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
227 #undef TARGET_INIT_BUILTINS
228 #define TARGET_INIT_BUILTINS picochip_init_builtins
230 #undef TARGET_EXPAND_BUILTIN
231 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
233 #undef TARGET_RTX_COSTS
234 #define TARGET_RTX_COSTS picochip_rtx_costs
236 #undef TARGET_SCHED_ISSUE_RATE
237 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
239 #undef TARGET_SCHED_REORDER
240 #define TARGET_SCHED_REORDER picochip_sched_reorder
242 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
243 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
244 picochip_sched_lookahead
246 #undef TARGET_SCHED_ADJUST_COST
247 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
249 #undef TARGET_ASM_NAMED_SECTION
250 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
252 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
253 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
255 #undef TARGET_INIT_LIBFUNCS
256 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
258 #undef TARGET_ASM_FILE_START
259 #define TARGET_ASM_FILE_START picochip_asm_file_start
261 #undef TARGET_ASM_FILE_END
262 #define TARGET_ASM_FILE_END picochip_asm_file_end
264 #undef TARGET_MACHINE_DEPENDENT_REORG
265 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
267 #undef TARGET_ARG_PARTIAL_BYTES
268 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
270 #undef TARGET_FUNCTION_ARG
271 #define TARGET_FUNCTION_ARG picochip_function_arg
273 #undef TARGET_FUNCTION_INCOMING_ARG
274 #define TARGET_FUNCTION_INCOMING_ARG picochip_incoming_function_arg
276 #undef TARGET_FUNCTION_ARG_ADVANCE
277 #define TARGET_FUNCTION_ARG_ADVANCE picochip_arg_advance
279 #undef TARGET_FUNCTION_ARG_BOUNDARY
280 #define TARGET_FUNCTION_ARG_BOUNDARY picochip_function_arg_boundary
282 #undef TARGET_PROMOTE_FUNCTION_MODE
283 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
284 #undef TARGET_PROMOTE_PROTOTYPES
285 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
287 /* Target support for Anchored Addresses optimization */
288 #undef TARGET_MIN_ANCHOR_OFFSET
289 #define TARGET_MIN_ANCHOR_OFFSET 0
290 #undef TARGET_MAX_ANCHOR_OFFSET
291 #define TARGET_MAX_ANCHOR_OFFSET 7
292 #undef TARGET_ASM_OUTPUT_ANCHOR
293 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
295 #undef TARGET_FUNCTION_VALUE
296 #define TARGET_FUNCTION_VALUE picochip_function_value
298 #undef TARGET_LIBGCC_CMP_RETURN_MODE
299 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
302 #undef TARGET_LEGITIMATE_ADDRESS_P
303 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
305 #undef TARGET_LEGITIMIZE_ADDRESS
306 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
308 /* Loading and storing QImode values to and from memory
309 usually requires a scratch register. */
310 #undef TARGET_SECONDARY_RELOAD
311 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
313 /* How Large Values are Returned */
315 #undef TARGET_RETURN_IN_MEMORY
316 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
318 #undef TARGET_STATIC_CHAIN
319 #define TARGET_STATIC_CHAIN picochip_static_chain
321 #undef TARGET_OPTION_OVERRIDE
322 #define TARGET_OPTION_OVERRIDE picochip_option_override
324 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
325 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
327 /* The 2nd scheduling pass option is switched off, and a machine
328 dependent reorganisation ensures that it is run later on, after the
329 second jump optimisation. */
330 #undef TARGET_DELAY_SCHED2
331 #define TARGET_DELAY_SCHED2 true
333 /* Variable tracking should be run after all optimizations which
334 change order of insns. It also needs a valid CFG. */
335 #undef TARGET_DELAY_VARTRACK
336 #define TARGET_DELAY_VARTRACK true
338 struct gcc_target targetm
= TARGET_INITIALIZER
;
341 /* Only return a value in memory if it is greater than 4 bytes.
342 int_size_in_bytes returns -1 for variable size objects, which go in
343 memory always. The cast to unsigned makes -1 > 8. */
346 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
348 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
351 /* Allow some options to be overriden. */
354 picochip_option_override (void)
356 /* If we are optimizing for stack, dont let inliner to inline functions
357 that could potentially increase stack size.*/
358 if (flag_conserve_stack
)
360 maybe_set_param_value (PARAM_LARGE_STACK_FRAME
, 0,
361 global_options
.x_param_values
,
362 global_options_set
.x_param_values
);
363 maybe_set_param_value (PARAM_STACK_FRAME_GROWTH
, 0,
364 global_options
.x_param_values
,
365 global_options_set
.x_param_values
);
368 /* Turn off the elimination of unused types. The elaborator
369 generates various interesting types to represent constants,
370 generics, and so on, and it is useful to retain this information
371 in the debug output. The increased size of the debug information
372 is not really an issue for us. */
373 flag_eliminate_unused_debug_types
= 0;
375 /* Even if the user specifies a -fno-omit-frame-pointer on the
376 command line, we still want to go ahead and omit frame pointer
377 usages, since we dont really have a frame pointer register.
378 So, all accesses to FP need to be converted to accesses off
380 flag_omit_frame_pointer
= 1;
382 /* Turning on anchored addresses by default. This is an optimization
383 that could decrease the code size by placing anchors in data and
384 accessing offsets from the anchor for file local data variables.*/
386 flag_section_anchors
= 1;
388 /* The second scheduling pass runs within picochip_reorg, to avoid
389 having the second jump optimisation trash the instruction modes
390 (e.g., instructions are changed to TImode to mark the beginning
391 of cycles). Two types of DFA scheduling are possible: space and
392 speed. In both cases, instructions are reordered to avoid stalls
393 (e.g., memory loads stall for one cycle). Speed scheduling will
394 also enable VLIW instruction packing. VLIW instructions use more
395 code space, so VLIW scheduling is disabled when scheduling for
397 if (flag_schedule_insns_after_reload
)
400 picochip_schedule_type
= DFA_TYPE_SPACE
;
403 picochip_schedule_type
= DFA_TYPE_SPEED
;
404 flag_delayed_branch
= 0;
408 picochip_schedule_type
= DFA_TYPE_NONE
;
410 /* Ensure that the debug level is always at least -g2. The flow
411 analyser works at its best if it always has debug
412 information. DWARF is non-intrusive, so it makes no difference to
413 code quality if debug is always enabled. */
414 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
416 debug_info_level
= DINFO_LEVEL_NORMAL
;
417 write_symbols
= DWARF2_DEBUG
;
420 /* Options of the form -mae=mac, and so on will be substituted by
421 the compiler driver for the appropriate byte access and multiply
422 unit ISA options. Any unrecognised AE types will end up being
423 passed to the compiler, which should reject them as invalid. */
424 if (picochip_ae_type_string
!= NULL
)
425 error ("invalid AE type specified (%s)", picochip_ae_type_string
);
427 /* Override any specific capabilities of the instruction set. These
428 take precedence over any capabilities inferred from the AE type,
429 regardless of where the options appear on the command line. */
430 if (picochip_mul_type_string
== NULL
)
432 /* Default to MEM-type multiply, for historical compatibility. */
433 picochip_has_mac_unit
= false;
434 picochip_has_mul_unit
= true;
438 picochip_has_mac_unit
= false;
439 picochip_has_mul_unit
= false;
441 if (strcmp (picochip_mul_type_string
, "mul") == 0)
442 picochip_has_mul_unit
= true;
443 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
444 picochip_has_mac_unit
= true;
445 else if (strcmp (picochip_mul_type_string
, "none") == 0)
446 { /* Do nothing. Unit types already set to false. */ }
448 error ("invalid mul type specified (%s) - expected mac, mul or none",
449 picochip_mul_type_string
);
454 /* Initialise the library functions to handle arithmetic on some of
457 picochip_init_libfuncs (void)
460 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
461 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
462 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
464 /* 64-bit signed multiplication. */
465 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
467 /* Signed division */
468 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
469 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
472 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
473 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
475 /* 32-bit count leading Zeros*/
476 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
478 /* 64-bit comparison */
479 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
480 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
482 /* 64-bit addition and subtraction*/
483 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
484 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
487 /* Memcpy function */
489 picochip_expand_movmemhi (rtx
*operands
)
491 rtx src_addr_reg
, dst_addr_reg
, count_reg
, src_mem
, dst_mem
, tmp_reg
;
494 src_addr_reg
= gen_reg_rtx(HImode
);
495 dst_addr_reg
= gen_reg_rtx(HImode
);
496 count_reg
= gen_reg_rtx(HImode
);
497 emit_insn (gen_movhi (count_reg
, operands
[2]));
498 emit_insn (gen_movqi (src_addr_reg
, XEXP(operands
[1], 0)));
499 emit_insn (gen_movqi (dst_addr_reg
, XEXP(operands
[0], 0)));
500 gcc_assert (GET_CODE(count_reg
) == REG
);
501 start_label
= gen_label_rtx ();
502 emit_label (start_label
);
504 /* We can specialise the code for different alignments */
505 align
= INTVAL(operands
[3]);
506 size
= INTVAL(operands
[2]);
507 gcc_assert(align
>= 0 && size
>= 0);
510 if (size
% 4 == 0 && align
% 4 == 0)
512 src_mem
= gen_rtx_MEM(SImode
, src_addr_reg
);
513 dst_mem
= gen_rtx_MEM(SImode
, dst_addr_reg
);
514 tmp_reg
= gen_reg_rtx(SImode
);
515 emit_insn (gen_movsi (tmp_reg
, src_mem
));
516 emit_insn (gen_movsi (dst_mem
, tmp_reg
));
517 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, GEN_INT(4)));
518 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, GEN_INT(4)));
519 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-4)));
520 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
521 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
523 else if (size
% 2 == 0 && align
% 2 == 0)
525 src_mem
= gen_rtx_MEM(HImode
, src_addr_reg
);
526 dst_mem
= gen_rtx_MEM(HImode
, dst_addr_reg
);
527 tmp_reg
= gen_reg_rtx(HImode
);
528 emit_insn (gen_movhi (tmp_reg
, src_mem
));
529 emit_insn (gen_movhi (dst_mem
, tmp_reg
));
530 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const2_rtx
));
531 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const2_rtx
));
532 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-2)));
533 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
534 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
538 src_mem
= gen_rtx_MEM(QImode
, src_addr_reg
);
539 dst_mem
= gen_rtx_MEM(QImode
, dst_addr_reg
);
540 tmp_reg
= gen_reg_rtx(QImode
);
541 emit_insn (gen_movqi (tmp_reg
, src_mem
));
542 emit_insn (gen_movqi (dst_mem
, tmp_reg
));
543 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const1_rtx
));
544 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const1_rtx
));
545 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-1)));
546 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
547 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
554 /* Return the register class for letter C. */
556 picochip_reg_class_from_letter (unsigned c
)
574 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
576 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
579 picochip_order_regs_for_local_alloc (void)
581 /* We change the order for leaf functions alone. We put r12 at
582 the end since using it will prevent us to combine stw/ldws to
583 stl/ldl and it gives no benefit. In non-leaf functions, we
584 would anyway saveup/restore r12, so it makes sense to use it.*/
586 if (leaf_function_p())
588 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
589 FIRST_PSEUDO_REGISTER
* sizeof (int));
593 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
594 FIRST_PSEUDO_REGISTER
* sizeof (int));
598 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
600 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
605 case 'I': /* 4 bits signed. */
606 return value
+ 8 < 16;
607 case 'J': /* 4 bits unsigned. */
609 case 'K': /* 8 bits signed. */
610 return value
+ 128 < 256;
611 case 'M': /* 4-bit magnitude. */
612 return abs (value
) < 16;
613 case 'N': /* 10 bits signed. */
614 return value
+ 512 > 1024;
615 case 'O': /* 16 bits signed. */
616 return value
+ 32768 < 65536;
617 default: /* Unknown letter. */
622 /* Stack utility functions. */
624 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
627 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
633 /* Emit a set of parallel register expressions used to store
634 blockmode values to pass to functions. */
636 picochip_emit_register_parallel (int size_in_units
, int offset
)
640 rtx vector
[MAX_CALL_PARAMETER_REGS
];
644 /* Compute the base register, and number of required registers. */
645 base_reg
= offset
/ 2;
646 num_regs
= size_in_units
/ 2;
647 if (size_in_units
% 2 == 1)
650 /* Emit a register for each part of the block mode value to be
651 passed in a register. */
652 for (i
= 0; i
< num_regs
; i
++)
653 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
654 gen_rtx_REG (HImode
, base_reg
+ i
),
656 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
662 /* Emit an instruction to allocate a suitable amount of space on the
663 stack, by decrementing the stack pointer. */
665 picochip_emit_stack_allocate (int adjustment
)
668 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
670 /* Use an addition of a negative value. */
671 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
672 GEN_INT (-adjustment
)));
674 /* Make the instruction frame related. Also add an expression note,
675 so that the correct Dwarf information is generated (see documention
676 for RTX_FRAME_RELATED_P for more details). */
677 RTX_FRAME_RELATED_P (insn
) = 1;
678 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
679 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
680 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
681 GEN_INT (-adjustment
))));
685 /* Emit an instruction to save a register of the given mode. The
686 offset at which to save the register is given relative to the stack
689 picochip_emit_save_register (rtx reg
, int offset
)
691 rtx stack_pointer
, address
, mem
, insn
;
693 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
695 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
697 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
699 insn
= emit_move_insn (mem
, reg
);
700 RTX_FRAME_RELATED_P (insn
) = 1;
702 /* For modes other than HImode, create a note explaining that
703 multiple registers have been saved. This allows the correct DWARF
704 call frame information to be generated. */
705 switch (GET_MODE (reg
))
708 /* The RTL is sufficient to explain HImode register saves. */
712 /* SImode must be broken down into parallel HImode register saves. */
720 gen_rtx_PLUS (Pmode
, stack_pointer
,
722 gen_rtx_REG (HImode
, REGNO (reg
)));
723 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
726 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
731 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
732 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
734 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
735 gen_rtx_PARALLEL (VOIDmode
, p
));
742 ("unexpected mode %s encountered in picochip_emit_save_register",
743 GET_MODE_NAME (GET_MODE (reg
)));
748 /* Emit an instruction to restore a register of the given mode. The
749 offset from which to restore the register is given relative to the
752 picochip_emit_restore_register (rtx reg
, int offset
)
754 rtx stack_pointer
, address
, mem
;
756 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
758 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
760 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
762 emit_move_insn (reg
, mem
);
766 /* Check that the given byte offset is aligned to the given number of
769 picochip_is_aligned (int byte_offset
, int bit_alignment
)
771 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
772 return (byte_offset
% byte_alignment
) == 0;
775 /*****************************************************************************
778 * The following section contains code which controls how the stack is
781 * The stack is laid out as follows (high addresses first):
784 * Pretend arguments (ARG PTR)
788 * Outgoing arguments (SP)
790 * The (constant) offsets of the different areas must be calculated
791 * relative to the stack area immediately below, and aligned
792 * appropriately. For example, the frame offset is computed by
793 * determining the offset of the special register area, adding the
794 * size of the special register area, and then aligning the resulting
795 * offset correctly. In turn, the special register offset is computed
796 * from the general register offset, and so on. This enables the
797 * different offsets to change size and alignment, without requiring
798 * the code for other offset calculations to be rewritten.
800 * The argument pointer, and the frame pointer are eliminated wherever
801 * possible, by replacing them with a constant offset from the stack
802 * pointer. In the rare cases where constant offsets from the stack
803 * pointer cannot be computed, another register will be allocated to
804 * serve as the argument pointer, or the frame pointer.
806 * The save registers are stored at small offsets from the caller, to
807 * enable the more efficient SP-based ISA instructions to be used.
809 ****************************************************************************/
811 /* Compute the size of an argument in units. */
813 picochip_compute_arg_size (const_tree type
, enum machine_mode mode
)
815 int type_size_in_units
= 0;
818 type_size_in_units
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
820 type_size_in_units
= GET_MODE_SIZE (mode
);
822 return type_size_in_units
;
826 /* Determine where the next outgoing arg should be placed. */
828 picochip_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
829 const_tree type
, bool named ATTRIBUTE_UNUSED
)
831 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
833 int type_align_in_units
= 0;
834 int type_size_in_units
;
836 int offset_overflow
= 0;
838 /* VOIDmode is passed when computing the second argument to a `call'
839 pattern. This can be ignored. */
840 if (mode
== VOIDmode
)
843 /* Compute the alignment and size of the parameter. */
844 type_align_in_units
=
845 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
846 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
848 /* Compute the correct offset (i.e., ensure that the offset meets
849 the alignment requirements). */
850 offset_overflow
= *cum
% type_align_in_units
;
851 if (offset_overflow
== 0)
854 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
858 printf ("Function arg:\n");
859 printf (" Type valid: %s\n", (type
? "yes" : "no"));
860 printf (" Cumulative Value: %d\n", *cum
);
861 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
862 printf (" Type size: %i units\n", type_size_in_units
);
863 printf (" Alignment: %i units\n", type_align_in_units
);
864 printf (" New offset: %i\n", new_offset
);
868 /* If the new offset is outside the register space, return. */
869 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
872 /* If the end of the argument is outside the register space, then
873 the argument must overlap the register space. Return the first
874 available register. */
875 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
876 return gen_rtx_REG (HImode
, new_offset
/ 2);
878 /* Create a register of the required mode to hold the parameter. */
879 reg
= new_offset
/ 2;
894 return gen_rtx_REG (mode
, reg
);
898 /* Empty blockmode values can be passed as arguments (e.g.,
899 * empty structs). These require no registers
900 * whatsoever. Non-empty blockmode values are passed in a set
901 * of parallel registers. */
902 if (type_size_in_units
== 0)
905 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
910 (0, "defaulting to stack for %s register creation",
911 GET_MODE_NAME (mode
));
919 /* Determine where the next incoming function argument will
920 appear. Normally, this works in exactly the same way as
921 picochip_function_arg, except when the function in question is a
922 varadic function. In this case, the incoming arguments all appear
923 to be passed on the stack (actually, some of the arguments are
924 passed in registers, which are then pushed onto the stack by the
925 function prologue). */
927 picochip_incoming_function_arg (cumulative_args_t cum
,
928 enum machine_mode mode
,
929 const_tree type
, bool named
)
935 return picochip_function_arg (cum
, mode
, type
, named
);
939 /* Gives the alignment boundary, in bits, of an argument with the
942 picochip_function_arg_boundary (enum machine_mode mode
,
943 const_tree type ATTRIBUTE_UNUSED
)
948 align
= STACK_BOUNDARY
;
950 align
= GET_MODE_ALIGNMENT (mode
);
952 if (align
< PARM_BOUNDARY
)
953 align
= PARM_BOUNDARY
;
959 /* Compute partial registers. */
961 picochip_arg_partial_bytes (cumulative_args_t p_cum
, enum machine_mode mode
,
962 tree type
, bool named ATTRIBUTE_UNUSED
)
964 int type_align_in_units
= 0;
965 int type_size_in_units
;
967 int offset_overflow
= 0;
969 unsigned cum
= *get_cumulative_args (p_cum
);
971 /* VOIDmode is passed when computing the second argument to a `call'
972 pattern. This can be ignored. */
973 if (mode
== VOIDmode
)
976 /* Compute the alignment and size of the parameter. */
977 type_align_in_units
=
978 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
979 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
981 /* Compute the correct offset (i.e., ensure that the offset meets
982 the alignment requirements). */
983 offset_overflow
= cum
% type_align_in_units
;
984 if (offset_overflow
== 0)
987 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
991 printf ("Partial function arg nregs:\n");
992 printf (" Type valid: %s\n", (type
? "yes" : "no"));
993 printf (" Cumulative Value: %d\n", cum
);
994 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
995 printf (" Type size: %i units\n", type_size_in_units
);
996 printf (" Alignment: %i units\n", type_align_in_units
);
997 printf (" New offset: %i\n", new_offset
);
1001 /* If the new offset is outside the register space, return. */
1002 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
1005 /* If the end of the argument is outside the register space, then
1006 the argument must overlap the register space. Return the number
1007 of bytes which are passed in registers. */
1008 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
1009 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
1015 /* Advance the cumulative args counter CUM. */
1017 picochip_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1018 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1020 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1021 int type_align_in_units
= 0;
1022 int type_size_in_units
;
1024 int offset_overflow
= 0;
1026 /* VOIDmode is passed when computing the second argument to a `call'
1027 pattern. This can be ignored. */
1028 if (mode
== VOIDmode
)
1031 /* Compute the alignment and size of the parameter. */
1032 type_align_in_units
=
1033 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
1034 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
1036 /* Compute the correct offset (i.e., ensure that the offset meets
1037 the alignment requirements). */
1038 offset_overflow
= *cum
% type_align_in_units
;
1039 if (offset_overflow
== 0)
1042 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
1044 /* Advance past the last argument. */
1045 new_offset
+= type_size_in_units
;
1050 /* Determine whether a register needs saving/restoring. It does if it
1051 is live in a function, and isn't a call-used register. */
1053 picochip_reg_needs_saving (int reg_num
)
1055 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
1058 /* Compute and return offset of the main frame. */
1060 picochip_frame_byte_offset (void)
1062 gcc_assert(picochip_is_aligned
1063 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
1065 return crtl
->outgoing_args_size
;
1068 /* Return the size of the main frame. */
1070 picochip_frame_size_in_bytes (void)
1072 int frame_size
= get_frame_size();
1073 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
1074 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
1075 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
1076 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
1080 /* Compute and return the size (in bytes) of the register save/restore
1081 area for the current function. This only includes the general
1082 purpose registers - the special purpose stack pointer and link
1083 registers are not included in this area. */
1085 picochip_save_area_size_in_bytes (void)
1087 int num_regs_to_save
= 0;
1090 /* Read through all the registers, determining which need to be saved. */
1091 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1093 if (picochip_reg_needs_saving (i
))
1094 num_regs_to_save
+= 1;
1097 return num_regs_to_save
* UNITS_PER_WORD
;
1101 /* Compute and return offset of the save area base. */
1103 picochip_save_area_byte_offset (void)
1105 int base_offset
= (picochip_frame_byte_offset () +
1106 picochip_frame_size_in_bytes ());
1108 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1114 /* Compute and return offset of the special register save area. This
1115 area can be found immediately above the normal save area. It must
1116 be aligned, to allow the registers to be saved and restored as a
1119 picochip_special_save_area_byte_offset (void)
1121 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1122 int offset
= (picochip_save_area_byte_offset () +
1123 picochip_save_area_size_in_bytes ());
1125 if ((offset
% byte_alignment
) != 0)
1126 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1132 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1134 picochip_can_eliminate_link_sp_save (void)
1136 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1137 changing during optimizations phases. So, this function returns different
1138 values when called from initial_elimination_offset and then again when it
1139 is called from prologue/epilogue generation. This means that argument
1140 accesses become wrong. This wouldnt happen only if we were not using the
1141 stack at all. The following conditions ensures that.*/
1143 return (crtl
->is_leaf
&&
1144 !df_regs_ever_live_p(LINK_REGNUM
) &&
1145 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1146 (picochip_special_save_area_byte_offset() == 0) &&
1147 (crtl
->args
.size
== 0) &&
1148 (crtl
->args
.pretend_args_size
== 0));
1151 /* Compute the size of the special reg save area (SP and LNK). If the
1152 SP/LNK registers don't need to be saved, this area can shrink to
1155 picochip_special_save_area_size_in_bytes (void)
1159 if (picochip_can_eliminate_link_sp_save ())
1162 return 2 * UNITS_PER_WORD
;
1165 /* Return the number of pretend arguments. If this function is
1166 varadic, all the incoming arguments are effectively passed on the
1167 stack. If this function has real pretend arguments (caused by a
1168 value being passed partially on the stack and partially in
1169 registers), then return the number of registers used. */
1171 picochip_pretend_arg_area_size (void)
1174 if (crtl
->args
.pretend_args_size
!= 0)
1176 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1178 return crtl
->args
.pretend_args_size
;
1180 else if (cfun
->stdarg
)
1187 /* Compute and return the offset of the pretend arguments. The pretend
1188 arguments are contiguous with the incoming arguments, and must be
1189 correctly aligned. */
1191 picochip_pretend_arg_area_byte_offset (void)
1193 int base_offset
= 0;
1195 base_offset
= (picochip_special_save_area_byte_offset () +
1196 picochip_special_save_area_size_in_bytes ());
1198 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1199 gcc_assert(picochip_is_aligned
1200 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1206 /* Compute and return the offset of the incoming arguments. If a
1207 static chain is in use, this will be passed just before the other
1208 arguments. This means that the pretend argument mechanism, used in
1209 variadic functions, doesn't work properly. Thus, static chains work
1210 on their own, as do variadic functions, but not the combination of
1211 the two. This isn't really a problem. */
1213 picochip_arg_area_byte_offset (void)
1215 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1216 picochip_pretend_arg_area_size ());
1218 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1219 the alignment on a 32-bit boundary must be maintained. */
1220 if (cfun
->static_chain_decl
!= NULL
)
1222 gcc_assert (!cfun
->stdarg
);
1226 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1233 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
1236 /* Special case - only one register needed. */
1237 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1240 /* We actually do not allocate acc0 ever. But, it seems like we need to
1241 make it look like a allocatable register for the dataflow checks to work
1242 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1247 /* General case - compute how much space in terms of units. */
1248 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1253 picochip_class_max_nregs (int reg_class
, enum machine_mode mode
)
1255 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1257 if (reg_class
== ACC_REGS
)
1260 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1267 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1268 argument pointer) by replacing it with a constant offset from the
1269 main stack register. */
1271 initial_elimination_offset (int from
, int to
)
1273 int offset_from_sp
= 0;
1275 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1276 offset_from_sp
= picochip_frame_byte_offset ();
1277 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1278 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1282 return offset_from_sp
;
1286 /* Compute and return the size of the incoming argument area. */
1288 picochip_arg_area_size_in_bytes (void)
1290 return crtl
->args
.size
;
1293 /* Determine whether the given register is valid. When the strict mode
1294 is used, only hard registers are valid, otherwise any register is
1297 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1300 /* Sanity check - non-registers shouldn't make it here, but... */
1301 if (REG
!= GET_CODE (x
))
1305 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1311 /* Determine whether the given constant is in the range required for
1312 the given base register. */
1314 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1316 HOST_WIDE_INT corrected_offset
;
1318 if (GET_MODE_SIZE (mode
) != 0)
1320 if (GET_MODE_SIZE(mode
) <= 4)
1322 /* We used to allow incorrect offsets if strict is 0. But, this would
1323 then rely on reload doing the right thing. We have had problems
1324 there before, and on > 4.3 compiler, there are no benefits. */
1325 if (offset
% GET_MODE_SIZE (mode
) != 0)
1327 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1331 if (offset
% 4 != 0)
1333 corrected_offset
= offset
/ 4;
1338 /* Default to the byte offset as supplied. */
1339 corrected_offset
= offset
;
1342 /* The offset from the base register can be different depending upon
1343 the base register. The stack/frame/argument pointer offsets can
1344 all be greater than a simple register-based offset. Note that the
1345 frame/argument pointer registers are actually eliminations of the
1346 stack pointer, so a value which is valid for an offset to, for
1347 example, the frame pointer, might be invalid for the stack
1348 pointer once the elimination has occurred. However, there is no
1349 need to handle this special case here, as the stack offset is
1350 always checked after elimination anyway, and the generated code
1351 seems to have identical performance. */
1352 if (regno
== STACK_POINTER_REGNUM
||
1353 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1354 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1356 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1360 /* Determine whether a given rtx is a legitimate address for machine_mode
1361 MODE. STRICT is non-zero if we're being strict - any pseudo that
1362 is not a hard register must be a memory reference. */
1364 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1368 switch (GET_CODE (x
))
1371 valid
= picochip_legitimate_address_register (x
, strict
);
1376 rtx base
= XEXP (x
, 0);
1377 rtx offset
= XEXP (x
, 1);
1378 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1384 valid
= (REG
== GET_CODE (base
) &&
1385 picochip_legitimate_address_register (base
, strict
) &&
1386 CONST_INT
== GET_CODE (offset
) &&
1387 picochip_const_ok_for_base (mode
, REGNO (base
),
1393 /* The user can select whether a symbol can be used as a memory
1394 address. Typically, this will decrease execution time (no
1395 register load is required first), but will increase code size
1396 (because the symbol will be used several times, rather than
1397 loaded once into a register.*/
1398 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1403 /* A constant memory address must be a (plus (symbol_ref)
1404 (const_int)), and is only allowed when the symbols are
1405 permitted addresses. */
1406 rtx inner
= XEXP (x
, 0);
1408 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1409 PLUS
== GET_CODE (inner
) &&
1410 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1411 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1425 /* For all memory operations, picochip allows a uconst4 offset value. It
1426 is hence beneficial to turn an
1427 addr = <reg + long_const>
1432 X = reg + long_const & FFF0
1433 diff = long_const - (long_const & FFF0)
1436 X can be reused in subsequent memory operations.
1439 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1440 enum machine_mode mode
)
1447 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1463 if (GET_CODE (x
) == PLUS
1464 && GET_CODE (XEXP (x
, 0)) == REG
1465 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1467 int high_val
, low_val
, offset
;
1468 offset
= INTVAL (XEXP (x
, 1));
1469 /* Ignore cases with negative offsets. */
1472 high_val
= offset
& mask_val
;
1473 low_val
= offset
- high_val
;
1476 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1477 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1484 /* For all memory operations, picochip allows a uconst4 offset value. It
1485 is hence beneficial to turn an
1486 addr = <reg + long_const>
1491 X = reg + long_const & FFF0
1492 diff = long_const - (long_const & FFF0)
1495 X can be reused in subsequent memory operations.
1498 picochip_legitimize_reload_address (rtx
*x
,
1499 enum machine_mode mode
,
1500 int opnum
, int type
,
1501 int ind_levels ATTRIBUTE_UNUSED
)
1505 if (picochip_symbol_offset(*x
))
1507 *x
= gen_rtx_CONST(mode
, *x
);
1513 /* We should recognise addresses that we created.*/
1514 if (GET_CODE (*x
) == PLUS
1515 && GET_CODE (XEXP (*x
, 0)) == PLUS
1516 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1517 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1518 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1520 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1521 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1522 opnum
, (enum reload_type
)type
);
1526 /* Depending on mode, the offsets allowed are either 16/32/64. */
1542 if (GET_CODE (*x
) == PLUS
1543 && GET_CODE (XEXP (*x
, 0)) == REG
1544 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1546 int high_val
, low_val
, offset
;
1547 offset
= INTVAL (XEXP (*x
, 1));
1548 /* Ignore cases with negative offsets. */
1551 high_val
= offset
& mask_val
;
1552 low_val
= offset
- high_val
;
1555 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1556 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1557 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1558 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1559 opnum
, (enum reload_type
)type
);
1567 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1569 picochip_symbol_offset (rtx operand
)
1572 return (PLUS
== GET_CODE (operand
) &&
1573 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1574 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1578 /* Assembly output. */
1580 /* The format here should match the format used in the output of
1581 symbol_ref's elsewhere in this file. */
1583 picochip_output_label (FILE * stream
, const char name
[])
1585 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1587 /* If VLIW scheduling is in use, any Call Frame Information labels
1588 generated inside a packet must have their output deferred until
1589 the end of the packet. */
1590 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1591 is_cfi_label
&& picochip_vliw_continuation
)
1593 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1595 internal_error ("LCFI labels have already been deferred");
1597 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1598 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1599 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1603 assemble_name (stream
, name
);
1605 if (strncmp (name
, "picoMark_", 9) == 0)
1606 fprintf (stream
, "=\n");
1608 fprintf (stream
, ":\n");
1614 /* The format here should match the format used in the output of
1615 symbol_ref's elsewhere in this file. */
1617 picochip_output_labelref (FILE * stream
, const char name
[])
1619 fprintf (stream
, "_%s", name
);
1623 picochip_weaken_label (FILE * stream
, const char name
[])
1625 fprintf (stream
, ".weak ");
1626 assemble_name (stream
, name
);
1627 fprintf (stream
, "\n");
1630 /* Return true if the given label (or label prefix) denotes a marker
1631 label which should be emitted in the form LABEL= */
1633 picochip_is_marker_prefix (const char *prefix
)
1635 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1636 && strcmp (prefix
, "LP") != 0);
1640 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1644 /* Emit different types of label, based upon their prefix. They
1645 are handled differently to allow the assembler to ensure that
1646 branch target labels are properly aligned, while other labels
1647 will only serve as code markers, not branch targets. Aligning
1648 labels unnecessarily can result in much code wastage. */
1649 if (picochip_is_marker_prefix (prefix
))
1651 /* Special label marker. If it appears in the middle of a VLIW
1652 packet, defer it until the end of the packet. There has
1653 never been a need to handle more than one lm label at a time. */
1654 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1655 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1657 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1658 internal_error ("LM label has already been deferred");
1660 sprintf (picochip_current_vliw_state
.lm_label_name
,
1661 "picoMark_%s%ld", prefix
, num
);
1663 else if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1664 (strcmp (prefix
, "LCFI")) == 0 && picochip_vliw_continuation
)
1666 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1668 internal_error ("LCFI labels have already been deferred.");
1670 sprintf(picochip_current_vliw_state
.cfi_label_name
[
1671 picochip_current_vliw_state
.num_cfi_labels_deferred
],
1672 "picoMark_%s%ld", prefix
, num
);
1673 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1678 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1685 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1691 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1693 /* Two types of internal label can be generated: branch target
1694 labels and code marker labels. Branch target labels must always
1695 be aligned (since code will execute at these
1696 points). Differentiate between the two by prepending markers with
1697 a unique prefix, which can later be used in output_label to
1698 figure out which label syntax to use. */
1699 if (picochip_is_marker_prefix (prefix
))
1700 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1702 sprintf (str
, "%s%ld", prefix
, num
);
1707 picochip_asm_output_anchor (rtx symbol
)
1709 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1710 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1714 picochip_output_aligned_common (FILE * stream
, const char *name
,
1715 unsigned size
, unsigned alignment
)
1718 fprintf (stream
, ".commonData ");
1719 assemble_name (stream
, name
);
1720 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1721 picochip_output_global (stream
, name
);
1726 picochip_output_aligned_local (FILE * stream
, const char *name
,
1727 unsigned size
, unsigned alignment
)
1730 fprintf (stream
, ".commonData ");
1731 assemble_name (stream
, name
);
1732 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1737 picochip_output_global (FILE * stream
, const char *name
)
1739 fprintf (stream
, ".global ");
1740 assemble_name (stream
, name
);
1741 fprintf (stream
, "\n");
1744 /* Output an assembly language string. Output as a sequence of decimal
1745 numbers, followed by the literal string to make it obvious what the
1746 numbers represent. */
1748 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1752 fprintf (file
, ".ascii ");
1754 for (i
= 0; i
< length
; ++i
)
1756 fprintf (file
, "16#%x# ", (char) (str
[i
]));
1759 fprintf (file
, " ; ");
1761 for (i
= 0; i
< length
; ++i
)
1768 fprintf (file
, "\\n");
1771 fprintf (file
, "\\t");
1774 fprintf (file
, "\\0");
1777 fprintf (file
, "%c", c
);
1782 fprintf (file
, "\n");
1786 /* Output the beginning of an ASM file. */
1788 picochip_asm_file_start (void)
1790 default_file_start ();
1792 fprintf (asm_out_file
, "// picoChip ASM file\n");
1793 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1795 fprintf (asm_out_file
, "// Has byte access: %s\n",
1796 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1798 if (TARGET_HAS_MUL_UNIT
)
1799 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1800 else if (TARGET_HAS_MAC_UNIT
)
1801 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1803 fprintf (asm_out_file
, "// Has multiply: No\n");
1806 /* Output the end of an ASM file. */
1808 picochip_asm_file_end (void)
1810 /* Include a segment end to make it easy for PERL scripts to grab
1811 segments. This is now done by assembler*/
1813 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1817 /* Output frame debug information to the given stream. */
1819 picochip_output_frame_debug (FILE * file
)
1824 fprintf (file
, "\t\t// Leaf function\n");
1826 fprintf (file
, "\t\t// Non-leaf function\n");
1828 if (picochip_can_eliminate_link_sp_save ())
1829 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1831 if (cfun
->static_chain_decl
!= NULL
)
1832 fprintf (file
, "\t\t// Static chain in use\n");
1834 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1835 picochip_arg_area_size_in_bytes ());
1836 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1837 picochip_arg_area_byte_offset ());
1838 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1839 picochip_pretend_arg_area_size ());
1840 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1841 picochip_pretend_arg_area_byte_offset ());
1842 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1843 picochip_special_save_area_size_in_bytes ());
1844 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1845 picochip_special_save_area_byte_offset ());
1847 /* Output which registers are saved. */
1848 fprintf (file
, "\t\t// Saved regs: ");
1849 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1851 if (picochip_reg_needs_saving (i
))
1852 fprintf (file
, "%s ", picochip_regnames
[i
]);
1854 fprintf (file
, "\t\t\n");
1856 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1857 picochip_save_area_size_in_bytes ());
1858 fprintf (file
, "\t\t// Save area offset: %d\n",
1859 picochip_save_area_byte_offset ());
1861 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1862 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1863 picochip_frame_byte_offset ());
1865 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1866 crtl
->outgoing_args_size
);
1870 /* Output picoChip function prologue. This contains human-readable
1871 information about the function. */
1873 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1875 /* Get the function's name, as described by its RTL. This may be
1876 different from the DECL_NAME name used in the source file. The
1877 real declaration name must be used, to ensure that the prologue
1878 emits the right information for the linker. */
1881 x
= DECL_RTL (current_function_decl
);
1882 gcc_assert (MEM_P (x
));
1884 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1885 fnname
= XSTR (x
, 0);
1887 /* Note that the name of the function is given in the &_%s
1888 form. This matches the name of the function as used in labels,
1889 and function calls, and enables processCallGraph to match
1890 function calls to the name of the function, as defined here. */
1891 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1892 fnname
, picochip_arg_area_byte_offset ());
1894 picochip_output_frame_debug (file
);
1895 fprintf (file
, "\n");
1899 /* Output picoChip function epilogue. */
1901 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1906 x
= DECL_RTL (current_function_decl
);
1907 gcc_assert (MEM_P (x
));
1909 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1910 fnname
= XSTR (x
, 0);
1911 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1915 /* Manipulate the asm output. Some machines only execute the code when
1916 there is actually a chance of needing it (e.g., FRV doesn't execute
1917 it if the scheduling pass wasn't used). We always execute it,
1918 simple to ensure that it is exercised more often, and bugs are more
1921 This function's prime reason for existence is to insert the VLIW
1922 separators where appropriate. The separators must be inserted
1923 before any comments which appear at the end of the file.
1927 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1931 /* Flag to specify when a VLIW continuation has been inserted onto
1932 the line. Continuations are either inserted before any comments,
1933 or before the end of the line is reached. The flag ensures that
1934 we don't insert continuations twice (i.e., at the comment and the
1936 int continuation_inserted
= 0;
1938 /* If the instruction uses multiple lines (i.e., a new line
1939 character appears in the opcode), then ensure that no attempt is
1940 made to pack it into a VLIW. */
1941 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1943 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s",
1947 /* If a delay slot is pending, output the directive to the assembler
1948 before the instruction. */
1949 if (picochip_is_delay_slot_pending
)
1951 picochip_is_delay_slot_pending
= 0;
1955 /* Keep going for entire opcode. All substitution performed ourselves. */
1960 /* Determine whether a VLIW continuation must be inserted before
1961 any comments, or the end of the opcode. A flag is set to show
1962 that we have inserted a continuation on this line, so that we
1963 don't try to insert another continuation when the end of the
1964 opcode is reached. The only other case for a continuation
1965 might have been a newline, but these aren't allowed in
1966 conjunction with VLIW continuations (see above code). */
1967 if (picochip_vliw_continuation
&&
1968 !continuation_inserted
&&
1969 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1972 continuation_inserted
= 1;
1975 /* Detect an explicit VLIW separator. */
1976 if (c
== '%' && (*ptr
== '|'))
1981 /* Detect the need for an ALU id operand. */
1982 else if (c
== '%' && (*ptr
== '#'))
1984 fputc (picochip_get_vliw_alu_id (), f
);
1987 printf ("Generated ALU char at %s for insn %d\n", ptr
,
1988 INSN_UID (picochip_current_prescan_insn
));
1990 /* Skip past unwanted # */
1993 /* Detect the need for branch delay slot. */
1994 else if (c
== '%' && (*ptr
== '>'))
1996 /* Only emit delay slots (NOP's, or otherwise) when delay
1997 * slot scheduling has actually been enabled, otherwise VLIW
1998 * scheduling and delay slot scheduling output combine to
1999 * produce nasty effects. */
2000 if (flag_delayed_branch
)
2002 if (dbr_sequence_length () == 0)
2003 fputs ("\n=->\tNOP", f
);
2005 picochip_is_delay_slot_pending
= 1;
2008 /* Skip past unwanted > */
2011 /* Detect any %digit specifiers. */
2012 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
2015 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
2016 while ((c
= *ptr
) >= '0' && c
<= '9')
2019 /* Detect any %letterdigit specifiers. */
2020 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2021 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2023 int letter
= *ptr
++;
2030 output_asm_label (recog_data
.operand
[c
]);
2034 output_address (recog_data
.operand
[c
]);
2038 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
2041 while ((c
= *ptr
) >= '0' && c
<= '9')
2046 ("picochip_asm_output_opcode - can%'t output unknown operator %c",
2052 /* Reached the end of the packet. If any labels were deferred
2053 during output, emit them now. */
2054 if (!picochip_vliw_continuation
)
2056 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
2059 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
2061 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
2064 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
2069 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
2072 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
2077 /* Output an end-of-packet marker if requested. */
2078 if (!picochip_vliw_continuation
&&
2079 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
2080 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
2085 /* Function RTL expansion. */
2087 /* Expand the prologue into RTL. */
2089 picochip_expand_prologue (void)
2091 int stack_adjustment
= 0;
2092 int special_save_offset
= 0;
2093 int general_save_offset
= 0;
2094 int reg_save_offset
= 0;
2097 stack_adjustment
= picochip_arg_area_byte_offset ();
2098 general_save_offset
=
2099 -(stack_adjustment
- picochip_save_area_byte_offset ());
2100 special_save_offset
=
2101 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2103 /* Save the link registers. We could try to save just one register
2104 here. This would reduce the amount of stack space required.
2105 There hasn't been a good reason to do that so far. */
2106 if (!picochip_can_eliminate_link_sp_save ())
2107 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2108 special_save_offset
);
2110 /* Save callee-save registers. */
2111 reg_save_offset
= 0;
2112 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2114 if (picochip_reg_needs_saving (i
))
2117 /* If this register is an even numbered register, and the
2118 next register also needs to be saved, use a SImode save,
2119 which does both in one instruction. Note that a special
2120 check is performed to ensure that the double word aligned
2121 store is valid (e.g., it is possible that r6, r8, r9 need
2122 to be saved, in which case once r6 has been saved, the
2123 stored offset is no longer aligned, and an STL/LDL
2124 instruction becomes invalid). Alternately, we could store all
2125 aligned registers first and then save the single one(s). */
2127 picochip_reg_needs_saving (i
+ 1) &&
2128 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2130 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2131 general_save_offset
+
2133 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2138 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2139 general_save_offset
+
2141 reg_save_offset
+= UNITS_PER_WORD
;
2147 /* Emit a stack adjustment where required. */
2148 if (stack_adjustment
!= 0)
2149 picochip_emit_stack_allocate (stack_adjustment
);
2151 /* If this function uses varadic arguments, write any unnamed
2152 registers to the stack. */
2155 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2157 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2158 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2160 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2161 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2163 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2170 /* Expand the epilogue into RTL. */
2172 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2174 int stack_adjustment
= 0;
2175 int special_save_offset
= 0;
2176 int general_save_offset
= 0;
2177 int reg_save_offset
= 0;
2179 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2182 stack_adjustment
= picochip_arg_area_byte_offset ();
2183 general_save_offset
=
2184 -(stack_adjustment
- picochip_save_area_byte_offset ());
2185 special_save_offset
=
2186 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2188 /* Emit a stack adjustment where required. */
2189 if (stack_adjustment
!= 0)
2191 /* If the link/fp is already being restored, and the offset to
2192 their save location is small enough, don't bother adjusting
2193 the stack explicitly. */
2194 if (picochip_special_save_area_byte_offset () < 512 &&
2195 !picochip_can_eliminate_link_sp_save ())
2196 use_link_fp_restore_stack_adjust
= 1;
2198 /* Explicitly restore the stack. */
2199 picochip_emit_stack_allocate (-stack_adjustment
);
2202 /* Restore the Link/FP registers. Only save the link register? */
2203 if (!picochip_can_eliminate_link_sp_save ())
2205 if (use_link_fp_restore_stack_adjust
)
2206 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2207 picochip_special_save_area_byte_offset
2210 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2211 special_save_offset
);
2214 /* Restore callee-save registers. */
2215 reg_save_offset
= 0;
2216 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2218 if (picochip_reg_needs_saving (i
))
2221 /* If this register is an even numbered register, and the
2222 next register also needs to be saved, use a SImode save,
2223 which does both in one instruction. Note that a special
2224 check is performed to ensure that the double word aligned
2225 store is valid (e.g., it is possible that r6, r8, r9 need
2226 to be saved, in which case once r6 has been saved, the
2227 stored offset is no longer aligned, and an STL/LDL
2228 instruction becomes invalid). We could store all aligned
2229 registers first, and then save the single one(s). */
2231 picochip_reg_needs_saving (i
+ 1) &&
2232 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2234 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2235 general_save_offset
+
2237 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2242 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2243 general_save_offset
+
2245 reg_save_offset
+= UNITS_PER_WORD
;
2251 /* Emit a return instruction, which matches a (parallel
2252 [(return) (use r12)]) */
2255 p
= rtvec_alloc (2);
2257 RTVEC_ELT (p
, 0) = ret_rtx
;
2258 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2259 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2260 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2265 /* Assembly instruction output. */
2267 /* Test whether the given branch instruction is short, or long. Short
2268 * branches are equivalent to real branches, and may be DFA
2269 * scheduled. Long branches expand to a macro which is handled by the
2270 * elaborator, and cannot be scheduled. Occasionally, the branch
2271 * shortening pass, which is run after DFA scheduling, will change the
2272 * code layout and cause the short branch to be reverted into a long
2273 * branch. Instead of having to fix this up by emitting new assembly,
2274 * the short branch is emitted anyway. There is plenty of slack in the
2275 * calculation of long and short branches (10-bit offset, but only
2276 * 9-bits used in computation), so there is enough slack for this to
2279 picochip_is_short_branch (rtx insn
)
2281 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2283 return (isRealShortBranch
||
2284 picochip_current_vliw_state
.num_insns_in_packet
> 1);
2287 /* Output a compare-and-branch instruction (matching the cbranch
2290 picochip_output_cbranch (rtx operands
[])
2293 if (HImode
!= GET_MODE (operands
[1]) ||
2294 (HImode
!= GET_MODE (operands
[2]) &&
2295 GET_CODE (operands
[2]) != CONST_INT
))
2297 internal_error ("%s: at least one operand can%'t be handled",
2301 /* Use the type of comparison to output the appropriate condition
2303 switch (GET_CODE (operands
[0]))
2306 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2309 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2312 /* Reverse the operand order to be GE */
2313 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2316 /* Reverse operand order of GEU. */
2317 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2320 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2323 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2326 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2329 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2332 /* Reversed operand version of LT. */
2333 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2336 /* Reverse an LTU. */
2337 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2344 /* Output a compare-and-branch instruction (matching the cbranch
2345 pattern). This function is current unused since the cbranch
2346 split is disabled. The function is kept around so we can use
2347 it when we understand how to do cbranch split safely. */
2349 picochip_output_compare (rtx operands
[])
2353 if (HImode
!= GET_MODE (operands
[1]) ||
2354 (HImode
!= GET_MODE (operands
[2]) &&
2355 GET_CODE (operands
[2]) != CONST_INT
))
2357 internal_error ("%s: at least one operand can%'t be handled",
2361 code
= GET_CODE (operands
[0]);
2362 /* Use the type of comparison to output the appropriate condition
2367 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2370 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2373 /* Reverse the operand order to be GE */
2374 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2377 /* Reverse operand order of GEU. */
2378 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2381 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2384 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2387 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2390 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2393 /* Reversed operand version of LT. */
2394 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2397 /* Reverse an LTU. */
2398 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2405 /* Output the branch insn part of a compare-and-branch split. */
2407 picochip_output_branch (rtx operands
[], rtx insn
)
2410 int code
= GET_CODE(operands
[2]);
2411 if (picochip_is_short_branch (insn
))
2413 /* Short branches can be output directly using the
2414 appropriate instruction. */
2418 return ("BNE %l0 %>");
2420 return ("BEQ %l0 %>");
2422 return ("BGE %l0 %>");
2424 return ("BHS %l0 %>");
2426 return ("BGE %l0 %>");
2428 return ("BHS %l0 %>");
2430 return ("BLT %l0 %>");
2432 return ("BLO %l0 %>");
2434 return ("BLT %l0 %>");
2436 return ("BLO %l0 %>");
2438 internal_error ("unknown short branch in %s (type %d)",
2439 __FUNCTION__
, (int) INTVAL (operands
[1]));
2440 return "UNKNOWN_BRANCH";
2445 /* Long branches result in the emission of a special
2446 instruction, which the assembler expands into a suitable long
2449 /* Use the type of comparison to output the appropriate condition
2454 return ("JMPNE %l0 %>");
2456 return ("JMPEQ %l0 %>");
2458 return ("JMPGE %l0 %>");
2460 return ("JMPHS %l0 %>");
2462 return ("JMPGE %l0 %>");
2464 return ("JMPHS %l0 %>");
2466 return ("JMPLT %l0 %>");
2468 return ("JMPLO %l0 %>");
2470 return ("JMPLT %l0 %>");
2472 return ("JMPLO %l0 %>");
2475 internal_error ("unknown long branch in %s (type %d)",
2476 __FUNCTION__
, (int) INTVAL (operands
[1]));
2477 return "UNKNOWN_BRANCH";
2483 /* Output a jump instruction. */
2485 picochip_output_jump (rtx insn
)
2487 if (picochip_is_short_branch (insn
))
2490 return "JMPRA %l0%>";
2494 picochip_output_put_array (int alternative
, rtx operands
[])
2496 /* Local output buffer. */
2499 int portArraySize
= INTVAL(operands
[1]);
2500 int portBaseIndex
= INTVAL(operands
[2]);
2502 if (alternative
== 0)
2504 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2505 portArraySize
, portBaseIndex
);
2506 output_asm_insn (buf
, operands
);
2508 else if (alternative
== 1)
2510 /* Constant port id. Emit a real instruction. */
2511 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2512 if (portIndex
< portBaseIndex
||
2513 portIndex
>= (portBaseIndex
+ portArraySize
))
2515 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2516 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2518 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2519 output_asm_insn (buf
, operands
);
2524 /* Both alternatives output the insn directly. */
2528 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2530 /* Local output buffer. */
2533 int portArraySize
= INTVAL(operands
[1]);
2534 int portBaseIndex
= INTVAL(operands
[2]);
2536 if (alternative
== 0)
2538 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2539 portArraySize
, portBaseIndex
);
2540 output_asm_insn (buf
, operands
);
2542 else if (alternative
== 1)
2544 /* Constant port id. Emit a real instruction. */
2545 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2546 if (portIndex
< portBaseIndex
||
2547 portIndex
>= (portBaseIndex
+ portArraySize
))
2549 error ("GET uses port array index %d, which is out of range [%d..%d)",
2550 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2552 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2553 output_asm_insn (buf
, operands
);
2558 /* Both alternatives output the insn directly. */
2562 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2564 /* Local output buffer. */
2567 int portArraySize
= INTVAL(operands
[2]);
2568 int portBaseIndex
= INTVAL(operands
[3]);
2570 if (alternative
== 0)
2572 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2573 portArraySize
, portBaseIndex
);
2574 output_asm_insn (buf
, operands
);
2576 else if (alternative
== 1)
2578 /* Constant port id. Emit a real instruction. */
2579 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2580 if (portIndex
< portBaseIndex
||
2581 portIndex
>= (portBaseIndex
+ portArraySize
))
2583 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2584 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2586 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2587 output_asm_insn (buf
, operands
);
2592 /* Both alternatives output the insn directly. */
2596 /* Output a comparison operand as a symbol (e.g., >). */
2598 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2603 /* Output just the comparison symbol. */
2604 switch (GET_CODE (operand
))
2607 fprintf (file
, "!=");
2610 fprintf (file
, "==");
2613 fprintf (file
, ">=");
2616 fprintf (file
, ">={U}");
2619 fprintf (file
, "<");
2622 fprintf (file
, "<{U}");
2625 fprintf (file
, "<=");
2628 fprintf (file
, "<={U}");
2631 fprintf (file
, ">");
2634 fprintf (file
, ">{U}");
2642 /* Output the comparison formatted as operand,symbol,operand */
2643 rtx op0
= XEXP (operand
, 0);
2644 rtx op1
= XEXP (operand
, 1);
2646 picochip_print_operand (file
, op0
, 0);
2647 picochip_print_comparison (file
, operand
, 'i');
2648 picochip_print_operand (file
, op1
, 0);
2652 /* This function generates a memory address operand in the given
2653 mode. That is, if the address contains a constant offset, then the
2654 offset is divided by the required mode size to compute the
2655 mode specific offset. By default, picochip_print_operand_address calls
2656 this function using the natural mode of the operand, but special
2657 operand codes can be used to invoke the computation using an
2658 unnatural mode (e.g., compute the HI aligned address of an SI mode
2661 picochip_print_memory_address (FILE * file
, rtx operand
,
2662 enum machine_mode mode
)
2664 rtx address
= XEXP (operand
, 0);
2667 if (MEM
!= GET_CODE (operand
))
2668 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2673 printf ("picochip_print_memory_address: ");
2674 print_rtl (stdout
, operand
);
2678 switch (GET_CODE (address
))
2682 /* Grab the address components. */
2683 rtx base
= XEXP (address
, 0);
2684 rtx offset
= XEXP (address
, 1);
2686 /* Only handle reg+const addresses */
2687 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2689 /* Sanity check. If an FP+offset address is given, ensure
2690 that the offset lies within the given frame, or a lower
2692 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2693 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2696 /* Print the base register - identical for all modes. */
2697 fprintf (file
, "(");
2698 picochip_print_operand (file
, base
, 'r');
2699 fprintf (file
, ")");
2701 /* Print the constant offset with compensation for the mode. */
2705 picochip_print_operand (file
, offset
, 'Q');
2709 picochip_print_operand (file
, offset
, 'H');
2714 picochip_print_operand (file
, offset
, 'S');
2718 picochip_print_operand (file
, offset
, 'D');
2732 picochip_print_operand (file
, address
, 's');
2741 inner
= XEXP (address
, 0);
2743 /* Sanity check - the CONST memory address must be a base+offset. */
2744 gcc_assert (PLUS
== GET_CODE (inner
));
2746 base
= XEXP (inner
, 0);
2747 offset
= XEXP (inner
, 1);
2749 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2755 /* Register operand. Provide a zero offset. */
2756 fprintf (file
, "(");
2757 picochip_print_operand (file
, address
, 'r');
2758 fprintf (file
, ")0");
2767 /* Output an operand. Formatting letters allow particular parts of
2768 the operand to be output. */
2770 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2773 /* Handle special cases. */
2776 /* VLIW continuation, for explicit VLIW sequences. */
2778 fprintf (file
, "\\");
2783 fputc (picochip_get_vliw_alu_id (), file
);
2786 /* Delay slot specifier. */
2788 /* This should be handled in asm_output_opcode. */
2791 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2793 switch (GET_CODE (operand
))
2796 fprintf (file
, "AND");
2799 fprintf (file
, "OR");
2802 fprintf (file
, "XOR");
2805 fprintf (file
, "ADD");
2808 fprintf (file
, "SUB");
2815 /* Symbolic instructions (e.g., lshift becomes <<). */
2817 switch (GET_CODE (operand
))
2820 fprintf (file
, "&");
2823 fprintf (file
, "|");
2826 fprintf (file
, "^");
2829 fprintf (file
, "+");
2832 fprintf (file
, "-");
2835 fprintf (file
, "UNKNOWN_INSN");
2840 default: /* Not a punctuation character - process as normal. */
2844 switch (GET_CODE (operand
))
2850 /* Write a range of registers. */
2851 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2855 /* The upper register of a pair is requested. */
2856 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2860 /* The lower register of a pair is requested. Equivalent to the
2861 default, but included for completeness. */
2862 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2866 /* The 3rd register of a DI mode register. */
2867 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2871 /* The 4th register of a DI mode register. */
2872 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2876 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2881 /* A range of letters can be used to format integers. The
2882 letters Q/H/S are used to divide the constant by the width of
2883 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2884 to obtain the upper and lower 16-bits of a 32-bit
2885 constant. Where possible, signed numbers are used, since
2886 signed representations of numbers may be more compact (e.g.,
2887 65535 can be represented as -1, which fits into a small
2888 constant, whereas 65535 requires a large constant). */
2892 fprintf (file
, "%ld", INTVAL (operand
));
2896 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2900 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2904 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2908 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2912 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2916 fprintf (file
, "%ld", INTVAL (operand
));
2926 if (GET_MODE (operand
) != SFmode
)
2927 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2929 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2930 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2935 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2939 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2947 /* Output a symbol. The output format must match that of
2948 picochip_output_label. */
2950 /* Ensure that the symbol is marked as referenced. Gcc can
2951 occasionally omit the function bodies when it believes them
2952 to be unreferenced. */
2953 if (SYMBOL_REF_DECL (operand
))
2954 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2955 fprintf (file
, "&");
2956 assemble_name (file
, XSTR (operand
, 0));
2960 /* This format must match that of picochip_output_label. */
2961 fprintf (file
, "&");
2962 output_asm_label (operand
);
2967 rtx addr
= XEXP (operand
, 0);
2972 if (PLUS
!= GET_CODE (addr
))
2973 fatal_insn ("Bad address, not (reg+disp):", addr
);
2975 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2979 /* Output a memory address in byte mode notation (i.e., the
2980 constant address (if any) is the actual byte address. */
2981 picochip_print_memory_address (file
, operand
, QImode
);
2984 /* Output a constant offset of the given mode (i.e., divide
2985 the constant by the number of units in the mode to get the
2988 picochip_print_memory_address (file
, operand
, QImode
);
2992 picochip_print_memory_address (file
, operand
, HImode
);
2996 picochip_print_memory_address (file
, operand
, SImode
);
3000 picochip_print_memory_address (file
, operand
, SFmode
);
3004 if (PLUS
!= GET_CODE (addr
))
3005 fatal_insn ("Bad address, not (reg+disp):", addr
);
3007 picochip_print_operand (file
, XEXP (addr
, 0), 0);
3010 /* When the mem operand is (reg + big offset) which cannot
3011 be represented in an instruction as operand, the compiler
3012 automatically generates the instruction to put in (reg +
3013 big offset) into another register. In such cases, it
3014 returns '0' as the character. This needs to be handled
3018 if (REG
!= GET_CODE (addr
))
3019 fatal_insn ("Bad address, not register:", addr
);
3021 picochip_print_operand (file
, addr
, 0);
3025 fprintf (file
, "Unknown mem operand - letter %c ",
3027 print_rtl (file
, operand
);
3035 rtx const_exp
= XEXP (operand
, 0);
3037 /* Handle constant offsets to symbol references. */
3038 if (PLUS
== GET_CODE (const_exp
) &&
3039 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
3040 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
3043 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
3044 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
3045 fprintf (file
, "+");
3046 /* else use the - from the operand (i.e., AP-2)) */
3048 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
3057 /* PLUS expressions are of the form (base + offset). Different
3058 options (analagous to those of memory PLUS expressions) are used
3059 to extract the base and offset components. */
3064 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3068 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3073 /* If the expression is composed entirely of constants,
3074 evaluate the result. This should only occur with the
3075 picoChip specific comms instructions, which are emitted as
3076 base+offset expressions. */
3077 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
3078 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
3080 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
3081 XINT (XEXP (operand
, 1), 0));
3082 fprintf (file
, "%ld", result
);
3086 fprintf (file
, "(");
3087 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3088 fprintf (file
, "+");
3089 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3090 fprintf (file
, ")");
3097 /* Comparison operations. */
3108 picochip_print_comparison (file
, operand
, letter
);
3112 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3113 print_rtl (file
, operand
);
3120 /* Output an operand address */
3122 picochip_print_operand_address (FILE * file
, rtx operand
)
3125 switch (GET_CODE (operand
))
3129 /* This format must match that of picochip_output_label. */
3130 assemble_name (file
, XSTR (operand
, 0));
3134 /* Note this format must match that of picochip_output_label. */
3135 fprintf (file
, "_L%d", XINT (operand
, 5));
3139 /* Pass on to a specialised memory address generator. */
3140 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3151 /* Scheduling functions. */
3153 /* Save some of the contents of recog_data. */
3155 picochip_save_recog_data (void)
3157 picochip_saved_which_alternative
= which_alternative
;
3158 memcpy (&picochip_saved_recog_data
, &recog_data
,
3159 sizeof (struct recog_data_d
));
3162 /* Restore some of the contents of global variable recog_data. */
3164 picochip_restore_recog_data (void)
3166 which_alternative
= picochip_saved_which_alternative
;
3167 memcpy (&recog_data
, &picochip_saved_recog_data
,
3168 sizeof (struct recog_data_d
));
3171 /* Ensure that no var tracking notes are emitted in the middle of a
3172 three-instruction bundle. */
3174 reorder_var_tracking_notes (void)
3178 FOR_EACH_BB_FN (bb
, cfun
)
3180 rtx insn
, next
, last_insn
= NULL_RTX
;
3181 rtx queue
= NULL_RTX
;
3183 /* Iterate through the bb and find the last non-debug insn */
3184 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= NEXT_INSN(insn
))
3186 if (NONDEBUG_INSN_P(insn
))
3190 /* In all normal cases, queue up notes and emit them just before a TImode
3191 instruction. For the last instruction, emit the queued notes just after
3192 the last instruction. */
3193 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= next
)
3195 next
= NEXT_INSN (insn
);
3197 if (insn
== last_insn
)
3201 rtx next_queue
= PREV_INSN (queue
);
3202 PREV_INSN (NEXT_INSN(insn
)) = queue
;
3203 NEXT_INSN(queue
) = NEXT_INSN(insn
);
3204 PREV_INSN(queue
) = insn
;
3205 NEXT_INSN(insn
) = queue
;
3208 /* There is no more to do for this bb. break*/
3211 else if (NONDEBUG_INSN_P (insn
))
3213 /* Emit queued up notes before the first instruction of a bundle. */
3214 if (GET_MODE (insn
) == TImode
)
3218 rtx next_queue
= PREV_INSN (queue
);
3219 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3220 PREV_INSN (queue
) = PREV_INSN(insn
);
3221 PREV_INSN (insn
) = queue
;
3222 NEXT_INSN (queue
) = insn
;
3227 else if (NOTE_P (insn
))
3229 rtx prev
= PREV_INSN (insn
);
3230 PREV_INSN (next
) = prev
;
3231 NEXT_INSN (prev
) = next
;
3232 /* Ignore call_arg notes. They are expected to be just after the
3233 call insn. If the call is start of a long VLIW, labels are
3234 emitted in the middle of a VLIW, which our assembler can not
3236 if (NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
3238 PREV_INSN (insn
) = queue
;
3243 /* Make sure we are not dropping debug instructions.*/
3244 gcc_assert (queue
== NULL_RTX
);
3248 /* Perform machine dependent operations on the rtl chain INSNS. */
3250 picochip_reorg (void)
3252 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3253 int vliw_insn_location
= 0;
3255 /* We are freeing block_for_insn in the toplev to keep compatibility
3256 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3257 compute_bb_for_insn ();
3262 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3264 timevar_push (TV_SCHED2
);
3266 /* Process the instruction list, computing the sizes of each
3267 instruction, and consequently branch distances. This can
3268 result in some branches becoming short enough to be treated
3269 as a real branch instruction, rather than an assembly branch
3270 macro which may expand into multiple instructions. The
3271 benefit of shortening branches is that real branch
3272 instructions can be properly DFA scheduled, whereas macro
3274 shorten_branches (get_insns ());
3276 /* Do control and data sched analysis again,
3277 and write some more of the results to dump file. */
3283 timevar_pop (TV_SCHED2
);
3287 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3289 /* Whenever a VLIW packet is generated, all instructions in
3290 that packet must appear to come from the same source
3291 location. The following code finds all the VLIW packets,
3292 and tags their instructions with the location of the first
3293 instruction from the packet. Clearly this will result in
3294 strange behaviour when debugging the code, but since
3295 debugging and optimisation are being used in conjunction,
3296 strange behaviour is certain to occur anyway. */
3297 /* Slight bit of change. If the vliw set contains a branch
3298 or call instruction, we pick its location.*/
3299 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3302 /* If this is the first instruction in the VLIW packet,
3303 extract its location. */
3304 if (GET_MODE (insn
) == TImode
)
3307 vliw_insn_location
= INSN_LOCATION (insn
);
3309 if (JUMP_P (insn
) || CALL_P(insn
))
3311 vliw_insn_location
= INSN_LOCATION (insn
);
3312 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3313 INSN_LOCATION (insn1
) = vliw_insn_location
;
3315 /* Tag subsequent instructions with the same location. */
3316 INSN_LOCATION (insn
) = vliw_insn_location
;
3322 /* Locate the note marking the end of the function's prologue. If
3323 the note appears in the middle of a VLIW packet, move the note to
3324 the end. This avoids unpleasant consequences such as trying to
3325 emit prologue markers (e.g., .loc/.file directives) in the middle
3327 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3329 rtx prologue_end_note
= NULL
;
3330 rtx last_insn_in_packet
= NULL
;
3332 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3334 /* The prologue end must be moved to the end of the VLIW packet. */
3335 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3337 prologue_end_note
= insn
;
3342 /* Find the last instruction in this packet. */
3343 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3345 if (GET_MODE (insn
) == TImode
)
3348 last_insn_in_packet
= insn
;
3351 if (last_insn_in_packet
!= NULL
)
3354 = emit_note_after ((enum insn_note
) NOTE_KIND (prologue_end_note
),
3355 last_insn_in_packet
);
3356 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3357 delete_insn (prologue_end_note
);
3361 if (flag_var_tracking
)
3363 timevar_push (TV_VAR_TRACKING
);
3364 variable_tracking_main ();
3365 /* We also have to deal with variable tracking notes in the
3366 middle of VLIW packets. */
3367 reorder_var_tracking_notes();
3368 timevar_pop (TV_VAR_TRACKING
);
3372 /* Return the ALU character identifier for the current
3373 instruction. This will be 0 or 1. */
3375 picochip_get_vliw_alu_id (void)
3379 /* Always use ALU 0 if VLIW scheduling is disabled. */
3380 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3383 /* Get the attribute type of the instruction. Note that this can
3384 ruin the contents of recog_data, so save/restore around the
3386 picochip_save_recog_data ();
3387 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3388 picochip_restore_recog_data ();
3390 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3393 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3394 else it must be the other ALU (either basic or nonCc)
3395 instruction which goes into 1. */
3396 if (attr_type
== TYPE_PICOALU
)
3402 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3404 /* Is this the non CC instruction? If it is, then stuff it into
3405 ALU 1, else it must be a picoAlu or basicAlu, in which case
3406 it goes into ALU 0. */
3407 if (attr_type
== TYPE_NONCCALU
)
3414 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3415 whether an ALU instruction has already been scheduled in this
3417 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3420 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3424 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3428 internal_error ("too many ALU instructions emitted (%d)",
3429 picochip_current_vliw_state
.num_alu_insns_so_far
);
3436 /* Reset any information about the current VLIW packing status. */
3438 picochip_reset_vliw (rtx insn
)
3440 rtx local_insn
= insn
;
3442 /* Nothing to do if VLIW scheduling isn't being used. */
3443 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3447 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3450 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3451 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3452 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3453 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3454 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3455 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3457 /* Read through the VLIW packet, classifying the instructions where
3462 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3464 local_insn
= NEXT_INSN (local_insn
);
3467 else if (!INSN_P (local_insn
))
3471 /* It is an instruction, but is it ours? */
3472 if (INSN_CODE (local_insn
) != -1)
3476 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3478 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3479 get_attr_type function can overwrite the values in
3480 the recog_data global, hence this is saved and
3481 restored around the call. Not doing so results in
3482 asm_output_opcode being called with a different
3483 instruction to final_prescan_insn, which is fatal. */
3484 picochip_save_recog_data ();
3485 attr_type
= get_attr_type (local_insn
);
3486 picochip_restore_recog_data ();
3488 if (attr_type
== TYPE_PICOALU
)
3489 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3490 if (attr_type
== TYPE_NONCCALU
)
3491 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3496 /* Get the next instruction. */
3497 local_insn
= NEXT_INSN (local_insn
);
3499 /* Keep going while the next instruction is part of the same
3500 VLIW packet (i.e., its a valid instruction and doesn't mark
3501 the start of a new VLIW packet. */
3503 while (local_insn
&&
3504 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3509 picochip_sched_reorder (FILE * file
, int verbose
,
3510 rtx
* ready ATTRIBUTE_UNUSED
,
3511 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3515 fprintf (file
, ";;\tClock %d\n", clock
);
3517 return picochip_sched_issue_rate ();
3522 picochip_sched_lookahead (void)
3524 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3530 picochip_sched_issue_rate (void)
3535 /* Adjust the scheduling cost between the two given instructions,
3536 which have the given dependency. */
3538 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3543 printf ("Sched Adjust Cost: %d->%d is %d\n",
3544 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3546 printf (" Dependency type:");
3547 switch (REG_NOTE_KIND (link
))
3555 case REG_DEP_OUTPUT
:
3556 printf ("OUTPUT\n");
3559 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3563 /* Anti-dependencies are used to enforce the ordering between a
3564 * branch, and any subsequent instructions. For example:
3569 * The ADD instruction must execute after the branch, and this is
3570 * enforced using an anti-dependency. Unfortunately, VLIW machines
3571 * are happy to execute anti-dependent instructions in the same
3572 * cycle, which then results in a schedule like the following being
3575 * BNE someLabel \ ADD.0 r0,r1,r2
3577 * The instruction which would normally be conditionally executed
3578 * depending upon the outcome of the branch, is now unconditionally
3579 * executed every time. To prevent this happening, any
3580 * anti-dependencies between a branch and another instruction are
3581 * promoted to become real dependencies.
3583 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3587 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3588 INSN_UID (insn
), INSN_UID (dep_insn
));
3597 /* Return the minimum of the two values */
3599 minimum (int a
, int b
)
3605 /* I dont expect to get to this function with a==b.*/
3610 /* This function checks if the memory of the two stores are just off by 2 bytes.
3611 It returns the lower memory operand's index.*/
3614 memory_just_off (rtx opnd1
, rtx opnd2
)
3616 int offset1
= 0, offset2
= 0;
3619 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3621 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3622 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3626 reg1
= REGNO(XEXP(opnd1
, 0));
3628 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3630 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3631 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3635 reg2
= REGNO(XEXP(opnd2
, 0));
3638 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3639 should be 4 byte aligned. We can currently guarantee that only if the base
3640 address is FP(R13) and the offset is aligned. */
3642 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3643 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3649 registers_just_off (rtx opnd1
, rtx opnd2
)
3652 reg1
= REGNO(opnd1
);
3653 reg2
= REGNO(opnd2
);
3654 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3655 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3659 /* Check to see if the two LDWs can be peepholed together into a LDL
3660 They can be if the registers getting loaded into are contiguous
3661 and the memory addresses are contiguous as well.
3665 can be merged together into
3669 1. The LDWs themselves only guarantee that r11 will be a 2-byte
3670 aligned address. Only FP can be assumed to be 4 byte aligned.
3671 2. The progression of addresses and the register numbers should
3672 be similar. For eg., if you swap r2 and r3 in the above instructions,
3673 the resultant pair cannot be merged.
3677 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3679 int memtest
=0,regtest
=0;
3680 regtest
= registers_just_off(opnd1
,opnd3
);
3684 memtest
= memory_just_off(opnd0
,opnd2
);
3688 if (regtest
== memtest
)
3695 /* Similar to LDW peephole */
3697 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3699 int memtest
=0,regtest
=0;
3700 regtest
= registers_just_off(opnd1
,opnd3
);
3704 memtest
= memory_just_off(opnd0
,opnd2
);
3708 if (regtest
== memtest
)
3716 /* Generate a SImode register with the register number that is the smaller of the two */
3718 gen_min_reg(rtx opnd1
,rtx opnd2
)
3720 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3723 /* Generate a SImode memory with the address that is the smaller of the two */
3725 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3727 int offset1
=0,offset2
=0;
3730 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3732 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3733 reg
= XEXP(XEXP(opnd1
,0),0);
3737 reg
= XEXP(opnd1
,0);
3739 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3741 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3743 address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3744 return gen_rtx_MEM(SImode
,address
);
3748 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
3749 int opno ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3756 /* Need to penalize immediates that need to be encoded as long constants.*/
3757 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3759 *total
= COSTS_N_INSNS(1);
3767 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3772 /* if_then_else come out of cbranch instructions. It will get split into
3773 a condition code generating subtraction and a branch */
3774 *total
= COSTS_N_INSNS (2);
3781 if (GET_MODE(x
) == SImode
)
3782 *total
= COSTS_N_INSNS (2);
3783 if (GET_MODE(x
) == DImode
)
3784 *total
= COSTS_N_INSNS (4);
3788 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3789 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3790 *total
= COSTS_N_INSNS (10);
3792 /* 64-bit accesses have to be done through 2 32-bit access */
3793 if (GET_MODE(x
) == DImode
)
3794 *total
= COSTS_N_INSNS (2);
3800 /* SImode shifts are expensive */
3801 if (GET_MODE(x
) == SImode
)
3802 *total
= COSTS_N_INSNS (10);
3804 /* Register shift by constant is cheap. */
3805 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3806 && GET_CODE(XEXP(x
, 0)) == REG
3807 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3808 *total
= COSTS_N_INSNS (1);
3810 *total
= COSTS_N_INSNS (4);
3817 /* Divisions are more expensive than the default 7*/
3818 if (GET_MODE(x
) == SImode
)
3819 *total
= COSTS_N_INSNS (20);
3821 *total
= COSTS_N_INSNS (12);
3826 /* Look for the simple cases of multiplying register*register or
3827 register*constant. */
3828 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3829 && ((GET_CODE(XEXP(x
, 0)) == REG
3830 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3831 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3832 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3833 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3834 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3837 /* When optimising for size, multiplication by constant
3838 should be discouraged slightly over multiplication by a
3840 if (picochip_has_mac_unit
)
3842 /* Single cycle multiplication, but the result must be
3843 loaded back into a general register afterwards. */
3844 *total
= COSTS_N_INSNS(2);
3847 else if (picochip_has_mul_unit
)
3849 /* Single cycle multiplication. */
3850 *total
= COSTS_N_INSNS(1);
3853 /* Else no multiply available. Use default cost. */
3863 if (localTotal
!= 0)
3865 *total
= localTotal
;
3876 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3877 int num_operands ATTRIBUTE_UNUSED
)
3881 picochip_current_prescan_insn
= insn
;
3884 printf ("Final prescan on INSN %d with mode %s\n",
3885 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3887 /* If this is the start of a new instruction cycle, or no scheduling
3888 is used, then reset the VLIW status. */
3889 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3890 picochip_reset_vliw (insn
);
3892 /* No VLIW scheduling occurred, so don't go any further. */
3893 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3896 /* Look for the next printable instruction. This loop terminates on
3897 any recognisable instruction, and on any unrecognisable
3898 instruction with TImode. */
3900 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3901 local_insn
= NEXT_INSN (local_insn
))
3903 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3905 else if (!INSN_P (local_insn
))
3907 else if (GET_MODE (local_insn
) == TImode
3908 || INSN_CODE (local_insn
) != -1)
3912 /* Set the continuation flag if the next instruction can be packed
3913 with the current instruction (i.e., the next instruction is
3914 valid, and isn't the start of a new cycle). */
3915 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3916 (GET_MODE (local_insn
) != TImode
));
3920 /* Builtin functions. */
3921 /* Given a builtin function taking 2 operands (i.e., target + source),
3922 emit the RTL for the underlying instruction. */
3924 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3928 enum machine_mode tmode
, mode0
;
3930 /* Grab the incoming argument and emit its RTL. */
3931 arg0
= CALL_EXPR_ARG (call
, 0);
3932 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3934 /* Determine the modes of the instruction operands. */
3935 tmode
= insn_data
[icode
].operand
[0].mode
;
3936 mode0
= insn_data
[icode
].operand
[1].mode
;
3938 /* Ensure that the incoming argument RTL is in a register of the
3940 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3941 op0
= copy_to_mode_reg (mode0
, op0
);
3943 /* If there isn't a suitable target, emit a target register. */
3945 || GET_MODE (target
) != tmode
3946 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3947 target
= gen_reg_rtx (tmode
);
3949 /* Emit and return the new instruction. */
3950 pat
= GEN_FCN (icode
) (target
, op0
);
3959 /* Given a builtin function taking 3 operands (i.e., target + two
3960 source), emit the RTL for the underlying instruction. */
3962 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3966 enum machine_mode tmode
, mode0
, mode1
;
3968 /* Grab the function's arguments. */
3969 arg0
= CALL_EXPR_ARG (call
, 0);
3970 arg1
= CALL_EXPR_ARG (call
, 1);
3972 /* Emit rtl sequences for the function arguments. */
3973 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3974 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3976 /* Get the mode's of each of the instruction operands. */
3977 tmode
= insn_data
[icode
].operand
[0].mode
;
3978 mode0
= insn_data
[icode
].operand
[1].mode
;
3979 mode1
= insn_data
[icode
].operand
[2].mode
;
3981 /* Ensure that each of the function argument rtl sequences are in a
3982 register of the correct mode. */
3983 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3984 op0
= copy_to_mode_reg (mode0
, op0
);
3985 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3986 op1
= copy_to_mode_reg (mode1
, op1
);
3988 /* If no target has been given, create a register to use as the target. */
3990 || GET_MODE (target
) != tmode
3991 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3992 target
= gen_reg_rtx (tmode
);
3994 /* Emit and return the new instruction. */
3995 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
4004 /* Expand a builtin function which takes two arguments, and returns a void. */
4006 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
4010 enum machine_mode mode0
, mode1
;
4012 /* Grab the function's arguments. */
4013 arg0
= CALL_EXPR_ARG (call
, 0);
4014 arg1
= CALL_EXPR_ARG (call
, 1);
4016 /* Emit rtl sequences for the function arguments. */
4017 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4018 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4020 /* Get the mode's of each of the instruction operands. */
4021 mode0
= insn_data
[icode
].operand
[0].mode
;
4022 mode1
= insn_data
[icode
].operand
[1].mode
;
4024 /* Ensure that each of the function argument rtl sequences are in a
4025 register of the correct mode. */
4026 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
4027 op0
= copy_to_mode_reg (mode0
, op0
);
4028 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
4029 op1
= copy_to_mode_reg (mode1
, op1
);
4031 /* Emit and return the new instruction. */
4032 pat
= GEN_FCN (icode
) (op0
, op1
);
4041 /* Expand an array get into the corresponding RTL. */
4043 picochip_expand_array_get (tree call
, rtx target
)
4045 tree arg0
, arg1
, arg2
;
4046 rtx op0
, op1
, op2
, pat
;
4048 /* Grab the function's arguments. */
4049 arg0
= CALL_EXPR_ARG (call
, 0);
4050 arg1
= CALL_EXPR_ARG (call
, 1);
4051 arg2
= CALL_EXPR_ARG (call
, 2) ;
4053 /* Emit rtl sequences for the function arguments. */
4054 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4055 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4056 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4058 /* The second and third operands must be constant. Nothing else will
4060 if (CONST_INT
!= GET_CODE (op1
))
4061 internal_error ("%s: Second source operand is not a constant",
4063 if (CONST_INT
!= GET_CODE (op2
))
4064 internal_error ("%s: Third source operand is not a constant",
4067 /* If no target has been given, create a register to use as the target. */
4068 if (target
== 0 || GET_MODE (target
) != SImode
)
4069 target
= gen_reg_rtx (SImode
);
4071 /* The first operand must be a HImode register or a constant. If it
4072 isn't, force it into a HImode register. */
4073 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4074 op0
= copy_to_mode_reg (HImode
, op0
);
4077 /* Emit and return the new instruction. */
4078 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
4085 /* Expand an array put into the corresponding RTL. */
4087 picochip_expand_array_put (tree call
, rtx target
)
4089 tree arg0
, arg1
, arg2
, arg3
;
4090 rtx op0
, op1
, op2
, op3
, pat
;
4092 /* Grab the function's arguments. */
4093 arg0
= CALL_EXPR_ARG (call
, 0);
4094 arg1
= CALL_EXPR_ARG (call
, 1);
4095 arg2
= CALL_EXPR_ARG (call
, 2);
4096 arg3
= CALL_EXPR_ARG (call
, 3);
4098 /* Emit rtl sequences for the function arguments. */
4099 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4100 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4101 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4102 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4104 /* The first operand must be an SImode register. */
4105 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
4106 op0
= copy_to_mode_reg (SImode
, op0
);
4108 /* The second (index) operand must be a HImode register, or a
4109 constant. If it isn't, force it into a HImode register. */
4110 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
4111 op1
= copy_to_mode_reg (HImode
, op1
);
4113 /* The remaining operands must be constant. Nothing else will do. */
4114 if (CONST_INT
!= GET_CODE (op2
))
4115 internal_error ("%s: Third source operand is not a constant",
4117 if (CONST_INT
!= GET_CODE (op3
))
4118 internal_error ("%s: Fourth source operand is not a constant",
4121 /* Emit and return the new instruction. */
4122 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
4129 /* Expand an array testport into the corresponding RTL. */
4131 picochip_expand_array_testport (tree call
, rtx target
)
4133 tree arg0
, arg1
, arg2
;
4134 rtx op0
, op1
, op2
, pat
;
4136 /* Grab the function's arguments. */
4137 arg0
= CALL_EXPR_ARG (call
, 0);
4138 arg1
= CALL_EXPR_ARG (call
, 1);
4139 arg2
= CALL_EXPR_ARG (call
, 2);
4141 /* Emit rtl sequences for the function arguments. */
4142 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4143 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4144 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4146 /* The first operand must be a HImode register, or a constant. If it
4147 isn't, force it into a HImode register. */
4148 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4149 op0
= copy_to_mode_reg (HImode
, op0
);
4151 /* The second and third operands must be constant. Nothing else will
4153 if (CONST_INT
!= GET_CODE (op1
))
4154 internal_error ("%s: Second source operand is not a constant",
4156 if (CONST_INT
!= GET_CODE (op2
))
4157 internal_error ("%s: Third source operand is not a constant",
4160 /* If no target has been given, create a HImode register to use as
4162 if (target
== 0 || GET_MODE (target
) != HImode
)
4163 target
= gen_reg_rtx (HImode
);
4165 /* Emit and return the new instruction. */
4166 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4173 /* Generate a unique HALT instruction by giving the instruction a
4174 unique integer. This integer makes no difference to the assembly
4175 output (other than a comment indicating the supplied id), but the
4176 presence of the unique integer prevents the compiler from combining
4177 several different halt instructions into one instruction. This
4178 means that each use of the halt instruction is unique, which in
4179 turn means that assertions work as expected. */
4181 picochip_generate_halt (void)
4183 static int currentId
= 0;
4185 rtx id
= GEN_INT (currentId
);
4189 emit_insn (gen_halt (id
));
4191 /* A barrier is inserted to prevent the compiler from thinking that
4192 it has to continue execution after the HALT.*/
4195 insns
= get_insns();
4202 /* Initialise the builtin functions. Start by initialising
4203 descriptions of different types of functions (e.g., void fn(int),
4204 int fn(void)), and then use these to define the builtins. */
4206 picochip_init_builtins (void)
4210 tree int_ftype_int
, int_ftype_int_int
;
4211 tree long_ftype_int
, long_ftype_int_int_int
;
4212 tree void_ftype_int_long
, int_ftype_int_int_int
,
4213 void_ftype_long_int_int_int
;
4214 tree void_ftype_void
, unsigned_ftype_unsigned
;
4216 /* void func (void) */
4217 void_ftype_void
= build_function_type_list (void_type_node
, NULL_TREE
);
4219 /* int func (int) */
4220 int_ftype_int
= build_function_type_list (integer_type_node
,
4221 integer_type_node
, NULL_TREE
);
4223 /* unsigned int func (unsigned int) */
4224 unsigned_ftype_unsigned
4225 = build_function_type_list (unsigned_type_node
,
4226 unsigned_type_node
, NULL_TREE
);
4228 /* int func(int, int) */
4230 = build_function_type_list (integer_type_node
,
4231 integer_type_node
, integer_type_node
,
4234 /* long func(int) */
4235 long_ftype_int
= build_function_type_list (long_integer_type_node
,
4236 integer_type_node
, NULL_TREE
);
4238 /* long func(int, int, int) */
4239 long_ftype_int_int_int
4240 = build_function_type_list (long_integer_type_node
,
4241 integer_type_node
, integer_type_node
,
4242 integer_type_node
, NULL_TREE
);
4244 /* int func(int, int, int) */
4245 int_ftype_int_int_int
4246 = build_function_type_list (integer_type_node
,
4247 integer_type_node
, integer_type_node
,
4248 integer_type_node
, NULL_TREE
);
4250 /* void func(int, long) */
4252 = build_function_type_list (void_type_node
,
4253 integer_type_node
, long_integer_type_node
,
4256 /* void func(long, int, int, int) */
4257 void_ftype_long_int_int_int
4258 = build_function_type_list (void_type_node
,
4259 long_integer_type_node
, integer_type_node
,
4260 integer_type_node
, integer_type_node
,
4263 /* Initialise the sign-bit-count function. */
4264 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4265 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4267 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4268 BUILT_IN_MD
, NULL
, NULL_TREE
);
4270 /* Initialise the bit reverse function. */
4271 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4272 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4274 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4275 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4278 /* Initialise the byte swap function. */
4279 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4280 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4282 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4283 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4286 /* Initialise the ASRI function (note that while this can be coded
4287 using a signed shift in C, extra scratch registers are required,
4288 which we avoid by having a direct builtin to map to the
4290 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4291 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4294 /* Initialise saturating addition. */
4295 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4296 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4298 add_builtin_function ("picoAdds", int_ftype_int_int
,
4299 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4302 /* Initialise saturating subtraction. */
4303 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4304 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4306 add_builtin_function ("picoSubs", int_ftype_int_int
,
4307 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4310 /* Scalar comms builtins. */
4311 add_builtin_function ("__builtin_get", long_ftype_int
,
4312 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4314 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4315 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4317 add_builtin_function ("__builtin_testport", int_ftype_int
,
4318 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4321 /* Array comms builtins. */
4322 add_builtin_function ("__builtin_put_array",
4323 void_ftype_long_int_int_int
,
4324 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4326 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4327 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4329 add_builtin_function ("__builtin_testport_array",
4330 int_ftype_int_int_int
,
4331 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4334 /* Halt instruction. Note that the builtin function is marked as
4335 having the attribute `noreturn' so that the compiler realises
4336 that the halt stops the program dead. */
4337 noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4338 add_builtin_function ("__builtin_halt", void_ftype_void
,
4339 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4341 add_builtin_function ("picoHalt", void_ftype_void
,
4342 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4347 /* Expand a call to a builtin function. */
4349 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4350 enum machine_mode mode ATTRIBUTE_UNUSED
,
4351 int ignore ATTRIBUTE_UNUSED
)
4353 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4354 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4358 case PICOCHIP_BUILTIN_ASRI
:
4359 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4362 case PICOCHIP_BUILTIN_ADDS
:
4363 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4366 case PICOCHIP_BUILTIN_SUBS
:
4367 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4370 case PICOCHIP_BUILTIN_SBC
:
4371 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4373 case PICOCHIP_BUILTIN_BREV
:
4374 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4376 case PICOCHIP_BUILTIN_BYTESWAP
:
4377 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4379 case PICOCHIP_BUILTIN_GET
:
4380 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4382 case PICOCHIP_BUILTIN_PUT
:
4383 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4385 case PICOCHIP_BUILTIN_TESTPORT
:
4386 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4389 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4390 return picochip_expand_array_put (exp
, target
);
4392 case PICOCHIP_BUILTIN_GET_ARRAY
:
4393 return picochip_expand_array_get (exp
, target
);
4395 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4396 return picochip_expand_array_testport (exp
, target
);
4398 case PICOCHIP_BUILTIN_HALT
:
4399 return picochip_generate_halt ();
4406 /* Should really do something sensible here. */
4410 /* Emit warnings. */
4412 picochip_warn_inefficient (const char *msg
)
4414 if (TARGET_INEFFICIENT_WARNINGS
)
4415 warning (OPT_minefficient_warnings
,
4416 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4420 warn_of_byte_access (void)
4422 static int warned
= 0;
4426 picochip_warn_inefficient
4427 ("byte access is synthesised - consider using MUL AE");
4434 picochip_function_value (const_tree valtype
, const_tree func
,
4435 bool outgoing ATTRIBUTE_UNUSED
)
4437 enum machine_mode mode
= TYPE_MODE (valtype
);
4438 int unsignedp
= TYPE_UNSIGNED (valtype
);
4440 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4441 just as PROMOTE_MODE does. */
4442 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4444 return gen_rtx_REG (mode
, 0);
4448 /* Check that the value of the given mode will fit in the register of
4451 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4454 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4455 return regno
== CC_REGNUM
;
4457 /* If the CC register is being used, then only CC mode values are
4458 allowed (which have already been tested). */
4459 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4462 /* Must be a valid register. */
4466 /* Modes QI and HI may be placed in any register except the CC. */
4467 if (mode
== QImode
|| mode
== HImode
)
4470 /* DI must be in a quad register. */
4472 return (regno
% 4 == 0);
4474 /* All other modes must be placed in a even numbered register. */
4475 return !(regno
& 1);
4479 /* Extract the lower and upper components of a constant value. */
4482 picochip_get_low_const (rtx value
)
4484 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4488 picochip_get_high_const (rtx value
)
4490 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4491 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4495 /* Loading and storing QImode values to and from memory in a machine
4496 without byte access requires might require a scratch
4497 register. However, the scratch register might correspond to the
4498 register in which the value is being loaded. To ensure that a
4499 scratch register is supplied which is definitely different to the
4500 output register, request a register pair. This effectively gives a
4501 choice of two registers to choose from, so that we a guaranteed to
4502 get at least one register which is different to the output
4503 register. This trick is taken from the alpha implementation. */
4505 picochip_secondary_reload (bool in_p
,
4506 rtx x ATTRIBUTE_UNUSED
,
4507 reg_class_t cla ATTRIBUTE_UNUSED
,
4508 enum machine_mode mode
,
4509 secondary_reload_info
*sri
)
4511 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4514 sri
->icode
= CODE_FOR_reload_outqi
;
4516 sri
->icode
= CODE_FOR_reload_inqi
;
4519 /* We dont need to return a register class type when we need only a
4520 scratch register. It realizes the scratch register type by looking
4521 at the instruction definition for sri->icode. We only need to
4522 return the register type when we need intermediaries for copies.*/
4526 /* Return true if the given memory operand can be aligned to a
4527 word+offset memory reference (e.g., FP+3 can be converted into the
4528 memory operand FP+2, with the offset 1). */
4530 picochip_alignable_memory_operand (rtx mem_operand
,
4531 enum machine_mode mode ATTRIBUTE_UNUSED
)
4535 /* Not a mem operand. Refuse immediately. */
4536 if (MEM
!= GET_CODE (mem_operand
))
4539 address
= XEXP (mem_operand
, 0);
4541 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4542 return ((PLUS
== GET_CODE (address
) &&
4543 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4544 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4545 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4546 || (REG
== GET_CODE (address
)
4547 && REGNO (address
) == STACK_POINTER_REGNUM
));
4551 /* Return true if the given memory reference is to a word aligned
4552 address. Currently this means it must be either SP, or
4553 SP+offset. We could replace this function with alignable
4554 memory references in the above function?. */
4556 picochip_word_aligned_memory_reference (rtx operand
)
4560 /* The address must be the SP register, or a constant, aligned
4561 offset from SP which doesn't exceed the FP+offset
4563 return ((PLUS
== GET_CODE (operand
)
4564 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4565 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4566 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4568 || (REG
== GET_CODE (operand
)
4569 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4573 /* Given an alignable memory location, convert the memory location
4574 into a HI mode access, storing the new memory reference in
4575 paligned_mem, and the number of bits by which to shift in pbitnum
4576 (i.e., given a reference to FP+3, this creates an aligned reference
4577 of FP+2, with an 8-bit shift). This code is a modification of that
4578 found in the Alpha port. */
4580 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4583 HOST_WIDE_INT offset
= 0;
4585 gcc_assert (GET_CODE (ref
) == MEM
);
4587 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4589 base
= find_replacement (&XEXP (ref
, 0));
4591 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4595 base
= XEXP (ref
, 0);
4598 if (GET_CODE (base
) == PLUS
)
4600 offset
+= INTVAL (XEXP (base
, 1));
4601 base
= XEXP (base
, 0);
4604 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4611 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4615 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4619 /* Return true if the given operand is an absolute address in memory
4620 (i.e., a symbolic offset). */
4622 picochip_absolute_memory_operand (rtx op
,
4623 enum machine_mode mode ATTRIBUTE_UNUSED
)
4626 if (MEM
== GET_CODE (op
))
4628 rtx address
= XEXP (op
, 0);
4630 /* Symbols are valid absolute addresses. */
4631 if (SYMBOL_REF
== GET_CODE (address
))
4634 /* Constant offsets to symbols are valid absolute addresses. */
4635 if (CONST
== GET_CODE (address
) &&
4636 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4637 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4638 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4645 /* Symbols are valid absolute addresses. */
4646 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4655 picochip_asm_named_section (const char *name
,
4656 unsigned int flags ATTRIBUTE_UNUSED
,
4657 tree decl ATTRIBUTE_UNUSED
)
4659 fprintf (asm_out_file
, ".section %s\n", name
);
4663 /* Check if we can make a conditional copy instruction. This is emitted as an
4664 instruction to set the condition register, followed by an instruction which
4665 uses the condition registers to perform the conditional move. */
4667 picochip_check_conditional_copy (rtx
* operands
)
4670 rtx branch_op_0
= XEXP (operands
[1], 0);
4671 rtx branch_op_1
= XEXP (operands
[1], 1);
4673 /* Only HI mode conditional moves are currently allowed. Can we add
4675 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4678 /* Is the comparison valid? Only allow operands which are registers
4679 if they are HImode. SI mode comparisons against 0 could be
4680 handled using logical operations (e.g., SIreg != 0 when low ||
4681 high). Need to find test cases to provoke this though (fixunssfdi
4682 in libgcc does, but is complicated). */
4683 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4684 GET_MODE(branch_op_0
) != HImode
)
4686 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4687 GET_MODE(branch_op_1
) != HImode
)
4696 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4700 addr
= arg_pointer_rtx
;
4702 addr
= plus_constant (Pmode
, stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4703 return gen_frame_mem (Pmode
, addr
);