gcc/config/picochip/picochip.h

   1 /* Definitions of target machine for GNU compiler for picoChip
   2    Copyright (C) 2001, 2008, 2009, 2010, 2011, 2012
   3    Free Software Foundation, Inc.
   4
   5    Contributed by Picochip Ltd. (http://www.picochip.com)
   6    Maintained by Daniel Towner (daniel.towner@picochip.com) and
   7    Hariharan Sandanagobalane (hariharan@picochip.com).
   8
   9 This file is part of GCC.
  10
  11 GCC is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 3, or (at your option)
  14 any later version.
  15
  16 GCC is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with GCC; see the file COPYING3.  If not, see
  23 <http://www.gnu.org/licenses/>. */
  24
  25 /* Which type of DFA scheduling to use - schedule for speed (VLIW), or
  26    schedule for space.  When scheduling for space, attempt to schedule
  27    into stall cycles, but don't pack instructions. */
  28
  29 enum picochip_dfa_type
  30 {
  31   DFA_TYPE_NONE,
  32   DFA_TYPE_SPACE,
  33   DFA_TYPE_SPEED
  34 };
  35
  36 extern enum picochip_dfa_type picochip_schedule_type;
  37
  38 /* Controlling the Compilation Driver */
  39
  40 /* Pass through the save-temps command option. */
  41 #define LINK_SPEC " %{save-temps:--save-temps}"
  42
  43 /* This is an embedded processor, and only supports a cut-down version of
  44  * the standard C library. */
  45 #define LIB_SPEC "-lpicoC"
  46
  47 /* The start file is automatically provided by the linker. */
  48 #define STARTFILE_SPEC ""
  49 \f
  50 /* Run-time Target Specification  */
  51
  52 /* Define some additional pre-processor macros. */
  53 #define TARGET_CPU_CPP_BUILTINS()                       \
  54   do                                                    \
  55     {                                                   \
  56       builtin_define ("NO_TRAMPOLINES");                \
  57       builtin_define ("PICOCHIP");                      \
  58       builtin_define ("__PICOCHIP__");                      \
  59     }                                                   \
  60   while (0)
  61
  62 /* Translate requests for particular AEs into their respective ISA
  63    options. Note that byte access is enabled by default. */
  64 #define DRIVER_SELF_SPECS                                       \
  65   "%{mae=ANY:-mmul-type=none -mno-byte-access} %<mae=ANY",      \
  66   "%{mae=ANY2:-mmul-type=none -mno-byte-access} %<mae=ANY2",    \
  67   "%{mae=ANY3:-mmul-type=none} %<mae=ANY3",                     \
  68   "%{mae=STAN:-mmul-type=none -mno-byte-access} %<mae=STAN",    \
  69   "%{mae=STAN2:-mmul-type=mac -mno-byte-access} %<mae=STAN2",   \
  70   "%{mae=STAN3:-mmul-type=mac} %<mae=STAN3",                    \
  71   "%{mae=MAC:-mmul-type=mac -mno-byte-access} %<mae=MAC",       \
  72   "%{mae=MUL:-mmul-type=mul} %<mae=MUL",                        \
  73   "%{mae=MEM:-mmul-type=mul} %<mae=MEM",                        \
  74   "%{mae=MEM2:-mmul-type=mul} %<mae=MEM2",                      \
  75   "%{mae=CTRL:-mmul-type=mul} %<mae=CTRL",                      \
  76   "%{mae=CTRL2:-mmul-type=mul} %<mae=CTRL2"
  77
  78 /* Specify the default options, so that the multilib build doesn't
  79    need to provide special cases for the defaults. */
  80 #define MULTILIB_DEFAULTS \
  81   { "mmul-type=mul", "mbyte-access"}
  82
  83 #define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access)
  84 #define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit)
  85 #define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit)
  86 #define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit)
  87 \f
  88 /* Storage Layout */
  89
  90 /* picoChip processors are 16-bit machines, little endian. */
  91
  92 #define BITS_BIG_ENDIAN 0
  93 #define BYTES_BIG_ENDIAN 0
  94 #define WORDS_BIG_ENDIAN 0
  95
  96 #define BITS_PER_UNIT 8
  97
  98 #define BITS_PER_WORD 16
  99 #define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
 100
 101 #define POINTER_SIZE BITS_PER_WORD
 102
 103 /* Promote those modes that are smaller than an int, to int mode.  */
 104 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
 105   ((GET_MODE_CLASS (MODE) == MODE_INT                   \
 106       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)         \
 107       ? (MODE) = HImode : 0)
 108
 109 /* All parameters are at least this aligned.  Parameters are passed
 110    one-per-register. */
 111 #define PARM_BOUNDARY BITS_PER_WORD
 112
 113 /* The main stack pointer is guaranteed to be aligned to the most
 114    strict data alignment. */
 115 #define STACK_BOUNDARY 32
 116
 117 /* Function entry point is byte aligned. */
 118 #define FUNCTION_BOUNDARY 8
 119
 120 /* This is the biggest alignment that can be allowed on this machine.
 121    Since the STANs have only 256 byte memory, it doesnt make sense
 122    to have alignments greater than 32 bytes. Hence the value */
 123 #define MAX_OFILE_ALIGNMENT 32*8
 124
 125 /* The strictest data object alignment, which repesents a register pair. */
 126 #define BIGGEST_ALIGNMENT 32
 127
 128 /* The hardware doesn't allow unaligned memory access.  */
 129 #define STRICT_ALIGNMENT 1
 130
 131 /* We want the 'unix' style bitfield packing algorithm.  */
 132 #define PCC_BITFIELD_TYPE_MATTERS 1
 133
 134 /* Support up to 64-bit integers. */
 135 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
 136
 137 /* We don't support floating point, but give it a sensible definition. */
 138 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
 139 \f
 140 /* Layout of Source Language Data Types.  */
 141
 142 #define INT_TYPE_SIZE BITS_PER_WORD
 143
 144 /* The normal sizes for C scalar data. */
 145 #define CHAR_TYPE_SIZE 8
 146 #define SHORT_TYPE_SIZE 16
 147 #define LONG_TYPE_SIZE 32
 148 #define LONG_LONG_TYPE_SIZE 64
 149
 150 /* We don't support the following data types, but still give them
 151    sensible values.  */
 152 #define FLOAT_TYPE_SIZE 32
 153 #define DOUBLE_TYPE_SIZE 32
 154 #define LONG_DOUBLE_TYPE_SIZE 32
 155
 156 /* Plain `char' is a signed type, since the hardware sign-extends
 157    bytes when loading them from memory into a register. */
 158 #define DEFAULT_SIGNED_CHAR 1
 159
 160 /* Note that the names of the types used in the following macros must
 161    be precisely the same as those defined internally in gcc.  For
 162    example, `unsigned short' wouldn't work as a type string, since gcc
 163    doesn't define any type with this exact string.  The correct string
 164    to use is `short unsigned int'. */
 165
 166 #define SIZE_TYPE "unsigned int"
 167
 168 #define PTRDIFF_TYPE "int"
 169
 170 #define WCHAR_TYPE "short unsigned int"
 171 #define WCHAR_TYPE_SIZE 16
 172
 173 #define WINT_TYPE "unsigned int"
 174 \f
 175 /* Register Usage  */
 176
 177 /* Picochip has 16 16-bit registers, a condition code register and an
 178    (inaccessible) instruction pointer.  One of these registers (r15) is
 179    special, and is either used to load a constant anywhere a register
 180    can normally be used, or is used to specify a dummy destination
 181    (e.g., when setting condition flags).  We also define some pseudo
 182    registers to represent condition codes, the frame pointer and the
 183    argument pointer.  The latter two are eliminated wherever possible.
 184
 185    Pairs of general registers may be combined to form 32-bit registers.
 186
 187    The picoChip registers are as follows:
 188
 189    0..1 - function return value
 190    0..5 - first 6 function parameters
 191    6..11 - General purpose
 192    12 - link register
 193    13 - stack pointer
 194    14 - specialized pointer
 195    15 - long constant or /dev/null
 196    (16) acc0
 197    (17) pseudo condition code
 198    (18) pseudo frame pointer
 199    (19) pseudo arg pointer
 200
 201    Registers 0..6, 12, 13, 14, 15 are caller save
 202    Registers 0..12, 14 are available to the register allocator.
 203
 204    In addition, the DSP variant of the ISA allows extra accumulator
 205    registers to be accessed.  These are special purpose registers,
 206    which are not currently used by the compiler.
 207
 208   */
 209
 210 /* Basic Characteristics of Registers  */
 211
 212 /* We have 16 hard registers plus 3 pseudo hard registers and an accumulator.  */
 213 #define FIRST_PSEUDO_REGISTER 20
 214
 215 /* The first non-hard register.  Only used internally by the picoChip port. */
 216 #define FIRST_NONHARD_REGISTER 18
 217
 218 /* Cannot use SP, CST, CC, FP, AP */
 219 #define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1}
 220
 221 /* Those that are clobbered by a function call (includes pseudo-regs) */
 222 #define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
 223 #define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
 224
 225 /* Define the number of the picoChip link and condition pseudo registers. */
 226 #define LINK_REGNUM 12
 227 #define CC_REGNUM 17
 228 #define ACC_REGNUM 16
 229
 230 /* Order of Allocation of Registers  */
 231
 232 /* The registers are allocated starting with the caller-clobbered
 233    registers, in reverse order.  The registers are then listed in an
 234    order which means that they are efficiently saved in pairs (i.e.,
 235    one 32-bit store can be used instead of two 16-bit stores to save
 236    the registers into the stack). The exception to this is the use of
 237    r14 (AP) register, which also appears early on.  This is because the
 238    AP register can be used to encode memory operations more
 239    efficiently than other registers.  Some code can be made more
 240    compact as a result. */
 241    /* My current feeling is that r14 should go to the end and maybe even r12.
 242    It seems like the overhead of store/load that will occur since we cant
 243    pair anything up with r14 will be higher than the advantage of smaller
 244    encoding.
 245    Also r12 is put towards the end for leaf functions. Since leaf functions
 246    do not have any calls, the prologue/epilogue for them wouldnt save up/
 247    restore its value. So, it doesnt make sense for us to use it in the middle,
 248    if we can avoid it. */
 249 #define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
 250 #define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
 251
 252 /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
 253    It would be desirable to change it for leaf functions so we can put
 254    r12 at the end of this list.*/
 255 #define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc ()
 256
 257 /* How Values Fit in Registers  */
 258
 259 /* Number of consecutive hard regs needed starting at reg REGNO
 260    to hold something of mode MODE.  */
 261 #define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE))
 262
 263 /* Is it ok to place MODE in REGNO?  Require that the register number
 264    be aligned. */
 265 #define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE)
 266
 267 #define MODES_TIEABLE_P(MODE1,MODE2) 1
 268
 269 /* Don't copy the cc register ('cos you can't put it back).  */
 270 #define AVOID_CCMODE_COPIES 1
 271 \f
 272 /* Register Classes */
 273
 274 enum reg_class
 275 {
 276   NO_REGS,                      /* no registers in set */
 277   FRAME_REGS,                   /* registers with a long offset  */
 278   PTR_REGS,                     /* registers without an offset  */
 279   CONST_REGS,                   /* registers for long constants  */
 280   NULL_REGS,                    /* registers which ignore writes  */
 281   CC_REGS,                      /* condition code registers  */
 282   ACC_REGS,                     /* Accumulator registers  */
 283   TWIN_REGS,                    /* registers which can be paired */
 284   GR_REGS,                      /* general purpose registers */
 285   ALL_REGS,                     /* all registers */
 286   LIM_REG_CLASSES,              /* max value + 1 */
 287
 288   /* Some aliases  */
 289   GENERAL_REGS = GR_REGS
 290 };
 291
 292 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 293
 294
 295 /* The names of the register classes  */
 296 #define REG_CLASS_NAMES                                                 \
 297 {                                                                       \
 298   "NO_REGS",                                                            \
 299   "FRAME_REGS",                                                         \
 300   "PTR_REGS",                                                           \
 301   "CONST_REGS",                                                         \
 302   "NULL_REGS",                                                          \
 303   "CC_REGS",                                                            \
 304   "ACC_REGS",                                                           \
 305   "TWIN_REGS",                                                          \
 306   "GR_REGS",                                                            \
 307   "ALL_REGS"                                                            \
 308 }
 309
 310 /* Each reg class is an array of 32-bit integers.  Each array must be
 311    long enough to store one bit for every pseudo register. Thus in the
 312    following code, each array only stores one 32-bit value. */
 313 #define REG_CLASS_CONTENTS                                              \
 314 {                                                                       \
 315   {0x00000000}, /* no registers */                                      \
 316   {0x00002000}, /* frame */                                             \
 317   {0x00004000}, /* pointer  */                                          \
 318   {0x00008000}, /* const */                                             \
 319   {0x00008000}, /* null  */                                             \
 320   {0x00020000}, /* cc */                                                \
 321   {0x00010000}, /* acc0 */                                              \
 322   {0x00000FFF}, /* twin */                                              \
 323   {0x000CFFFF}, /* general registers - includes pseudo-arg */           \
 324   {0x000FFFFF}  /* all registers - includes pseudo-arg */               \
 325 }
 326
 327 /* The earliest register class containing the given register.  */
 328 extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER];
 329 #define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO]
 330
 331 /* Any register can be a base pointer.  */
 332 #define BASE_REG_CLASS GR_REGS
 333
 334 /* Any register can be an index.  */
 335 #define INDEX_REG_CLASS GR_REGS
 336
 337 #define REGNO_OK_FOR_BASE_P(REGNO)                                      \
 338   (REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS)
 339
 340 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 341
 342 #define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE)
 343
 344 \f
 345 /* Stack Layout and Calling Conventions  */
 346
 347 #define STACK_GROWS_DOWNWARD 1
 348
 349 /* The frame pointer points to the outgoing argument area, so the
 350    locals are above that.  */
 351 #define STARTING_FRAME_OFFSET 0
 352
 353 #define FIRST_PARM_OFFSET(FNDECL) 0
 354
 355 /* Specify where the return address lives before entry to the
 356    prologue.  This is required to enable DWARF debug information to be
 357    generated. */
 358 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, LINK_REGNUM)
 359
 360 #define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr)
 361
 362 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)
 363
 364 /* Registers that Address the Stack Frame  */
 365
 366 #define STACK_POINTER_REGNUM 13
 367 #define FRAME_POINTER_REGNUM 18
 368 #define ARG_POINTER_REGNUM   19
 369
 370 /* Eliminating Frame Pointer and Arg Pointer.  The frame and argument
 371    pointers are eliminated wherever possible, by replacing them with
 372    offsets from the stack pointer. */
 373
 374 #define ELIMINABLE_REGS                                                 \
 375   {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},                          \
 376    {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
 377
 378 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
 379   OFFSET = initial_elimination_offset(FROM, TO);
 380
 381 #define ACCUMULATE_OUTGOING_ARGS 1
 382
 383 #define PUSH_ARGS 0
 384
 385 /* Passing Arguments in Registers  */
 386
 387 /* Store the offset of the next argument. */
 388 #define CUMULATIVE_ARGS unsigned
 389
 390 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
 391   ((CUM) = 0)
 392
 393 /* The first 6 registers can hold parameters.  */
 394 #define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6)
 395
 396 /* How Scalar Function Values are Returned
 397    Do we need this?? */
 398 #define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0)
 399
 400 #define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0))
 401
 402 /* Results are in register zero.  If an SImode register is returned,
 403    reg0 will suffice to mean R[0:1]. */
 404 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
 405
 406 /* Don't automatically pass struct's in memory - use the
 407  * RETURN_IN_MEMORY macro to determine when structs are returned in
 408  * memory, and when in registers. */
 409 #define DEFAULT_PCC_STRUCT_RETURN 0
 410
 411 /* Function Entry and Exit  */
 412
 413 /* The epilogue doesn't clobber anything.  */
 414 #define EPILOGUE_USES(REGNO) 0
 415
 416 /* Generating Code for Profiling.  No profiling implemented  */
 417
 418 #define FUNCTION_PROFILER(FILE,LABELNO)
 419 \f
 420 /* Trampolines for Nested Functions  */
 421
 422 /* No trampolines.  */
 423 #define TRAMPOLINE_SIZE 0
 424 \f
 425 /* Addressing Modes  */
 426
 427 #define MAX_REGS_PER_ADDRESS 1
 428
 429 /* Legitimize reload address tries machine dependent means of
 430    reloading addresses.  There seems to be a strange error in gcc,
 431    which necessitates this macro.  Consider:
 432
 433      set (reg A) (symbol_ref)
 434      set (reg B) (plus (reg A) (const_int))
 435
 436    A symbol_ref is a valid constant, so the symbol_ref is propagated
 437    into the second instruction to generate the instruction:
 438
 439      set (reg B) (plus (symbol_ref) (const_int))
 440
 441    This is an invalid address, and find_reloads_address correctly
 442    determines this.  However, that function doesn't generate a valid
 443    replacement for the now invalid address, and the invalid address is
 444    output into the assembly language.  To fix the problem without
 445    changing gcc itself, the following macro tests when such an invalid
 446    address has been computed, and wraps it up inside a constant rtx.  A
 447    constant rtx can be correctly reloaded by the function, and hence
 448    correct code is generated. */
 449
 450 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)          \
 451 do {                                                                         \
 452   if (picochip_legitimize_reload_address(&X,MODE,OPNUM,TYPE,IND_LEVELS))     \
 453     goto WIN;                                                                \
 454   } while(0);                                                                \
 455
 456 \f
 457 /* Condition Code Status  */
 458
 459 #define CC_STATUS_MDEP unsigned
 460 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
 461 \f
 462 /* Describing Relative Costs of Operations  */
 463
 464 /* Bytes are no faster than words.  */
 465 #define SLOW_BYTE_ACCESS 1
 466
 467 /* The assembler is often able to optimise function call branches, so
 468    don't try to CSE them in the compiler. This was the thinking before.
 469    But now, we realise that the benefits from CSE would mostly outweigh
 470    the disadvantages. */
 471 #define NO_FUNCTION_CSE
 472
 473 \f
 474 /* Dividing the Output into Sections  */
 475
 476 #define TEXT_SECTION_ASM_OP ".section .text\n"
 477 #define DATA_SECTION_ASM_OP ".section .data\n"
 478 #define BSS_SECTION_ASM_OP ".section .bss\n"
 479 /* picoChip is Harvard (separate data/instruction memories), so
 480    read-only data must go into the data section. */
 481 #define READONLY_DATA_SECTION_ASM_OP ".section .data\n"
 482 \f
 483 /* Defining the Output Assembler Language  */
 484
 485 /* The Overall Framework of an Assembler File  */
 486
 487 #define ASM_FILE_COMMENT "// "
 488
 489 #define ASM_APP_ON "// High-level ASM start\n"
 490 #define ASM_APP_OFF "// High-level ASM end\n"
 491
 492 #undef TARGET_ASM_OUTPUT_IDENT
 493 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
 494
 495 /* Output of Data  */
 496
 497 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN);
 498
 499 /* Output of Uninitialized Variables  */
 500 #define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \
 501   picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN)
 502
 503 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
 504   picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN)
 505
 506 /* Output and Generation of Labels  */
 507
 508 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
 509   do { picochip_output_label(STREAM, NAME); } while (0);
 510
 511 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 512   { picochip_output_labelref(STREAM, NAME); }
 513
 514 /* Format must match that of picochip_output_label. */
 515 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
 516  picochip_generate_internal_label(STRING,PREFIX,(long)NUM)
 517
 518 #define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME);
 519
 520 /* Store in OUTPUT a string (made with alloca) containing an
 521    assembler-name for a local static variable named NAME.  LABELNO is
 522    an integer which is different for each call.  The assembler can't
 523    use periods to generate the name, so we use a ___ separator
 524    instead. */
 525
 526 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)  \
 527 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15),    \
 528   sprintf ((OUTPUT), "%s___%lu", (NAME), (unsigned long)(LABELNO)))
 529
 530 /* Macros Controlling Initialization Routines  */
 531
 532 /* By defining this, the main function won't try to call `__main'. */
 533 #define HAS_INIT_SECTION
 534
 535 /* Output of Assembler Instructions  */
 536
 537 #define REGISTER_NAMES                                                  \
 538 {"R0",  "R1",  "R2",  "R3",                                             \
 539  "R4",  "R5",  "R6",  "R7",                                             \
 540  "R8",  "R9",  "R10", "R11",                                            \
 541  "R12", "FP", "R14", "R15",                                             \
 542  "acc0", "pseudoCC", "pseudoFP", "pseudoAP"}
 543
 544 #define ADDITIONAL_REGISTER_NAMES                                       \
 545 {                                                                       \
 546   { "R0",        0},                                                    \
 547   { "R1",        1},                                                    \
 548   { "R2",        2},                                                    \
 549   { "R3",        3},                                                    \
 550   { "R4",        4},                                                    \
 551   { "R5",        5},                                                    \
 552   { "R6",        6},                                                    \
 553   { "R7",        7},                                                    \
 554   { "R8",        8},                                                    \
 555   { "R9",        9},                                                    \
 556   { "R10",      10},                                                    \
 557   { "R11",      11},                                                    \
 558   { "R12",      12},                                                    \
 559   { "FP",       13},                                                    \
 560   { "R14",      14},                                                    \
 561   { "R15",      15},                                                    \
 562   { "acc0",     16},                                                    \
 563   { "sp",       12}, /* ABI stack pointer */                            \
 564   { "ln",       13}, /* arch link register */                           \
 565   { "ptr",      14}, /* arch constant pointer */                        \
 566   { "rc",       15}, /* arch constant register */                       \
 567   { "rz",       15}, /* arch zero */                                    \
 568 }
 569
 570 /* Final prescan insn is called just before an instruction is
 571    output.  In our case, we use this to detect the VLIW slot to which
 572    the instruction has been assigned, preparatory to generating the
 573    VLIW output in ASM_OUTPUT_OPCODE. */
 574 #define FINAL_PRESCAN_INSN(insn, operand, nop) \
 575   picochip_final_prescan_insn (insn, operand,nop)
 576
 577 #define ASM_OUTPUT_OPCODE(FILE,PTR) \
 578   { PTR = picochip_asm_output_opcode(FILE, PTR); }
 579
 580 #define PRINT_OPERAND(STREAM,X,CODE) \
 581   picochip_print_operand(STREAM, X, CODE)
 582
 583 #define PRINT_OPERAND_PUNCT_VALID_P(code) \
 584   (((code) == '|') || ((code) == '#') || ((code) == '>'))
 585
 586 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
 587   picochip_print_operand_address(STREAM,X)
 588
 589 /* Output of Dispatch Tables  */
 590
 591 /* Initialise a data memory location to an absolute code label.  Used
 592    for building switch statement jump tables.  Note - the format of the
 593    label must match that of the function picochip_output_label. */
 594 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 595   fprintf (stream, ".initWord _L%d\n", value);
 596
 597 /* Assembler Commands for Alignment  */
 598
 599 #define ASM_OUTPUT_SKIP(STREAM,BYTES) \
 600   fprintf(STREAM, ".skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", BYTES);
 601 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 602   fprintf(STREAM, ".align %u\n", 1 << POWER);
 603
 604 /* The elaborator doesn't output zero bytes in the text section. */
 605 #define ASM_NO_SKIP_IN_TEXT 1
 606 \f
 607 /* Controlling Debugging Information Format  */
 608
 609 /* Macros Affecting All Debugging Formats  */
 610
 611 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
 612
 613 #define DWARF2_DEBUGGING_INFO
 614 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 615 #define DWARF2_FRAME_INFO 1
 616
 617 /* Generate .file/.loc directives, so that the assembler generates the
 618    line table. */
 619 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 620 \f
 621 /* Miscellaneous Parameters  */
 622
 623 #define CASE_VECTOR_MODE HImode
 624 #define WORD_REGISTER_OPERATIONS
 625 #define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND)
 626 #define MOVE_MAX 4
 627 #define SHIFT_COUNT_TRUNCATED 1
 628 #define Pmode HImode
 629 #define FUNCTION_MODE QImode
 630 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
 631
 632 #define ASM_LONG ":TODO:.word\t"
 633
 634 /* Define builtins for selected special-purpose instructions. */
 635 enum picochip_builtins
 636 {
 637   PICOCHIP_BUILTIN_SBC,
 638   PICOCHIP_BUILTIN_PUT,
 639   PICOCHIP_BUILTIN_GET,
 640   PICOCHIP_BUILTIN_TESTPORT,
 641   PICOCHIP_BUILTIN_COPYSW,
 642   PICOCHIP_BUILTIN_ADDS,
 643   PICOCHIP_BUILTIN_SUBS,
 644   PICOCHIP_BUILTIN_BREV,
 645   PICOCHIP_BUILTIN_BYTESWAP,
 646   PICOCHIP_BUILTIN_GET_ARRAY,
 647   PICOCHIP_BUILTIN_PUT_ARRAY,
 648   PICOCHIP_BUILTIN_TESTPORT_ARRAY,
 649   PICOCHIP_BUILTIN_ASRI,
 650   PICOCHIP_BUILTIN_HALT
 651 };
 652
 653 #define NO_DOLLAR_IN_LABEL 1
 654 #define NO_DOT_IN_LABEL 1
 655
 656 /* The assembler does support LEB128, despite the auto-configure test
 657    not detecting this. */
 658 #define HAVE_AS_LEB128 1
 659
 660 /* The End */