gcc/config/riscv/bitmanip.md

   1 ;; Machine description for RISC-V Bit Manipulation operations.
   2 ;; Copyright (C) 2021-2023 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; ZBA extension.
  21
  22 (define_insn "*zero_extendsidi2_bitmanip"
  23   [(set (match_operand:DI 0 "register_operand" "=r,r")
  24         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
  25   "TARGET_64BIT && TARGET_ZBA"
  26   "@
  27    zext.w\t%0,%1
  28    lwu\t%0,%1"
  29   [(set_attr "type" "bitmanip,load")
  30    (set_attr "mode" "DI")])
  31
  32 (define_insn "*shNadd"
  33   [(set (match_operand:X 0 "register_operand" "=r")
  34         (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
  35                           (match_operand:QI 2 "imm123_operand" "Ds3"))
  36                 (match_operand:X 3 "register_operand" "r")))]
  37   "TARGET_ZBA"
  38   "sh%2add\t%0,%1,%3"
  39   [(set_attr "type" "bitmanip")
  40    (set_attr "mode" "<X:MODE>")])
  41
  42 ; When using strength-reduction, we will reduce a multiplication to a
  43 ; sequence of shifts and adds.  If this is performed with 32-bit types
  44 ; and followed by a division, the lack of w-form sh[123]add will make
  45 ; combination impossible and lead to a slli + addw being generated.
  46 ; Split the sequence with the knowledge that a w-form div will perform
  47 ; implicit sign-extensions.
  48 (define_split
  49   [(set (match_operand:DI 0 "register_operand")
  50         (sign_extend:DI (div:SI (plus:SI (subreg:SI (ashift:DI (match_operand:DI 1 "register_operand")
  51                                                                (match_operand:QI 2 "imm123_operand")) 0)
  52                                                     (subreg:SI (match_operand:DI 3 "register_operand") 0))
  53                 (subreg:SI (match_operand:DI 4 "register_operand") 0))))
  54    (clobber (match_operand:DI 5 "register_operand"))]
  55   "TARGET_64BIT && TARGET_ZBA"
  56    [(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
  57     (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (subreg:SI (match_dup 4) 0))))])
  58
  59 ; Zba does not provide W-forms of sh[123]add(.uw)?, which leads to an
  60 ; interesting irregularity: we can generate a signed 32-bit result
  61 ; using slli(.uw)?+ addw, but a unsigned 32-bit result can be more
  62 ; efficiently be generated as sh[123]add+zext.w (the .uw can be
  63 ; dropped, if we zero-extend the output anyway).
  64 ;
  65 ; To enable this optimization, we split [ slli(.uw)?, addw, zext.w ]
  66 ; into [ sh[123]add, zext.w ] for use during combine.
  67 (define_split
  68   [(set (match_operand:DI 0 "register_operand")
  69         (zero_extend:DI (plus:SI (ashift:SI (subreg:SI (match_operand:DI 1 "register_operand") 0)
  70                                                        (match_operand:QI 2 "imm123_operand"))
  71                                  (subreg:SI (match_operand:DI 3 "register_operand") 0))))]
  72   "TARGET_64BIT && TARGET_ZBA"
  73   [(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
  74    (set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 0) 0)))])
  75
  76 (define_split
  77   [(set (match_operand:DI 0 "register_operand")
  78         (zero_extend:DI (plus:SI (subreg:SI (and:DI (ashift:DI (match_operand:DI 1 "register_operand")
  79                                                                (match_operand:QI 2 "imm123_operand"))
  80                                                     (match_operand:DI 3 "consecutive_bits_operand")) 0)
  81                                  (subreg:SI (match_operand:DI 4 "register_operand") 0))))]
  82   "TARGET_64BIT && TARGET_ZBA
  83    && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))"
  84   [(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 4)))
  85    (set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 0) 0)))])
  86
  87 ; Make sure that an andi followed by a sh[123]add remains a two instruction
  88 ; sequence--and is not torn apart into slli, slri, add.
  89 (define_insn_and_split "*andi_add.uw"
  90   [(set (match_operand:DI 0 "register_operand" "=r")
  91         (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
  92                                     (match_operand:QI 2 "imm123_operand" "Ds3"))
  93                          (match_operand:DI 3 "consecutive_bits_operand" ""))
  94                  (match_operand:DI 4 "register_operand" "r")))
  95    (clobber (match_scratch:DI 5 "=&r"))]
  96   "TARGET_64BIT && TARGET_ZBA
  97    && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
  98    && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))"
  99   "#"
 100   "&& reload_completed"
 101   [(set (match_dup 5) (and:DI (match_dup 1) (match_dup 3)))
 102    (set (match_dup 0) (plus:DI (ashift:DI (match_dup 5) (match_dup 2))
 103                                (match_dup 4)))]
 104 {
 105         operands[3] = GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2]));
 106 })
 107
 108 (define_insn "*shNadduw"
 109   [(set (match_operand:DI 0 "register_operand" "=r")
 110         (plus:DI
 111           (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
 112                              (match_operand:QI 2 "imm123_operand" "Ds3"))
 113                  (match_operand 3 "immediate_operand" "n"))
 114           (match_operand:DI 4 "register_operand" "r")))]
 115   "TARGET_64BIT && TARGET_ZBA
 116    && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
 117   "sh%2add.uw\t%0,%1,%4"
 118   [(set_attr "type" "bitmanip")
 119    (set_attr "mode" "DI")])
 120
 121 ;; During combine, we may encounter an attempt to combine
 122 ;;   slli rtmp, rs, #imm
 123 ;;   zext.w rtmp, rtmp
 124 ;;   sh[123]add rd, rtmp, rs2
 125 ;; which will lead to the immediate not satisfying the above constraints.
 126 ;; By splitting the compound expression, we can simplify to a slli and a
 127 ;; sh[123]add.uw.
 128 (define_split
 129   [(set (match_operand:DI 0 "register_operand")
 130         (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand")
 131                                     (match_operand:QI 2 "immediate_operand"))
 132                          (match_operand:DI 3 "consecutive_bits_operand"))
 133                  (match_operand:DI 4 "register_operand")))
 134    (clobber (match_operand:DI 5 "register_operand"))]
 135   "TARGET_64BIT && TARGET_ZBA"
 136   [(set (match_dup 5) (ashift:DI (match_dup 1) (match_dup 6)))
 137    (set (match_dup 0) (plus:DI (and:DI (ashift:DI (match_dup 5)
 138                                                   (match_dup 7))
 139                                        (match_dup 8))
 140                                (match_dup 4)))]
 141 {
 142         unsigned HOST_WIDE_INT mask = UINTVAL (operands[3]);
 143         /* scale: shift within the sh[123]add.uw */
 144         unsigned HOST_WIDE_INT scale = 32 - clz_hwi (mask);
 145         /* bias:  pre-scale amount (i.e. the prior shift amount) */
 146         int bias = ctz_hwi (mask) - scale;
 147
 148         /* If the bias + scale don't add up to operand[2], reject. */
 149         if ((scale + bias) != UINTVAL (operands[2]))
 150            FAIL;
 151
 152         /* If the shift-amount is out-of-range for sh[123]add.uw, reject. */
 153         if ((scale < 1) || (scale > 3))
 154            FAIL;
 155
 156         /* If there's no bias, the '*shNadduw' pattern should have matched. */
 157         if (bias == 0)
 158            FAIL;
 159
 160         operands[6] = GEN_INT (bias);
 161         operands[7] = GEN_INT (scale);
 162         operands[8] = GEN_INT (0xffffffffULL << scale);
 163 })
 164
 165 (define_insn "*add.uw"
 166   [(set (match_operand:DI 0 "register_operand" "=r")
 167         (plus:DI (zero_extend:DI
 168                    (match_operand:SI 1 "register_operand" "r"))
 169                  (match_operand:DI 2 "register_operand" "r")))]
 170   "TARGET_64BIT && TARGET_ZBA"
 171   "add.uw\t%0,%1,%2"
 172   [(set_attr "type" "bitmanip")
 173    (set_attr "mode" "DI")])
 174
 175 (define_insn "*slliuw"
 176   [(set (match_operand:DI 0 "register_operand" "=r")
 177         (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
 178                            (match_operand:QI 2 "immediate_operand" "I"))
 179                 (match_operand 3 "immediate_operand" "n")))]
 180   "TARGET_64BIT && TARGET_ZBA
 181    && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
 182   "slli.uw\t%0,%1,%2"
 183   [(set_attr "type" "bitmanip")
 184    (set_attr "mode" "DI")])
 185
 186 ;; ZBB extension.
 187
 188 (define_expand "clzdi2"
 189   [(set (match_operand:DI 0 "register_operand")
 190         (clz:DI (match_operand:DI 1 "register_operand")))]
 191   "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)")
 192
 193 (define_expand "clzsi2"
 194   [(set (match_operand:SI 0 "register_operand")
 195         (clz:SI (match_operand:SI 1 "register_operand")))]
 196   "TARGET_ZBB || (!TARGET_64BIT && TARGET_XTHEADBB)")
 197
 198 (define_expand "ctz<mode>2"
 199   [(set (match_operand:GPR 0 "register_operand")
 200         (ctz:GPR (match_operand:GPR 1 "register_operand")))]
 201   "TARGET_ZBB")
 202
 203 (define_expand "popcount<mode>2"
 204   [(set (match_operand:GPR 0 "register_operand")
 205         (popcount:GPR (match_operand:GPR 1 "register_operand")))]
 206   "TARGET_ZBB")
 207
 208 (define_insn "*<optab>_not<mode>"
 209   [(set (match_operand:X 0 "register_operand" "=r")
 210         (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
 211                             (match_operand:X 2 "register_operand" "r")))]
 212   "TARGET_ZBB || TARGET_ZBKB"
 213   "<insn>n\t%0,%2,%1"
 214   [(set_attr "type" "bitmanip")
 215    (set_attr "mode" "<X:MODE>")])
 216
 217 ;; '(a >= 0) ? b : 0' is emitted branchless (from if-conversion).  Without a
 218 ;; bit of extra help for combine (i.e., the below split), we end up emitting
 219 ;; not/srai/and instead of combining the not into an andn.
 220 (define_split
 221   [(set (match_operand:DI 0 "register_operand")
 222         (and:DI (neg:DI (ge:DI (match_operand:DI 1 "register_operand")
 223                                (const_int 0)))
 224                 (match_operand:DI 2 "register_operand")))
 225    (clobber (match_operand:DI 3 "register_operand"))]
 226   "TARGET_ZBB || TARGET_ZBKB"
 227   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
 228    (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 229
 230 (define_insn "*xor_not<mode>"
 231   [(set (match_operand:X 0 "register_operand" "=r")
 232         (not:X (xor:X (match_operand:X 1 "register_operand" "r")
 233                       (match_operand:X 2 "register_operand" "r"))))]
 234   "TARGET_ZBB || TARGET_ZBKB"
 235   "xnor\t%0,%1,%2"
 236   [(set_attr "type" "bitmanip")
 237    (set_attr "mode" "<X:MODE>")])
 238
 239 (define_insn "*<bitmanip_optab>si2"
 240   [(set (match_operand:SI 0 "register_operand" "=r")
 241         (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
 242   "TARGET_ZBB"
 243   "<bitmanip_insn>%~\t%0,%1"
 244   [(set_attr "type" "<bitmanip_insn>")
 245    (set_attr "mode" "SI")])
 246
 247 (define_insn "*<bitmanip_optab>disi2"
 248   [(set (match_operand:DI 0 "register_operand" "=r")
 249         (sign_extend:DI
 250           (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
 251   "TARGET_64BIT && TARGET_ZBB"
 252   "<bitmanip_insn>w\t%0,%1"
 253   [(set_attr "type" "<bitmanip_insn>")
 254    (set_attr "mode" "SI")])
 255
 256 (define_insn "*<bitmanip_optab>di2"
 257   [(set (match_operand:DI 0 "register_operand" "=r")
 258         (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
 259   "TARGET_64BIT && TARGET_ZBB"
 260   "<bitmanip_insn>\t%0,%1"
 261   [(set_attr "type" "<bitmanip_insn>")
 262    (set_attr "mode" "DI")])
 263
 264 (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
 265   [(set (match_operand:GPR 0 "register_operand" "=r,r")
 266         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 267   "TARGET_ZBB"
 268   "@
 269    zext.h\t%0,%1
 270    lhu\t%0,%1"
 271   [(set_attr "type" "bitmanip,load")
 272    (set_attr "mode" "<GPR:MODE>")])
 273
 274 (define_insn "*extend<SHORT:mode><SUPERQI:mode>2_zbb"
 275   [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
 276         (sign_extend:SUPERQI
 277             (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
 278   "TARGET_ZBB"
 279   "@
 280    sext.<SHORT:size>\t%0,%1
 281    l<SHORT:size>\t%0,%1"
 282   [(set_attr "type" "bitmanip,load")
 283    (set_attr "mode" "<SUPERQI:MODE>")])
 284
 285 (define_insn "*zero_extendhi<GPR:mode>2_zbb"
 286   [(set (match_operand:GPR    0 "register_operand"     "=r,r")
 287         (zero_extend:GPR
 288             (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
 289   "TARGET_ZBB"
 290   "@
 291    zext.h\t%0,%1
 292    lhu\t%0,%1"
 293   [(set_attr "type" "bitmanip,load")
 294    (set_attr "mode" "HI")])
 295
 296 (define_expand "rotr<mode>3"
 297   [(set (match_operand:GPR 0 "register_operand")
 298         (rotatert:GPR (match_operand:GPR 1 "register_operand")
 299                      (match_operand:QI 2 "arith_operand")))]
 300   "TARGET_ZBB || TARGET_XTHEADBB || TARGET_ZBKB"
 301 {
 302   if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
 303     FAIL;
 304 })
 305
 306 (define_insn "*rotrsi3"
 307   [(set (match_operand:SI 0 "register_operand" "=r")
 308         (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 309                      (match_operand:QI 2 "arith_operand" "rI")))]
 310   "TARGET_ZBB || TARGET_ZBKB"
 311   "ror%i2%~\t%0,%1,%2"
 312   [(set_attr "type" "bitmanip")])
 313
 314 (define_insn "*rotrdi3"
 315   [(set (match_operand:DI 0 "register_operand" "=r")
 316         (rotatert:DI (match_operand:DI 1 "register_operand" "r")
 317                      (match_operand:QI 2 "arith_operand" "rI")))]
 318   "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
 319   "ror%i2\t%0,%1,%2"
 320   [(set_attr "type" "bitmanip")])
 321
 322 (define_insn "*rotrsi3_sext"
 323   [(set (match_operand:DI 0 "register_operand" "=r")
 324         (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 325                                  (match_operand:QI 2 "arith_operand" "rI"))))]
 326   "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
 327   "ror%i2%~\t%0,%1,%2"
 328   [(set_attr "type" "bitmanip")])
 329
 330 (define_insn "rotlsi3"
 331   [(set (match_operand:SI 0 "register_operand" "=r")
 332         (rotate:SI (match_operand:SI 1 "register_operand" "r")
 333                    (match_operand:QI 2 "register_operand" "r")))]
 334   "TARGET_ZBB || TARGET_ZBKB"
 335   "rol%~\t%0,%1,%2"
 336   [(set_attr "type" "bitmanip")])
 337
 338 (define_insn "rotldi3"
 339   [(set (match_operand:DI 0 "register_operand" "=r")
 340         (rotate:DI (match_operand:DI 1 "register_operand" "r")
 341                    (match_operand:QI 2 "register_operand" "r")))]
 342   "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
 343   "rol\t%0,%1,%2"
 344   [(set_attr "type" "bitmanip")])
 345
 346 (define_insn "rotlsi3_sext"
 347   [(set (match_operand:DI 0 "register_operand" "=r")
 348         (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
 349                                    (match_operand:QI 2 "register_operand" "r"))))]
 350   "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
 351   "rolw\t%0,%1,%2"
 352   [(set_attr "type" "bitmanip")])
 353
 354 ;; orc.b (or-combine) is added as an unspec for the benefit of the support
 355 ;; for optimized string functions (such as strcmp).
 356 (define_insn "orcb<mode>2"
 357   [(set (match_operand:X 0 "register_operand" "=r")
 358         (unspec:X [(match_operand:X 1 "register_operand" "r")] UNSPEC_ORC_B))]
 359   "TARGET_ZBB"
 360   "orc.b\t%0,%1"
 361   [(set_attr "type" "bitmanip")])
 362
 363 (define_expand "bswapdi2"
 364   [(set (match_operand:DI 0 "register_operand")
 365         (bswap:DI (match_operand:DI 1 "register_operand")))]
 366   "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB || TARGET_ZBKB)")
 367
 368 (define_expand "bswapsi2"
 369   [(set (match_operand:SI 0 "register_operand")
 370         (bswap:SI (match_operand:SI 1 "register_operand")))]
 371   "(!TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)) || TARGET_XTHEADBB")
 372
 373 (define_insn "*bswap<mode>2"
 374   [(set (match_operand:X 0 "register_operand" "=r")
 375         (bswap:X (match_operand:X 1 "register_operand" "r")))]
 376   "TARGET_ZBB || TARGET_ZBKB"
 377   "rev8\t%0,%1"
 378   [(set_attr "type" "bitmanip")])
 379
 380 ;; HI bswap can be emulated using SI/DI bswap followed
 381 ;; by a logical shift right
 382 ;; SI bswap for TARGET_64BIT is already similarly in
 383 ;; the common code.
 384 (define_expand "bswaphi2"
 385   [(set (match_operand:HI 0 "register_operand" "=r")
 386         (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
 387   "TARGET_ZBB"
 388 {
 389   rtx tmp = gen_reg_rtx (word_mode);
 390   rtx newop1 = gen_lowpart (word_mode, operands[1]);
 391   if (TARGET_64BIT)
 392     emit_insn (gen_bswapdi2 (tmp, newop1));
 393   else
 394     emit_insn (gen_bswapsi2 (tmp, newop1));
 395   rtx tmp1 = gen_reg_rtx (word_mode);
 396   if (TARGET_64BIT)
 397     emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16)));
 398   else
 399     emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16)));
 400   emit_move_insn (operands[0], gen_lowpart (HImode, tmp1));
 401   DONE;
 402 })
 403
 404 (define_expand "<bitmanip_optab>di3"
 405   [(set (match_operand:DI 0 "register_operand" "=r")
 406         (bitmanip_minmax:DI (match_operand:DI 1 "register_operand" "r")
 407                             (match_operand:DI 2 "register_operand" "r")))]
 408   "TARGET_64BIT && TARGET_ZBB")
 409
 410 (define_expand "<bitmanip_optab>si3"
 411   [(set (match_operand:SI 0 "register_operand" "=r")
 412         (bitmanip_minmax:SI (match_operand:SI 1 "register_operand" "r")
 413                             (match_operand:SI 2 "register_operand" "r")))]
 414   "TARGET_ZBB"
 415 {
 416   if (TARGET_64BIT)
 417     {
 418       rtx t = gen_reg_rtx (DImode);
 419       operands[1] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[1]));
 420       operands[2] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[2]));
 421       emit_insn (gen_<bitmanip_optab>di3 (t, operands[1], operands[2]));
 422       emit_move_insn (operands[0], gen_lowpart (SImode, t));
 423       DONE;
 424     }
 425 })
 426
 427 (define_insn "*<bitmanip_optab><mode>3"
 428   [(set (match_operand:X 0 "register_operand" "=r")
 429         (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
 430                            (match_operand:X 2 "reg_or_0_operand" "rJ")))]
 431   "TARGET_ZBB"
 432   "<bitmanip_insn>\t%0,%1,%z2"
 433   [(set_attr "type" "<bitmanip_insn>")])
 434
 435 ;; Optimize the common case of a SImode min/max against a constant
 436 ;; that is safe both for sign- and zero-extension.
 437 (define_insn_and_split "*minmax"
 438   [(set (match_operand:DI 0 "register_operand" "=r")
 439         (sign_extend:DI
 440           (subreg:SI
 441             (bitmanip_minmax:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 442                                                 (match_operand:DI 2 "immediate_operand" "i"))
 443            0)))
 444    (clobber (match_scratch:DI 3 "=&r"))
 445    (clobber (match_scratch:DI 4 "=&r"))]
 446   "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
 447   "#"
 448   "&& reload_completed"
 449   [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
 450    (set (match_dup 4) (match_dup 2))
 451    (set (match_dup 0) (<minmax_optab>:DI (match_dup 3) (match_dup 4)))])
 452
 453 ;; ZBS extension.
 454
 455 (define_insn "*bset<mode>"
 456   [(set (match_operand:X 0 "register_operand" "=r")
 457         (ior:X (ashift:X (const_int 1)
 458                          (match_operand:QI 2 "register_operand" "r"))
 459                (match_operand:X 1 "register_operand" "r")))]
 460   "TARGET_ZBS"
 461   "bset\t%0,%1,%2"
 462   [(set_attr "type" "bitmanip")])
 463
 464 (define_insn "*bset<mode>_mask"
 465   [(set (match_operand:X 0 "register_operand" "=r")
 466         (ior:X (ashift:X (const_int 1)
 467                          (subreg:QI
 468                           (and:X (match_operand:X 2 "register_operand" "r")
 469                                  (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0))
 470                (match_operand:X 1 "register_operand" "r")))]
 471   "TARGET_ZBS"
 472   "bset\t%0,%1,%2"
 473   [(set_attr "type" "bitmanip")])
 474
 475 (define_insn "*bset<mode>_1"
 476   [(set (match_operand:X 0 "register_operand" "=r")
 477         (ashift:X (const_int 1)
 478                   (match_operand:QI 1 "register_operand" "r")))]
 479   "TARGET_ZBS"
 480   "bset\t%0,x0,%1"
 481   [(set_attr "type" "bitmanip")])
 482
 483 (define_insn "*bset<mode>_1_mask"
 484   [(set (match_operand:X 0 "register_operand" "=r")
 485         (ashift:X (const_int 1)
 486                   (subreg:QI
 487                    (and:X (match_operand:X 1 "register_operand" "r")
 488                           (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))]
 489   "TARGET_ZBS"
 490   "bset\t%0,x0,%1"
 491   [(set_attr "type" "bitmanip")])
 492
 493 (define_insn "*bseti<mode>"
 494   [(set (match_operand:X 0 "register_operand" "=r")
 495         (ior:X (match_operand:X 1 "register_operand" "r")
 496                (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
 497   "TARGET_ZBS"
 498   "bseti\t%0,%1,%S2"
 499   [(set_attr "type" "bitmanip")])
 500
 501 ;; As long as the SImode operand is not a partial subreg, we can use a
 502 ;; bseti without postprocessing, as the middle end is smart enough to
 503 ;; stay away from the signbit.
 504 (define_insn "*bsetidisi"
 505   [(set (match_operand:DI 0 "register_operand" "=r")
 506         (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 507                 (match_operand 2 "single_bit_mask_operand" "i")))]
 508   "TARGET_ZBS && TARGET_64BIT
 509    && !partial_subreg_p (operands[1])"
 510   "bseti\t%0,%1,%S2"
 511   [(set_attr "type" "bitmanip")])
 512
 513 (define_insn "*bclr<mode>"
 514   [(set (match_operand:X 0 "register_operand" "=r")
 515         (and:X (rotate:X (const_int -2)
 516                          (match_operand:QI 2 "register_operand" "r"))
 517                (match_operand:X 1 "register_operand" "r")))]
 518   "TARGET_ZBS"
 519   "bclr\t%0,%1,%2"
 520   [(set_attr "type" "bitmanip")])
 521
 522 (define_insn "*bclri<mode>"
 523   [(set (match_operand:X 0 "register_operand" "=r")
 524         (and:X (match_operand:X 1 "register_operand" "r")
 525                (match_operand:X 2 "not_single_bit_mask_operand" "DnS")))]
 526   "TARGET_ZBS"
 527   "bclri\t%0,%1,%T2"
 528   [(set_attr "type" "bitmanip")])
 529
 530 ;; In case we have "val & ~IMM" where ~IMM has 2 bits set.
 531 (define_insn_and_split "*bclri<mode>_nottwobits"
 532   [(set (match_operand:X 0 "register_operand" "=r")
 533         (and:X (match_operand:X 1 "register_operand" "r")
 534                (match_operand:X 2 "const_nottwobits_not_arith_operand" "i")))]
 535   "TARGET_ZBS && !paradoxical_subreg_p (operands[1])"
 536   "#"
 537   "&& reload_completed"
 538   [(set (match_dup 0) (and:X (match_dup 1) (match_dup 3)))
 539    (set (match_dup 0) (and:X (match_dup 0) (match_dup 4)))]
 540 {
 541         unsigned HOST_WIDE_INT bits = ~UINTVAL (operands[2]);
 542         unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);
 543
 544         operands[3] = GEN_INT (~bits | topbit);
 545         operands[4] = GEN_INT (~topbit);
 546 })
 547
 548 ;; In case of a paradoxical subreg, the sign bit and the high bits are
 549 ;; not allowed to be changed
 550 (define_insn_and_split "*bclridisi_nottwobits"
 551   [(set (match_operand:DI 0 "register_operand" "=r")
 552         (and:DI (match_operand:DI 1 "register_operand" "r")
 553                 (match_operand:DI 2 "const_nottwobits_not_arith_operand" "i")))]
 554   "TARGET_64BIT && TARGET_ZBS
 555    && clz_hwi (~UINTVAL (operands[2])) > 33"
 556   "#"
 557   "&& reload_completed"
 558   [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
 559    (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
 560 {
 561         unsigned HOST_WIDE_INT bits = ~UINTVAL (operands[2]);
 562         unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);
 563
 564         operands[3] = GEN_INT (~bits | topbit);
 565         operands[4] = GEN_INT (~topbit);
 566 })
 567
 568 (define_insn "*binv<mode>"
 569   [(set (match_operand:X 0 "register_operand" "=r")
 570         (xor:X (ashift:X (const_int 1)
 571                          (match_operand:QI 2 "register_operand" "r"))
 572                (match_operand:X 1 "register_operand" "r")))]
 573   "TARGET_ZBS"
 574   "binv\t%0,%1,%2"
 575   [(set_attr "type" "bitmanip")])
 576
 577 (define_insn "*binvi<mode>"
 578   [(set (match_operand:X 0 "register_operand" "=r")
 579         (xor:X (match_operand:X 1 "register_operand" "r")
 580                (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
 581   "TARGET_ZBS"
 582   "binvi\t%0,%1,%S2"
 583   [(set_attr "type" "bitmanip")])
 584
 585 (define_insn "*bext<mode>"
 586   [(set (match_operand:X 0 "register_operand" "=r")
 587         (zero_extract:X (match_operand:X 1 "register_operand" "r")
 588                         (const_int 1)
 589                         (zero_extend:X
 590                          (match_operand:QI 2 "register_operand" "r"))))]
 591   "TARGET_ZBS"
 592   "bext\t%0,%1,%2"
 593   [(set_attr "type" "bitmanip")])
 594
 595 ;; When performing `(a & (1UL << bitno)) ? 0 : -1` the combiner
 596 ;; usually has the `bitno` typed as X-mode (i.e. no further
 597 ;; zero-extension is performed around the bitno).
 598 (define_insn "*bext<mode>"
 599   [(set (match_operand:X 0 "register_operand" "=r")
 600         (zero_extract:X (match_operand:X 1 "register_operand" "r")
 601                         (const_int 1)
 602                         (match_operand:X 2 "register_operand" "r")))]
 603   "TARGET_ZBS"
 604   "bext\t%0,%1,%2"
 605   [(set_attr "type" "bitmanip")])
 606
 607 (define_insn "*bexti"
 608   [(set (match_operand:X 0 "register_operand" "=r")
 609         (zero_extract:X (match_operand:X 1 "register_operand" "r")
 610                         (const_int 1)
 611                         (match_operand 2 "immediate_operand" "n")))]
 612   "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
 613   "bexti\t%0,%1,%2"
 614   [(set_attr "type" "bitmanip")])
 615
 616 ;; Split for "(a & (1 << BIT_NO)) ? 0 : 1":
 617 ;; We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1",
 618 ;; so we don't have to use a temporary.  Instead we extract the bit and then
 619 ;; invert bit 0 ("a ^ 1") only.
 620 (define_split
 621   [(set (match_operand:X 0 "register_operand")
 622         (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
 623                                   (subreg:QI (match_operand:X 2 "register_operand") 0)))
 624                (const_int 1)))]
 625   "TARGET_ZBS"
 626   [(set (match_dup 0) (zero_extract:X (match_dup 1)
 627                                       (const_int 1)
 628                                       (match_dup 2)))
 629    (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
 630
 631 ;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 })
 632 ;; using a bext(i) followed by an addi instruction.
 633 ;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1".
 634 (define_split
 635   [(set (match_operand:GPR 0 "register_operand")
 636        (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand")
 637                                           (const_int 1)
 638                                           (match_operand 2))
 639                         (const_int 0))))]
 640   "TARGET_ZBS"
 641   [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2)))
 642    (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))])
 643
 644 ;; Catch those cases where we can use a bseti/binvi + ori/xori or
 645 ;; bseti/binvi + bseti/binvi instead of a lui + addi + or/xor sequence.
 646 (define_insn_and_split "*<or_optab>i<mode>_extrabit"
 647   [(set (match_operand:X 0 "register_operand" "=r")
 648         (any_or:X (match_operand:X 1 "register_operand" "r")
 649                   (match_operand:X 2 "uimm_extra_bit_or_twobits" "i")))]
 650   "TARGET_ZBS"
 651   "#"
 652   "&& reload_completed"
 653   [(set (match_dup 0) (<or_optab>:X (match_dup 1) (match_dup 3)))
 654    (set (match_dup 0) (<or_optab>:X (match_dup 0) (match_dup 4)))]
 655 {
 656         unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
 657         unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);
 658
 659         operands[3] = GEN_INT (bits &~ topbit);
 660         operands[4] = GEN_INT (topbit);
 661 })
 662
 663 ;; Same to use blcri + andi and blcri + bclri
 664 (define_insn_and_split "*andi<mode>_extrabit"
 665   [(set (match_operand:X 0 "register_operand" "=r")
 666         (and:X (match_operand:X 1 "register_operand" "r")
 667                (match_operand:X 2 "not_uimm_extra_bit_or_nottwobits" "i")))]
 668   "TARGET_ZBS"
 669   "#"
 670   "&& reload_completed"
 671   [(set (match_dup 0) (and:X (match_dup 1) (match_dup 3)))
 672    (set (match_dup 0) (and:X (match_dup 0) (match_dup 4)))]
 673 {
 674         unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
 675         unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (~bits);
 676
 677         operands[3] = GEN_INT (bits | topbit);
 678         operands[4] = GEN_INT (~topbit);
 679 })
 680
 681 ;; IF_THEN_ELSE: test for 2 bits of opposite polarity
 682 (define_insn_and_split "*branch<X:mode>_mask_twobits_equals_singlebit"
 683   [(set (pc)
 684         (if_then_else
 685           (match_operator 1 "equality_operator"
 686             [(and:X (match_operand:X 2 "register_operand" "r")
 687                     (match_operand:X 3 "const_twobits_not_arith_operand" "i"))
 688              (match_operand:X 4 "single_bit_mask_operand" "i")])
 689          (label_ref (match_operand 0 "" ""))
 690          (pc)))
 691    (clobber (match_scratch:X 5 "=&r"))
 692    (clobber (match_scratch:X 6 "=&r"))]
 693   "TARGET_ZBS && TARGET_ZBB"
 694   "#"
 695   "&& reload_completed"
 696   [(set (match_dup 5) (zero_extract:X (match_dup 2)
 697                                       (const_int 1)
 698                                       (match_dup 8)))
 699    (set (match_dup 6) (zero_extract:X (match_dup 2)
 700                                       (const_int 1)
 701                                       (match_dup 9)))
 702    (set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5)))
 703    (set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)])
 704                            (label_ref (match_dup 0))
 705                            (pc)))]
 706 {
 707    unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]);
 708    unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]);
 709
 710    /* We should never see an unsatisfiable condition.  */
 711    gcc_assert (twobits_mask & singlebit_mask);
 712
 713    int setbit = ctz_hwi (singlebit_mask);
 714    int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask);
 715
 716    operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE,
 717                                  <X:MODE>mode, operands[6], GEN_INT(0));
 718
 719    operands[8] = GEN_INT (setbit);
 720    operands[9] = GEN_INT (clearbit);
 721 })