gcc/config/riscv/iterators.md

   1 ;; Iterators for the machine description for RISC-V
   2 ;; Copyright (C) 2011-2023 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but
  12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 ;; General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20
  21 ;; -------------------------------------------------------------------
  22 ;; Mode Iterators
  23 ;; -------------------------------------------------------------------
  24
  25 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
  26 ;; from the same template.
  27 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
  28
  29 ;; This mode iterator allows :P to be used for patterns that operate on
  30 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
  31 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
  32
  33 ;; Likewise, but for XLEN-sized quantities.
  34 (define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
  35
  36 ;; Branches operate on XLEN-sized quantities, but for RV64 we accept
  37 ;; QImode values so we can force zero-extension.
  38 (define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")])
  39
  40 ;; 32-bit moves for which we provide move patterns.
  41 (define_mode_iterator MOVE32 [SI])
  42
  43 ;; 64-bit modes for which we provide move patterns.
  44 (define_mode_iterator MOVE64 [DI DF])
  45
  46 ;; Iterator for sub-32-bit integer modes.
  47 (define_mode_iterator SHORT [QI HI])
  48
  49 ;; Iterator for HImode constant generation.
  50 (define_mode_iterator HISI [HI SI])
  51
  52 ;; Iterator for QImode extension patterns.
  53 (define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")])
  54
  55 ;; Iterator for hardware integer modes narrower than XLEN.
  56 (define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])
  57
  58 ;; Iterator for hardware-supported integer modes.
  59 (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
  60
  61 ;; Iterator for hardware-supported floating-point modes.
  62 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
  63                             (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
  64                             (HF "TARGET_ZFH || TARGET_ZHINX")])
  65
  66 ;; Iterator for floating-point modes that can be loaded into X registers.
  67 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
  68
  69
  70 ;; -------------------------------------------------------------------
  71 ;; Mode attributes
  72 ;; -------------------------------------------------------------------
  73
  74 ;; This attribute gives the length suffix for a sign- or zero-extension
  75 ;; instruction.
  76 (define_mode_attr size [(QI "b") (HI "h")])
  77
  78 ;; Mode attributes for loads.
  79 (define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (HF "flh") (SF "flw") (DF "fld")])
  80
  81 ;; Instruction names for integer loads that aren't explicitly sign or zero
  82 ;; extended.  See riscv_output_move and LOAD_EXTEND_OP.
  83 (define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
  84
  85 ;; Mode attribute for FP loads into integer registers.
  86 (define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
  87
  88 ;; Instruction names for stores.
  89 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") (SF "fsw") (DF "fsd")])
  90
  91 ;; Instruction names for FP stores from integer registers.
  92 (define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")])
  93
  94 ;; This attribute gives the best constraint to use for registers of
  95 ;; a given mode.
  96 (define_mode_attr reg [(SI "d") (DI "d") (CC "d")])
  97
  98 ;; This attribute gives the format suffix for floating-point operations.
  99 (define_mode_attr fmt [(HF "h") (SF "s") (DF "d")])
 100
 101 ;; This attribute gives the integer suffix for floating-point conversions.
 102 (define_mode_attr ifmt [(SI "w") (DI "l")])
 103
 104 ;; This attribute gives the format suffix for atomic memory operations.
 105 (define_mode_attr amo [(SI "w") (DI "d")])
 106
 107 ;; This attribute gives the upper-case mode name for one unit of a
 108 ;; floating-point mode.
 109 (define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")])
 110
 111 ;; This attribute gives the integer mode that has half the size of
 112 ;; the controlling mode.
 113 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
 114
 115 ; bitmanip mode attribute
 116 (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
 117 (define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")])
 118
 119 ;; -------------------------------------------------------------------
 120 ;; Code Iterators
 121 ;; -------------------------------------------------------------------
 122
 123 ;; This code iterator allows signed and unsigned widening multiplications
 124 ;; to use the same template.
 125 (define_code_iterator any_extend [sign_extend zero_extend])
 126
 127 ;; This code iterator allows the two right shift instructions to be
 128 ;; generated from the same template.
 129 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
 130
 131 ;; This code iterator allows the three shift instructions to be generated
 132 ;; from the same template.
 133 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
 134
 135 ;; This code iterator allows the three bitwise instructions to be generated
 136 ;; from the same template.
 137 (define_code_iterator any_bitwise [and ior xor])
 138
 139 ;; This code iterator allows ior and xor instructions to be generated
 140 ;; from the same template.
 141 (define_code_iterator any_or [ior xor])
 142
 143 ;; This code iterator allows unsigned and signed division to be generated
 144 ;; from the same template.
 145 (define_code_iterator any_div [div udiv mod umod])
 146
 147 ;; This code iterator allows unsigned and signed modulus to be generated
 148 ;; from the same template.
 149 (define_code_iterator any_mod [mod umod])
 150
 151 ;; These code iterators allow the signed and unsigned scc operations to use
 152 ;; the same template.
 153 (define_code_iterator any_gt [gt gtu])
 154 (define_code_iterator any_ge [ge geu])
 155 (define_code_iterator any_lt [lt ltu])
 156 (define_code_iterator any_le [le leu])
 157
 158 ; atomics code iterator
 159 (define_code_iterator any_atomic [plus ior xor and])
 160
 161 ; bitmanip code iterators
 162 (define_code_iterator bitmanip_bitwise [and ior])
 163
 164 (define_code_iterator bitmanip_minmax [smin umin smax umax])
 165
 166 (define_code_iterator clz_ctz_pcnt [clz ctz popcount])
 167
 168 ;; -------------------------------------------------------------------
 169 ;; Code Attributes
 170 ;; -------------------------------------------------------------------
 171
 172 ;; <u> expands to an empty string when doing a signed operation and
 173 ;; "u" when doing an unsigned operation.
 174 (define_code_attr u [(sign_extend "") (zero_extend "u")
 175                      (gt "") (gtu "u")
 176                      (ge "") (geu "u")
 177                      (lt "") (ltu "u")
 178                      (le "") (leu "u")])
 179
 180 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
 181 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
 182
 183 ;; <optab> expands to the name of the optab for a particular code.
 184 (define_code_attr optab [(ashift "ashl")
 185                          (ashiftrt "ashr")
 186                          (lshiftrt "lshr")
 187                          (div "div")
 188                          (mod "mod")
 189                          (udiv "udiv")
 190                          (umod "umod")
 191                          (ge "ge")
 192                          (le "le")
 193                          (gt "gt")
 194                          (lt "lt")
 195                          (ior "ior")
 196                          (xor "xor")
 197                          (and "and")
 198                          (plus "add")
 199                          (minus "sub")])
 200
 201 ;; <or_optab> code attributes
 202 (define_code_attr or_optab [(ior "ior")
 203                             (xor "xor")])
 204
 205 ;; <insn> expands to the name of the insn that implements a particular code.
 206 (define_code_attr insn [(ashift "sll")
 207                         (ashiftrt "sra")
 208                         (lshiftrt "srl")
 209                         (div "div")
 210                         (mod "rem")
 211                         (udiv "divu")
 212                         (umod "remu")
 213                         (ior "or")
 214                         (xor "xor")
 215                         (and "and")
 216                         (plus "add")
 217                         (minus "sub")])
 218
 219 ; atomics code attribute
 220 (define_code_attr atomic_optab
 221   [(plus "add") (ior "or") (xor "xor") (and "and")])
 222
 223 ; bitmanip code attributes
 224 (define_code_attr minmax_optab [(smin "smin")
 225                                 (smax "smax")
 226                                 (umin "umin")
 227                                 (umax "umax")])
 228 (define_code_attr bitmanip_optab [(smin "smin")
 229                                   (smax "smax")
 230                                   (umin "umin")
 231                                   (umax "umax")
 232                                   (clz "clz")
 233                                   (ctz "ctz")
 234                                   (popcount "popcount")])
 235 (define_code_attr bitmanip_insn [(smin "min")
 236                                  (smax "max")
 237                                  (umin "minu")
 238                                  (umax "maxu")
 239                                  (clz "clz")
 240                                  (ctz "ctz")
 241                                  (popcount "cpop")])
 242
 243 ;; -------------------------------------------------------------------
 244 ;; Int Iterators.
 245 ;; -------------------------------------------------------------------
 246
 247 ;; Iterator and attributes for floating-point rounding instructions.
 248 (define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND])
 249 (define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")])
 250 (define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")])
 251
 252 ;; Iterator and attributes for quiet comparisons.
 253 (define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET])
 254 (define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") (UNSPEC_FLE_QUIET "le")])
 255 (define_int_attr QUIET_PATTERN [(UNSPEC_FLT_QUIET "LT") (UNSPEC_FLE_QUIET "LE")])
 256