gcc/config/riscv/riscv-protos.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2023 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_PROTOS_H
  23 #define GCC_RISCV_PROTOS_H
  24
  25 /* Symbol types we understand.  The order of this list must match that of
  26    the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST.  */
  27 enum riscv_symbol_type {
  28   SYMBOL_ABSOLUTE,
  29   SYMBOL_PCREL,
  30   SYMBOL_GOT_DISP,
  31   SYMBOL_TLS,
  32   SYMBOL_TLS_LE,
  33   SYMBOL_TLS_IE,
  34   SYMBOL_TLS_GD
  35 };
  36 #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
  37
  38 /* Routines implemented in riscv.cc.  */
  39 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
  40 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
  41 extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
  42 extern int riscv_address_insns (rtx, machine_mode, bool);
  43 extern int riscv_const_insns (rtx);
  44 extern int riscv_split_const_insns (rtx);
  45 extern int riscv_load_store_insns (rtx, rtx_insn *);
  46 extern rtx riscv_emit_move (rtx, rtx);
  47 extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool);
  48 extern bool riscv_split_symbol_type (enum riscv_symbol_type);
  49 extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
  50 extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode, bool);
  51 extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
  52 extern rtx riscv_subword (rtx, bool);
  53 extern bool riscv_split_64bit_move_p (rtx, rtx);
  54 extern void riscv_split_doubleword_move (rtx, rtx);
  55 extern const char *riscv_output_move (rtx, rtx);
  56 extern const char *riscv_output_return ();
  57 #ifdef RTX_CODE
  58 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
  59 extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
  60 extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
  61 extern void riscv_expand_conditional_move (rtx, rtx, rtx, rtx_code, rtx, rtx);
  62 #endif
  63 extern rtx riscv_legitimize_call_address (rtx);
  64 extern void riscv_set_return_address (rtx, rtx);
  65 extern bool riscv_expand_block_move (rtx, rtx, rtx);
  66 extern rtx riscv_return_addr (int, rtx);
  67 extern poly_int64 riscv_initial_elimination_offset (int, int);
  68 extern void riscv_expand_prologue (void);
  69 extern void riscv_expand_epilogue (int);
  70 extern bool riscv_epilogue_uses (unsigned int);
  71 extern bool riscv_can_use_return_insn (void);
  72 extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
  73 extern bool riscv_expand_block_move (rtx, rtx, rtx);
  74 extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
  75 extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
  76 extern bool riscv_gpr_save_operation_p (rtx);
  77 extern void riscv_reinit (void);
  78 extern poly_uint64 riscv_regmode_natural_size (machine_mode);
  79 extern bool riscv_v_ext_vector_mode_p (machine_mode);
  80 extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
  81
  82 /* Routines implemented in riscv-c.cc.  */
  83 void riscv_cpu_cpp_builtins (cpp_reader *);
  84 void riscv_register_pragmas (void);
  85
  86 /* Routines implemented in riscv-builtins.cc.  */
  87 extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
  88 extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
  89 extern tree riscv_builtin_decl (unsigned int, bool);
  90 extern void riscv_init_builtins (void);
  91
  92 /* Routines implemented in riscv-common.cc.  */
  93 extern std::string riscv_arch_str (bool version_p = true);
  94 extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
  95
  96 extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
  97
  98 rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
  99 rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
 100
 101 /* Information about one CPU we know about.  */
 102 struct riscv_cpu_info {
 103   /* This CPU's canonical name.  */
 104   const char *name;
 105
 106   /* Default arch for this CPU, could be NULL if no default arch.  */
 107   const char *arch;
 108
 109   /* Which automaton to use for tuning.  */
 110   const char *tune;
 111 };
 112
 113 extern const riscv_cpu_info *riscv_find_cpu (const char *);
 114
 115 /* Routines implemented in riscv-selftests.cc.  */
 116 #if CHECKING_P
 117 namespace selftest {
 118 extern void riscv_run_selftests (void);
 119 } // namespace selftest
 120 #endif
 121
 122 namespace riscv_vector {
 123 #define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
 124 enum vlmul_type
 125 {
 126   LMUL_1 = 0,
 127   LMUL_2 = 1,
 128   LMUL_4 = 2,
 129   LMUL_8 = 3,
 130   LMUL_RESERVED = 4,
 131   LMUL_F8 = 5,
 132   LMUL_F4 = 6,
 133   LMUL_F2 = 7,
 134 };
 135
 136 enum avl_type
 137 {
 138   NONVLMAX,
 139   VLMAX,
 140 };
 141 /* Routines implemented in riscv-vector-builtins.cc.  */
 142 extern void init_builtins (void);
 143 extern const char *mangle_builtin_type (const_tree);
 144 #ifdef GCC_TARGET_H
 145 extern bool verify_type_context (location_t, type_context_kind, const_tree, bool);
 146 #endif
 147 extern void handle_pragma_vector (void);
 148 extern tree builtin_decl (unsigned, bool);
 149 extern rtx expand_builtin (unsigned int, tree, rtx);
 150 extern bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 151 extern bool legitimize_move (rtx, rtx, machine_mode);
 152 extern void emit_pred_op (unsigned, rtx, rtx, machine_mode);
 153 extern enum vlmul_type get_vlmul (machine_mode);
 154 extern unsigned int get_ratio (machine_mode);
 155 extern int get_ta (rtx);
 156 extern int get_ma (rtx);
 157 extern int get_avl_type (rtx);
 158 extern unsigned int calculate_ratio (unsigned int, enum vlmul_type);
 159 enum tail_policy
 160 {
 161   TAIL_UNDISTURBED = 0,
 162   TAIL_AGNOSTIC = 1,
 163   TAIL_ANY = 2,
 164 };
 165
 166 enum mask_policy
 167 {
 168   MASK_UNDISTURBED = 0,
 169   MASK_AGNOSTIC = 1,
 170   MASK_ANY = 2,
 171 };
 172 enum tail_policy get_prefer_tail_policy ();
 173 enum mask_policy get_prefer_mask_policy ();
 174 rtx get_avl_type_rtx (enum avl_type);
 175 }
 176
 177 /* We classify builtin types into two classes:
 178    1. General builtin class which is defined in riscv_builtins.
 179    2. Vector builtin class which is a special builtin architecture
 180       that implement intrinsic short into "pragma".  */
 181 enum riscv_builtin_class
 182 {
 183   RISCV_BUILTIN_GENERAL,
 184   RISCV_BUILTIN_VECTOR
 185 };
 186
 187 const unsigned int RISCV_BUILTIN_SHIFT = 1;
 188
 189 /* Mask that selects the riscv_builtin_class part of a function code.  */
 190 const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
 191
 192 #endif /* ! GCC_RISCV_PROTOS_H */