gcc/config/riscv/riscv-vector-builtins.def

   1 /* Builtins macros for RISC-V 'V' Extension for GNU compiler.
   2    Copyright (C) 2022-2023 Free Software Foundation, Inc.
   3    Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3, or (at your option)
  10 any later version.
  11
  12 GCC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING3.  If not see
  19 <http://www.gnu.org/licenses/>.  */
  20
  21 /* Use "DEF_RVV_TYPE" macro to define RVV datatype builtins.
  22    1.The 'NAME' argument is the name exposed to users.
  23      For example, "vint32m1_t".
  24    2.The 'NCHARS' argument is the length of ABI-name.
  25      For example, length of "__rvv_int32m1_t" is 15.
  26    3.The 'ABI_NAME' argument is the ABI-name. For example, "__rvv_int32m1_t".
  27    4.The 'SCALAR_TYPE' argument is associated scalar type which is used in
  28      "build_vector_type_for_mode". For "vint32m1_t", we use "intSI_type_node" in
  29      RV64. Otherwise, we use "long_integer_type_node".
  30    5.The 'VECTOR_MODE' is the machine modes of corresponding RVV type used
  31      in "build_vector_type_for_mode" when TARGET_MIN_VLEN > 32.
  32      For example: VECTOR_MODE = VNx2SI for "vint32m1_t".
  33    6.The 'VECTOR_MODE_MIN_VLEN_32' is the machine modes of corresponding RVV
  34      type used in "build_vector_type_for_mode" when TARGET_MIN_VLEN = 32. For
  35      example: VECTOR_MODE_MIN_VLEN_32 = VNx1SI for "vint32m1_t".
  36    7.The 'VECTOR_SUFFIX' define mode suffix for vector type.
  37      For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vector = i32m1.
  38    8.The 'SCALAR_SUFFIX' define mode suffix for scalar type.
  39      For example: type_suffixes[VECTOR_TYPE_vin32m1_t].scalar = i32.
  40    9.The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction.
  41      For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vsetvl = e32m1.
  42 */
  43
  44 #ifndef DEF_RVV_TYPE
  45 #define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE,         \
  46                      VECTOR_MODE_MIN_VLEN_32, VECTOR_SUFFIX, SCALAR_SUFFIX,    \
  47                      VSETVL_SUFFIX, MASK_TYPE)
  48 #endif
  49
  50 /* Use "DEF_RVV_OP_TYPE" macro to define RVV operand types.
  51    The 'NAME' will be concatenated into intrinsic function name.  */
  52 #ifndef DEF_RVV_OP_TYPE
  53 #define DEF_RVV_OP_TYPE(NAME)
  54 #endif
  55
  56 /* Use "DEF_RVV_PRED_TYPE" macro to define RVV predication types.
  57    The 'NAME' will be concatenated into intrinsic function name.  */
  58 #ifndef DEF_RVV_PRED_TYPE
  59 #define DEF_RVV_PRED_TYPE(NAME)
  60 #endif
  61
  62 /* SEW/LMUL = 64:
  63    Only enable when TARGET_MIN_VLEN > 32 and machine mode = VNx1BImode.  */
  64 DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, VNx1BI, VOID, _b64, , , vbool64_t)
  65 /* SEW/LMUL = 32:
  66    Machine mode = VNx2BImode when TARGET_MIN_VLEN > 32.
  67    Machine mode = VNx1BImode when TARGET_MIN_VLEN = 32.  */
  68 DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, VNx2BI, VNx1BI, _b32, , , vbool32_t)
  69 /* SEW/LMUL = 16:
  70    Machine mode = VNx2BImode when TARGET_MIN_VLEN = 32.
  71    Machine mode = VNx4BImode when TARGET_MIN_VLEN > 32.  */
  72 DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, VNx4BI, VNx2BI, _b16, , , vbool16_t)
  73 /* SEW/LMUL = 8:
  74    Machine mode = VNx8BImode when TARGET_MIN_VLEN > 32.
  75    Machine mode = VNx4BImode when TARGET_MIN_VLEN = 32.  */
  76 DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, VNx8BI, VNx4BI, _b8, , , vbool8_t)
  77 /* SEW/LMUL = 4:
  78    Machine mode = VNx16BImode when TARGET_MIN_VLEN > 32.
  79    Machine mode = VNx8BImode when TARGET_MIN_VLEN = 32.  */
  80 DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, VNx16BI, VNx8BI, _b4, , , vbool4_t)
  81 /* SEW/LMUL = 2:
  82    Machine mode = VNx32BImode when TARGET_MIN_VLEN > 32.
  83    Machine mode = VNx16BImode when TARGET_MIN_VLEN = 32.  */
  84 DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, VNx32BI, VNx16BI, _b2, , , vbool2_t)
  85 /* SEW/LMUL = 1:
  86    Machine mode = VNx64BImode when TARGET_MIN_VLEN > 32.
  87    Machine mode = VNx32BImode when TARGET_MIN_VLEN = 32.  */
  88 DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, VNx64BI, VNx32BI, _b1, , , vbool1_t)
  89
  90 /* LMUL = 1/8:
  91    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1QImode.  */
  92 DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, int8, VNx1QI, VOID, _i8mf8, _i8,
  93               _e8mf8, vbool64_t)
  94 DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, uint8, VNx1QI, VOID,
  95               _u8mf8, _u8, _e8mf8, vbool64_t)
  96 /* LMUL = 1/4:
  97    Machine mode = VNx2QImode when TARGET_MIN_VLEN > 32.
  98    Machine mode = VNx1QImode when TARGET_MIN_VLEN = 32.  */
  99 DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, int8, VNx2QI, VNx1QI, _i8mf4,
 100               _i8, _e8mf4, vbool32_t)
 101 DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, uint8, VNx2QI, VNx1QI,
 102               _u8mf4, _u8, _e8mf4, vbool32_t)
 103 /* LMUL = 1/2:
 104    Machine mode = VNx4QImode when TARGET_MIN_VLEN > 32.
 105    Machine mode = VNx2QImode when TARGET_MIN_VLEN = 32.  */
 106 DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, int8, VNx4QI, VNx2QI, _i8mf2,
 107               _i8, _e8mf2, vbool16_t)
 108 DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, uint8, VNx4QI, VNx2QI,
 109               _u8mf2, _u8, _e8mf2, vbool16_t)
 110 /* LMUL = 1:
 111    Machine mode = VNx8QImode when TARGET_MIN_VLEN > 32.
 112    Machine mode = VNx4QImode when TARGET_MIN_VLEN = 32.  */
 113 DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, int8, VNx8QI, VNx4QI, _i8m1, _i8,
 114               _e8m1, vbool8_t)
 115 DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, uint8, VNx8QI, VNx4QI,
 116               _u8m1, _u8, _e8m1, vbool8_t)
 117 /* LMUL = 2:
 118    Machine mode = VNx16QImode when TARGET_MIN_VLEN > 32.
 119    Machine mode = VNx8QImode when TARGET_MIN_VLEN = 32.  */
 120 DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, int8, VNx16QI, VNx8QI, _i8m2, _i8,
 121               _e8m2, vbool4_t)
 122 DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, uint8, VNx16QI, VNx8QI,
 123               _u8m2, _u8, _e8m2, vbool4_t)
 124 /* LMUL = 4:
 125    Machine mode = VNx32QImode when TARGET_MIN_VLEN > 32.
 126    Machine mode = VNx16QImode when TARGET_MIN_VLEN = 32.  */
 127 DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, int8, VNx32QI, VNx16QI, _i8m4,
 128               _i8, _e8m4, vbool2_t)
 129 DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, uint8, VNx32QI, VNx16QI,
 130               _u8m4, _u8, _e8m4, vbool2_t)
 131 /* LMUL = 8:
 132    Machine mode = VNx64QImode when TARGET_MIN_VLEN > 32.
 133    Machine mode = VNx32QImode when TARGET_MIN_VLEN = 32.  */
 134 DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, int8, VNx64QI, VNx32QI, _i8m8,
 135               _i8, _e8m8, vbool1_t)
 136 DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, uint8, VNx64QI, VNx32QI,
 137               _u8m8, _u8, _e8m8, vbool1_t)
 138
 139 /* LMUL = 1/4:
 140    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1HImode.  */
 141 DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, int16, VNx1HI, VOID, _i16mf4,
 142               _i16, _e16mf4, vbool64_t)
 143 DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, uint16, VNx1HI, VOID,
 144               _u16mf4, _u16, _e16mf4, vbool64_t)
 145 /* LMUL = 1/2:
 146    Machine mode = VNx2HImode when TARGET_MIN_VLEN > 32.
 147    Machine mode = VNx1HImode when TARGET_MIN_VLEN = 32.  */
 148 DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, int16, VNx2HI, VNx1HI, _i16mf2,
 149               _i16, _e16mf2, vbool32_t)
 150 DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, uint16, VNx2HI,
 151               VNx1HI, _u16mf2, _u16, _e16mf2, vbool32_t)
 152 /* LMUL = 1:
 153    Machine mode = VNx4HImode when TARGET_MIN_VLEN > 32.
 154    Machine mode = VNx2HImode when TARGET_MIN_VLEN = 32.  */
 155 DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, int16, VNx4HI, VNx2HI, _i16m1,
 156               _i16, _e16m1, vbool16_t)
 157 DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, uint16, VNx4HI, VNx2HI,
 158               _u16m1, _u16, _e16m1, vbool16_t)
 159 /* LMUL = 2:
 160    Machine mode = VNx8HImode when TARGET_MIN_VLEN > 32.
 161    Machine mode = VNx4HImode when TARGET_MIN_VLEN = 32.  */
 162 DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, int16, VNx8HI, VNx4HI, _i16m2,
 163               _i16, _e16m2, vbool8_t)
 164 DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, uint16, VNx8HI, VNx4HI,
 165               _u16m2, _u16, _e16m2, vbool8_t)
 166 /* LMUL = 4:
 167    Machine mode = VNx16HImode when TARGET_MIN_VLEN > 32.
 168    Machine mode = VNx8HImode when TARGET_MIN_VLEN = 32.  */
 169 DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, int16, VNx16HI, VNx8HI, _i16m4,
 170               _i16, _e16m4, vbool4_t)
 171 DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, uint16, VNx16HI,
 172               VNx8HI, _u16m4, _u16, _e16m4, vbool4_t)
 173 /* LMUL = 8:
 174    Machine mode = VNx32HImode when TARGET_MIN_VLEN > 32.
 175    Machine mode = VNx16HImode when TARGET_MIN_VLEN = 32.  */
 176 DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, int16, VNx32HI, VNx16HI, _i16m8,
 177               _i16, _e16m8, vbool2_t)
 178 DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, uint16, VNx32HI,
 179               VNx16HI, _u16m8, _u16, _e16m8, vbool2_t)
 180
 181 /* LMUL = 1/2:
 182    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SImode.  */
 183 DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, VNx1SI, VOID, _i32mf2,
 184               _i32, _e32mf2, vbool64_t)
 185 DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, uint32, VNx1SI, VOID,
 186               _u32mf2, _u32, _e32mf2, vbool64_t)
 187 /* LMUL = 1:
 188    Machine mode = VNx2SImode when TARGET_MIN_VLEN > 32.
 189    Machine mode = VNx1SImode when TARGET_MIN_VLEN = 32.  */
 190 DEF_RVV_TYPE (vint32m1_t, 15, __rvv_int32m1_t, int32, VNx2SI, VNx1SI, _i32m1,
 191               _i32, _e32m1, vbool32_t)
 192 DEF_RVV_TYPE (vuint32m1_t, 16, __rvv_uint32m1_t, uint32, VNx2SI, VNx1SI,
 193               _u32m1, _u32, _e32m1, vbool32_t)
 194 /* LMUL = 2:
 195    Machine mode = VNx4SImode when TARGET_MIN_VLEN > 32.
 196    Machine mode = VNx2SImode when TARGET_MIN_VLEN = 32.  */
 197 DEF_RVV_TYPE (vint32m2_t, 15, __rvv_int32m2_t, int32, VNx4SI, VNx2SI, _i32m2,
 198               _i32, _e32m2, vbool16_t)
 199 DEF_RVV_TYPE (vuint32m2_t, 16, __rvv_uint32m2_t, uint32, VNx4SI, VNx2SI,
 200               _u32m2, _u32, _e32m2, vbool16_t)
 201 /* LMUL = 4:
 202    Machine mode = VNx8SImode when TARGET_MIN_VLEN > 32.
 203    Machine mode = VNx4SImode when TARGET_MIN_VLEN = 32.  */
 204 DEF_RVV_TYPE (vint32m4_t, 15, __rvv_int32m4_t, int32, VNx8SI, VNx4SI, _i32m4,
 205               _i32, _e32m4, vbool8_t)
 206 DEF_RVV_TYPE (vuint32m4_t, 16, __rvv_uint32m4_t, uint32, VNx8SI, VNx4SI,
 207               _u32m4, _u32, _e32m4, vbool8_t)
 208 /* LMUL = 8:
 209    Machine mode = VNx16SImode when TARGET_MIN_VLEN > 32.
 210    Machine mode = VNx8SImode when TARGET_MIN_VLEN = 32.  */
 211 DEF_RVV_TYPE (vint32m8_t, 15, __rvv_int32m8_t, int32, VNx16SI, VNx8SI, _i32m8,
 212               _i32, _e32m8, vbool4_t)
 213 DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI,
 214               VNx8SI, _u32m8, _u32, _e32m8, vbool4_t)
 215
 216 /* SEW = 64:
 217    Disable when TARGET_MIN_VLEN > 32.  */
 218 DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1,
 219               _i64, _e64m1, vbool64_t)
 220 DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID,
 221               _u64m1, _u64, _e64m1, vbool64_t)
 222 DEF_RVV_TYPE (vint64m2_t, 15, __rvv_int64m2_t, int64, VNx2DI, VOID, _i64m2,
 223               _i64, _e64m2, vbool32_t)
 224 DEF_RVV_TYPE (vuint64m2_t, 16, __rvv_uint64m2_t, uint64, VNx2DI, VOID,
 225               _u64m2, _u64, _e64m2, vbool32_t)
 226 DEF_RVV_TYPE (vint64m4_t, 15, __rvv_int64m4_t, int64, VNx4DI, VOID, _i64m4,
 227               _i64, _e64m4, vbool16_t)
 228 DEF_RVV_TYPE (vuint64m4_t, 16, __rvv_uint64m4_t, uint64, VNx4DI, VOID,
 229               _u64m4, _u64, _e64m4, vbool16_t)
 230 DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, VNx8DI, VOID, _i64m8,
 231               _i64, _e64m8, vbool8_t)
 232 DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx8DI, VOID,
 233               _u64m8, _u64, _e64m8, vbool8_t)
 234
 235 /* LMUL = 1/2:
 236    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SFmode.  */
 237 DEF_RVV_TYPE (vfloat32mf2_t, 18, __rvv_float32mf2_t, float, VNx1SF, VOID,
 238               _f32mf2, _f32, _e32mf2, vbool64_t)
 239 /* LMUL = 1:
 240    Machine mode = VNx2SFmode when TARGET_MIN_VLEN > 32.
 241    Machine mode = VNx1SFmode when TARGET_MIN_VLEN = 32.  */
 242 DEF_RVV_TYPE (vfloat32m1_t, 17, __rvv_float32m1_t, float, VNx2SF, VNx1SF,
 243               _f32m1, _f32, _e32m1, vbool32_t)
 244 /* LMUL = 2:
 245    Machine mode = VNx4SFmode when TARGET_MIN_VLEN > 32.
 246    Machine mode = VNx2SFmode when TARGET_MIN_VLEN = 32.  */
 247 DEF_RVV_TYPE (vfloat32m2_t, 17, __rvv_float32m2_t, float, VNx4SF, VNx2SF,
 248               _f32m2, _f32, _e32m2, vbool16_t)
 249 /* LMUL = 4:
 250    Machine mode = VNx8SFmode when TARGET_MIN_VLEN > 32.
 251    Machine mode = VNx4SFmode when TARGET_MIN_VLEN = 32.  */
 252 DEF_RVV_TYPE (vfloat32m4_t, 17, __rvv_float32m4_t, float, VNx8SF, VNx4SF,
 253               _f32m4, _f32, _e32m4, vbool8_t)
 254 /* LMUL = 8:
 255    Machine mode = VNx16SFmode when TARGET_MIN_VLEN > 32.
 256    Machine mode = VNx8SFmode when TARGET_MIN_VLEN = 32.  */
 257 DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF,
 258               _f32m8, _f32, _e32m8, vbool4_t)
 259
 260 /* SEW = 64:
 261    Disable when TARGET_VECTOR_FP64.  */
 262 DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1,
 263               _f64, _e64m1, vbool64_t)
 264 DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2,
 265               _f64, _e64m2, vbool32_t)
 266 DEF_RVV_TYPE (vfloat64m4_t, 17, __rvv_float64m4_t, double, VNx4DF, VOID, _f64m4,
 267               _f64, _e64m4, vbool16_t)
 268 DEF_RVV_TYPE (vfloat64m8_t, 17, __rvv_float64m8_t, double, VNx8DF, VOID, _f64m8,
 269               _f64, _e64m8, vbool8_t)
 270
 271 DEF_RVV_OP_TYPE (vv)
 272 DEF_RVV_OP_TYPE (vx)
 273 DEF_RVV_OP_TYPE (v)
 274 DEF_RVV_OP_TYPE (wv)
 275 DEF_RVV_OP_TYPE (wx)
 276 DEF_RVV_OP_TYPE (x_v)
 277 DEF_RVV_OP_TYPE (vf2)
 278 DEF_RVV_OP_TYPE (vf4)
 279 DEF_RVV_OP_TYPE (vf8)
 280 DEF_RVV_OP_TYPE (vvm)
 281 DEF_RVV_OP_TYPE (vxm)
 282 DEF_RVV_OP_TYPE (x_w)
 283 DEF_RVV_OP_TYPE (x)
 284 DEF_RVV_OP_TYPE (vs)
 285 DEF_RVV_OP_TYPE (mm)
 286 DEF_RVV_OP_TYPE (m)
 287 DEF_RVV_OP_TYPE (vf)
 288 DEF_RVV_OP_TYPE (vm)
 289 DEF_RVV_OP_TYPE (wf)
 290 DEF_RVV_OP_TYPE (vfm)
 291 DEF_RVV_OP_TYPE (v_f)
 292
 293 DEF_RVV_PRED_TYPE (ta)
 294 DEF_RVV_PRED_TYPE (tu)
 295 DEF_RVV_PRED_TYPE (ma)
 296 DEF_RVV_PRED_TYPE (mu)
 297 DEF_RVV_PRED_TYPE (tama)
 298 DEF_RVV_PRED_TYPE (tamu)
 299 DEF_RVV_PRED_TYPE (tuma)
 300 DEF_RVV_PRED_TYPE (tumu)
 301 DEF_RVV_PRED_TYPE (m)
 302 DEF_RVV_PRED_TYPE (tam)
 303 DEF_RVV_PRED_TYPE (tum)
 304
 305 #undef DEF_RVV_PRED_TYPE
 306 #undef DEF_RVV_OP_TYPE
 307 #undef DEF_RVV_TYPE