gcc/config/riscv/riscv-vector-builtins.def

   1 /* Builtins macros for RISC-V 'V' Extension for GNU compiler.
   2    Copyright (C) 2022-2023 Free Software Foundation, Inc.
   3    Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3, or (at your option)
  10 any later version.
  11
  12 GCC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING3.  If not see
  19 <http://www.gnu.org/licenses/>.  */
  20
  21 /* Use "DEF_RVV_TYPE" macro to define RVV datatype builtins.
  22    1.The 'NAME' argument is the name exposed to users.
  23      For example, "vint32m1_t".
  24    2.The 'NCHARS' argument is the length of ABI-name.
  25      For example, length of "__rvv_int32m1_t" is 15.
  26    3.The 'ABI_NAME' argument is the ABI-name. For example, "__rvv_int32m1_t".
  27    4.The 'SCALAR_TYPE' argument is associated scalar type which is used in
  28      "build_vector_type_for_mode". For "vint32m1_t", we use "intSI_type_node" in
  29      RV64. Otherwise, we use "long_integer_type_node".
  30    5.The 'VECTOR_MODE' is the machine modes of corresponding RVV type used
  31      in "build_vector_type_for_mode" when TARGET_MIN_VLEN > 32.
  32      For example: VECTOR_MODE = VNx2SI for "vint32m1_t".
  33    6.The 'VECTOR_MODE_MIN_VLEN_32' is the machine modes of corresponding RVV
  34      type used in "build_vector_type_for_mode" when TARGET_MIN_VLEN = 32. For
  35      example: VECTOR_MODE_MIN_VLEN_32 = VNx1SI for "vint32m1_t".
  36    7.The 'VECTOR_SUFFIX' define mode suffix for vector type.
  37      For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vector = i32m1.
  38    8.The 'SCALAR_SUFFIX' define mode suffix for scalar type.
  39      For example: type_suffixes[VECTOR_TYPE_vin32m1_t].scalar = i32.
  40    9.The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction.
  41      For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vsetvl = e32m1.
  42 */
  43
  44 #ifndef DEF_RVV_TYPE
  45 #define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE,         \
  46                      VECTOR_MODE_MIN_VLEN_32, VECTOR_SUFFIX, SCALAR_SUFFIX,    \
  47                      VSETVL_SUFFIX)
  48 #endif
  49
  50 /* Use "DEF_RVV_OP_TYPE" macro to define RVV operand types.
  51    The 'NAME' will be concatenated into intrinsic function name.  */
  52 #ifndef DEF_RVV_OP_TYPE
  53 #define DEF_RVV_OP_TYPE(NAME)
  54 #endif
  55
  56 /* Use "DEF_RVV_PRED_TYPE" macro to define RVV predication types.
  57    The 'NAME' will be concatenated into intrinsic function name.  */
  58 #ifndef DEF_RVV_PRED_TYPE
  59 #define DEF_RVV_PRED_TYPE(NAME)
  60 #endif
  61
  62 /* Use "DEF_RVV_BASE_TYPE" macro to define RVV base types.
  63    The 'NAME' will be concatenated into intrinsic function name.  */
  64 #ifndef DEF_RVV_BASE_TYPE
  65 #define DEF_RVV_BASE_TYPE(NAME, TYPE)
  66 #endif
  67
  68 /* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types.
  69    The 'NAME' will be concatenated into intrinsic function name.  */
  70 #ifndef DEF_RVV_TYPE_INDEX
  71 #define DEF_RVV_TYPE_INDEX(VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, \
  72                       EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC,           \
  73                       QUAD_TRUNC, OCT_TRUNC, DOUBLE_TRUNC_SCALAR,              \
  74                       DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED,              \
  75                       DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, \
  76                       LMUL1, WLMUL1, EEW8_INTERPRET, EEW16_INTERPRET,          \
  77                       EEW32_INTERPRET, EEW64_INTERPRET, X2_VLMUL_EXT,          \
  78                       X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT,               \
  79                       X32_VLMUL_EXT, X64_VLMUL_EXT)
  80 #endif
  81
  82 /* SEW/LMUL = 64:
  83    Only enable when TARGET_MIN_VLEN > 32 and machine mode = VNx1BImode.  */
  84 DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, VNx1BI, VOID, _b64, , )
  85 /* SEW/LMUL = 32:
  86    Machine mode = VNx2BImode when TARGET_MIN_VLEN > 32.
  87    Machine mode = VNx1BImode when TARGET_MIN_VLEN = 32.  */
  88 DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, VNx2BI, VNx1BI, _b32, , )
  89 /* SEW/LMUL = 16:
  90    Machine mode = VNx2BImode when TARGET_MIN_VLEN = 32.
  91    Machine mode = VNx4BImode when TARGET_MIN_VLEN > 32.  */
  92 DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, VNx4BI, VNx2BI, _b16, , )
  93 /* SEW/LMUL = 8:
  94    Machine mode = VNx8BImode when TARGET_MIN_VLEN > 32.
  95    Machine mode = VNx4BImode when TARGET_MIN_VLEN = 32.  */
  96 DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, VNx8BI, VNx4BI, _b8, , )
  97 /* SEW/LMUL = 4:
  98    Machine mode = VNx16BImode when TARGET_MIN_VLEN > 32.
  99    Machine mode = VNx8BImode when TARGET_MIN_VLEN = 32.  */
 100 DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, VNx16BI, VNx8BI, _b4, , )
 101 /* SEW/LMUL = 2:
 102    Machine mode = VNx32BImode when TARGET_MIN_VLEN > 32.
 103    Machine mode = VNx16BImode when TARGET_MIN_VLEN = 32.  */
 104 DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, VNx32BI, VNx16BI, _b2, , )
 105 /* SEW/LMUL = 1:
 106    Machine mode = VNx64BImode when TARGET_MIN_VLEN > 32.
 107    Machine mode = VNx32BImode when TARGET_MIN_VLEN = 32.  */
 108 DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, VNx64BI, VNx32BI, _b1, , )
 109
 110 /* LMUL = 1/8:
 111    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1QImode.  */
 112 DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, int8, VNx1QI, VOID, _i8mf8, _i8,
 113               _e8mf8)
 114 DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, uint8, VNx1QI, VOID, _u8mf8,
 115               _u8, _e8mf8)
 116 /* LMUL = 1/4:
 117    Machine mode = VNx2QImode when TARGET_MIN_VLEN > 32.
 118    Machine mode = VNx1QImode when TARGET_MIN_VLEN = 32.  */
 119 DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, int8, VNx2QI, VNx1QI, _i8mf4,
 120               _i8, _e8mf4)
 121 DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, uint8, VNx2QI, VNx1QI, _u8mf4,
 122               _u8, _e8mf4)
 123 /* LMUL = 1/2:
 124    Machine mode = VNx4QImode when TARGET_MIN_VLEN > 32.
 125    Machine mode = VNx2QImode when TARGET_MIN_VLEN = 32.  */
 126 DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, int8, VNx4QI, VNx2QI, _i8mf2,
 127               _i8, _e8mf2)
 128 DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, uint8, VNx4QI, VNx2QI, _u8mf2,
 129               _u8, _e8mf2)
 130 /* LMUL = 1:
 131    Machine mode = VNx8QImode when TARGET_MIN_VLEN > 32.
 132    Machine mode = VNx4QImode when TARGET_MIN_VLEN = 32.  */
 133 DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, int8, VNx8QI, VNx4QI, _i8m1, _i8,
 134               _e8m1)
 135 DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, uint8, VNx8QI, VNx4QI, _u8m1,
 136               _u8, _e8m1)
 137 /* LMUL = 2:
 138    Machine mode = VNx16QImode when TARGET_MIN_VLEN > 32.
 139    Machine mode = VNx8QImode when TARGET_MIN_VLEN = 32.  */
 140 DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, int8, VNx16QI, VNx8QI, _i8m2, _i8,
 141               _e8m2)
 142 DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, uint8, VNx16QI, VNx8QI, _u8m2,
 143               _u8, _e8m2)
 144 /* LMUL = 4:
 145    Machine mode = VNx32QImode when TARGET_MIN_VLEN > 32.
 146    Machine mode = VNx16QImode when TARGET_MIN_VLEN = 32.  */
 147 DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, int8, VNx32QI, VNx16QI, _i8m4, _i8,
 148               _e8m4)
 149 DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, uint8, VNx32QI, VNx16QI, _u8m4,
 150               _u8, _e8m4)
 151 /* LMUL = 8:
 152    Machine mode = VNx64QImode when TARGET_MIN_VLEN > 32.
 153    Machine mode = VNx32QImode when TARGET_MIN_VLEN = 32.  */
 154 DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, int8, VNx64QI, VNx32QI, _i8m8, _i8,
 155               _e8m8)
 156 DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, uint8, VNx64QI, VNx32QI, _u8m8,
 157               _u8, _e8m8)
 158
 159 /* LMUL = 1/4:
 160    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1HImode.  */
 161 DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, int16, VNx1HI, VOID, _i16mf4,
 162               _i16, _e16mf4)
 163 DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, uint16, VNx1HI, VOID,
 164               _u16mf4, _u16, _e16mf4)
 165 /* LMUL = 1/2:
 166    Machine mode = VNx2HImode when TARGET_MIN_VLEN > 32.
 167    Machine mode = VNx1HImode when TARGET_MIN_VLEN = 32.  */
 168 DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, int16, VNx2HI, VNx1HI, _i16mf2,
 169               _i16, _e16mf2)
 170 DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, uint16, VNx2HI, VNx1HI,
 171               _u16mf2, _u16, _e16mf2)
 172 /* LMUL = 1:
 173    Machine mode = VNx4HImode when TARGET_MIN_VLEN > 32.
 174    Machine mode = VNx2HImode when TARGET_MIN_VLEN = 32.  */
 175 DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, int16, VNx4HI, VNx2HI, _i16m1,
 176               _i16, _e16m1)
 177 DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, uint16, VNx4HI, VNx2HI, _u16m1,
 178               _u16, _e16m1)
 179 /* LMUL = 2:
 180    Machine mode = VNx8HImode when TARGET_MIN_VLEN > 32.
 181    Machine mode = VNx4HImode when TARGET_MIN_VLEN = 32.  */
 182 DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, int16, VNx8HI, VNx4HI, _i16m2,
 183               _i16, _e16m2)
 184 DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, uint16, VNx8HI, VNx4HI, _u16m2,
 185               _u16, _e16m2)
 186 /* LMUL = 4:
 187    Machine mode = VNx16HImode when TARGET_MIN_VLEN > 32.
 188    Machine mode = VNx8HImode when TARGET_MIN_VLEN = 32.  */
 189 DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, int16, VNx16HI, VNx8HI, _i16m4,
 190               _i16, _e16m4)
 191 DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, uint16, VNx16HI, VNx8HI,
 192               _u16m4, _u16, _e16m4)
 193 /* LMUL = 8:
 194    Machine mode = VNx32HImode when TARGET_MIN_VLEN > 32.
 195    Machine mode = VNx16HImode when TARGET_MIN_VLEN = 32.  */
 196 DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, int16, VNx32HI, VNx16HI, _i16m8,
 197               _i16, _e16m8)
 198 DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, uint16, VNx32HI, VNx16HI,
 199               _u16m8, _u16, _e16m8)
 200
 201 /* LMUL = 1/2:
 202    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SImode.  */
 203 DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, VNx1SI, VOID, _i32mf2,
 204               _i32, _e32mf2)
 205 DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, uint32, VNx1SI, VOID,
 206               _u32mf2, _u32, _e32mf2)
 207 /* LMUL = 1:
 208    Machine mode = VNx2SImode when TARGET_MIN_VLEN > 32.
 209    Machine mode = VNx1SImode when TARGET_MIN_VLEN = 32.  */
 210 DEF_RVV_TYPE (vint32m1_t, 15, __rvv_int32m1_t, int32, VNx2SI, VNx1SI, _i32m1,
 211               _i32, _e32m1)
 212 DEF_RVV_TYPE (vuint32m1_t, 16, __rvv_uint32m1_t, uint32, VNx2SI, VNx1SI, _u32m1,
 213               _u32, _e32m1)
 214 /* LMUL = 2:
 215    Machine mode = VNx4SImode when TARGET_MIN_VLEN > 32.
 216    Machine mode = VNx2SImode when TARGET_MIN_VLEN = 32.  */
 217 DEF_RVV_TYPE (vint32m2_t, 15, __rvv_int32m2_t, int32, VNx4SI, VNx2SI, _i32m2,
 218               _i32, _e32m2)
 219 DEF_RVV_TYPE (vuint32m2_t, 16, __rvv_uint32m2_t, uint32, VNx4SI, VNx2SI, _u32m2,
 220               _u32, _e32m2)
 221 /* LMUL = 4:
 222    Machine mode = VNx8SImode when TARGET_MIN_VLEN > 32.
 223    Machine mode = VNx4SImode when TARGET_MIN_VLEN = 32.  */
 224 DEF_RVV_TYPE (vint32m4_t, 15, __rvv_int32m4_t, int32, VNx8SI, VNx4SI, _i32m4,
 225               _i32, _e32m4)
 226 DEF_RVV_TYPE (vuint32m4_t, 16, __rvv_uint32m4_t, uint32, VNx8SI, VNx4SI, _u32m4,
 227               _u32, _e32m4)
 228 /* LMUL = 8:
 229    Machine mode = VNx16SImode when TARGET_MIN_VLEN > 32.
 230    Machine mode = VNx8SImode when TARGET_MIN_VLEN = 32.  */
 231 DEF_RVV_TYPE (vint32m8_t, 15, __rvv_int32m8_t, int32, VNx16SI, VNx8SI, _i32m8,
 232               _i32, _e32m8)
 233 DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI, VNx8SI,
 234               _u32m8, _u32, _e32m8)
 235
 236 /* SEW = 64:
 237    Enable when TARGET_MIN_VLEN > 32.  */
 238 DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1,
 239               _i64, _e64m1)
 240 DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID, _u64m1,
 241               _u64, _e64m1)
 242 DEF_RVV_TYPE (vint64m2_t, 15, __rvv_int64m2_t, int64, VNx2DI, VOID, _i64m2,
 243               _i64, _e64m2)
 244 DEF_RVV_TYPE (vuint64m2_t, 16, __rvv_uint64m2_t, uint64, VNx2DI, VOID, _u64m2,
 245               _u64, _e64m2)
 246 DEF_RVV_TYPE (vint64m4_t, 15, __rvv_int64m4_t, int64, VNx4DI, VOID, _i64m4,
 247               _i64, _e64m4)
 248 DEF_RVV_TYPE (vuint64m4_t, 16, __rvv_uint64m4_t, uint64, VNx4DI, VOID, _u64m4,
 249               _u64, _e64m4)
 250 DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, VNx8DI, VOID, _i64m8,
 251               _i64, _e64m8)
 252 DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx8DI, VOID, _u64m8,
 253               _u64, _e64m8)
 254
 255 /* LMUL = 1/2:
 256    Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SFmode.  */
 257 DEF_RVV_TYPE (vfloat32mf2_t, 18, __rvv_float32mf2_t, float, VNx1SF, VOID,
 258               _f32mf2, _f32, _e32mf2)
 259 /* LMUL = 1:
 260    Machine mode = VNx2SFmode when TARGET_MIN_VLEN > 32.
 261    Machine mode = VNx1SFmode when TARGET_MIN_VLEN = 32.  */
 262 DEF_RVV_TYPE (vfloat32m1_t, 17, __rvv_float32m1_t, float, VNx2SF, VNx1SF,
 263               _f32m1, _f32, _e32m1)
 264 /* LMUL = 2:
 265    Machine mode = VNx4SFmode when TARGET_MIN_VLEN > 32.
 266    Machine mode = VNx2SFmode when TARGET_MIN_VLEN = 32.  */
 267 DEF_RVV_TYPE (vfloat32m2_t, 17, __rvv_float32m2_t, float, VNx4SF, VNx2SF,
 268               _f32m2, _f32, _e32m2)
 269 /* LMUL = 4:
 270    Machine mode = VNx8SFmode when TARGET_MIN_VLEN > 32.
 271    Machine mode = VNx4SFmode when TARGET_MIN_VLEN = 32.  */
 272 DEF_RVV_TYPE (vfloat32m4_t, 17, __rvv_float32m4_t, float, VNx8SF, VNx4SF,
 273               _f32m4, _f32, _e32m4)
 274 /* LMUL = 8:
 275    Machine mode = VNx16SFmode when TARGET_MIN_VLEN > 32.
 276    Machine mode = VNx8SFmode when TARGET_MIN_VLEN = 32.  */
 277 DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF,
 278               _f32m8, _f32, _e32m8)
 279
 280 /* SEW = 64:
 281    Enable when TARGET_VECTOR_FP64.  */
 282 DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1,
 283               _f64, _e64m1)
 284 DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2,
 285               _f64, _e64m2)
 286 DEF_RVV_TYPE (vfloat64m4_t, 17, __rvv_float64m4_t, double, VNx4DF, VOID, _f64m4,
 287               _f64, _e64m4)
 288 DEF_RVV_TYPE (vfloat64m8_t, 17, __rvv_float64m8_t, double, VNx8DF, VOID, _f64m8,
 289               _f64, _e64m8)
 290
 291 DEF_RVV_OP_TYPE (vv)
 292 DEF_RVV_OP_TYPE (vx)
 293 DEF_RVV_OP_TYPE (v)
 294 DEF_RVV_OP_TYPE (wv)
 295 DEF_RVV_OP_TYPE (wx)
 296 DEF_RVV_OP_TYPE (x_v)
 297 DEF_RVV_OP_TYPE (vf2)
 298 DEF_RVV_OP_TYPE (vf4)
 299 DEF_RVV_OP_TYPE (vf8)
 300 DEF_RVV_OP_TYPE (vvm)
 301 DEF_RVV_OP_TYPE (vxm)
 302 DEF_RVV_OP_TYPE (x_w)
 303 DEF_RVV_OP_TYPE (x)
 304 DEF_RVV_OP_TYPE (vs)
 305 DEF_RVV_OP_TYPE (mm)
 306 DEF_RVV_OP_TYPE (m)
 307 DEF_RVV_OP_TYPE (vf)
 308 DEF_RVV_OP_TYPE (vm)
 309 DEF_RVV_OP_TYPE (wf)
 310 DEF_RVV_OP_TYPE (vfm)
 311 DEF_RVV_OP_TYPE (f)
 312 DEF_RVV_OP_TYPE (f_v)
 313 DEF_RVV_OP_TYPE (xu_v)
 314 DEF_RVV_OP_TYPE (f_w)
 315 DEF_RVV_OP_TYPE (xu_w)
 316 DEF_RVV_OP_TYPE (s)
 317
 318 DEF_RVV_PRED_TYPE (ta)
 319 DEF_RVV_PRED_TYPE (tu)
 320 DEF_RVV_PRED_TYPE (ma)
 321 DEF_RVV_PRED_TYPE (mu)
 322 DEF_RVV_PRED_TYPE (tama)
 323 DEF_RVV_PRED_TYPE (tamu)
 324 DEF_RVV_PRED_TYPE (tuma)
 325 DEF_RVV_PRED_TYPE (tumu)
 326 DEF_RVV_PRED_TYPE (m)
 327 DEF_RVV_PRED_TYPE (tam)
 328 DEF_RVV_PRED_TYPE (tum)
 329
 330 DEF_RVV_BASE_TYPE (vector, builtin_types[type_idx].vector)
 331 DEF_RVV_BASE_TYPE (scalar, builtin_types[type_idx].scalar)
 332 DEF_RVV_BASE_TYPE (mask, get_vector_type (type_idx))
 333 DEF_RVV_BASE_TYPE (signed_vector, get_vector_type (type_idx))
 334 DEF_RVV_BASE_TYPE (unsigned_vector, get_vector_type (type_idx))
 335 /* According to riscv-vector-builtins-types.def, the unsigned
 336    type is always the signed type + 1 (They have same SEW and LMUL).
 337    For example 'vuint8mf8_t' enum = 'vint8mf8_t' enum + 1.
 338    Note: We dont't allow type_idx to be unsigned type.  */
 339 DEF_RVV_BASE_TYPE (unsigned_scalar, builtin_types[type_idx + 1].scalar)
 340 DEF_RVV_BASE_TYPE (vector_ptr, builtin_types[type_idx].vector_ptr)
 341 /* According to the latest rvv-intrinsic-doc, it defines vsm.v intrinsic:
 342    __riscv_vsm (uint8_t *base, vbool1_t value, size_t vl).  */
 343 DEF_RVV_BASE_TYPE (scalar_ptr, get_scalar_ptr_type (type_idx))
 344 /* According to the latest rvv-intrinsic-doc, it defines vlm.v intrinsic:
 345    __riscv_vlm_v_b1 (const uint8_t *base, size_t vl).  */
 346 DEF_RVV_BASE_TYPE (scalar_const_ptr, get_scalar_const_ptr_type (type_idx))
 347 DEF_RVV_BASE_TYPE (void, void_type_node)
 348 DEF_RVV_BASE_TYPE (size, size_type_node)
 349 DEF_RVV_BASE_TYPE (ptrdiff, ptrdiff_type_node)
 350 DEF_RVV_BASE_TYPE (unsigned_long, long_unsigned_type_node)
 351 DEF_RVV_BASE_TYPE (long, long_integer_type_node)
 352 DEF_RVV_BASE_TYPE (eew8_index, get_vector_type (type_idx))
 353 DEF_RVV_BASE_TYPE (eew16_index, get_vector_type (type_idx))
 354 DEF_RVV_BASE_TYPE (eew32_index, get_vector_type (type_idx))
 355 DEF_RVV_BASE_TYPE (eew64_index, get_vector_type (type_idx))
 356 DEF_RVV_BASE_TYPE (shift_vector, get_vector_type (type_idx))
 357 DEF_RVV_BASE_TYPE (double_trunc_vector, get_vector_type (type_idx))
 358 DEF_RVV_BASE_TYPE (quad_trunc_vector, get_vector_type (type_idx))
 359 DEF_RVV_BASE_TYPE (oct_trunc_vector, get_vector_type (type_idx))
 360 DEF_RVV_BASE_TYPE (double_trunc_scalar, get_scalar_type (type_idx))
 361 DEF_RVV_BASE_TYPE (double_trunc_signed_vector, get_vector_type (type_idx))
 362 DEF_RVV_BASE_TYPE (double_trunc_unsigned_vector, get_vector_type (type_idx))
 363 DEF_RVV_BASE_TYPE (double_trunc_unsigned_scalar, get_scalar_type (type_idx))
 364 DEF_RVV_BASE_TYPE (double_trunc_float_vector, get_vector_type (type_idx))
 365 DEF_RVV_BASE_TYPE (float_vector, get_vector_type (type_idx))
 366 DEF_RVV_BASE_TYPE (lmul1_vector, get_vector_type (type_idx))
 367 DEF_RVV_BASE_TYPE (widen_lmul1_vector, get_vector_type (type_idx))
 368 DEF_RVV_BASE_TYPE (eew8_interpret, get_vector_type (type_idx))
 369 DEF_RVV_BASE_TYPE (eew16_interpret, get_vector_type (type_idx))
 370 DEF_RVV_BASE_TYPE (eew32_interpret, get_vector_type (type_idx))
 371 DEF_RVV_BASE_TYPE (eew64_interpret, get_vector_type (type_idx))
 372 DEF_RVV_BASE_TYPE (vlmul_ext_x2, get_vector_type (type_idx))
 373 DEF_RVV_BASE_TYPE (vlmul_ext_x4, get_vector_type (type_idx))
 374 DEF_RVV_BASE_TYPE (vlmul_ext_x8, get_vector_type (type_idx))
 375 DEF_RVV_BASE_TYPE (vlmul_ext_x16, get_vector_type (type_idx))
 376 DEF_RVV_BASE_TYPE (vlmul_ext_x32, get_vector_type (type_idx))
 377 DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type (type_idx))
 378 DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node))
 379
 380 #include "riscv-vector-type-indexer.gen.def"
 381
 382 #undef DEF_RVV_PRED_TYPE
 383 #undef DEF_RVV_OP_TYPE
 384 #undef DEF_RVV_TYPE
 385 #undef DEF_RVV_BASE_TYPE
 386 #undef DEF_RVV_TYPE_INDEX