1 /* Machine mode switch for RISC-V 'V' Extension for GNU compiler.
2 Copyright (C) 2022-2022 Free Software Foundation, Inc.
3 Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* This file is enable or disable the RVV modes according '-march'. */
23 /* According to rvv-intrinsic and RISC-V 'V' Extension ISA document:
24 https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md.
25 https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc.
28 Encode SEW and LMUL into data types.
29 We enforce the constraint LMUL ≥ SEW/ELEN in the implementation.
30 There are the following data types for MIN_VLEN > 32.
32 Note: N/A means the corresponding vector type is disabled.
34 |Types |LMUL=1|LMUL=2 |LMUL=4 |LMUL=8 |LMUL=1/2|LMUL=1/4|LMUL=1/8|
35 |int64_t |VNx1DI|VNx2DI |VNx4DI |VNx8DI |N/A |N/A |N/A |
36 |uint64_t|VNx1DI|VNx2DI |VNx4DI |VNx8DI |N/A |N/A |N/A |
37 |int32_t |VNx2SI|VNx4SI |VNx8SI |VNx16SI|VNx1SI |N/A |N/A |
38 |uint32_t|VNx2SI|VNx4SI |VNx8SI |VNx16SI|VNx1SI |N/A |N/A |
39 |int16_t |VNx4HI|VNx8HI |VNx16HI|VNx32HI|VNx2HI |VNx1HI |N/A |
40 |uint16_t|VNx4HI|VNx8HI |VNx16HI|VNx32HI|VNx2HI |VNx1HI |N/A |
41 |int8_t |VNx8QI|VNx16QI|VNx32QI|VNx64QI|VNx4QI |VNx2QI |VNx1QI |
42 |uint8_t |VNx8QI|VNx16QI|VNx32QI|VNx64QI|VNx4QI |VNx2QI |VNx1QI |
43 |float64 |VNx1DF|VNx2DF |VNx4DF |VNx8DF |N/A |N/A |N/A |
44 |float32 |VNx2SF|VNx4SF |VNx8SF |VNx16SF|VNx1SF |N/A |N/A |
45 |float16 |VNx4HF|VNx8HF |VNx16HF|VNx32HF|VNx2HF |VNx1HF |N/A |
47 Mask Types Encode the ratio of SEW/LMUL into the
48 mask types. There are the following mask types.
52 |Types|n=1 |n=2 |n=4 |n=8 |n=16 |n=32 |n=64 |
53 |bool |VNx64BI|VNx32BI|VNx16BI|VNx8BI|VNx4BI|VNx2BI|VNx1BI|
55 There are the following data types for MIN_VLEN = 32.
57 |Types |LMUL=1|LMUL=2|LMUL=4 |LMUL=8 |LMUL=1/2|LMUL=1/4|LMUL=1/8|
58 |int64_t |N/A |N/A |N/A |N/A |N/A |N/A |N/A |
59 |uint64_t|N/A |N/A |N/A |N/A |N/A |N/A |N/A |
60 |int32_t |VNx1SI|VNx2SI|VNx4SI |VNx8SI |N/A |N/A |N/A |
61 |uint32_t|VNx1SI|VNx2SI|VNx4SI |VNx8SI |N/A |N/A |N/A |
62 |int16_t |VNx2HI|VNx4HI|VNx8HI |VNx16HI|VNx1HI |N/A |N/A |
63 |uint16_t|VNx2HI|VNx4HI|VNx8HI |VNx16HI|VNx1HI |N/A |N/A |
64 |int8_t |VNx4QI|VNx8QI|VNx16QI|VNx32QI|VNx2QI |VNx1QI |N/A |
65 |uint8_t |VNx4QI|VNx8QI|VNx16QI|VNx32QI|VNx2QI |VNx1QI |N/A |
66 |float64 |N/A |N/A |N/A |N/A |N/A |N/A |N/A |
67 |float32 |VNx1SF|VNx2SF|VNx4SF |VNx8SF |N/A |N/A |N/A |
68 |float16 |VNx2HF|VNx4HF|VNx8HF |VNx16HF|VNx1HF |N/A |N/A |
70 Mask Types Encode the ratio of SEW/LMUL into the
71 mask types. There are the following mask types.
75 |Types|n=1 |n=2 |n=4 |n=8 |n=16 |n=32 |n=64|
76 |bool |VNx32BI|VNx16BI|VNx8BI|VNx4BI|VNx2BI|VNx1BI|N/A |
78 TODO: FP16 vector needs support of 'zvfh', we don't support it yet. */
80 /* Return 'REQUIREMENT' for machine_mode 'MODE'.
81 For example: 'MODE' = VNx64BImode needs TARGET_MIN_VLEN > 32. */
83 #define ENTRY(MODE, REQUIREMENT)
85 /* Flag of FP32 vector. */
86 #ifndef TARGET_VECTOR_FP32
87 #define TARGET_VECTOR_FP32 \
88 (TARGET_HARD_FLOAT && (TARGET_VECTOR_ELEN_FP_32 || TARGET_VECTOR_ELEN_FP_64))
90 /* Flag of FP64 vector. */
91 #ifndef TARGET_VECTOR_FP64
92 #define TARGET_VECTOR_FP64 \
93 (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64 && (TARGET_MIN_VLEN > 32))
96 /* Mask modes. Disable VNx64BImode when TARGET_MIN_VLEN == 32. */
97 ENTRY (VNx64BI, TARGET_MIN_VLEN > 32)
105 /* SEW = 8. Disable VNx64QImode when TARGET_MIN_VLEN == 32. */
106 ENTRY (VNx64QI, TARGET_MIN_VLEN > 32)
107 ENTRY (VNx32QI, true)
108 ENTRY (VNx16QI, true)
114 /* SEW = 16. Disable VNx32HImode when TARGET_MIN_VLEN == 32. */
115 ENTRY (VNx32HI, TARGET_MIN_VLEN > 32)
116 ENTRY (VNx16HI, true)
122 /* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */
123 ENTRY (VNx32HF, false)
124 ENTRY (VNx16HF, false)
125 ENTRY (VNx8HF, false)
126 ENTRY (VNx4HF, false)
127 ENTRY (VNx2HF, false)
128 ENTRY (VNx1HF, false)
130 /* SEW = 32. Disable VNx16SImode when TARGET_MIN_VLEN == 32.
131 For single-precision floating-point, we need TARGET_VECTOR_FP32 ==
133 ENTRY (VNx16SI, TARGET_MIN_VLEN > 32)
139 ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32))
140 ENTRY (VNx8SF, TARGET_VECTOR_FP32)
141 ENTRY (VNx4SF, TARGET_VECTOR_FP32)
142 ENTRY (VNx2SF, TARGET_VECTOR_FP32)
143 ENTRY (VNx1SF, TARGET_VECTOR_FP32)
145 /* SEW = 64. Enable when TARGET_MIN_VLEN > 32.
146 For double-precision floating-point, we need TARGET_VECTOR_FP64 ==
148 ENTRY (VNx8DI, TARGET_MIN_VLEN > 32)
149 ENTRY (VNx4DI, TARGET_MIN_VLEN > 32)
150 ENTRY (VNx2DI, TARGET_MIN_VLEN > 32)
151 ENTRY (VNx1DI, TARGET_MIN_VLEN > 32)
153 ENTRY (VNx8DF, TARGET_VECTOR_FP64 && (TARGET_MIN_VLEN > 32))
154 ENTRY (VNx4DF, TARGET_VECTOR_FP64)
155 ENTRY (VNx2DF, TARGET_VECTOR_FP64)
156 ENTRY (VNx1DF, TARGET_VECTOR_FP64)
158 #undef TARGET_VECTOR_FP32
159 #undef TARGET_VECTOR_FP64