1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
27 #include "coretypes.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
37 #include "stringpool.h"
40 #include "stor-layout.h"
49 #include "target-def.h"
50 #include "basic-block.h"
55 #include "diagnostic.h"
59 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
60 #define UNSPEC_ADDRESS_P(X) \
61 (GET_CODE (X) == UNSPEC \
62 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
63 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
65 /* Extract the symbol or label from UNSPEC wrapper X. */
66 #define UNSPEC_ADDRESS(X) \
69 /* Extract the symbol type from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS_TYPE(X) \
71 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
73 /* True if bit BIT is set in VALUE. */
74 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
76 /* Classifies an address.
79 A natural register + offset address. The register satisfies
80 riscv_valid_base_register_p and the offset is a const_arith_operand.
83 A LO_SUM rtx. The first operand is a valid base register and
84 the second operand is a symbolic address.
87 A signed 16-bit constant address.
90 A constant symbolic address. */
91 enum riscv_address_type
{
98 /* Information about a function's frame layout. */
99 struct GTY(()) riscv_frame_info
{
100 /* The size of the frame in bytes. */
101 HOST_WIDE_INT total_size
;
103 /* Bit X is set if the function saves or restores GPR X. */
106 /* Likewise FPR X. */
109 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
110 unsigned save_libcall_adjustment
;
112 /* Offsets of fixed-point and floating-point save areas from frame bottom */
113 HOST_WIDE_INT gp_sp_offset
;
114 HOST_WIDE_INT fp_sp_offset
;
116 /* Offset of virtual frame pointer from stack pointer/frame bottom */
117 HOST_WIDE_INT frame_pointer_offset
;
119 /* Offset of hard frame pointer from stack pointer/frame bottom */
120 HOST_WIDE_INT hard_frame_pointer_offset
;
122 /* The offset of arg_pointer_rtx from the bottom of the frame. */
123 HOST_WIDE_INT arg_pointer_offset
;
126 enum riscv_privilege_levels
{
127 UNKNOWN_MODE
, USER_MODE
, SUPERVISOR_MODE
, MACHINE_MODE
130 struct GTY(()) machine_function
{
131 /* The number of extra stack bytes taken up by register varargs.
132 This area is allocated by the callee at the very top of the frame. */
135 /* True if current function is a naked function. */
138 /* True if current function is an interrupt function. */
139 bool interrupt_handler_p
;
140 /* For an interrupt handler, indicates the privilege level. */
141 enum riscv_privilege_levels interrupt_mode
;
143 /* True if attributes on current function have been checked. */
144 bool attributes_checked_p
;
146 /* The current frame information, calculated by riscv_compute_frame_info. */
147 struct riscv_frame_info frame
;
150 /* Information about a single argument. */
151 struct riscv_arg_info
{
152 /* True if the argument is at least partially passed on the stack. */
155 /* The number of integer registers allocated to this argument. */
156 unsigned int num_gprs
;
158 /* The offset of the first register used, provided num_gprs is nonzero.
159 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
160 unsigned int gpr_offset
;
162 /* The number of floating-point registers allocated to this argument. */
163 unsigned int num_fprs
;
165 /* The offset of the first register used, provided num_fprs is nonzero. */
166 unsigned int fpr_offset
;
169 /* Information about an address described by riscv_address_type.
175 REG is the base register and OFFSET is the constant offset.
178 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
179 is the type of symbol it references.
182 SYMBOL_TYPE is the type of symbol that the address references. */
183 struct riscv_address_info
{
184 enum riscv_address_type type
;
187 enum riscv_symbol_type symbol_type
;
190 /* One stage in a constant building sequence. These sequences have
194 A = A CODE[1] VALUE[1]
195 A = A CODE[2] VALUE[2]
198 where A is an accumulator, each CODE[i] is a binary rtl operation
199 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
200 struct riscv_integer_op
{
202 unsigned HOST_WIDE_INT value
;
205 /* The largest number of operations needed to load an integer constant.
206 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
207 #define RISCV_MAX_INTEGER_OPS 8
209 /* Costs of various operations on the different architectures. */
211 struct riscv_tune_info
213 unsigned short fp_add
[2];
214 unsigned short fp_mul
[2];
215 unsigned short fp_div
[2];
216 unsigned short int_mul
[2];
217 unsigned short int_div
[2];
218 unsigned short issue_rate
;
219 unsigned short branch_cost
;
220 unsigned short memory_cost
;
221 bool slow_unaligned_access
;
224 /* Information about one CPU we know about. */
225 struct riscv_cpu_info
{
226 /* This CPU's canonical name. */
229 /* Which automaton to use for tuning. */
230 enum riscv_microarchitecture_type microarchitecture
;
232 /* Tuning parameters for this CPU. */
233 const struct riscv_tune_info
*tune_info
;
236 /* Global variables for machine-dependent things. */
238 /* Whether unaligned accesses execute very slowly. */
239 bool riscv_slow_unaligned_access_p
;
241 /* Stack alignment to assume/maintain. */
242 unsigned riscv_stack_boundary
;
244 /* If non-zero, this is an offset to be added to SP to redefine the CFA
245 when restoring the FP register from the stack. Only valid when generating
247 static int epilogue_cfa_sp_offset
;
249 /* Which tuning parameters to use. */
250 static const struct riscv_tune_info
*tune_info
;
252 /* Which automaton to use for tuning. */
253 enum riscv_microarchitecture_type riscv_microarchitecture
;
255 /* Index R is the smallest register class that contains register R. */
256 const enum reg_class riscv_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
257 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
258 GR_REGS
, GR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
259 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
260 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
261 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
262 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
263 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
264 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
265 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
266 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
267 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
268 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
269 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
270 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
271 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
272 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
273 FRAME_REGS
, FRAME_REGS
,
276 /* Costs to use when optimizing for rocket. */
277 static const struct riscv_tune_info rocket_tune_info
= {
278 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
279 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
280 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
281 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
282 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
286 true, /* slow_unaligned_access */
289 /* Costs to use when optimizing for Sifive 7 Series. */
290 static const struct riscv_tune_info sifive_7_tune_info
= {
291 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
292 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
293 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
294 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
295 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
299 true, /* slow_unaligned_access */
302 /* Costs to use when optimizing for size. */
303 static const struct riscv_tune_info optimize_size_tune_info
= {
304 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
305 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
306 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
307 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
308 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
312 false, /* slow_unaligned_access */
315 static tree
riscv_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
316 static tree
riscv_handle_type_attribute (tree
*, tree
, tree
, int, bool *);
318 /* Defining target-specific uses of __attribute__. */
319 static const struct attribute_spec riscv_attribute_table
[] =
321 /* Syntax: { name, min_len, max_len, decl_required, type_required,
322 function_type_required, affects_type_identity, handler,
325 /* The attribute telling no prologue/epilogue. */
326 { "naked", 0, 0, true, false, false, false,
327 riscv_handle_fndecl_attribute
, NULL
},
328 /* This attribute generates prologue/epilogue for interrupt handlers. */
329 { "interrupt", 0, 1, false, true, true, false,
330 riscv_handle_type_attribute
, NULL
},
332 /* The last attribute spec is set to be NULL. */
333 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
336 /* A table describing all the processors GCC knows about. */
337 static const struct riscv_cpu_info riscv_cpu_info_table
[] = {
338 { "rocket", generic
, &rocket_tune_info
},
339 { "sifive-3-series", generic
, &rocket_tune_info
},
340 { "sifive-5-series", generic
, &rocket_tune_info
},
341 { "sifive-7-series", sifive_7
, &sifive_7_tune_info
},
342 { "size", generic
, &optimize_size_tune_info
},
345 /* Return the riscv_cpu_info entry for the given name string. */
347 static const struct riscv_cpu_info
*
348 riscv_parse_cpu (const char *cpu_string
)
350 for (unsigned i
= 0; i
< ARRAY_SIZE (riscv_cpu_info_table
); i
++)
351 if (strcmp (riscv_cpu_info_table
[i
].name
, cpu_string
) == 0)
352 return riscv_cpu_info_table
+ i
;
354 error ("unknown cpu %qs for %<-mtune%>", cpu_string
);
355 return riscv_cpu_info_table
;
358 /* Helper function for riscv_build_integer; arguments are as for
359 riscv_build_integer. */
362 riscv_build_integer_1 (struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
],
363 HOST_WIDE_INT value
, machine_mode mode
)
365 HOST_WIDE_INT low_part
= CONST_LOW_PART (value
);
366 int cost
= RISCV_MAX_INTEGER_OPS
+ 1, alt_cost
;
367 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
369 if (SMALL_OPERAND (value
) || LUI_OPERAND (value
))
371 /* Simply ADDI or LUI. */
372 codes
[0].code
= UNKNOWN
;
373 codes
[0].value
= value
;
377 /* End with ADDI. When constructing HImode constants, do not generate any
378 intermediate value that is not itself a valid HImode constant. The
379 XORI case below will handle those remaining HImode constants. */
382 || value
- low_part
<= ((1 << (GET_MODE_BITSIZE (HImode
) - 1)) - 1)))
384 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
- low_part
, mode
);
387 alt_codes
[alt_cost
-1].code
= PLUS
;
388 alt_codes
[alt_cost
-1].value
= low_part
;
389 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
395 if (cost
> 2 && (low_part
< 0 || mode
== HImode
))
397 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
^ low_part
, mode
);
400 alt_codes
[alt_cost
-1].code
= XOR
;
401 alt_codes
[alt_cost
-1].value
= low_part
;
402 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
407 /* Eliminate trailing zeros and end with SLLI. */
408 if (cost
> 2 && (value
& 1) == 0)
410 int shift
= ctz_hwi (value
);
411 unsigned HOST_WIDE_INT x
= value
;
412 x
= sext_hwi (x
>> shift
, HOST_BITS_PER_WIDE_INT
- shift
);
414 /* Don't eliminate the lower 12 bits if LUI might apply. */
415 if (shift
> IMM_BITS
&& !SMALL_OPERAND (x
) && LUI_OPERAND (x
<< IMM_BITS
))
416 shift
-= IMM_BITS
, x
<<= IMM_BITS
;
418 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, x
, mode
);
421 alt_codes
[alt_cost
-1].code
= ASHIFT
;
422 alt_codes
[alt_cost
-1].value
= shift
;
423 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
428 gcc_assert (cost
<= RISCV_MAX_INTEGER_OPS
);
432 /* Fill CODES with a sequence of rtl operations to load VALUE.
433 Return the number of operations needed. */
436 riscv_build_integer (struct riscv_integer_op
*codes
, HOST_WIDE_INT value
,
439 int cost
= riscv_build_integer_1 (codes
, value
, mode
);
441 /* Eliminate leading zeros and end with SRLI. */
442 if (value
> 0 && cost
> 2)
444 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
445 int alt_cost
, shift
= clz_hwi (value
);
446 HOST_WIDE_INT shifted_val
;
448 /* Try filling trailing bits with 1s. */
449 shifted_val
= (value
<< shift
) | ((((HOST_WIDE_INT
) 1) << shift
) - 1);
450 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
453 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
454 alt_codes
[alt_cost
-1].value
= shift
;
455 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
459 /* Try filling trailing bits with 0s. */
460 shifted_val
= value
<< shift
;
461 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
464 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
465 alt_codes
[alt_cost
-1].value
= shift
;
466 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
474 /* Return the cost of constructing VAL in the event that a scratch
475 register is available. */
478 riscv_split_integer_cost (HOST_WIDE_INT val
)
481 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
482 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
483 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
485 cost
= 2 + riscv_build_integer (codes
, loval
, VOIDmode
);
487 cost
+= riscv_build_integer (codes
, hival
, VOIDmode
);
492 /* Return the cost of constructing the integer constant VAL. */
495 riscv_integer_cost (HOST_WIDE_INT val
)
497 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
498 return MIN (riscv_build_integer (codes
, val
, VOIDmode
),
499 riscv_split_integer_cost (val
));
502 /* Try to split a 64b integer into 32b parts, then reassemble. */
505 riscv_split_integer (HOST_WIDE_INT val
, machine_mode mode
)
507 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
508 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
509 rtx hi
= gen_reg_rtx (mode
), lo
= gen_reg_rtx (mode
);
511 riscv_move_integer (hi
, hi
, hival
);
512 riscv_move_integer (lo
, lo
, loval
);
514 hi
= gen_rtx_fmt_ee (ASHIFT
, mode
, hi
, GEN_INT (32));
515 hi
= force_reg (mode
, hi
);
517 return gen_rtx_fmt_ee (PLUS
, mode
, hi
, lo
);
520 /* Return true if X is a thread-local symbol. */
523 riscv_tls_symbol_p (const_rtx x
)
525 return SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0;
528 /* Return true if symbol X binds locally. */
531 riscv_symbol_binds_local_p (const_rtx x
)
533 if (SYMBOL_REF_P (x
))
534 return (SYMBOL_REF_DECL (x
)
535 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
536 : SYMBOL_REF_LOCAL_P (x
));
541 /* Return the method that should be used to access SYMBOL_REF or
544 static enum riscv_symbol_type
545 riscv_classify_symbol (const_rtx x
)
547 if (riscv_tls_symbol_p (x
))
550 if (GET_CODE (x
) == SYMBOL_REF
&& flag_pic
&& !riscv_symbol_binds_local_p (x
))
551 return SYMBOL_GOT_DISP
;
553 return riscv_cmodel
== CM_MEDLOW
? SYMBOL_ABSOLUTE
: SYMBOL_PCREL
;
556 /* Classify the base of symbolic expression X. */
558 enum riscv_symbol_type
559 riscv_classify_symbolic_expression (rtx x
)
563 split_const (x
, &x
, &offset
);
564 if (UNSPEC_ADDRESS_P (x
))
565 return UNSPEC_ADDRESS_TYPE (x
);
567 return riscv_classify_symbol (x
);
570 /* Return true if X is a symbolic constant. If it is, store the type of
571 the symbol in *SYMBOL_TYPE. */
574 riscv_symbolic_constant_p (rtx x
, enum riscv_symbol_type
*symbol_type
)
578 split_const (x
, &x
, &offset
);
579 if (UNSPEC_ADDRESS_P (x
))
581 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
582 x
= UNSPEC_ADDRESS (x
);
584 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
585 *symbol_type
= riscv_classify_symbol (x
);
589 if (offset
== const0_rtx
)
592 /* Nonzero offsets are only valid for references that don't use the GOT. */
593 switch (*symbol_type
)
595 case SYMBOL_ABSOLUTE
:
598 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
599 return sext_hwi (INTVAL (offset
), 32) == INTVAL (offset
);
606 /* Returns the number of instructions necessary to reference a symbol. */
608 static int riscv_symbol_insns (enum riscv_symbol_type type
)
612 case SYMBOL_TLS
: return 0; /* Depends on the TLS model. */
613 case SYMBOL_ABSOLUTE
: return 2; /* LUI + the reference. */
614 case SYMBOL_PCREL
: return 2; /* AUIPC + the reference. */
615 case SYMBOL_TLS_LE
: return 3; /* LUI + ADD TP + the reference. */
616 case SYMBOL_GOT_DISP
: return 3; /* AUIPC + LD GOT + the reference. */
617 default: gcc_unreachable ();
621 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
624 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
626 return riscv_const_insns (x
) > 0;
629 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
632 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
634 enum riscv_symbol_type type
;
637 /* There is no assembler syntax for expressing an address-sized
639 if (GET_CODE (x
) == HIGH
)
642 split_const (x
, &base
, &offset
);
643 if (riscv_symbolic_constant_p (base
, &type
))
645 /* As an optimization, don't spill symbolic constants that are as
646 cheap to rematerialize as to access in the constant pool. */
647 if (SMALL_OPERAND (INTVAL (offset
)) && riscv_symbol_insns (type
) > 0)
650 /* As an optimization, avoid needlessly generate dynamic relocations. */
655 /* TLS symbols must be computed by riscv_legitimize_move. */
656 if (tls_referenced_p (x
))
662 /* Return true if register REGNO is a valid base register for mode MODE.
663 STRICT_P is true if REG_OK_STRICT is in effect. */
666 riscv_regno_mode_ok_for_base_p (int regno
,
667 machine_mode mode ATTRIBUTE_UNUSED
,
670 if (!HARD_REGISTER_NUM_P (regno
))
674 regno
= reg_renumber
[regno
];
677 /* These fake registers will be eliminated to either the stack or
678 hard frame pointer, both of which are usually valid base registers.
679 Reload deals with the cases where the eliminated form isn't valid. */
680 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
683 return GP_REG_P (regno
);
686 /* Return true if X is a valid base register for mode MODE.
687 STRICT_P is true if REG_OK_STRICT is in effect. */
690 riscv_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
692 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
696 && riscv_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
699 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
700 can address a value of mode MODE. */
703 riscv_valid_offset_p (rtx x
, machine_mode mode
)
705 /* Check that X is a signed 12-bit number. */
706 if (!const_arith_operand (x
, Pmode
))
709 /* We may need to split multiword moves, so make sure that every word
711 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
712 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
718 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
721 riscv_split_symbol_type (enum riscv_symbol_type symbol_type
)
723 if (symbol_type
== SYMBOL_TLS_LE
)
726 if (!TARGET_EXPLICIT_RELOCS
)
729 return symbol_type
== SYMBOL_ABSOLUTE
|| symbol_type
== SYMBOL_PCREL
;
732 /* Return true if a LO_SUM can address a value of mode MODE when the
733 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
734 is used when the mode is BLKmode. */
737 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type
, machine_mode mode
,
742 /* Check that symbols of type SYMBOL_TYPE can be used to access values
744 if (riscv_symbol_insns (sym_type
) == 0)
747 /* Check that there is a known low-part relocation. */
748 if (!riscv_split_symbol_type (sym_type
))
751 /* We can't tell size or alignment when we have BLKmode, so try extracing a
752 decl from the symbol if possible. */
757 /* Extract the symbol from the LO_SUM operand, if any. */
758 split_const (x
, &x
, &offset
);
760 /* Might be a CODE_LABEL. We can compute align but not size for that,
761 so don't bother trying to handle it. */
762 if (!SYMBOL_REF_P (x
))
765 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
766 align
= (SYMBOL_REF_DECL (x
)
767 ? DECL_ALIGN (SYMBOL_REF_DECL (x
))
769 size
= (SYMBOL_REF_DECL (x
) && DECL_SIZE (SYMBOL_REF_DECL (x
))
770 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x
)))
775 align
= GET_MODE_ALIGNMENT (mode
);
776 size
= GET_MODE_BITSIZE (mode
);
779 /* We may need to split multiword moves, so make sure that each word
780 can be accessed without inducing a carry. */
781 if (size
> BITS_PER_WORD
782 && (!TARGET_STRICT_ALIGN
|| size
> align
))
788 /* Return true if X is a valid address for machine mode MODE. If it is,
789 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
793 riscv_classify_address (struct riscv_address_info
*info
, rtx x
,
794 machine_mode mode
, bool strict_p
)
796 switch (GET_CODE (x
))
800 info
->type
= ADDRESS_REG
;
802 info
->offset
= const0_rtx
;
803 return riscv_valid_base_register_p (info
->reg
, mode
, strict_p
);
806 info
->type
= ADDRESS_REG
;
807 info
->reg
= XEXP (x
, 0);
808 info
->offset
= XEXP (x
, 1);
809 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
810 && riscv_valid_offset_p (info
->offset
, mode
));
813 info
->type
= ADDRESS_LO_SUM
;
814 info
->reg
= XEXP (x
, 0);
815 info
->offset
= XEXP (x
, 1);
816 /* We have to trust the creator of the LO_SUM to do something vaguely
817 sane. Target-independent code that creates a LO_SUM should also
818 create and verify the matching HIGH. Target-independent code that
819 adds an offset to a LO_SUM must prove that the offset will not
820 induce a carry. Failure to do either of these things would be
821 a bug, and we are not required to check for it here. The RISC-V
822 backend itself should only create LO_SUMs for valid symbolic
823 constants, with the high part being either a HIGH or a copy
826 = riscv_classify_symbolic_expression (info
->offset
);
827 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
828 && riscv_valid_lo_sum_p (info
->symbol_type
, mode
, info
->offset
));
831 /* Small-integer addresses don't occur very often, but they
832 are legitimate if x0 is a valid base register. */
833 info
->type
= ADDRESS_CONST_INT
;
834 return SMALL_OPERAND (INTVAL (x
));
841 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
844 riscv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
846 struct riscv_address_info addr
;
848 return riscv_classify_address (&addr
, x
, mode
, strict_p
);
851 /* Return the number of instructions needed to load or store a value
852 of mode MODE at address X. Return 0 if X isn't valid for MODE.
853 Assume that multiword moves may need to be split into word moves
854 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
858 riscv_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
860 struct riscv_address_info addr
;
863 if (!riscv_classify_address (&addr
, x
, mode
, false))
865 /* This could be a pattern from the pic.md file. In which case we want
866 this address to always have a cost of 3 to make it as expensive as the
867 most expensive symbol. This prevents constant propagation from
868 preferring symbols over register plus offset. */
872 /* BLKmode is used for single unaligned loads and stores and should
873 not count as a multiword mode. */
874 if (mode
!= BLKmode
&& might_split_p
)
875 n
+= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
877 if (addr
.type
== ADDRESS_LO_SUM
)
878 n
+= riscv_symbol_insns (addr
.symbol_type
) - 1;
883 /* Return the number of instructions needed to load constant X.
884 Return 0 if X isn't a valid constant. */
887 riscv_const_insns (rtx x
)
889 enum riscv_symbol_type symbol_type
;
892 switch (GET_CODE (x
))
895 if (!riscv_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
896 || !riscv_split_symbol_type (symbol_type
))
899 /* This is simply an LUI. */
904 int cost
= riscv_integer_cost (INTVAL (x
));
905 /* Force complicated constants to memory. */
906 return cost
< 4 ? cost
: 0;
911 /* We can use x0 to load floating-point zero. */
912 return x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
915 /* See if we can refer to X directly. */
916 if (riscv_symbolic_constant_p (x
, &symbol_type
))
917 return riscv_symbol_insns (symbol_type
);
919 /* Otherwise try splitting the constant into a base and offset. */
920 split_const (x
, &x
, &offset
);
923 int n
= riscv_const_insns (x
);
925 return n
+ riscv_integer_cost (INTVAL (offset
));
931 return riscv_symbol_insns (riscv_classify_symbol (x
));
938 /* X is a doubleword constant that can be handled by splitting it into
939 two words and loading each word separately. Return the number of
940 instructions required to do this. */
943 riscv_split_const_insns (rtx x
)
945 unsigned int low
, high
;
947 low
= riscv_const_insns (riscv_subword (x
, false));
948 high
= riscv_const_insns (riscv_subword (x
, true));
949 gcc_assert (low
> 0 && high
> 0);
953 /* Return the number of instructions needed to implement INSN,
954 given that it loads from or stores to MEM. */
957 riscv_load_store_insns (rtx mem
, rtx_insn
*insn
)
963 gcc_assert (MEM_P (mem
));
964 mode
= GET_MODE (mem
);
966 /* Try to prove that INSN does not need to be split. */
967 might_split_p
= true;
968 if (GET_MODE_BITSIZE (mode
) <= 32)
969 might_split_p
= false;
970 else if (GET_MODE_BITSIZE (mode
) == 64)
972 set
= single_set (insn
);
973 if (set
&& !riscv_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
974 might_split_p
= false;
977 return riscv_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
980 /* Emit a move from SRC to DEST. Assume that the move expanders can
981 handle all moves if !can_create_pseudo_p (). The distinction is
982 important because, unlike emit_move_insn, the move expanders know
983 how to force Pmode objects into the constant pool even when the
984 constant pool address is not itself legitimate. */
987 riscv_emit_move (rtx dest
, rtx src
)
989 return (can_create_pseudo_p ()
990 ? emit_move_insn (dest
, src
)
991 : emit_move_insn_1 (dest
, src
));
994 /* Emit an instruction of the form (set TARGET SRC). */
997 riscv_emit_set (rtx target
, rtx src
)
999 emit_insn (gen_rtx_SET (target
, src
));
1003 /* Emit an instruction of the form (set DEST (CODE X Y)). */
1006 riscv_emit_binary (enum rtx_code code
, rtx dest
, rtx x
, rtx y
)
1008 return riscv_emit_set (dest
, gen_rtx_fmt_ee (code
, GET_MODE (dest
), x
, y
));
1011 /* Compute (CODE X Y) and store the result in a new register
1012 of mode MODE. Return that new register. */
1015 riscv_force_binary (machine_mode mode
, enum rtx_code code
, rtx x
, rtx y
)
1017 return riscv_emit_binary (code
, gen_reg_rtx (mode
), x
, y
);
1020 /* Copy VALUE to a register and return that register. If new pseudos
1021 are allowed, copy it into a new register, otherwise use DEST. */
1024 riscv_force_temporary (rtx dest
, rtx value
)
1026 if (can_create_pseudo_p ())
1027 return force_reg (Pmode
, value
);
1030 riscv_emit_move (dest
, value
);
1035 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
1036 then add CONST_INT OFFSET to the result. */
1039 riscv_unspec_address_offset (rtx base
, rtx offset
,
1040 enum riscv_symbol_type symbol_type
)
1042 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1043 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1044 if (offset
!= const0_rtx
)
1045 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
1046 return gen_rtx_CONST (Pmode
, base
);
1049 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1050 type SYMBOL_TYPE. */
1053 riscv_unspec_address (rtx address
, enum riscv_symbol_type symbol_type
)
1057 split_const (address
, &base
, &offset
);
1058 return riscv_unspec_address_offset (base
, offset
, symbol_type
);
1061 /* If OP is an UNSPEC address, return the address to which it refers,
1062 otherwise return OP itself. */
1065 riscv_strip_unspec_address (rtx op
)
1069 split_const (op
, &base
, &offset
);
1070 if (UNSPEC_ADDRESS_P (base
))
1071 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
1075 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1076 high part to BASE and return the result. Just return BASE otherwise.
1077 TEMP is as for riscv_force_temporary.
1079 The returned expression can be used as the first operand to a LO_SUM. */
1082 riscv_unspec_offset_high (rtx temp
, rtx addr
, enum riscv_symbol_type symbol_type
)
1084 addr
= gen_rtx_HIGH (Pmode
, riscv_unspec_address (addr
, symbol_type
));
1085 return riscv_force_temporary (temp
, addr
);
1088 /* Load an entry from the GOT for a TLS GD access. */
1090 static rtx
riscv_got_load_tls_gd (rtx dest
, rtx sym
)
1092 if (Pmode
== DImode
)
1093 return gen_got_load_tls_gddi (dest
, sym
);
1095 return gen_got_load_tls_gdsi (dest
, sym
);
1098 /* Load an entry from the GOT for a TLS IE access. */
1100 static rtx
riscv_got_load_tls_ie (rtx dest
, rtx sym
)
1102 if (Pmode
== DImode
)
1103 return gen_got_load_tls_iedi (dest
, sym
);
1105 return gen_got_load_tls_iesi (dest
, sym
);
1108 /* Add in the thread pointer for a TLS LE access. */
1110 static rtx
riscv_tls_add_tp_le (rtx dest
, rtx base
, rtx sym
)
1112 rtx tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1113 if (Pmode
== DImode
)
1114 return gen_tls_add_tp_ledi (dest
, base
, tp
, sym
);
1116 return gen_tls_add_tp_lesi (dest
, base
, tp
, sym
);
1119 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1120 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1121 constant in that context and can be split into high and low parts.
1122 If so, and if LOW_OUT is nonnull, emit the high part and store the
1123 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1125 TEMP is as for riscv_force_temporary and is used to load the high
1126 part into a register.
1128 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1129 a legitimize SET_SRC for an .md pattern, otherwise the low part
1130 is guaranteed to be a legitimate address for mode MODE. */
1133 riscv_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
1135 enum riscv_symbol_type symbol_type
;
1137 if ((GET_CODE (addr
) == HIGH
&& mode
== MAX_MACHINE_MODE
)
1138 || !riscv_symbolic_constant_p (addr
, &symbol_type
)
1139 || riscv_symbol_insns (symbol_type
) == 0
1140 || !riscv_split_symbol_type (symbol_type
))
1144 switch (symbol_type
)
1146 case SYMBOL_ABSOLUTE
:
1148 rtx high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
1149 high
= riscv_force_temporary (temp
, high
);
1150 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
1156 static unsigned seqno
;
1160 ssize_t bytes
= snprintf (buf
, sizeof (buf
), ".LA%u", seqno
);
1161 gcc_assert ((size_t) bytes
< sizeof (buf
));
1163 label
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
1164 SYMBOL_REF_FLAGS (label
) |= SYMBOL_FLAG_LOCAL
;
1165 /* ??? Ugly hack to make weak symbols work. May need to change the
1166 RTL for the auipc and/or low patterns to get a better fix for
1168 if (! nonzero_address_p (addr
))
1169 SYMBOL_REF_WEAK (label
) = 1;
1172 temp
= gen_reg_rtx (Pmode
);
1174 if (Pmode
== DImode
)
1175 emit_insn (gen_auipcdi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1177 emit_insn (gen_auipcsi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1179 *low_out
= gen_rtx_LO_SUM (Pmode
, temp
, label
);
1192 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1193 riscv_force_temporary; it is only needed when OFFSET is not a
1197 riscv_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1199 if (!SMALL_OPERAND (offset
))
1203 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1204 The addition inside the macro CONST_HIGH_PART may cause an
1205 overflow, so we need to force a sign-extension check. */
1206 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
1207 offset
= CONST_LOW_PART (offset
);
1208 high
= riscv_force_temporary (temp
, high
);
1209 reg
= riscv_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
1211 return plus_constant (Pmode
, reg
, offset
);
1214 /* The __tls_get_attr symbol. */
1215 static GTY(()) rtx riscv_tls_symbol
;
1217 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1218 the TLS symbol we are referencing and TYPE is the symbol type to use
1219 (either global dynamic or local dynamic). RESULT is an RTX for the
1220 return value location. */
1223 riscv_call_tls_get_addr (rtx sym
, rtx result
)
1225 rtx a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
), func
;
1228 if (!riscv_tls_symbol
)
1229 riscv_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1230 func
= gen_rtx_MEM (FUNCTION_MODE
, riscv_tls_symbol
);
1234 emit_insn (riscv_got_load_tls_gd (a0
, sym
));
1235 insn
= emit_call_insn (gen_call_value (result
, func
, const0_rtx
, NULL
));
1236 RTL_CONST_CALL_P (insn
) = 1;
1237 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1238 insn
= get_insns ();
1245 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1246 its address. The return value will be both a valid address and a valid
1247 SET_SRC (either a REG or a LO_SUM). */
1250 riscv_legitimize_tls_address (rtx loc
)
1253 enum tls_model model
= SYMBOL_REF_TLS_MODEL (loc
);
1255 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1257 model
= TLS_MODEL_LOCAL_EXEC
;
1261 case TLS_MODEL_LOCAL_DYNAMIC
:
1262 /* Rely on section anchors for the optimization that LDM TLS
1263 provides. The anchor's address is loaded with GD TLS. */
1264 case TLS_MODEL_GLOBAL_DYNAMIC
:
1265 tmp
= gen_rtx_REG (Pmode
, GP_RETURN
);
1266 dest
= gen_reg_rtx (Pmode
);
1267 emit_libcall_block (riscv_call_tls_get_addr (loc
, tmp
), dest
, tmp
, loc
);
1270 case TLS_MODEL_INITIAL_EXEC
:
1271 /* la.tls.ie; tp-relative add */
1272 tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1273 tmp
= gen_reg_rtx (Pmode
);
1274 emit_insn (riscv_got_load_tls_ie (tmp
, loc
));
1275 dest
= gen_reg_rtx (Pmode
);
1276 emit_insn (gen_add3_insn (dest
, tmp
, tp
));
1279 case TLS_MODEL_LOCAL_EXEC
:
1280 tmp
= riscv_unspec_offset_high (NULL
, loc
, SYMBOL_TLS_LE
);
1281 dest
= gen_reg_rtx (Pmode
);
1282 emit_insn (riscv_tls_add_tp_le (dest
, tmp
, loc
));
1283 dest
= gen_rtx_LO_SUM (Pmode
, dest
,
1284 riscv_unspec_address (loc
, SYMBOL_TLS_LE
));
1293 /* If X is not a valid address for mode MODE, force it into a register. */
1296 riscv_force_address (rtx x
, machine_mode mode
)
1298 if (!riscv_legitimate_address_p (mode
, x
, false))
1299 x
= force_reg (Pmode
, x
);
1303 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1304 be legitimized in a way that the generic machinery might not expect,
1305 return a new address, otherwise return NULL. MODE is the mode of
1306 the memory being accessed. */
1309 riscv_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1314 if (riscv_tls_symbol_p (x
))
1315 return riscv_legitimize_tls_address (x
);
1317 /* See if the address can split into a high part and a LO_SUM. */
1318 if (riscv_split_symbol (NULL
, x
, mode
, &addr
))
1319 return riscv_force_address (addr
, mode
);
1321 /* Handle BASE + OFFSET using riscv_add_offset. */
1322 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
1323 && INTVAL (XEXP (x
, 1)) != 0)
1325 rtx base
= XEXP (x
, 0);
1326 HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
1328 if (!riscv_valid_base_register_p (base
, mode
, false))
1329 base
= copy_to_mode_reg (Pmode
, base
);
1330 addr
= riscv_add_offset (NULL
, base
, offset
);
1331 return riscv_force_address (addr
, mode
);
1337 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */
1340 riscv_move_integer (rtx temp
, rtx dest
, HOST_WIDE_INT value
)
1342 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
1347 mode
= GET_MODE (dest
);
1348 num_ops
= riscv_build_integer (codes
, value
, mode
);
1350 if (can_create_pseudo_p () && num_ops
> 2 /* not a simple constant */
1351 && num_ops
>= riscv_split_integer_cost (value
))
1352 x
= riscv_split_integer (value
, mode
);
1355 /* Apply each binary operation to X. */
1356 x
= GEN_INT (codes
[0].value
);
1358 for (i
= 1; i
< num_ops
; i
++)
1360 if (!can_create_pseudo_p ())
1361 x
= riscv_emit_set (temp
, x
);
1363 x
= force_reg (mode
, x
);
1365 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1369 riscv_emit_set (dest
, x
);
1372 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1373 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1377 riscv_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
1381 /* Split moves of big integers into smaller pieces. */
1382 if (splittable_const_int_operand (src
, mode
))
1384 riscv_move_integer (dest
, dest
, INTVAL (src
));
1388 /* Split moves of symbolic constants into high/low pairs. */
1389 if (riscv_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
1391 riscv_emit_set (dest
, src
);
1395 /* Generate the appropriate access sequences for TLS symbols. */
1396 if (riscv_tls_symbol_p (src
))
1398 riscv_emit_move (dest
, riscv_legitimize_tls_address (src
));
1402 /* If we have (const (plus symbol offset)), and that expression cannot
1403 be forced into memory, load the symbol first and add in the offset. Also
1404 prefer to do this even if the constant _can_ be forced into memory, as it
1405 usually produces better code. */
1406 split_const (src
, &base
, &offset
);
1407 if (offset
!= const0_rtx
1408 && (targetm
.cannot_force_const_mem (mode
, src
) || can_create_pseudo_p ()))
1410 base
= riscv_force_temporary (dest
, base
);
1411 riscv_emit_move (dest
, riscv_add_offset (NULL
, base
, INTVAL (offset
)));
1415 src
= force_const_mem (mode
, src
);
1417 /* When using explicit relocs, constant pool references are sometimes
1418 not legitimate addresses. */
1419 riscv_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
1420 riscv_emit_move (dest
, src
);
1423 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1424 sequence that is valid. */
1427 riscv_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
1429 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1431 riscv_emit_move (dest
, force_reg (mode
, src
));
1435 /* We need to deal with constants that would be legitimate
1436 immediate_operands but aren't legitimate move_operands. */
1437 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1439 riscv_legitimize_const_move (mode
, dest
, src
);
1440 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1444 /* RISC-V GCC may generate non-legitimate address due to we provide some
1445 pattern for optimize access PIC local symbol and it's make GCC generate
1446 unrecognizable instruction during optmizing. */
1448 if (MEM_P (dest
) && !riscv_legitimate_address_p (mode
, XEXP (dest
, 0),
1451 XEXP (dest
, 0) = riscv_force_address (XEXP (dest
, 0), mode
);
1454 if (MEM_P (src
) && !riscv_legitimate_address_p (mode
, XEXP (src
, 0),
1457 XEXP (src
, 0) = riscv_force_address (XEXP (src
, 0), mode
);
1463 /* Return true if there is an instruction that implements CODE and accepts
1464 X as an immediate operand. */
1467 riscv_immediate_operand_p (int code
, HOST_WIDE_INT x
)
1474 /* All shift counts are truncated to a valid constant. */
1483 /* These instructions take 12-bit signed immediates. */
1484 return SMALL_OPERAND (x
);
1487 /* We add 1 to the immediate and use SLT. */
1488 return SMALL_OPERAND (x
+ 1);
1491 /* Likewise SLTU, but reject the always-true case. */
1492 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
1496 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1500 /* By default assume that x0 can be used for 0. */
1505 /* Return the cost of binary operation X, given that the instruction
1506 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1507 instructions and that the sequence of a double-word operation takes
1508 DOUBLE_INSNS instructions. */
1511 riscv_binary_cost (rtx x
, int single_insns
, int double_insns
)
1513 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
1514 return COSTS_N_INSNS (double_insns
);
1515 return COSTS_N_INSNS (single_insns
);
1518 /* Return the cost of sign- or zero-extending OP. */
1521 riscv_extend_cost (rtx op
, bool unsigned_p
)
1526 if (unsigned_p
&& GET_MODE (op
) == QImode
)
1527 /* We can use ANDI. */
1528 return COSTS_N_INSNS (1);
1530 if (!unsigned_p
&& GET_MODE (op
) == SImode
)
1531 /* We can use SEXT.W. */
1532 return COSTS_N_INSNS (1);
1534 /* We need to use a shift left and a shift right. */
1535 return COSTS_N_INSNS (2);
1538 /* Implement TARGET_RTX_COSTS. */
1540 #define SINGLE_SHIFT_COST 1
1543 riscv_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1544 int *total
, bool speed
)
1546 bool float_mode_p
= FLOAT_MODE_P (mode
);
1549 switch (GET_CODE (x
))
1552 if (riscv_immediate_operand_p (outer_code
, INTVAL (x
)))
1563 if ((cost
= riscv_const_insns (x
)) > 0)
1565 /* If the constant is likely to be stored in a GPR, SETs of
1566 single-insn constants are as cheap as register sets; we
1567 never want to CSE them. */
1568 if (cost
== 1 && outer_code
== SET
)
1570 /* When we load a constant more than once, it usually is better
1571 to duplicate the last operation in the sequence than to CSE
1572 the constant itself. */
1573 else if (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
)
1574 *total
= COSTS_N_INSNS (1);
1576 else /* The instruction will be fetched from the constant pool. */
1577 *total
= COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE
));
1581 /* If the address is legitimate, return the number of
1582 instructions it needs. */
1583 if ((cost
= riscv_address_insns (XEXP (x
, 0), mode
, true)) > 0)
1585 *total
= COSTS_N_INSNS (cost
+ tune_info
->memory_cost
);
1588 /* Otherwise use the default handling. */
1592 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
1598 /* Double-word operations use two single-word operations. */
1599 *total
= riscv_binary_cost (x
, 1, 2);
1603 /* This is an SImode shift. */
1604 if (outer_code
== SET
&& (INTVAL (XEXP (x
, 2)) > 0)
1605 && (INTVAL (XEXP (x
, 1)) + INTVAL (XEXP (x
, 2)) == 32))
1607 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1615 *total
= riscv_binary_cost (x
, SINGLE_SHIFT_COST
,
1616 CONSTANT_P (XEXP (x
, 1)) ? 4 : 9);
1620 *total
= COSTS_N_INSNS (float_mode_p
? 1 : 3);
1624 *total
= set_src_cost (XEXP (x
, 0), mode
, speed
);
1628 /* This is an SImode shift. */
1629 if (outer_code
== SET
&& GET_MODE (x
) == DImode
1630 && GET_MODE (XEXP (x
, 0)) == SImode
)
1632 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1645 /* Branch comparisons have VOIDmode, so use the first operand's
1647 mode
= GET_MODE (XEXP (x
, 0));
1649 *total
= tune_info
->fp_add
[mode
== DFmode
];
1651 *total
= riscv_binary_cost (x
, 1, 3);
1656 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1657 mode
= GET_MODE (XEXP (x
, 0));
1658 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1663 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1664 mode
= GET_MODE (XEXP (x
, 0));
1665 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (3);
1672 /* FLT or FLE, but guarded by an FFLAGS read and write. */
1673 mode
= GET_MODE (XEXP (x
, 0));
1674 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (4);
1680 *total
= tune_info
->fp_add
[mode
== DFmode
];
1682 *total
= riscv_binary_cost (x
, 1, 4);
1687 rtx op
= XEXP (x
, 0);
1688 if (GET_CODE (op
) == FMA
&& !HONOR_SIGNED_ZEROS (mode
))
1690 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1691 + set_src_cost (XEXP (op
, 0), mode
, speed
)
1692 + set_src_cost (XEXP (op
, 1), mode
, speed
)
1693 + set_src_cost (XEXP (op
, 2), mode
, speed
));
1699 *total
= tune_info
->fp_add
[mode
== DFmode
];
1701 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
1706 *total
= tune_info
->fp_mul
[mode
== DFmode
];
1707 else if (!TARGET_MUL
)
1708 /* Estimate the cost of a library call. */
1709 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1710 else if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
1711 *total
= 3 * tune_info
->int_mul
[0] + COSTS_N_INSNS (2);
1713 *total
= COSTS_N_INSNS (1);
1715 *total
= tune_info
->int_mul
[mode
== DImode
];
1723 *total
= tune_info
->fp_div
[mode
== DFmode
];
1731 /* Estimate the cost of a library call. */
1732 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1734 *total
= tune_info
->int_div
[mode
== DImode
];
1736 *total
= COSTS_N_INSNS (1);
1740 /* This is an SImode shift. */
1741 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
1743 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1748 *total
= riscv_extend_cost (XEXP (x
, 0), GET_CODE (x
) == ZERO_EXTEND
);
1752 case UNSIGNED_FLOAT
:
1755 case FLOAT_TRUNCATE
:
1756 *total
= tune_info
->fp_add
[mode
== DFmode
];
1760 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1761 + set_src_cost (XEXP (x
, 0), mode
, speed
)
1762 + set_src_cost (XEXP (x
, 1), mode
, speed
)
1763 + set_src_cost (XEXP (x
, 2), mode
, speed
));
1767 if (XINT (x
, 1) == UNSPEC_AUIPC
)
1769 /* Make AUIPC cheap to avoid spilling its result to the stack. */
1780 /* Implement TARGET_ADDRESS_COST. */
1783 riscv_address_cost (rtx addr
, machine_mode mode
,
1784 addr_space_t as ATTRIBUTE_UNUSED
,
1785 bool speed ATTRIBUTE_UNUSED
)
1787 return riscv_address_insns (addr
, mode
, false);
1790 /* Return one word of double-word value OP. HIGH_P is true to select the
1791 high part or false to select the low part. */
1794 riscv_subword (rtx op
, bool high_p
)
1796 unsigned int byte
= high_p
? UNITS_PER_WORD
: 0;
1797 machine_mode mode
= GET_MODE (op
);
1799 if (mode
== VOIDmode
)
1800 mode
= TARGET_64BIT
? TImode
: DImode
;
1803 return adjust_address (op
, word_mode
, byte
);
1806 gcc_assert (!FP_REG_RTX_P (op
));
1808 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
1811 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
1814 riscv_split_64bit_move_p (rtx dest
, rtx src
)
1819 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
1820 of zeroing an FPR with FCVT.D.W. */
1821 if (TARGET_DOUBLE_FLOAT
1822 && ((FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
1823 || (FP_REG_RTX_P (dest
) && MEM_P (src
))
1824 || (FP_REG_RTX_P (src
) && MEM_P (dest
))
1825 || (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))))
1831 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
1832 this function handles 64-bit moves for which riscv_split_64bit_move_p
1833 holds. For 64-bit targets, this function handles 128-bit moves. */
1836 riscv_split_doubleword_move (rtx dest
, rtx src
)
1840 /* The operation can be split into two normal moves. Decide in
1841 which order to do them. */
1842 low_dest
= riscv_subword (dest
, false);
1843 if (REG_P (low_dest
) && reg_overlap_mentioned_p (low_dest
, src
))
1845 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1846 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1850 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1851 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1855 /* Return the appropriate instructions to move SRC into DEST. Assume
1856 that SRC is operand 1 and DEST is operand 0. */
1859 riscv_output_move (rtx dest
, rtx src
)
1861 enum rtx_code dest_code
, src_code
;
1865 dest_code
= GET_CODE (dest
);
1866 src_code
= GET_CODE (src
);
1867 mode
= GET_MODE (dest
);
1868 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
1870 if (dbl_p
&& riscv_split_64bit_move_p (dest
, src
))
1873 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
1875 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1876 return dbl_p
? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
1878 if (src_code
== MEM
)
1879 switch (GET_MODE_SIZE (mode
))
1881 case 1: return "lbu\t%0,%1";
1882 case 2: return "lhu\t%0,%1";
1883 case 4: return "lw\t%0,%1";
1884 case 8: return "ld\t%0,%1";
1887 if (src_code
== CONST_INT
)
1890 if (src_code
== HIGH
)
1891 return "lui\t%0,%h1";
1893 if (symbolic_operand (src
, VOIDmode
))
1894 switch (riscv_classify_symbolic_expression (src
))
1896 case SYMBOL_GOT_DISP
: return "la\t%0,%1";
1897 case SYMBOL_ABSOLUTE
: return "lla\t%0,%1";
1898 case SYMBOL_PCREL
: return "lla\t%0,%1";
1899 default: gcc_unreachable ();
1902 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
1903 || (src
== CONST0_RTX (mode
)))
1905 if (dest_code
== REG
)
1907 if (GP_REG_P (REGNO (dest
)))
1908 return "mv\t%0,%z1";
1910 if (FP_REG_P (REGNO (dest
)))
1913 return "fmv.s.x\t%0,%z1";
1915 return "fmv.d.x\t%0,%z1";
1916 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
1917 gcc_assert (src
== CONST0_RTX (mode
));
1918 return "fcvt.d.w\t%0,x0";
1921 if (dest_code
== MEM
)
1922 switch (GET_MODE_SIZE (mode
))
1924 case 1: return "sb\t%z1,%0";
1925 case 2: return "sh\t%z1,%0";
1926 case 4: return "sw\t%z1,%0";
1927 case 8: return "sd\t%z1,%0";
1930 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1932 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1933 return dbl_p
? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
1935 if (dest_code
== MEM
)
1936 return dbl_p
? "fsd\t%1,%0" : "fsw\t%1,%0";
1938 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1940 if (src_code
== MEM
)
1941 return dbl_p
? "fld\t%0,%1" : "flw\t%0,%1";
1947 riscv_output_return ()
1949 if (cfun
->machine
->naked_p
)
1956 /* Return true if CMP1 is a suitable second operand for integer ordering
1957 test CODE. See also the *sCC patterns in riscv.md. */
1960 riscv_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
1966 return reg_or_0_operand (cmp1
, VOIDmode
);
1970 return cmp1
== const1_rtx
;
1974 return arith_operand (cmp1
, VOIDmode
);
1977 return sle_operand (cmp1
, VOIDmode
);
1980 return sleu_operand (cmp1
, VOIDmode
);
1987 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
1988 integer ordering test *CODE, or if an equivalent combination can
1989 be formed by adjusting *CODE and *CMP1. When returning true, update
1990 *CODE and *CMP1 with the chosen code and operand, otherwise leave
1994 riscv_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
1997 HOST_WIDE_INT plus_one
;
1999 if (riscv_int_order_operand_ok_p (*code
, *cmp1
))
2002 if (CONST_INT_P (*cmp1
))
2006 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2007 if (INTVAL (*cmp1
) < plus_one
)
2010 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2016 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2020 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2031 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
2032 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
2033 is nonnull, it's OK to set TARGET to the inverse of the result and
2034 flip *INVERT_PTR instead. */
2037 riscv_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
2038 rtx target
, rtx cmp0
, rtx cmp1
)
2042 /* First see if there is a RISCV instruction that can do this operation.
2043 If not, try doing the same for the inverse operation. If that also
2044 fails, force CMP1 into a register and try again. */
2045 mode
= GET_MODE (cmp0
);
2046 if (riscv_canonicalize_int_order_test (&code
, &cmp1
, mode
))
2047 riscv_emit_binary (code
, target
, cmp0
, cmp1
);
2050 enum rtx_code inv_code
= reverse_condition (code
);
2051 if (!riscv_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
2053 cmp1
= force_reg (mode
, cmp1
);
2054 riscv_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
2056 else if (invert_ptr
== 0)
2058 rtx inv_target
= riscv_force_binary (GET_MODE (target
),
2059 inv_code
, cmp0
, cmp1
);
2060 riscv_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
2064 *invert_ptr
= !*invert_ptr
;
2065 riscv_emit_binary (inv_code
, target
, cmp0
, cmp1
);
2070 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2071 The register will have the same mode as CMP0. */
2074 riscv_zero_if_equal (rtx cmp0
, rtx cmp1
)
2076 if (cmp1
== const0_rtx
)
2079 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2080 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2083 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2086 riscv_extend_comparands (rtx_code code
, rtx
*op0
, rtx
*op1
)
2088 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2089 if (GET_MODE_SIZE (word_mode
) > GET_MODE_SIZE (GET_MODE (*op0
)))
2091 /* It is more profitable to zero-extend QImode values. But not if the
2092 first operand has already been sign-extended, and the second one is
2093 is a constant or has already been sign-extended also. */
2094 if (unsigned_condition (code
) == code
2095 && (GET_MODE (*op0
) == QImode
2096 && ! (GET_CODE (*op0
) == SUBREG
2097 && SUBREG_PROMOTED_VAR_P (*op0
)
2098 && SUBREG_PROMOTED_SIGNED_P (*op0
)
2099 && (CONST_INT_P (*op1
)
2100 || (GET_CODE (*op1
) == SUBREG
2101 && SUBREG_PROMOTED_VAR_P (*op1
)
2102 && SUBREG_PROMOTED_SIGNED_P (*op1
))))))
2104 *op0
= gen_rtx_ZERO_EXTEND (word_mode
, *op0
);
2105 if (CONST_INT_P (*op1
))
2106 *op1
= GEN_INT ((uint8_t) INTVAL (*op1
));
2108 *op1
= gen_rtx_ZERO_EXTEND (word_mode
, *op1
);
2112 *op0
= gen_rtx_SIGN_EXTEND (word_mode
, *op0
);
2113 if (*op1
!= const0_rtx
)
2114 *op1
= gen_rtx_SIGN_EXTEND (word_mode
, *op1
);
2119 /* Convert a comparison into something that can be used in a branch. On
2120 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2121 used to compare them. Update them to describe the final comparison. */
2124 riscv_emit_int_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2126 if (splittable_const_int_operand (*op1
, VOIDmode
))
2128 HOST_WIDE_INT rhs
= INTVAL (*op1
);
2130 if (*code
== EQ
|| *code
== NE
)
2132 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2133 if (SMALL_OPERAND (-rhs
))
2135 *op0
= riscv_force_binary (GET_MODE (*op0
), PLUS
, *op0
,
2142 static const enum rtx_code mag_comparisons
[][2] = {
2143 {LEU
, LTU
}, {GTU
, GEU
}, {LE
, LT
}, {GT
, GE
}
2146 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2147 for (size_t i
= 0; i
< ARRAY_SIZE (mag_comparisons
); i
++)
2149 HOST_WIDE_INT new_rhs
;
2150 bool increment
= *code
== mag_comparisons
[i
][0];
2151 bool decrement
= *code
== mag_comparisons
[i
][1];
2152 if (!increment
&& !decrement
)
2155 new_rhs
= rhs
+ (increment
? 1 : -1);
2156 if (riscv_integer_cost (new_rhs
) < riscv_integer_cost (rhs
)
2157 && (rhs
< 0) == (new_rhs
< 0))
2159 *op1
= GEN_INT (new_rhs
);
2160 *code
= mag_comparisons
[i
][increment
];
2167 riscv_extend_comparands (*code
, op0
, op1
);
2169 *op0
= force_reg (word_mode
, *op0
);
2170 if (*op1
!= const0_rtx
)
2171 *op1
= force_reg (word_mode
, *op1
);
2174 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2177 riscv_emit_float_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2179 rtx tmp0
, tmp1
, cmp_op0
= *op0
, cmp_op1
= *op1
;
2180 enum rtx_code fp_code
= *code
;
2190 /* a == a && b == b */
2191 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2192 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2193 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2199 /* ordered(a, b) > (a == b) */
2200 *code
= fp_code
== LTGT
? GTU
: EQ
;
2201 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2202 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2203 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2204 *op1
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op1
);
2207 #define UNORDERED_COMPARISON(CODE, CMP) \
2210 *op0 = gen_reg_rtx (word_mode); \
2211 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2212 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2213 else if (GET_MODE (cmp_op0) == SFmode) \
2214 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2215 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2216 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2217 else if (GET_MODE (cmp_op0) == DFmode) \
2218 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2220 gcc_unreachable (); \
2221 *op1 = const0_rtx; \
2225 std::swap (cmp_op0
, cmp_op1
);
2228 UNORDERED_COMPARISON(UNGT
, le
)
2231 std::swap (cmp_op0
, cmp_op1
);
2234 UNORDERED_COMPARISON(UNGE
, lt
)
2235 #undef UNORDERED_COMPARISON
2247 /* We have instructions for these cases. */
2248 *op0
= riscv_force_binary (word_mode
, fp_code
, cmp_op0
, cmp_op1
);
2257 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2260 riscv_expand_int_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2262 riscv_extend_comparands (code
, &op0
, &op1
);
2263 op0
= force_reg (word_mode
, op0
);
2265 if (code
== EQ
|| code
== NE
)
2267 rtx zie
= riscv_zero_if_equal (op0
, op1
);
2268 riscv_emit_binary (code
, target
, zie
, const0_rtx
);
2271 riscv_emit_int_order_test (code
, 0, target
, op0
, op1
);
2274 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2277 riscv_expand_float_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2279 riscv_emit_float_compare (&code
, &op0
, &op1
);
2281 rtx cmp
= riscv_force_binary (word_mode
, code
, op0
, op1
);
2282 riscv_emit_set (target
, lowpart_subreg (SImode
, cmp
, word_mode
));
2285 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2288 riscv_expand_conditional_branch (rtx label
, rtx_code code
, rtx op0
, rtx op1
)
2290 if (FLOAT_MODE_P (GET_MODE (op1
)))
2291 riscv_emit_float_compare (&code
, &op0
, &op1
);
2293 riscv_emit_int_compare (&code
, &op0
, &op1
);
2295 rtx condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2296 emit_jump_insn (gen_condjump (condition
, label
));
2299 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2300 least PARM_BOUNDARY bits of alignment, but will be given anything up
2301 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2304 riscv_function_arg_boundary (machine_mode mode
, const_tree type
)
2306 unsigned int alignment
;
2308 /* Use natural alignment if the type is not aggregate data. */
2309 if (type
&& !AGGREGATE_TYPE_P (type
))
2310 alignment
= TYPE_ALIGN (TYPE_MAIN_VARIANT (type
));
2312 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2314 return MIN (PREFERRED_STACK_BOUNDARY
, MAX (PARM_BOUNDARY
, alignment
));
2317 /* If MODE represents an argument that can be passed or returned in
2318 floating-point registers, return the number of registers, else 0. */
2321 riscv_pass_mode_in_fpr_p (machine_mode mode
)
2323 if (GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FP_ARG
)
2325 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2328 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
2337 HOST_WIDE_INT offset
;
2338 } riscv_aggregate_field
;
2340 /* Identify subfields of aggregates that are candidates for passing in
2341 floating-point registers. */
2344 riscv_flatten_aggregate_field (const_tree type
,
2345 riscv_aggregate_field fields
[2],
2346 int n
, HOST_WIDE_INT offset
)
2348 switch (TREE_CODE (type
))
2351 /* Can't handle incomplete types nor sizes that are not fixed. */
2352 if (!COMPLETE_TYPE_P (type
)
2353 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2354 || !tree_fits_uhwi_p (TYPE_SIZE (type
)))
2357 for (tree f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
2358 if (TREE_CODE (f
) == FIELD_DECL
)
2360 if (!TYPE_P (TREE_TYPE (f
)))
2363 HOST_WIDE_INT pos
= offset
+ int_byte_position (f
);
2364 n
= riscv_flatten_aggregate_field (TREE_TYPE (f
), fields
, n
, pos
);
2372 HOST_WIDE_INT n_elts
;
2373 riscv_aggregate_field subfields
[2];
2374 tree index
= TYPE_DOMAIN (type
);
2375 tree elt_size
= TYPE_SIZE_UNIT (TREE_TYPE (type
));
2376 int n_subfields
= riscv_flatten_aggregate_field (TREE_TYPE (type
),
2377 subfields
, 0, offset
);
2379 /* Can't handle incomplete types nor sizes that are not fixed. */
2380 if (n_subfields
<= 0
2381 || !COMPLETE_TYPE_P (type
)
2382 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2384 || !TYPE_MAX_VALUE (index
)
2385 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
2386 || !TYPE_MIN_VALUE (index
)
2387 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
2388 || !tree_fits_uhwi_p (elt_size
))
2391 n_elts
= 1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
2392 - tree_to_uhwi (TYPE_MIN_VALUE (index
));
2393 gcc_assert (n_elts
>= 0);
2395 for (HOST_WIDE_INT i
= 0; i
< n_elts
; i
++)
2396 for (int j
= 0; j
< n_subfields
; j
++)
2401 fields
[n
] = subfields
[j
];
2402 fields
[n
++].offset
+= i
* tree_to_uhwi (elt_size
);
2410 /* Complex type need consume 2 field, so n must be 0. */
2414 HOST_WIDE_INT elt_size
= GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type
)));
2416 if (elt_size
<= UNITS_PER_FP_ARG
)
2418 fields
[0].type
= TREE_TYPE (type
);
2419 fields
[0].offset
= offset
;
2420 fields
[1].type
= TREE_TYPE (type
);
2421 fields
[1].offset
= offset
+ elt_size
;
2431 && ((SCALAR_FLOAT_TYPE_P (type
)
2432 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FP_ARG
)
2433 || (INTEGRAL_TYPE_P (type
)
2434 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_WORD
)))
2436 fields
[n
].type
= type
;
2437 fields
[n
].offset
= offset
;
2445 /* Identify candidate aggregates for passing in floating-point registers.
2446 Candidates have at most two fields after flattening. */
2449 riscv_flatten_aggregate_argument (const_tree type
,
2450 riscv_aggregate_field fields
[2])
2452 if (!type
|| TREE_CODE (type
) != RECORD_TYPE
)
2455 return riscv_flatten_aggregate_field (type
, fields
, 0, 0);
2458 /* See whether TYPE is a record whose fields should be returned in one or
2459 two floating-point registers. If so, populate FIELDS accordingly. */
2462 riscv_pass_aggregate_in_fpr_pair_p (const_tree type
,
2463 riscv_aggregate_field fields
[2])
2465 int n
= riscv_flatten_aggregate_argument (type
, fields
);
2467 for (int i
= 0; i
< n
; i
++)
2468 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2471 return n
> 0 ? n
: 0;
2474 /* See whether TYPE is a record whose fields should be returned in one or
2475 floating-point register and one integer register. If so, populate
2476 FIELDS accordingly. */
2479 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type
,
2480 riscv_aggregate_field fields
[2])
2482 unsigned num_int
= 0, num_float
= 0;
2483 int n
= riscv_flatten_aggregate_argument (type
, fields
);
2485 for (int i
= 0; i
< n
; i
++)
2487 num_float
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2488 num_int
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2491 return num_int
== 1 && num_float
== 1;
2494 /* Return the representation of an argument passed or returned in an FPR
2495 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2496 two modes may be different for structures like:
2498 struct __attribute__((packed)) foo { float f; }
2500 where the SFmode value "f" is passed in REGNO but the struct itself
2501 has mode BLKmode. */
2504 riscv_pass_fpr_single (machine_mode type_mode
, unsigned regno
,
2505 machine_mode value_mode
,
2506 HOST_WIDE_INT offset
)
2508 rtx x
= gen_rtx_REG (value_mode
, regno
);
2510 if (type_mode
!= value_mode
)
2512 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, GEN_INT (offset
));
2513 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
2518 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
2519 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
2520 byte offset for the first value, likewise MODE2 and OFFSET2 for the
2524 riscv_pass_fpr_pair (machine_mode mode
, unsigned regno1
,
2525 machine_mode mode1
, HOST_WIDE_INT offset1
,
2526 unsigned regno2
, machine_mode mode2
,
2527 HOST_WIDE_INT offset2
)
2529 return gen_rtx_PARALLEL
2532 gen_rtx_EXPR_LIST (VOIDmode
,
2533 gen_rtx_REG (mode1
, regno1
),
2535 gen_rtx_EXPR_LIST (VOIDmode
,
2536 gen_rtx_REG (mode2
, regno2
),
2537 GEN_INT (offset2
))));
2540 /* Fill INFO with information about a single argument, and return an
2541 RTL pattern to pass or return the argument. CUM is the cumulative
2542 state for earlier arguments. MODE is the mode of this argument and
2543 TYPE is its type (if known). NAMED is true if this is a named
2544 (fixed) argument rather than a variable one. RETURN_P is true if
2545 returning the argument, or false if passing the argument. */
2548 riscv_get_arg_info (struct riscv_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
2549 machine_mode mode
, const_tree type
, bool named
,
2552 unsigned num_bytes
, num_words
;
2553 unsigned fpr_base
= return_p
? FP_RETURN
: FP_ARG_FIRST
;
2554 unsigned gpr_base
= return_p
? GP_RETURN
: GP_ARG_FIRST
;
2555 unsigned alignment
= riscv_function_arg_boundary (mode
, type
);
2557 memset (info
, 0, sizeof (*info
));
2558 info
->gpr_offset
= cum
->num_gprs
;
2559 info
->fpr_offset
= cum
->num_fprs
;
2563 riscv_aggregate_field fields
[2];
2564 unsigned fregno
= fpr_base
+ info
->fpr_offset
;
2565 unsigned gregno
= gpr_base
+ info
->gpr_offset
;
2567 /* Pass one- or two-element floating-point aggregates in FPRs. */
2568 if ((info
->num_fprs
= riscv_pass_aggregate_in_fpr_pair_p (type
, fields
))
2569 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2570 switch (info
->num_fprs
)
2573 return riscv_pass_fpr_single (mode
, fregno
,
2574 TYPE_MODE (fields
[0].type
),
2578 return riscv_pass_fpr_pair (mode
, fregno
,
2579 TYPE_MODE (fields
[0].type
),
2582 TYPE_MODE (fields
[1].type
),
2589 /* Pass real and complex floating-point numbers in FPRs. */
2590 if ((info
->num_fprs
= riscv_pass_mode_in_fpr_p (mode
))
2591 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2592 switch (GET_MODE_CLASS (mode
))
2595 return gen_rtx_REG (mode
, fregno
);
2597 case MODE_COMPLEX_FLOAT
:
2598 return riscv_pass_fpr_pair (mode
, fregno
, GET_MODE_INNER (mode
), 0,
2599 fregno
+ 1, GET_MODE_INNER (mode
),
2600 GET_MODE_UNIT_SIZE (mode
));
2606 /* Pass structs with one float and one integer in an FPR and a GPR. */
2607 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type
, fields
)
2608 && info
->gpr_offset
< MAX_ARGS_IN_REGISTERS
2609 && info
->fpr_offset
< MAX_ARGS_IN_REGISTERS
)
2614 if (!SCALAR_FLOAT_TYPE_P (fields
[0].type
))
2615 std::swap (fregno
, gregno
);
2617 return riscv_pass_fpr_pair (mode
, fregno
, TYPE_MODE (fields
[0].type
),
2619 gregno
, TYPE_MODE (fields
[1].type
),
2624 /* Work out the size of the argument. */
2625 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2626 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2628 /* Doubleword-aligned varargs start on an even register boundary. */
2629 if (!named
&& num_bytes
!= 0 && alignment
> BITS_PER_WORD
)
2630 info
->gpr_offset
+= info
->gpr_offset
& 1;
2632 /* Partition the argument between registers and stack. */
2634 info
->num_gprs
= MIN (num_words
, MAX_ARGS_IN_REGISTERS
- info
->gpr_offset
);
2635 info
->stack_p
= (num_words
- info
->num_gprs
) != 0;
2637 if (info
->num_gprs
|| return_p
)
2638 return gen_rtx_REG (mode
, gpr_base
+ info
->gpr_offset
);
2643 /* Implement TARGET_FUNCTION_ARG. */
2646 riscv_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
2647 const_tree type
, bool named
)
2649 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2650 struct riscv_arg_info info
;
2652 if (mode
== VOIDmode
)
2655 return riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2658 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
2661 riscv_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2662 const_tree type
, bool named
)
2664 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2665 struct riscv_arg_info info
;
2667 riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2669 /* Advance the register count. This has the effect of setting
2670 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
2671 argument required us to skip the final GPR and pass the whole
2672 argument on the stack. */
2673 cum
->num_fprs
= info
.fpr_offset
+ info
.num_fprs
;
2674 cum
->num_gprs
= info
.gpr_offset
+ info
.num_gprs
;
2677 /* Implement TARGET_ARG_PARTIAL_BYTES. */
2680 riscv_arg_partial_bytes (cumulative_args_t cum
,
2681 machine_mode mode
, tree type
, bool named
)
2683 struct riscv_arg_info arg
;
2685 riscv_get_arg_info (&arg
, get_cumulative_args (cum
), mode
, type
, named
, false);
2686 return arg
.stack_p
? arg
.num_gprs
* UNITS_PER_WORD
: 0;
2689 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
2690 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
2691 VALTYPE is null and MODE is the mode of the return value. */
2694 riscv_function_value (const_tree type
, const_tree func
, machine_mode mode
)
2696 struct riscv_arg_info info
;
2697 CUMULATIVE_ARGS args
;
2701 int unsigned_p
= TYPE_UNSIGNED (type
);
2703 mode
= TYPE_MODE (type
);
2705 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
2706 return values, promote the mode here too. */
2707 mode
= promote_function_mode (type
, mode
, &unsigned_p
, func
, 1);
2710 memset (&args
, 0, sizeof args
);
2711 return riscv_get_arg_info (&info
, &args
, mode
, type
, true, true);
2714 /* Implement TARGET_PASS_BY_REFERENCE. */
2717 riscv_pass_by_reference (cumulative_args_t cum_v
, machine_mode mode
,
2718 const_tree type
, bool named
)
2720 HOST_WIDE_INT size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2721 struct riscv_arg_info info
;
2722 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2724 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
2725 never pass variadic arguments in floating-point registers, so we can
2726 avoid the call to riscv_get_arg_info in this case. */
2729 /* Don't pass by reference if we can use a floating-point register. */
2730 riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2735 /* Pass by reference if the data do not fit in two integer registers. */
2736 return !IN_RANGE (size
, 0, 2 * UNITS_PER_WORD
);
2739 /* Implement TARGET_RETURN_IN_MEMORY. */
2742 riscv_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
2744 CUMULATIVE_ARGS args
;
2745 cumulative_args_t cum
= pack_cumulative_args (&args
);
2747 /* The rules for returning in memory are the same as for passing the
2748 first named argument by reference. */
2749 memset (&args
, 0, sizeof args
);
2750 return riscv_pass_by_reference (cum
, TYPE_MODE (type
), type
, true);
2753 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
2756 riscv_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
2757 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
2760 CUMULATIVE_ARGS local_cum
;
2763 /* The caller has advanced CUM up to, but not beyond, the last named
2764 argument. Advance a local copy of CUM past the last "real" named
2765 argument, to find out how many registers are left over. */
2766 local_cum
= *get_cumulative_args (cum
);
2767 riscv_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
, 1);
2769 /* Found out how many registers we need to save. */
2770 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
2772 if (!no_rtl
&& gp_saved
> 0)
2774 rtx ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
2775 REG_PARM_STACK_SPACE (cfun
->decl
)
2776 - gp_saved
* UNITS_PER_WORD
);
2777 rtx mem
= gen_frame_mem (BLKmode
, ptr
);
2778 set_mem_alias_set (mem
, get_varargs_alias_set ());
2780 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
2783 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
2784 cfun
->machine
->varargs_size
= gp_saved
* UNITS_PER_WORD
;
2787 /* Handle an attribute requiring a FUNCTION_DECL;
2788 arguments as in struct attribute_spec.handler. */
2790 riscv_handle_fndecl_attribute (tree
*node
, tree name
,
2791 tree args ATTRIBUTE_UNUSED
,
2792 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2794 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2796 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2798 *no_add_attrs
= true;
2804 /* Verify type based attributes. NODE is the what the attribute is being
2805 applied to. NAME is the attribute name. ARGS are the attribute args.
2806 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
2807 the attribute should be ignored. */
2810 riscv_handle_type_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
2811 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2813 /* Check for an argument. */
2814 if (is_attribute_p ("interrupt", name
))
2818 tree cst
= TREE_VALUE (args
);
2821 if (TREE_CODE (cst
) != STRING_CST
)
2823 warning (OPT_Wattributes
,
2824 "%qE attribute requires a string argument",
2826 *no_add_attrs
= true;
2830 string
= TREE_STRING_POINTER (cst
);
2831 if (strcmp (string
, "user") && strcmp (string
, "supervisor")
2832 && strcmp (string
, "machine"))
2834 warning (OPT_Wattributes
,
2835 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"",
2837 *no_add_attrs
= true;
2845 /* Return true if function TYPE is an interrupt function. */
2847 riscv_interrupt_type_p (tree type
)
2849 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
2852 /* Return true if FUNC is a naked function. */
2854 riscv_naked_function_p (tree func
)
2856 tree func_decl
= func
;
2857 if (func
== NULL_TREE
)
2858 func_decl
= current_function_decl
;
2859 return NULL_TREE
!= lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl
));
2862 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
2864 riscv_allocate_stack_slots_for_args ()
2866 /* Naked functions should not allocate stack slots for arguments. */
2867 return !riscv_naked_function_p (current_function_decl
);
2870 /* Implement TARGET_WARN_FUNC_RETURN. */
2872 riscv_warn_func_return (tree decl
)
2874 /* Naked functions are implemented entirely in assembly, including the
2875 return sequence, so suppress warnings about this. */
2876 return !riscv_naked_function_p (decl
);
2879 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
2882 riscv_va_start (tree valist
, rtx nextarg
)
2884 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
2885 std_expand_builtin_va_start (valist
, nextarg
);
2888 /* Make ADDR suitable for use as a call or sibcall target. */
2891 riscv_legitimize_call_address (rtx addr
)
2893 if (!call_insn_operand (addr
, VOIDmode
))
2895 rtx reg
= RISCV_PROLOGUE_TEMP (Pmode
);
2896 riscv_emit_move (reg
, addr
);
2902 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
2903 Assume that the areas do not overlap. */
2906 riscv_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
2908 HOST_WIDE_INT offset
, delta
;
2909 unsigned HOST_WIDE_INT bits
;
2911 enum machine_mode mode
;
2914 bits
= MAX (BITS_PER_UNIT
,
2915 MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
))));
2917 mode
= mode_for_size (bits
, MODE_INT
, 0).require ();
2918 delta
= bits
/ BITS_PER_UNIT
;
2920 /* Allocate a buffer for the temporary registers. */
2921 regs
= XALLOCAVEC (rtx
, length
/ delta
);
2923 /* Load as many BITS-sized chunks as possible. Use a normal load if
2924 the source has enough alignment, otherwise use left/right pairs. */
2925 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2927 regs
[i
] = gen_reg_rtx (mode
);
2928 riscv_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
2931 /* Copy the chunks to the destination. */
2932 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2933 riscv_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
2935 /* Mop up any left-over bytes. */
2936 if (offset
< length
)
2938 src
= adjust_address (src
, BLKmode
, offset
);
2939 dest
= adjust_address (dest
, BLKmode
, offset
);
2940 move_by_pieces (dest
, src
, length
- offset
,
2941 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), RETURN_BEGIN
);
2945 /* Helper function for doing a loop-based block operation on memory
2946 reference MEM. Each iteration of the loop will operate on LENGTH
2949 Create a new base register for use within the loop and point it to
2950 the start of MEM. Create a new memory reference that uses this
2951 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
2954 riscv_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
2955 rtx
*loop_reg
, rtx
*loop_mem
)
2957 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
2959 /* Although the new mem does not refer to a known location,
2960 it does keep up to LENGTH bytes of alignment. */
2961 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
2962 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
2965 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
2966 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
2967 the memory regions do not overlap. */
2970 riscv_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
2971 HOST_WIDE_INT bytes_per_iter
)
2973 rtx label
, src_reg
, dest_reg
, final_src
, test
;
2974 HOST_WIDE_INT leftover
;
2976 leftover
= length
% bytes_per_iter
;
2979 /* Create registers and memory references for use within the loop. */
2980 riscv_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
2981 riscv_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
2983 /* Calculate the value that SRC_REG should have after the last iteration
2985 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
2988 /* Emit the start of the loop. */
2989 label
= gen_label_rtx ();
2992 /* Emit the loop body. */
2993 riscv_block_move_straight (dest
, src
, bytes_per_iter
);
2995 /* Move on to the next block. */
2996 riscv_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
2997 riscv_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
2999 /* Emit the loop condition. */
3000 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
3001 if (Pmode
== DImode
)
3002 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
3004 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
3006 /* Mop up any left-over bytes. */
3008 riscv_block_move_straight (dest
, src
, leftover
);
3010 emit_insn(gen_nop ());
3013 /* Expand a movmemsi instruction, which copies LENGTH bytes from
3014 memory reference SRC to memory reference DEST. */
3017 riscv_expand_block_move (rtx dest
, rtx src
, rtx length
)
3019 if (CONST_INT_P (length
))
3021 HOST_WIDE_INT factor
, align
;
3023 align
= MIN (MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), BITS_PER_WORD
);
3024 factor
= BITS_PER_WORD
/ align
;
3026 if (optimize_function_for_size_p (cfun
)
3027 && INTVAL (length
) * factor
* UNITS_PER_WORD
> MOVE_RATIO (false))
3030 if (INTVAL (length
) <= RISCV_MAX_MOVE_BYTES_STRAIGHT
/ factor
)
3032 riscv_block_move_straight (dest
, src
, INTVAL (length
));
3035 else if (optimize
&& align
>= BITS_PER_WORD
)
3037 unsigned min_iter_words
3038 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER
/ UNITS_PER_WORD
;
3039 unsigned iter_words
= min_iter_words
;
3040 HOST_WIDE_INT bytes
= INTVAL (length
), words
= bytes
/ UNITS_PER_WORD
;
3042 /* Lengthen the loop body if it shortens the tail. */
3043 for (unsigned i
= min_iter_words
; i
< min_iter_words
* 2 - 1; i
++)
3045 unsigned cur_cost
= iter_words
+ words
% iter_words
;
3046 unsigned new_cost
= i
+ words
% i
;
3047 if (new_cost
<= cur_cost
)
3051 riscv_block_move_loop (dest
, src
, bytes
, iter_words
* UNITS_PER_WORD
);
3058 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
3059 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
3062 riscv_print_operand_reloc (FILE *file
, rtx op
, bool hi_reloc
)
3066 switch (riscv_classify_symbolic_expression (op
))
3068 case SYMBOL_ABSOLUTE
:
3069 reloc
= hi_reloc
? "%hi" : "%lo";
3073 reloc
= hi_reloc
? "%pcrel_hi" : "%pcrel_lo";
3077 reloc
= hi_reloc
? "%tprel_hi" : "%tprel_lo";
3084 fprintf (file
, "%s(", reloc
);
3085 output_addr_const (file
, riscv_strip_unspec_address (op
));
3089 /* Return true if the .AQ suffix should be added to an AMO to implement the
3090 acquire portion of memory model MODEL. */
3093 riscv_memmodel_needs_amo_acquire (enum memmodel model
)
3097 case MEMMODEL_ACQ_REL
:
3098 case MEMMODEL_SEQ_CST
:
3099 case MEMMODEL_SYNC_SEQ_CST
:
3100 case MEMMODEL_ACQUIRE
:
3101 case MEMMODEL_CONSUME
:
3102 case MEMMODEL_SYNC_ACQUIRE
:
3105 case MEMMODEL_RELEASE
:
3106 case MEMMODEL_SYNC_RELEASE
:
3107 case MEMMODEL_RELAXED
:
3115 /* Return true if a FENCE should be emitted to before a memory access to
3116 implement the release portion of memory model MODEL. */
3119 riscv_memmodel_needs_release_fence (enum memmodel model
)
3123 case MEMMODEL_ACQ_REL
:
3124 case MEMMODEL_SEQ_CST
:
3125 case MEMMODEL_SYNC_SEQ_CST
:
3126 case MEMMODEL_RELEASE
:
3127 case MEMMODEL_SYNC_RELEASE
:
3130 case MEMMODEL_ACQUIRE
:
3131 case MEMMODEL_CONSUME
:
3132 case MEMMODEL_SYNC_ACQUIRE
:
3133 case MEMMODEL_RELAXED
:
3141 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3143 'h' Print the high-part relocation associated with OP, after stripping
3145 'R' Print the low-part relocation associated with OP.
3146 'C' Print the integer branch condition for comparison OP.
3147 'A' Print the atomic operation suffix for memory model OP.
3148 'F' Print a FENCE if the memory model requires a release.
3149 'z' Print x0 if OP is zero, otherwise print OP normally.
3150 'i' Print i if the operand is not a register. */
3153 riscv_print_operand (FILE *file
, rtx op
, int letter
)
3155 machine_mode mode
= GET_MODE (op
);
3156 enum rtx_code code
= GET_CODE (op
);
3163 riscv_print_operand_reloc (file
, op
, true);
3167 riscv_print_operand_reloc (file
, op
, false);
3171 /* The RTL names match the instruction names. */
3172 fputs (GET_RTX_NAME (code
), file
);
3176 if (riscv_memmodel_needs_amo_acquire ((enum memmodel
) INTVAL (op
)))
3177 fputs (".aq", file
);
3181 if (riscv_memmodel_needs_release_fence ((enum memmodel
) INTVAL (op
)))
3182 fputs ("fence iorw,ow; ", file
);
3194 if (letter
&& letter
!= 'z')
3195 output_operand_lossage ("invalid use of '%%%c'", letter
);
3196 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
3200 if (letter
&& letter
!= 'z')
3201 output_operand_lossage ("invalid use of '%%%c'", letter
);
3203 output_address (mode
, XEXP (op
, 0));
3207 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
3208 fputs (reg_names
[GP_REG_FIRST
], file
);
3209 else if (letter
&& letter
!= 'z')
3210 output_operand_lossage ("invalid use of '%%%c'", letter
);
3212 output_addr_const (file
, riscv_strip_unspec_address (op
));
3218 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3221 riscv_print_operand_address (FILE *file
, machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3223 struct riscv_address_info addr
;
3225 if (riscv_classify_address (&addr
, x
, word_mode
, true))
3229 riscv_print_operand (file
, addr
.offset
, 0);
3230 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3233 case ADDRESS_LO_SUM
:
3234 riscv_print_operand_reloc (file
, addr
.offset
, false);
3235 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3238 case ADDRESS_CONST_INT
:
3239 output_addr_const (file
, x
);
3240 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
3243 case ADDRESS_SYMBOLIC
:
3244 output_addr_const (file
, riscv_strip_unspec_address (x
));
3251 riscv_size_ok_for_small_data_p (int size
)
3253 return g_switch_value
&& IN_RANGE (size
, 1, g_switch_value
);
3256 /* Return true if EXP should be placed in the small data section. */
3259 riscv_in_small_data_p (const_tree x
)
3261 if (TREE_CODE (x
) == STRING_CST
|| TREE_CODE (x
) == FUNCTION_DECL
)
3264 if (TREE_CODE (x
) == VAR_DECL
&& DECL_SECTION_NAME (x
))
3266 const char *sec
= DECL_SECTION_NAME (x
);
3267 return strcmp (sec
, ".sdata") == 0 || strcmp (sec
, ".sbss") == 0;
3270 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x
)));
3273 /* Switch to the appropriate section for output of DECL. */
3276 riscv_select_section (tree decl
, int reloc
,
3277 unsigned HOST_WIDE_INT align
)
3279 switch (categorize_decl_for_section (decl
, reloc
))
3281 case SECCAT_SRODATA
:
3282 return get_named_section (decl
, ".srodata", reloc
);
3285 return default_elf_select_section (decl
, reloc
, align
);
3289 /* Return a section for X, handling small data. */
3292 riscv_elf_select_rtx_section (machine_mode mode
, rtx x
,
3293 unsigned HOST_WIDE_INT align
)
3295 section
*s
= default_elf_select_rtx_section (mode
, x
, align
);
3297 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode
)))
3299 if (strncmp (s
->named
.name
, ".rodata.cst", strlen (".rodata.cst")) == 0)
3301 /* Rename .rodata.cst* to .srodata.cst*. */
3302 char *name
= (char *) alloca (strlen (s
->named
.name
) + 2);
3303 sprintf (name
, ".s%s", s
->named
.name
+ 1);
3304 return get_section (name
, s
->named
.common
.flags
, NULL
);
3307 if (s
== data_section
)
3308 return sdata_section
;
3314 /* Make the last instruction frame-related and note that it performs
3315 the operation described by FRAME_PATTERN. */
3318 riscv_set_frame_expr (rtx frame_pattern
)
3322 insn
= get_last_insn ();
3323 RTX_FRAME_RELATED_P (insn
) = 1;
3324 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3329 /* Return a frame-related rtx that stores REG at MEM.
3330 REG must be a single register. */
3333 riscv_frame_set (rtx mem
, rtx reg
)
3335 rtx set
= gen_rtx_SET (mem
, reg
);
3336 RTX_FRAME_RELATED_P (set
) = 1;
3340 /* Return true if the current function must save register REGNO. */
3343 riscv_save_reg_p (unsigned int regno
)
3345 bool call_saved
= !global_regs
[regno
] && !call_used_regs
[regno
];
3346 bool might_clobber
= crtl
->saves_all_registers
3347 || df_regs_ever_live_p (regno
);
3349 if (call_saved
&& might_clobber
)
3352 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
3355 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
3358 /* If this is an interrupt handler, then must save extra registers. */
3359 if (cfun
->machine
->interrupt_handler_p
)
3361 /* zero register is always zero. */
3362 if (regno
== GP_REG_FIRST
)
3365 /* The function will return the stack pointer to its original value. */
3366 if (regno
== STACK_POINTER_REGNUM
)
3369 /* By convention, we assume that gp and tp are safe. */
3370 if (regno
== GP_REGNUM
|| regno
== THREAD_POINTER_REGNUM
)
3373 /* We must save every register used in this function. If this is not a
3374 leaf function, then we must save all temporary registers. */
3375 if (df_regs_ever_live_p (regno
)
3376 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
3383 /* Determine whether to call GPR save/restore routines. */
3385 riscv_use_save_libcall (const struct riscv_frame_info
*frame
)
3387 if (!TARGET_SAVE_RESTORE
|| crtl
->calls_eh_return
|| frame_pointer_needed
3388 || cfun
->machine
->interrupt_handler_p
)
3391 return frame
->save_libcall_adjustment
!= 0;
3394 /* Determine which GPR save/restore routine to call. */
3397 riscv_save_libcall_count (unsigned mask
)
3399 for (unsigned n
= GP_REG_LAST
; n
> GP_REG_FIRST
; n
--)
3400 if (BITSET_P (mask
, n
))
3401 return CALLEE_SAVED_REG_NUMBER (n
) + 1;
3405 /* Populate the current function's riscv_frame_info structure.
3407 RISC-V stack frames grown downward. High addresses are at the top.
3409 +-------------------------------+
3411 | incoming stack arguments |
3413 +-------------------------------+ <-- incoming stack pointer
3415 | callee-allocated save area |
3416 | for arguments that are |
3417 | split between registers and |
3420 +-------------------------------+ <-- arg_pointer_rtx
3422 | callee-allocated save area |
3423 | for register varargs |
3425 +-------------------------------+ <-- hard_frame_pointer_rtx;
3426 | | stack_pointer_rtx + gp_sp_offset
3427 | GPR save area | + UNITS_PER_WORD
3429 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3430 | | + UNITS_PER_HWVALUE
3433 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3437 P +-------------------------------+
3439 | outgoing stack arguments |
3441 +-------------------------------+ <-- stack_pointer_rtx
3443 Dynamic stack allocations such as alloca insert data at point P.
3444 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3445 hard_frame_pointer_rtx unchanged. */
3447 static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info
*frame
);
3450 riscv_compute_frame_info (void)
3452 struct riscv_frame_info
*frame
;
3453 HOST_WIDE_INT offset
;
3454 bool interrupt_save_t1
= false;
3455 unsigned int regno
, i
, num_x_saved
= 0, num_f_saved
= 0;
3457 frame
= &cfun
->machine
->frame
;
3459 /* In an interrupt function, if we have a large frame, then we need to
3460 save/restore t1. We check for this before clearing the frame struct. */
3461 if (cfun
->machine
->interrupt_handler_p
)
3463 HOST_WIDE_INT step1
= riscv_first_stack_step (frame
);
3464 if (! SMALL_OPERAND (frame
->total_size
- step1
))
3465 interrupt_save_t1
= true;
3468 memset (frame
, 0, sizeof (*frame
));
3470 if (!cfun
->machine
->naked_p
)
3472 /* Find out which GPRs we need to save. */
3473 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3474 if (riscv_save_reg_p (regno
)
3475 || (interrupt_save_t1
&& (regno
== T1_REGNUM
)))
3476 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3478 /* If this function calls eh_return, we must also save and restore the
3479 EH data registers. */
3480 if (crtl
->calls_eh_return
)
3481 for (i
= 0; (regno
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
; i
++)
3482 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3484 /* Find out which FPRs we need to save. This loop must iterate over
3485 the same space as its companion in riscv_for_each_saved_reg. */
3486 if (TARGET_HARD_FLOAT
)
3487 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3488 if (riscv_save_reg_p (regno
))
3489 frame
->fmask
|= 1 << (regno
- FP_REG_FIRST
), num_f_saved
++;
3492 /* At the bottom of the frame are any outgoing stack arguments. */
3493 offset
= RISCV_STACK_ALIGN (crtl
->outgoing_args_size
);
3494 /* Next are local stack variables. */
3495 offset
+= RISCV_STACK_ALIGN (get_frame_size ());
3496 /* The virtual frame pointer points above the local variables. */
3497 frame
->frame_pointer_offset
= offset
;
3498 /* Next are the callee-saved FPRs. */
3500 offset
+= RISCV_STACK_ALIGN (num_f_saved
* UNITS_PER_FP_REG
);
3501 frame
->fp_sp_offset
= offset
- UNITS_PER_FP_REG
;
3502 /* Next are the callee-saved GPRs. */
3505 unsigned x_save_size
= RISCV_STACK_ALIGN (num_x_saved
* UNITS_PER_WORD
);
3506 unsigned num_save_restore
= 1 + riscv_save_libcall_count (frame
->mask
);
3508 /* Only use save/restore routines if they don't alter the stack size. */
3509 if (RISCV_STACK_ALIGN (num_save_restore
* UNITS_PER_WORD
) == x_save_size
)
3511 /* Libcall saves/restores 3 registers at once, so we need to
3512 allocate 12 bytes for callee-saved register. */
3514 x_save_size
= 3 * UNITS_PER_WORD
;
3516 frame
->save_libcall_adjustment
= x_save_size
;
3519 offset
+= x_save_size
;
3521 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
3522 /* The hard frame pointer points above the callee-saved GPRs. */
3523 frame
->hard_frame_pointer_offset
= offset
;
3524 /* Above the hard frame pointer is the callee-allocated varags save area. */
3525 offset
+= RISCV_STACK_ALIGN (cfun
->machine
->varargs_size
);
3526 /* Next is the callee-allocated area for pretend stack arguments. */
3527 offset
+= RISCV_STACK_ALIGN (crtl
->args
.pretend_args_size
);
3528 /* Arg pointer must be below pretend args, but must be above alignment
3530 frame
->arg_pointer_offset
= offset
- crtl
->args
.pretend_args_size
;
3531 frame
->total_size
= offset
;
3532 /* Next points the incoming stack pointer and any incoming arguments. */
3534 /* Only use save/restore routines when the GPRs are atop the frame. */
3535 if (frame
->hard_frame_pointer_offset
!= frame
->total_size
)
3536 frame
->save_libcall_adjustment
= 0;
3539 /* Make sure that we're not trying to eliminate to the wrong hard frame
3543 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
3545 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
3548 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
3549 or argument pointer. TO is either the stack pointer or hard frame
3553 riscv_initial_elimination_offset (int from
, int to
)
3555 HOST_WIDE_INT src
, dest
;
3557 riscv_compute_frame_info ();
3559 if (to
== HARD_FRAME_POINTER_REGNUM
)
3560 dest
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
3561 else if (to
== STACK_POINTER_REGNUM
)
3562 dest
= 0; /* The stack pointer is the base of all offsets, hence 0. */
3566 if (from
== FRAME_POINTER_REGNUM
)
3567 src
= cfun
->machine
->frame
.frame_pointer_offset
;
3568 else if (from
== ARG_POINTER_REGNUM
)
3569 src
= cfun
->machine
->frame
.arg_pointer_offset
;
3576 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
3580 riscv_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
3585 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
3588 /* Emit code to change the current function's return address to
3589 ADDRESS. SCRATCH is available as a scratch register, if needed.
3590 ADDRESS and SCRATCH are both word-mode GPRs. */
3593 riscv_set_return_address (rtx address
, rtx scratch
)
3597 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
3598 slot_address
= riscv_add_offset (scratch
, stack_pointer_rtx
,
3599 cfun
->machine
->frame
.gp_sp_offset
);
3600 riscv_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
3603 /* A function to save or store a register. The first argument is the
3604 register and the second is the stack slot. */
3605 typedef void (*riscv_save_restore_fn
) (rtx
, rtx
);
3607 /* Use FN to save or restore register REGNO. MODE is the register's
3608 mode and OFFSET is the offset of its save slot from the current
3612 riscv_save_restore_reg (machine_mode mode
, int regno
,
3613 HOST_WIDE_INT offset
, riscv_save_restore_fn fn
)
3617 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
, offset
));
3618 fn (gen_rtx_REG (mode
, regno
), mem
);
3621 /* Call FN for each register that is saved by the current function.
3622 SP_OFFSET is the offset of the current stack pointer from the start
3626 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset
, riscv_save_restore_fn fn
,
3627 bool epilogue
, bool maybe_eh_return
)
3629 HOST_WIDE_INT offset
;
3631 /* Save the link register and s-registers. */
3632 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
3633 for (unsigned int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3634 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3636 bool handle_reg
= TRUE
;
3638 /* If this is a normal return in a function that calls the eh_return
3639 builtin, then do not restore the eh return data registers as that
3640 would clobber the return value. But we do still need to save them
3641 in the prologue, and restore them for an exception return, so we
3642 need special handling here. */
3643 if (epilogue
&& !maybe_eh_return
&& crtl
->calls_eh_return
)
3645 unsigned int i
, regnum
;
3647 for (i
= 0; (regnum
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
;
3649 if (regno
== regnum
)
3657 riscv_save_restore_reg (word_mode
, regno
, offset
, fn
);
3658 offset
-= UNITS_PER_WORD
;
3661 /* This loop must iterate over the same space as its companion in
3662 riscv_compute_frame_info. */
3663 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
3664 for (unsigned int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3665 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
3667 machine_mode mode
= TARGET_DOUBLE_FLOAT
? DFmode
: SFmode
;
3669 riscv_save_restore_reg (mode
, regno
, offset
, fn
);
3670 offset
-= GET_MODE_SIZE (mode
);
3674 /* Save register REG to MEM. Make the instruction frame-related. */
3677 riscv_save_reg (rtx reg
, rtx mem
)
3679 riscv_emit_move (mem
, reg
);
3680 riscv_set_frame_expr (riscv_frame_set (mem
, reg
));
3683 /* Restore register REG from MEM. */
3686 riscv_restore_reg (rtx reg
, rtx mem
)
3688 rtx insn
= riscv_emit_move (reg
, mem
);
3689 rtx dwarf
= NULL_RTX
;
3690 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3692 if (epilogue_cfa_sp_offset
&& REGNO (reg
) == HARD_FRAME_POINTER_REGNUM
)
3694 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3695 GEN_INT (epilogue_cfa_sp_offset
));
3696 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3699 REG_NOTES (insn
) = dwarf
;
3700 RTX_FRAME_RELATED_P (insn
) = 1;
3703 /* Return the code to invoke the GPR save routine. */
3706 riscv_output_gpr_save (unsigned mask
)
3709 unsigned n
= riscv_save_libcall_count (mask
);
3711 ssize_t bytes
= snprintf (s
, sizeof (s
), "call\tt0,__riscv_save_%u", n
);
3712 gcc_assert ((size_t) bytes
< sizeof (s
));
3717 /* For stack frames that can't be allocated with a single ADDI instruction,
3718 compute the best value to initially allocate. It must at a minimum
3719 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
3720 try to pick a value that will allow compression of the register saves
3721 without adding extra instructions. */
3723 static HOST_WIDE_INT
3724 riscv_first_stack_step (struct riscv_frame_info
*frame
)
3726 if (SMALL_OPERAND (frame
->total_size
))
3727 return frame
->total_size
;
3729 HOST_WIDE_INT min_first_step
=
3730 RISCV_STACK_ALIGN (frame
->total_size
- frame
->fp_sp_offset
);
3731 HOST_WIDE_INT max_first_step
= IMM_REACH
/ 2 - PREFERRED_STACK_BOUNDARY
/ 8;
3732 HOST_WIDE_INT min_second_step
= frame
->total_size
- max_first_step
;
3733 gcc_assert (min_first_step
<= max_first_step
);
3735 /* As an optimization, use the least-significant bits of the total frame
3736 size, so that the second adjustment step is just LUI + ADD. */
3737 if (!SMALL_OPERAND (min_second_step
)
3738 && frame
->total_size
% IMM_REACH
< IMM_REACH
/ 2
3739 && frame
->total_size
% IMM_REACH
>= min_first_step
)
3740 return frame
->total_size
% IMM_REACH
;
3744 /* If we need two subtracts, and one is small enough to allow compressed
3745 loads and stores, then put that one first. */
3746 if (IN_RANGE (min_second_step
, 0,
3747 (TARGET_64BIT
? SDSP_REACH
: SWSP_REACH
)))
3748 return MAX (min_second_step
, min_first_step
);
3750 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
3751 with the minimum first step, so that we can get compressed loads and
3753 else if (!SMALL_OPERAND (min_second_step
))
3754 return min_first_step
;
3757 return max_first_step
;
3761 riscv_adjust_libcall_cfi_prologue ()
3763 rtx dwarf
= NULL_RTX
;
3764 rtx adjust_sp_rtx
, reg
, mem
, insn
;
3765 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3768 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3769 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3771 /* The save order is ra, s0, s1, s2 to s11. */
3772 if (regno
== RETURN_ADDR_REGNUM
)
3773 offset
= saved_size
- UNITS_PER_WORD
;
3774 else if (regno
== S0_REGNUM
)
3775 offset
= saved_size
- UNITS_PER_WORD
* 2;
3776 else if (regno
== S1_REGNUM
)
3777 offset
= saved_size
- UNITS_PER_WORD
* 3;
3779 offset
= saved_size
- ((regno
- S2_REGNUM
+ 4) * UNITS_PER_WORD
);
3781 reg
= gen_rtx_REG (SImode
, regno
);
3782 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3786 insn
= gen_rtx_SET (mem
, reg
);
3787 dwarf
= alloc_reg_note (REG_CFA_OFFSET
, insn
, dwarf
);
3790 /* Debug info for adjust sp. */
3791 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3792 stack_pointer_rtx
, GEN_INT (-saved_size
));
3793 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
3799 riscv_emit_stack_tie (void)
3801 if (Pmode
== SImode
)
3802 emit_insn (gen_stack_tiesi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3804 emit_insn (gen_stack_tiedi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3807 /* Expand the "prologue" pattern. */
3810 riscv_expand_prologue (void)
3812 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
3813 HOST_WIDE_INT size
= frame
->total_size
;
3814 unsigned mask
= frame
->mask
;
3817 if (flag_stack_usage_info
)
3818 current_function_static_stack_size
= size
;
3820 if (cfun
->machine
->naked_p
)
3823 /* When optimizing for size, call a subroutine to save the registers. */
3824 if (riscv_use_save_libcall (frame
))
3826 rtx dwarf
= NULL_RTX
;
3827 dwarf
= riscv_adjust_libcall_cfi_prologue ();
3829 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
3830 size
-= frame
->save_libcall_adjustment
;
3831 insn
= emit_insn (gen_gpr_save (GEN_INT (mask
)));
3833 RTX_FRAME_RELATED_P (insn
) = 1;
3834 REG_NOTES (insn
) = dwarf
;
3837 /* Save the registers. */
3838 if ((frame
->mask
| frame
->fmask
) != 0)
3840 HOST_WIDE_INT step1
= MIN (size
, riscv_first_stack_step (frame
));
3842 insn
= gen_add3_insn (stack_pointer_rtx
,
3845 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3847 riscv_for_each_saved_reg (size
, riscv_save_reg
, false, false);
3850 frame
->mask
= mask
; /* Undo the above fib. */
3852 /* Set up the frame pointer, if we're using one. */
3853 if (frame_pointer_needed
)
3855 insn
= gen_add3_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
,
3856 GEN_INT (frame
->hard_frame_pointer_offset
- size
));
3857 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3859 riscv_emit_stack_tie ();
3862 /* Allocate the rest of the frame. */
3865 if (SMALL_OPERAND (-size
))
3867 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3869 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3873 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), GEN_INT (-size
));
3874 emit_insn (gen_add3_insn (stack_pointer_rtx
,
3876 RISCV_PROLOGUE_TEMP (Pmode
)));
3878 /* Describe the effect of the previous instructions. */
3879 insn
= plus_constant (Pmode
, stack_pointer_rtx
, -size
);
3880 insn
= gen_rtx_SET (stack_pointer_rtx
, insn
);
3881 riscv_set_frame_expr (insn
);
3887 riscv_adjust_libcall_cfi_epilogue ()
3889 rtx dwarf
= NULL_RTX
;
3890 rtx adjust_sp_rtx
, reg
;
3891 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3893 /* Debug info for adjust sp. */
3894 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3895 stack_pointer_rtx
, GEN_INT (saved_size
));
3896 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
3899 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3900 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3902 reg
= gen_rtx_REG (SImode
, regno
);
3903 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3909 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
3910 style says which. */
3913 riscv_expand_epilogue (int style
)
3915 /* Split the frame into two. STEP1 is the amount of stack we should
3916 deallocate before restoring the registers. STEP2 is the amount we
3917 should deallocate afterwards.
3919 Start off by assuming that no registers need to be restored. */
3920 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
3921 unsigned mask
= frame
->mask
;
3922 HOST_WIDE_INT step1
= frame
->total_size
;
3923 HOST_WIDE_INT step2
= 0;
3924 bool use_restore_libcall
= ((style
== NORMAL_RETURN
)
3925 && riscv_use_save_libcall (frame
));
3926 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3929 /* We need to add memory barrier to prevent read from deallocated stack. */
3930 bool need_barrier_p
= (get_frame_size ()
3931 + cfun
->machine
->frame
.arg_pointer_offset
) != 0;
3933 if (cfun
->machine
->naked_p
)
3935 gcc_assert (style
== NORMAL_RETURN
);
3937 emit_jump_insn (gen_return ());
3942 if ((style
== NORMAL_RETURN
) && riscv_can_use_return_insn ())
3944 emit_jump_insn (gen_return ());
3948 /* Reset the epilogue cfa info before starting to emit the epilogue. */
3949 epilogue_cfa_sp_offset
= 0;
3951 /* Move past any dynamic stack allocations. */
3952 if (cfun
->calls_alloca
)
3954 /* Emit a barrier to prevent loads from a deallocated stack. */
3955 riscv_emit_stack_tie ();
3956 need_barrier_p
= false;
3958 rtx adjust
= GEN_INT (-frame
->hard_frame_pointer_offset
);
3959 if (!SMALL_OPERAND (INTVAL (adjust
)))
3961 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
3962 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
3966 gen_add3_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
,
3969 rtx dwarf
= NULL_RTX
;
3970 rtx cfa_adjust_value
= gen_rtx_PLUS (
3971 Pmode
, hard_frame_pointer_rtx
,
3972 GEN_INT (-frame
->hard_frame_pointer_offset
));
3973 rtx cfa_adjust_rtx
= gen_rtx_SET (stack_pointer_rtx
, cfa_adjust_value
);
3974 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, cfa_adjust_rtx
, dwarf
);
3975 RTX_FRAME_RELATED_P (insn
) = 1;
3977 REG_NOTES (insn
) = dwarf
;
3980 /* If we need to restore registers, deallocate as much stack as
3981 possible in the second step without going out of range. */
3982 if ((frame
->mask
| frame
->fmask
) != 0)
3984 step2
= riscv_first_stack_step (frame
);
3988 /* Set TARGET to BASE + STEP1. */
3991 /* Emit a barrier to prevent loads from a deallocated stack. */
3992 riscv_emit_stack_tie ();
3993 need_barrier_p
= false;
3995 /* Get an rtx for STEP1 that we can add to BASE. */
3996 rtx adjust
= GEN_INT (step1
);
3997 if (!SMALL_OPERAND (step1
))
3999 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4000 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4004 gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
, adjust
));
4006 rtx dwarf
= NULL_RTX
;
4007 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4010 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4011 RTX_FRAME_RELATED_P (insn
) = 1;
4013 REG_NOTES (insn
) = dwarf
;
4015 else if (frame_pointer_needed
)
4017 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
4019 epilogue_cfa_sp_offset
= step2
;
4022 if (use_restore_libcall
)
4023 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4025 /* Restore the registers. */
4026 riscv_for_each_saved_reg (frame
->total_size
- step2
, riscv_restore_reg
,
4027 true, style
== EXCEPTION_RETURN
);
4029 if (use_restore_libcall
)
4031 frame
->mask
= mask
; /* Undo the above fib. */
4032 gcc_assert (step2
>= frame
->save_libcall_adjustment
);
4033 step2
-= frame
->save_libcall_adjustment
;
4037 riscv_emit_stack_tie ();
4039 /* Deallocate the final bit of the frame. */
4042 insn
= emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4045 rtx dwarf
= NULL_RTX
;
4046 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4048 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4049 RTX_FRAME_RELATED_P (insn
) = 1;
4051 REG_NOTES (insn
) = dwarf
;
4054 if (use_restore_libcall
)
4056 rtx dwarf
= riscv_adjust_libcall_cfi_epilogue ();
4057 insn
= emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask
))));
4058 RTX_FRAME_RELATED_P (insn
) = 1;
4059 REG_NOTES (insn
) = dwarf
;
4061 emit_jump_insn (gen_gpr_restore_return (ra
));
4065 /* Add in the __builtin_eh_return stack adjustment. */
4066 if ((style
== EXCEPTION_RETURN
) && crtl
->calls_eh_return
)
4067 emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4068 EH_RETURN_STACKADJ_RTX
));
4070 /* Return from interrupt. */
4071 if (cfun
->machine
->interrupt_handler_p
)
4073 enum riscv_privilege_levels mode
= cfun
->machine
->interrupt_mode
;
4075 gcc_assert (mode
!= UNKNOWN_MODE
);
4077 if (mode
== MACHINE_MODE
)
4078 emit_jump_insn (gen_riscv_mret ());
4079 else if (mode
== SUPERVISOR_MODE
)
4080 emit_jump_insn (gen_riscv_sret ());
4082 emit_jump_insn (gen_riscv_uret ());
4084 else if (style
!= SIBCALL_RETURN
)
4085 emit_jump_insn (gen_simple_return_internal (ra
));
4088 /* Implement EPILOGUE_USES. */
4091 riscv_epilogue_uses (unsigned int regno
)
4093 if (regno
== RETURN_ADDR_REGNUM
)
4096 if (epilogue_completed
&& cfun
->machine
->interrupt_handler_p
)
4098 /* An interrupt function restores temp regs, so we must indicate that
4099 they are live at function end. */
4100 if (df_regs_ever_live_p (regno
)
4101 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
4108 /* Return nonzero if this function is known to have a null epilogue.
4109 This allows the optimizer to omit jumps to jumps if no stack
4113 riscv_can_use_return_insn (void)
4115 return (reload_completed
&& cfun
->machine
->frame
.total_size
== 0
4116 && ! cfun
->machine
->interrupt_handler_p
);
4119 /* Given that there exists at least one variable that is set (produced)
4120 by OUT_INSN and read (consumed) by IN_INSN, return true iff
4121 IN_INSN represents one or more memory store operations and none of
4122 the variables set by OUT_INSN is used by IN_INSN as the address of a
4123 store operation. If either IN_INSN or OUT_INSN does not represent
4124 a "single" RTL SET expression (as loosely defined by the
4125 implementation of the single_set function) or a PARALLEL with only
4126 SETs, CLOBBERs, and USEs inside, this function returns false.
4128 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
4129 conditions that result in assertion failures in the generic
4130 store_data_bypass_p function and returns FALSE in such cases.
4132 This is required to make -msave-restore work with the sifive-7
4133 pipeline description. */
4136 riscv_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
4138 rtx out_set
, in_set
;
4139 rtx out_pat
, in_pat
;
4140 rtx out_exp
, in_exp
;
4143 in_set
= single_set (in_insn
);
4146 if (MEM_P (SET_DEST (in_set
)))
4148 out_set
= single_set (out_insn
);
4151 out_pat
= PATTERN (out_insn
);
4152 if (GET_CODE (out_pat
) == PARALLEL
)
4154 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
4156 out_exp
= XVECEXP (out_pat
, 0, i
);
4157 if ((GET_CODE (out_exp
) == CLOBBER
)
4158 || (GET_CODE (out_exp
) == USE
))
4160 else if (GET_CODE (out_exp
) != SET
)
4169 in_pat
= PATTERN (in_insn
);
4170 if (GET_CODE (in_pat
) != PARALLEL
)
4173 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
4175 in_exp
= XVECEXP (in_pat
, 0, i
);
4176 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
4178 else if (GET_CODE (in_exp
) != SET
)
4181 if (MEM_P (SET_DEST (in_exp
)))
4183 out_set
= single_set (out_insn
);
4186 out_pat
= PATTERN (out_insn
);
4187 if (GET_CODE (out_pat
) != PARALLEL
)
4189 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
4191 out_exp
= XVECEXP (out_pat
, 0, j
);
4192 if ((GET_CODE (out_exp
) == CLOBBER
)
4193 || (GET_CODE (out_exp
) == USE
))
4195 else if (GET_CODE (out_exp
) != SET
)
4203 return store_data_bypass_p (out_insn
, in_insn
);
4206 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4208 When floating-point registers are wider than integer ones, moves between
4209 them must go through memory. */
4212 riscv_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
4215 return (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4216 && (class1
== FP_REGS
) != (class2
== FP_REGS
));
4219 /* Implement TARGET_REGISTER_MOVE_COST. */
4222 riscv_register_move_cost (machine_mode mode
,
4223 reg_class_t from
, reg_class_t to
)
4225 return riscv_secondary_memory_needed (mode
, from
, to
) ? 8 : 2;
4228 /* Implement TARGET_HARD_REGNO_NREGS. */
4231 riscv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
4233 if (FP_REG_P (regno
))
4234 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_REG
- 1) / UNITS_PER_FP_REG
;
4236 /* All other registers are word-sized. */
4237 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4240 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4243 riscv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4245 unsigned int nregs
= riscv_hard_regno_nregs (regno
, mode
);
4247 if (GP_REG_P (regno
))
4249 if (!GP_REG_P (regno
+ nregs
- 1))
4252 else if (FP_REG_P (regno
))
4254 if (!FP_REG_P (regno
+ nregs
- 1))
4257 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4258 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4261 /* Only use callee-saved registers if a potential callee is guaranteed
4262 to spill the requisite width. */
4263 if (GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_REG
4264 || (!call_used_regs
[regno
]
4265 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_ARG
))
4271 /* Require same callee-savedness for all registers. */
4272 for (unsigned i
= 1; i
< nregs
; i
++)
4273 if (call_used_regs
[regno
] != call_used_regs
[regno
+ i
])
4279 /* Implement TARGET_MODES_TIEABLE_P.
4281 Don't allow floating-point modes to be tied, since type punning of
4282 single-precision and double-precision is implementation defined. */
4285 riscv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4287 return (mode1
== mode2
4288 || !(GET_MODE_CLASS (mode1
) == MODE_FLOAT
4289 && GET_MODE_CLASS (mode2
) == MODE_FLOAT
));
4292 /* Implement CLASS_MAX_NREGS. */
4294 static unsigned char
4295 riscv_class_max_nregs (reg_class_t rclass
, machine_mode mode
)
4297 if (reg_class_subset_p (FP_REGS
, rclass
))
4298 return riscv_hard_regno_nregs (FP_REG_FIRST
, mode
);
4300 if (reg_class_subset_p (GR_REGS
, rclass
))
4301 return riscv_hard_regno_nregs (GP_REG_FIRST
, mode
);
4306 /* Implement TARGET_MEMORY_MOVE_COST. */
4309 riscv_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
4311 return (tune_info
->memory_cost
4312 + memory_move_secondary_cost (mode
, rclass
, in
));
4315 /* Return the number of instructions that can be issued per cycle. */
4318 riscv_issue_rate (void)
4320 return tune_info
->issue_rate
;
4323 /* Auxiliary function to emit RISC-V ELF attribute. */
4325 riscv_emit_attribute ()
4327 fprintf (asm_out_file
, "\t.attribute arch, \"%s\"\n",
4328 riscv_arch_str ().c_str ());
4330 fprintf (asm_out_file
, "\t.attribute unaligned_access, %d\n",
4331 TARGET_STRICT_ALIGN
? 0 : 1);
4333 fprintf (asm_out_file
, "\t.attribute stack_align, %d\n",
4334 riscv_stack_boundary
/ 8);
4337 /* Implement TARGET_ASM_FILE_START. */
4340 riscv_file_start (void)
4342 default_file_start ();
4344 /* Instruct GAS to generate position-[in]dependent code. */
4345 fprintf (asm_out_file
, "\t.option %spic\n", (flag_pic
? "" : "no"));
4347 /* If the user specifies "-mno-relax" on the command line then disable linker
4348 relaxation in the assembler. */
4350 fprintf (asm_out_file
, "\t.option norelax\n");
4352 if (riscv_emit_attribute_p
)
4353 riscv_emit_attribute ();
4356 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4357 in order to avoid duplicating too much logic from elsewhere. */
4360 riscv_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
4361 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4364 rtx this_rtx
, temp1
, temp2
, fnaddr
;
4367 /* Pretend to be a post-reload pass while generating rtl. */
4368 reload_completed
= 1;
4370 /* Mark the end of the (empty) prologue. */
4371 emit_note (NOTE_INSN_PROLOGUE_END
);
4373 /* Determine if we can use a sibcall to call FUNCTION directly. */
4374 fnaddr
= gen_rtx_MEM (FUNCTION_MODE
, XEXP (DECL_RTL (function
), 0));
4376 /* We need two temporary registers in some cases. */
4377 temp1
= gen_rtx_REG (Pmode
, RISCV_PROLOGUE_TEMP_REGNUM
);
4378 temp2
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
4380 /* Find out which register contains the "this" pointer. */
4381 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
4382 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
4384 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
4386 /* Add DELTA to THIS_RTX. */
4389 rtx offset
= GEN_INT (delta
);
4390 if (!SMALL_OPERAND (delta
))
4392 riscv_emit_move (temp1
, offset
);
4395 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
4398 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4399 if (vcall_offset
!= 0)
4403 /* Set TEMP1 to *THIS_RTX. */
4404 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
4406 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4407 addr
= riscv_add_offset (temp2
, temp1
, vcall_offset
);
4409 /* Load the offset and add it to THIS_RTX. */
4410 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
4411 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
4414 /* Jump to the target function. */
4415 insn
= emit_call_insn (gen_sibcall (fnaddr
, const0_rtx
, NULL
, const0_rtx
));
4416 SIBLING_CALL_P (insn
) = 1;
4418 /* Run just enough of rest_of_compilation. This sequence was
4419 "borrowed" from alpha.c. */
4420 insn
= get_insns ();
4421 split_all_insns_noflow ();
4422 shorten_branches (insn
);
4423 final_start_function (insn
, file
, 1);
4424 final (insn
, file
, 1);
4425 final_end_function ();
4427 /* Clean up the vars set above. Note that final_end_function resets
4428 the global pointer for us. */
4429 reload_completed
= 0;
4432 /* Allocate a chunk of memory for per-function machine-dependent data. */
4434 static struct machine_function
*
4435 riscv_init_machine_status (void)
4437 return ggc_cleared_alloc
<machine_function
> ();
4440 /* Implement TARGET_OPTION_OVERRIDE. */
4443 riscv_option_override (void)
4445 const struct riscv_cpu_info
*cpu
;
4447 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4448 SUBTARGET_OVERRIDE_OPTIONS
;
4451 flag_pcc_struct_return
= 0;
4456 /* The presence of the M extension implies that division instructions
4457 are present, so include them unless explicitly disabled. */
4458 if (TARGET_MUL
&& (target_flags_explicit
& MASK_DIV
) == 0)
4459 target_flags
|= MASK_DIV
;
4460 else if (!TARGET_MUL
&& TARGET_DIV
)
4461 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
4463 /* Likewise floating-point division and square root. */
4464 if (TARGET_HARD_FLOAT
&& (target_flags_explicit
& MASK_FDIV
) == 0)
4465 target_flags
|= MASK_FDIV
;
4467 /* Handle -mtune. */
4468 cpu
= riscv_parse_cpu (riscv_tune_string
? riscv_tune_string
:
4469 RISCV_TUNE_STRING_DEFAULT
);
4470 riscv_microarchitecture
= cpu
->microarchitecture
;
4471 tune_info
= optimize_size
? &optimize_size_tune_info
: cpu
->tune_info
;
4473 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
4474 for size. For architectures that trap and emulate unaligned accesses,
4475 the performance cost is too great, even for -Os. Similarly, if
4476 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
4477 riscv_slow_unaligned_access_p
= (cpu
->tune_info
->slow_unaligned_access
4478 || TARGET_STRICT_ALIGN
);
4479 if ((target_flags_explicit
& MASK_STRICT_ALIGN
) == 0
4480 && cpu
->tune_info
->slow_unaligned_access
)
4481 target_flags
|= MASK_STRICT_ALIGN
;
4483 /* If the user hasn't specified a branch cost, use the processor's
4485 if (riscv_branch_cost
== 0)
4486 riscv_branch_cost
= tune_info
->branch_cost
;
4488 /* Function to allocate machine-dependent function status. */
4489 init_machine_status
= &riscv_init_machine_status
;
4492 riscv_cmodel
= CM_PIC
;
4494 /* We get better code with explicit relocs for CM_MEDLOW, but
4495 worse code for the others (for now). Pick the best default. */
4496 if ((target_flags_explicit
& MASK_EXPLICIT_RELOCS
) == 0)
4497 if (riscv_cmodel
== CM_MEDLOW
)
4498 target_flags
|= MASK_EXPLICIT_RELOCS
;
4500 /* Require that the ISA supports the requested floating-point ABI. */
4501 if (UNITS_PER_FP_ARG
> (TARGET_HARD_FLOAT
? UNITS_PER_FP_REG
: 0))
4502 error ("requested ABI requires %<-march%> to subsume the %qc extension",
4503 UNITS_PER_FP_ARG
> 8 ? 'Q' : (UNITS_PER_FP_ARG
> 4 ? 'D' : 'F'));
4505 if (TARGET_RVE
&& riscv_abi
!= ABI_ILP32E
)
4506 error ("rv32e requires ilp32e ABI");
4508 /* We do not yet support ILP32 on RV64. */
4509 if (BITS_PER_WORD
!= POINTER_SIZE
)
4510 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE
);
4512 /* Validate -mpreferred-stack-boundary= value. */
4513 riscv_stack_boundary
= ABI_STACK_BOUNDARY
;
4514 if (riscv_preferred_stack_boundary_arg
)
4516 int min
= ctz_hwi (STACK_BOUNDARY
/ 8);
4519 if (!IN_RANGE (riscv_preferred_stack_boundary_arg
, min
, max
))
4520 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d",
4521 riscv_preferred_stack_boundary_arg
, min
, max
);
4523 riscv_stack_boundary
= 8 << riscv_preferred_stack_boundary_arg
;
4526 if (riscv_emit_attribute_p
< 0)
4527 #ifdef HAVE_AS_RISCV_ATTRIBUTE
4528 riscv_emit_attribute_p
= TARGET_RISCV_ATTRIBUTE
;
4530 riscv_emit_attribute_p
= 0;
4532 if (riscv_emit_attribute_p
)
4533 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"
4534 " [%<-mriscv-attribute%>]");
4538 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4541 riscv_conditional_register_usage (void)
4543 /* We have only x0~x15 on RV32E. */
4546 for (int r
= 16; r
<= 31; r
++)
4550 if (riscv_abi
== ABI_ILP32E
)
4552 for (int r
= 16; r
<= 31; r
++)
4553 call_used_regs
[r
] = 1;
4556 if (!TARGET_HARD_FLOAT
)
4558 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4559 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4562 /* In the soft-float ABI, there are no callee-saved FP registers. */
4563 if (UNITS_PER_FP_ARG
== 0)
4565 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4566 call_used_regs
[regno
] = 1;
4570 /* Return a register priority for hard reg REGNO. */
4573 riscv_register_priority (int regno
)
4575 /* Favor x8-x15/f8-f15 to improve the odds of RVC instruction selection. */
4576 if (TARGET_RVC
&& (IN_RANGE (regno
, GP_REG_FIRST
+ 8, GP_REG_FIRST
+ 15)
4577 || IN_RANGE (regno
, FP_REG_FIRST
+ 8, FP_REG_FIRST
+ 15)))
4583 /* Implement TARGET_TRAMPOLINE_INIT. */
4586 riscv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4588 rtx addr
, end_addr
, mem
;
4589 uint32_t trampoline
[4];
4591 HOST_WIDE_INT static_chain_offset
, target_function_offset
;
4593 /* Work out the offsets of the pointers from the start of the
4595 gcc_assert (ARRAY_SIZE (trampoline
) * 4 == TRAMPOLINE_CODE_SIZE
);
4597 /* Get pointers to the beginning and end of the code block. */
4598 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
4599 end_addr
= riscv_force_binary (Pmode
, PLUS
, addr
,
4600 GEN_INT (TRAMPOLINE_CODE_SIZE
));
4603 if (Pmode
== SImode
)
4605 chain_value
= force_reg (Pmode
, chain_value
);
4607 rtx target_function
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
4608 /* lui t2, hi(chain)
4610 addi t2, t2, lo(chain)
4613 unsigned HOST_WIDE_INT lui_hi_chain_code
, lui_hi_func_code
;
4614 unsigned HOST_WIDE_INT lo_chain_code
, lo_func_code
;
4616 rtx uimm_mask
= force_reg (SImode
, gen_int_mode (-IMM_REACH
, SImode
));
4619 rtx imm12_mask
= gen_reg_rtx (SImode
);
4620 emit_insn (gen_one_cmplsi2 (imm12_mask
, uimm_mask
));
4622 rtx fixup_value
= force_reg (SImode
, gen_int_mode (IMM_REACH
/2, SImode
));
4624 /* Gen lui t2, hi(chain). */
4625 rtx hi_chain
= riscv_force_binary (SImode
, PLUS
, chain_value
,
4627 hi_chain
= riscv_force_binary (SImode
, AND
, hi_chain
,
4629 lui_hi_chain_code
= OPCODE_LUI
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4630 rtx lui_hi_chain
= riscv_force_binary (SImode
, IOR
, hi_chain
,
4631 gen_int_mode (lui_hi_chain_code
, SImode
));
4633 mem
= adjust_address (m_tramp
, SImode
, 0);
4634 riscv_emit_move (mem
, lui_hi_chain
);
4636 /* Gen lui t1, hi(func). */
4637 rtx hi_func
= riscv_force_binary (SImode
, PLUS
, target_function
,
4639 hi_func
= riscv_force_binary (SImode
, AND
, hi_func
,
4641 lui_hi_func_code
= OPCODE_LUI
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
);
4642 rtx lui_hi_func
= riscv_force_binary (SImode
, IOR
, hi_func
,
4643 gen_int_mode (lui_hi_func_code
, SImode
));
4645 mem
= adjust_address (m_tramp
, SImode
, 1 * GET_MODE_SIZE (SImode
));
4646 riscv_emit_move (mem
, lui_hi_func
);
4648 /* Gen addi t2, t2, lo(chain). */
4649 rtx lo_chain
= riscv_force_binary (SImode
, AND
, chain_value
,
4651 lo_chain
= riscv_force_binary (SImode
, ASHIFT
, lo_chain
, GEN_INT (20));
4653 lo_chain_code
= OPCODE_ADDI
4654 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4655 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
);
4657 rtx addi_lo_chain
= riscv_force_binary (SImode
, IOR
, lo_chain
,
4658 force_reg (SImode
, GEN_INT (lo_chain_code
)));
4660 mem
= adjust_address (m_tramp
, SImode
, 2 * GET_MODE_SIZE (SImode
));
4661 riscv_emit_move (mem
, addi_lo_chain
);
4663 /* Gen jr r1, lo(func). */
4664 rtx lo_func
= riscv_force_binary (SImode
, AND
, target_function
,
4666 lo_func
= riscv_force_binary (SImode
, ASHIFT
, lo_func
, GEN_INT (20));
4668 lo_func_code
= OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4670 rtx jr_lo_func
= riscv_force_binary (SImode
, IOR
, lo_func
,
4671 force_reg (SImode
, GEN_INT (lo_func_code
)));
4673 mem
= adjust_address (m_tramp
, SImode
, 3 * GET_MODE_SIZE (SImode
));
4674 riscv_emit_move (mem
, jr_lo_func
);
4678 static_chain_offset
= TRAMPOLINE_CODE_SIZE
;
4679 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
4682 l[wd] t1, target_function_offset(t2)
4683 l[wd] t2, static_chain_offset(t2)
4686 trampoline
[0] = OPCODE_AUIPC
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4687 trampoline
[1] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4688 | (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
)
4689 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4690 | (target_function_offset
<< SHIFT_IMM
);
4691 trampoline
[2] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4692 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4693 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4694 | (static_chain_offset
<< SHIFT_IMM
);
4695 trampoline
[3] = OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4697 /* Copy the trampoline code. */
4698 for (i
= 0; i
< ARRAY_SIZE (trampoline
); i
++)
4700 mem
= adjust_address (m_tramp
, SImode
, i
* GET_MODE_SIZE (SImode
));
4701 riscv_emit_move (mem
, gen_int_mode (trampoline
[i
], SImode
));
4704 /* Set up the static chain pointer field. */
4705 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
4706 riscv_emit_move (mem
, chain_value
);
4708 /* Set up the target function field. */
4709 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
4710 riscv_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
4713 /* Flush the code part of the trampoline. */
4714 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
4715 emit_insn (gen_clear_cache (addr
, end_addr
));
4718 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
4721 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
4722 tree exp ATTRIBUTE_UNUSED
)
4724 /* Don't use sibcalls when use save-restore routine. */
4725 if (TARGET_SAVE_RESTORE
)
4728 /* Don't use sibcall for naked functions. */
4729 if (cfun
->machine
->naked_p
)
4732 /* Don't use sibcall for interrupt functions. */
4733 if (cfun
->machine
->interrupt_handler_p
)
4739 /* Get the intterupt type, return UNKNOWN_MODE if it's not
4740 interrupt function. */
4741 static enum riscv_privilege_levels
4742 riscv_get_interrupt_type (tree decl
)
4744 gcc_assert (decl
!= NULL_TREE
);
4746 if ((TREE_CODE(decl
) != FUNCTION_DECL
)
4747 || (!riscv_interrupt_type_p (TREE_TYPE (decl
))))
4748 return UNKNOWN_MODE
;
4751 = TREE_VALUE (lookup_attribute ("interrupt",
4752 TYPE_ATTRIBUTES (TREE_TYPE (decl
))));
4754 if (attr_args
&& TREE_CODE (TREE_VALUE (attr_args
)) != VOID_TYPE
)
4756 const char *string
= TREE_STRING_POINTER (TREE_VALUE (attr_args
));
4758 if (!strcmp (string
, "user"))
4760 else if (!strcmp (string
, "supervisor"))
4761 return SUPERVISOR_MODE
;
4762 else /* Must be "machine". */
4763 return MACHINE_MODE
;
4766 /* Interrupt attributes are machine mode by default. */
4767 return MACHINE_MODE
;
4770 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
4771 /* Sanity cheching for above function attributes. */
4773 riscv_set_current_function (tree decl
)
4775 if (decl
== NULL_TREE
4776 || current_function_decl
== NULL_TREE
4777 || current_function_decl
== error_mark_node
4779 || cfun
->machine
->attributes_checked_p
)
4782 cfun
->machine
->naked_p
= riscv_naked_function_p (decl
);
4783 cfun
->machine
->interrupt_handler_p
4784 = riscv_interrupt_type_p (TREE_TYPE (decl
));
4786 if (cfun
->machine
->naked_p
&& cfun
->machine
->interrupt_handler_p
)
4787 error ("function attributes %qs and %qs are mutually exclusive",
4788 "interrupt", "naked");
4790 if (cfun
->machine
->interrupt_handler_p
)
4792 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
4793 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
4795 if (TREE_CODE (ret
) != VOID_TYPE
)
4796 error ("%qs function cannot return a value", "interrupt");
4798 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
4799 error ("%qs function cannot have arguments", "interrupt");
4801 cfun
->machine
->interrupt_mode
= riscv_get_interrupt_type (decl
);
4803 gcc_assert (cfun
->machine
->interrupt_mode
!= UNKNOWN_MODE
);
4806 /* Don't print the above diagnostics more than once. */
4807 cfun
->machine
->attributes_checked_p
= 1;
4810 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
4812 riscv_merge_decl_attributes (tree olddecl
, tree newdecl
)
4814 tree combined_attrs
;
4816 enum riscv_privilege_levels old_interrupt_type
4817 = riscv_get_interrupt_type (olddecl
);
4818 enum riscv_privilege_levels new_interrupt_type
4819 = riscv_get_interrupt_type (newdecl
);
4821 /* Check old and new has same interrupt type. */
4822 if ((old_interrupt_type
!= UNKNOWN_MODE
)
4823 && (new_interrupt_type
!= UNKNOWN_MODE
)
4824 && (old_interrupt_type
!= new_interrupt_type
))
4825 error ("%qs function cannot have different intterupt type.", "interrupt");
4827 /* Create combined attributes. */
4828 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
4829 DECL_ATTRIBUTES (newdecl
));
4831 return combined_attrs
;
4834 /* Implement TARGET_CANNOT_COPY_INSN_P. */
4837 riscv_cannot_copy_insn_p (rtx_insn
*insn
)
4839 return recog_memoized (insn
) >= 0 && get_attr_cannot_copy (insn
);
4842 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
4845 riscv_slow_unaligned_access (machine_mode
, unsigned int)
4847 return riscv_slow_unaligned_access_p
;
4850 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
4853 riscv_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t rclass
)
4855 return !reg_classes_intersect_p (FP_REGS
, rclass
);
4859 /* Implement TARGET_CONSTANT_ALIGNMENT. */
4861 static HOST_WIDE_INT
4862 riscv_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
4864 if (TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
4865 return MAX (align
, BITS_PER_WORD
);
4869 /* Initialize the GCC target structure. */
4870 #undef TARGET_ASM_ALIGNED_HI_OP
4871 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
4872 #undef TARGET_ASM_ALIGNED_SI_OP
4873 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
4874 #undef TARGET_ASM_ALIGNED_DI_OP
4875 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
4877 #undef TARGET_OPTION_OVERRIDE
4878 #define TARGET_OPTION_OVERRIDE riscv_option_override
4880 #undef TARGET_LEGITIMIZE_ADDRESS
4881 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
4883 #undef TARGET_SCHED_ISSUE_RATE
4884 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
4886 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
4887 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
4889 #undef TARGET_SET_CURRENT_FUNCTION
4890 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
4892 #undef TARGET_REGISTER_MOVE_COST
4893 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
4894 #undef TARGET_MEMORY_MOVE_COST
4895 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
4896 #undef TARGET_RTX_COSTS
4897 #define TARGET_RTX_COSTS riscv_rtx_costs
4898 #undef TARGET_ADDRESS_COST
4899 #define TARGET_ADDRESS_COST riscv_address_cost
4901 #undef TARGET_ASM_FILE_START
4902 #define TARGET_ASM_FILE_START riscv_file_start
4903 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4904 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4906 #undef TARGET_EXPAND_BUILTIN_VA_START
4907 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
4909 #undef TARGET_PROMOTE_FUNCTION_MODE
4910 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
4912 #undef TARGET_RETURN_IN_MEMORY
4913 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
4915 #undef TARGET_ASM_OUTPUT_MI_THUNK
4916 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
4917 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
4918 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
4920 #undef TARGET_PRINT_OPERAND
4921 #define TARGET_PRINT_OPERAND riscv_print_operand
4922 #undef TARGET_PRINT_OPERAND_ADDRESS
4923 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
4925 #undef TARGET_SETUP_INCOMING_VARARGS
4926 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
4927 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
4928 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
4929 #undef TARGET_STRICT_ARGUMENT_NAMING
4930 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
4931 #undef TARGET_MUST_PASS_IN_STACK
4932 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
4933 #undef TARGET_PASS_BY_REFERENCE
4934 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
4935 #undef TARGET_ARG_PARTIAL_BYTES
4936 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
4937 #undef TARGET_FUNCTION_ARG
4938 #define TARGET_FUNCTION_ARG riscv_function_arg
4939 #undef TARGET_FUNCTION_ARG_ADVANCE
4940 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
4941 #undef TARGET_FUNCTION_ARG_BOUNDARY
4942 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
4944 /* The generic ELF target does not always have TLS support. */
4946 #undef TARGET_HAVE_TLS
4947 #define TARGET_HAVE_TLS true
4950 #undef TARGET_CANNOT_FORCE_CONST_MEM
4951 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
4953 #undef TARGET_LEGITIMATE_CONSTANT_P
4954 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
4956 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
4957 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
4959 #undef TARGET_LEGITIMATE_ADDRESS_P
4960 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
4962 #undef TARGET_CAN_ELIMINATE
4963 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
4965 #undef TARGET_CONDITIONAL_REGISTER_USAGE
4966 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
4968 #undef TARGET_CLASS_MAX_NREGS
4969 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
4971 #undef TARGET_TRAMPOLINE_INIT
4972 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
4974 #undef TARGET_IN_SMALL_DATA_P
4975 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
4977 #undef TARGET_HAVE_SRODATA_SECTION
4978 #define TARGET_HAVE_SRODATA_SECTION true
4980 #undef TARGET_ASM_SELECT_SECTION
4981 #define TARGET_ASM_SELECT_SECTION riscv_select_section
4983 #undef TARGET_ASM_SELECT_RTX_SECTION
4984 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
4986 #undef TARGET_MIN_ANCHOR_OFFSET
4987 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
4989 #undef TARGET_MAX_ANCHOR_OFFSET
4990 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
4992 #undef TARGET_REGISTER_PRIORITY
4993 #define TARGET_REGISTER_PRIORITY riscv_register_priority
4995 #undef TARGET_CANNOT_COPY_INSN_P
4996 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
4998 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
4999 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
5001 #undef TARGET_INIT_BUILTINS
5002 #define TARGET_INIT_BUILTINS riscv_init_builtins
5004 #undef TARGET_BUILTIN_DECL
5005 #define TARGET_BUILTIN_DECL riscv_builtin_decl
5007 #undef TARGET_EXPAND_BUILTIN
5008 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
5010 #undef TARGET_HARD_REGNO_NREGS
5011 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
5012 #undef TARGET_HARD_REGNO_MODE_OK
5013 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
5015 #undef TARGET_MODES_TIEABLE_P
5016 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
5018 #undef TARGET_SLOW_UNALIGNED_ACCESS
5019 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
5021 #undef TARGET_SECONDARY_MEMORY_NEEDED
5022 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
5024 #undef TARGET_CAN_CHANGE_MODE_CLASS
5025 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
5027 #undef TARGET_CONSTANT_ALIGNMENT
5028 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
5030 #undef TARGET_MERGE_DECL_ATTRIBUTES
5031 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
5033 #undef TARGET_ATTRIBUTE_TABLE
5034 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
5036 #undef TARGET_WARN_FUNC_RETURN
5037 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
5039 /* The low bit is ignored by jump instructions so is safe to use. */
5040 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
5041 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
5043 struct gcc_target targetm
= TARGET_INITIALIZER
;
5045 #include "gt-riscv.h"