1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
27 #include "coretypes.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
37 #include "stringpool.h"
40 #include "stor-layout.h"
49 #include "target-def.h"
50 #include "basic-block.h"
55 #include "diagnostic.h"
59 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
60 #define UNSPEC_ADDRESS_P(X) \
61 (GET_CODE (X) == UNSPEC \
62 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
63 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
65 /* Extract the symbol or label from UNSPEC wrapper X. */
66 #define UNSPEC_ADDRESS(X) \
69 /* Extract the symbol type from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS_TYPE(X) \
71 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
73 /* True if bit BIT is set in VALUE. */
74 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
76 /* Classifies an address.
79 A natural register + offset address. The register satisfies
80 riscv_valid_base_register_p and the offset is a const_arith_operand.
83 A LO_SUM rtx. The first operand is a valid base register and
84 the second operand is a symbolic address.
87 A signed 16-bit constant address.
90 A constant symbolic address. */
91 enum riscv_address_type
{
98 /* Information about a function's frame layout. */
99 struct GTY(()) riscv_frame_info
{
100 /* The size of the frame in bytes. */
101 HOST_WIDE_INT total_size
;
103 /* Bit X is set if the function saves or restores GPR X. */
106 /* Likewise FPR X. */
109 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
110 unsigned save_libcall_adjustment
;
112 /* Offsets of fixed-point and floating-point save areas from frame bottom */
113 HOST_WIDE_INT gp_sp_offset
;
114 HOST_WIDE_INT fp_sp_offset
;
116 /* Offset of virtual frame pointer from stack pointer/frame bottom */
117 HOST_WIDE_INT frame_pointer_offset
;
119 /* Offset of hard frame pointer from stack pointer/frame bottom */
120 HOST_WIDE_INT hard_frame_pointer_offset
;
122 /* The offset of arg_pointer_rtx from the bottom of the frame. */
123 HOST_WIDE_INT arg_pointer_offset
;
126 enum riscv_privilege_levels
{
127 UNKNOWN_MODE
, USER_MODE
, SUPERVISOR_MODE
, MACHINE_MODE
130 struct GTY(()) machine_function
{
131 /* The number of extra stack bytes taken up by register varargs.
132 This area is allocated by the callee at the very top of the frame. */
135 /* True if current function is a naked function. */
138 /* True if current function is an interrupt function. */
139 bool interrupt_handler_p
;
140 /* For an interrupt handler, indicates the privilege level. */
141 enum riscv_privilege_levels interrupt_mode
;
143 /* True if attributes on current function have been checked. */
144 bool attributes_checked_p
;
146 /* The current frame information, calculated by riscv_compute_frame_info. */
147 struct riscv_frame_info frame
;
150 /* Information about a single argument. */
151 struct riscv_arg_info
{
152 /* True if the argument is at least partially passed on the stack. */
155 /* The number of integer registers allocated to this argument. */
156 unsigned int num_gprs
;
158 /* The offset of the first register used, provided num_gprs is nonzero.
159 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
160 unsigned int gpr_offset
;
162 /* The number of floating-point registers allocated to this argument. */
163 unsigned int num_fprs
;
165 /* The offset of the first register used, provided num_fprs is nonzero. */
166 unsigned int fpr_offset
;
169 /* Information about an address described by riscv_address_type.
175 REG is the base register and OFFSET is the constant offset.
178 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
179 is the type of symbol it references.
182 SYMBOL_TYPE is the type of symbol that the address references. */
183 struct riscv_address_info
{
184 enum riscv_address_type type
;
187 enum riscv_symbol_type symbol_type
;
190 /* One stage in a constant building sequence. These sequences have
194 A = A CODE[1] VALUE[1]
195 A = A CODE[2] VALUE[2]
198 where A is an accumulator, each CODE[i] is a binary rtl operation
199 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
200 struct riscv_integer_op
{
202 unsigned HOST_WIDE_INT value
;
205 /* The largest number of operations needed to load an integer constant.
206 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
207 #define RISCV_MAX_INTEGER_OPS 8
209 /* Costs of various operations on the different architectures. */
211 struct riscv_tune_info
213 unsigned short fp_add
[2];
214 unsigned short fp_mul
[2];
215 unsigned short fp_div
[2];
216 unsigned short int_mul
[2];
217 unsigned short int_div
[2];
218 unsigned short issue_rate
;
219 unsigned short branch_cost
;
220 unsigned short memory_cost
;
221 bool slow_unaligned_access
;
224 /* Information about one CPU we know about. */
225 struct riscv_cpu_info
{
226 /* This CPU's canonical name. */
229 /* Which automaton to use for tuning. */
230 enum riscv_microarchitecture_type microarchitecture
;
232 /* Tuning parameters for this CPU. */
233 const struct riscv_tune_info
*tune_info
;
236 /* Global variables for machine-dependent things. */
238 /* Whether unaligned accesses execute very slowly. */
239 bool riscv_slow_unaligned_access_p
;
241 /* Stack alignment to assume/maintain. */
242 unsigned riscv_stack_boundary
;
244 /* If non-zero, this is an offset to be added to SP to redefine the CFA
245 when restoring the FP register from the stack. Only valid when generating
247 static int epilogue_cfa_sp_offset
;
249 /* Which tuning parameters to use. */
250 static const struct riscv_tune_info
*tune_info
;
252 /* Which automaton to use for tuning. */
253 enum riscv_microarchitecture_type riscv_microarchitecture
;
255 /* Index R is the smallest register class that contains register R. */
256 const enum reg_class riscv_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
257 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
258 GR_REGS
, GR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
259 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
260 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
261 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
262 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
263 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
264 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
265 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
266 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
267 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
268 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
269 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
270 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
271 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
272 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
273 FRAME_REGS
, FRAME_REGS
,
276 /* Costs to use when optimizing for rocket. */
277 static const struct riscv_tune_info rocket_tune_info
= {
278 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
279 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
280 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
281 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
282 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
286 true, /* slow_unaligned_access */
289 /* Costs to use when optimizing for Sifive 7 Series. */
290 static const struct riscv_tune_info sifive_7_tune_info
= {
291 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
292 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
293 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
294 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
295 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
299 true, /* slow_unaligned_access */
302 /* Costs to use when optimizing for size. */
303 static const struct riscv_tune_info optimize_size_tune_info
= {
304 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
305 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
306 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
307 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
308 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
312 false, /* slow_unaligned_access */
315 static tree
riscv_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
316 static tree
riscv_handle_type_attribute (tree
*, tree
, tree
, int, bool *);
318 /* Defining target-specific uses of __attribute__. */
319 static const struct attribute_spec riscv_attribute_table
[] =
321 /* Syntax: { name, min_len, max_len, decl_required, type_required,
322 function_type_required, affects_type_identity, handler,
325 /* The attribute telling no prologue/epilogue. */
326 { "naked", 0, 0, true, false, false, false,
327 riscv_handle_fndecl_attribute
, NULL
},
328 /* This attribute generates prologue/epilogue for interrupt handlers. */
329 { "interrupt", 0, 1, false, true, true, false,
330 riscv_handle_type_attribute
, NULL
},
332 /* The last attribute spec is set to be NULL. */
333 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
336 /* A table describing all the processors GCC knows about. */
337 static const struct riscv_cpu_info riscv_cpu_info_table
[] = {
338 { "rocket", generic
, &rocket_tune_info
},
339 { "sifive-3-series", generic
, &rocket_tune_info
},
340 { "sifive-5-series", generic
, &rocket_tune_info
},
341 { "sifive-7-series", sifive_7
, &sifive_7_tune_info
},
342 { "size", generic
, &optimize_size_tune_info
},
345 /* Return the riscv_cpu_info entry for the given name string. */
347 static const struct riscv_cpu_info
*
348 riscv_parse_cpu (const char *cpu_string
)
350 for (unsigned i
= 0; i
< ARRAY_SIZE (riscv_cpu_info_table
); i
++)
351 if (strcmp (riscv_cpu_info_table
[i
].name
, cpu_string
) == 0)
352 return riscv_cpu_info_table
+ i
;
354 error ("unknown cpu %qs for %<-mtune%>", cpu_string
);
355 return riscv_cpu_info_table
;
358 /* Helper function for riscv_build_integer; arguments are as for
359 riscv_build_integer. */
362 riscv_build_integer_1 (struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
],
363 HOST_WIDE_INT value
, machine_mode mode
)
365 HOST_WIDE_INT low_part
= CONST_LOW_PART (value
);
366 int cost
= RISCV_MAX_INTEGER_OPS
+ 1, alt_cost
;
367 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
369 if (SMALL_OPERAND (value
) || LUI_OPERAND (value
))
371 /* Simply ADDI or LUI. */
372 codes
[0].code
= UNKNOWN
;
373 codes
[0].value
= value
;
377 /* End with ADDI. When constructing HImode constants, do not generate any
378 intermediate value that is not itself a valid HImode constant. The
379 XORI case below will handle those remaining HImode constants. */
382 || value
- low_part
<= ((1 << (GET_MODE_BITSIZE (HImode
) - 1)) - 1)))
384 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
- low_part
, mode
);
387 alt_codes
[alt_cost
-1].code
= PLUS
;
388 alt_codes
[alt_cost
-1].value
= low_part
;
389 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
395 if (cost
> 2 && (low_part
< 0 || mode
== HImode
))
397 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
^ low_part
, mode
);
400 alt_codes
[alt_cost
-1].code
= XOR
;
401 alt_codes
[alt_cost
-1].value
= low_part
;
402 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
407 /* Eliminate trailing zeros and end with SLLI. */
408 if (cost
> 2 && (value
& 1) == 0)
410 int shift
= ctz_hwi (value
);
411 unsigned HOST_WIDE_INT x
= value
;
412 x
= sext_hwi (x
>> shift
, HOST_BITS_PER_WIDE_INT
- shift
);
414 /* Don't eliminate the lower 12 bits if LUI might apply. */
415 if (shift
> IMM_BITS
&& !SMALL_OPERAND (x
) && LUI_OPERAND (x
<< IMM_BITS
))
416 shift
-= IMM_BITS
, x
<<= IMM_BITS
;
418 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, x
, mode
);
421 alt_codes
[alt_cost
-1].code
= ASHIFT
;
422 alt_codes
[alt_cost
-1].value
= shift
;
423 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
428 gcc_assert (cost
<= RISCV_MAX_INTEGER_OPS
);
432 /* Fill CODES with a sequence of rtl operations to load VALUE.
433 Return the number of operations needed. */
436 riscv_build_integer (struct riscv_integer_op
*codes
, HOST_WIDE_INT value
,
439 int cost
= riscv_build_integer_1 (codes
, value
, mode
);
441 /* Eliminate leading zeros and end with SRLI. */
442 if (value
> 0 && cost
> 2)
444 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
445 int alt_cost
, shift
= clz_hwi (value
);
446 HOST_WIDE_INT shifted_val
;
448 /* Try filling trailing bits with 1s. */
449 shifted_val
= (value
<< shift
) | ((((HOST_WIDE_INT
) 1) << shift
) - 1);
450 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
453 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
454 alt_codes
[alt_cost
-1].value
= shift
;
455 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
459 /* Try filling trailing bits with 0s. */
460 shifted_val
= value
<< shift
;
461 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
464 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
465 alt_codes
[alt_cost
-1].value
= shift
;
466 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
474 /* Return the cost of constructing VAL in the event that a scratch
475 register is available. */
478 riscv_split_integer_cost (HOST_WIDE_INT val
)
481 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
482 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
483 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
485 cost
= 2 + riscv_build_integer (codes
, loval
, VOIDmode
);
487 cost
+= riscv_build_integer (codes
, hival
, VOIDmode
);
492 /* Return the cost of constructing the integer constant VAL. */
495 riscv_integer_cost (HOST_WIDE_INT val
)
497 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
498 return MIN (riscv_build_integer (codes
, val
, VOIDmode
),
499 riscv_split_integer_cost (val
));
502 /* Try to split a 64b integer into 32b parts, then reassemble. */
505 riscv_split_integer (HOST_WIDE_INT val
, machine_mode mode
)
507 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
508 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
509 rtx hi
= gen_reg_rtx (mode
), lo
= gen_reg_rtx (mode
);
511 riscv_move_integer (hi
, hi
, hival
, mode
);
512 riscv_move_integer (lo
, lo
, loval
, mode
);
514 hi
= gen_rtx_fmt_ee (ASHIFT
, mode
, hi
, GEN_INT (32));
515 hi
= force_reg (mode
, hi
);
517 return gen_rtx_fmt_ee (PLUS
, mode
, hi
, lo
);
520 /* Return true if X is a thread-local symbol. */
523 riscv_tls_symbol_p (const_rtx x
)
525 return SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0;
528 /* Return true if symbol X binds locally. */
531 riscv_symbol_binds_local_p (const_rtx x
)
533 if (SYMBOL_REF_P (x
))
534 return (SYMBOL_REF_DECL (x
)
535 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
536 : SYMBOL_REF_LOCAL_P (x
));
541 /* Return the method that should be used to access SYMBOL_REF or
544 static enum riscv_symbol_type
545 riscv_classify_symbol (const_rtx x
)
547 if (riscv_tls_symbol_p (x
))
550 if (GET_CODE (x
) == SYMBOL_REF
&& flag_pic
&& !riscv_symbol_binds_local_p (x
))
551 return SYMBOL_GOT_DISP
;
553 return riscv_cmodel
== CM_MEDLOW
? SYMBOL_ABSOLUTE
: SYMBOL_PCREL
;
556 /* Classify the base of symbolic expression X. */
558 enum riscv_symbol_type
559 riscv_classify_symbolic_expression (rtx x
)
563 split_const (x
, &x
, &offset
);
564 if (UNSPEC_ADDRESS_P (x
))
565 return UNSPEC_ADDRESS_TYPE (x
);
567 return riscv_classify_symbol (x
);
570 /* Return true if X is a symbolic constant. If it is, store the type of
571 the symbol in *SYMBOL_TYPE. */
574 riscv_symbolic_constant_p (rtx x
, enum riscv_symbol_type
*symbol_type
)
578 split_const (x
, &x
, &offset
);
579 if (UNSPEC_ADDRESS_P (x
))
581 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
582 x
= UNSPEC_ADDRESS (x
);
584 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
585 *symbol_type
= riscv_classify_symbol (x
);
589 if (offset
== const0_rtx
)
592 /* Nonzero offsets are only valid for references that don't use the GOT. */
593 switch (*symbol_type
)
595 case SYMBOL_ABSOLUTE
:
598 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
599 return sext_hwi (INTVAL (offset
), 32) == INTVAL (offset
);
606 /* Returns the number of instructions necessary to reference a symbol. */
608 static int riscv_symbol_insns (enum riscv_symbol_type type
)
612 case SYMBOL_TLS
: return 0; /* Depends on the TLS model. */
613 case SYMBOL_ABSOLUTE
: return 2; /* LUI + the reference. */
614 case SYMBOL_PCREL
: return 2; /* AUIPC + the reference. */
615 case SYMBOL_TLS_LE
: return 3; /* LUI + ADD TP + the reference. */
616 case SYMBOL_GOT_DISP
: return 3; /* AUIPC + LD GOT + the reference. */
617 default: gcc_unreachable ();
621 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
624 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
626 return riscv_const_insns (x
) > 0;
629 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
632 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
634 enum riscv_symbol_type type
;
637 /* There is no assembler syntax for expressing an address-sized
639 if (GET_CODE (x
) == HIGH
)
642 split_const (x
, &base
, &offset
);
643 if (riscv_symbolic_constant_p (base
, &type
))
645 /* As an optimization, don't spill symbolic constants that are as
646 cheap to rematerialize as to access in the constant pool. */
647 if (SMALL_OPERAND (INTVAL (offset
)) && riscv_symbol_insns (type
) > 0)
650 /* As an optimization, avoid needlessly generate dynamic relocations. */
655 /* TLS symbols must be computed by riscv_legitimize_move. */
656 if (tls_referenced_p (x
))
662 /* Return true if register REGNO is a valid base register for mode MODE.
663 STRICT_P is true if REG_OK_STRICT is in effect. */
666 riscv_regno_mode_ok_for_base_p (int regno
,
667 machine_mode mode ATTRIBUTE_UNUSED
,
670 if (!HARD_REGISTER_NUM_P (regno
))
674 regno
= reg_renumber
[regno
];
677 /* These fake registers will be eliminated to either the stack or
678 hard frame pointer, both of which are usually valid base registers.
679 Reload deals with the cases where the eliminated form isn't valid. */
680 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
683 return GP_REG_P (regno
);
686 /* Return true if X is a valid base register for mode MODE.
687 STRICT_P is true if REG_OK_STRICT is in effect. */
690 riscv_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
692 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
696 && riscv_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
699 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
700 can address a value of mode MODE. */
703 riscv_valid_offset_p (rtx x
, machine_mode mode
)
705 /* Check that X is a signed 12-bit number. */
706 if (!const_arith_operand (x
, Pmode
))
709 /* We may need to split multiword moves, so make sure that every word
711 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
712 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
718 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
721 riscv_split_symbol_type (enum riscv_symbol_type symbol_type
)
723 if (symbol_type
== SYMBOL_TLS_LE
)
726 if (!TARGET_EXPLICIT_RELOCS
)
729 return symbol_type
== SYMBOL_ABSOLUTE
|| symbol_type
== SYMBOL_PCREL
;
732 /* Return true if a LO_SUM can address a value of mode MODE when the
733 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
734 is used when the mode is BLKmode. */
737 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type
, machine_mode mode
,
742 /* Check that symbols of type SYMBOL_TYPE can be used to access values
744 if (riscv_symbol_insns (sym_type
) == 0)
747 /* Check that there is a known low-part relocation. */
748 if (!riscv_split_symbol_type (sym_type
))
751 /* We can't tell size or alignment when we have BLKmode, so try extracing a
752 decl from the symbol if possible. */
757 /* Extract the symbol from the LO_SUM operand, if any. */
758 split_const (x
, &x
, &offset
);
760 /* Might be a CODE_LABEL. We can compute align but not size for that,
761 so don't bother trying to handle it. */
762 if (!SYMBOL_REF_P (x
))
765 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
766 align
= (SYMBOL_REF_DECL (x
)
767 ? DECL_ALIGN (SYMBOL_REF_DECL (x
))
769 size
= (SYMBOL_REF_DECL (x
) && DECL_SIZE (SYMBOL_REF_DECL (x
))
770 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x
)))
775 align
= GET_MODE_ALIGNMENT (mode
);
776 size
= GET_MODE_BITSIZE (mode
);
779 /* We may need to split multiword moves, so make sure that each word
780 can be accessed without inducing a carry. */
781 if (size
> BITS_PER_WORD
782 && (!TARGET_STRICT_ALIGN
|| size
> align
))
788 /* Return true if X is a valid address for machine mode MODE. If it is,
789 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
793 riscv_classify_address (struct riscv_address_info
*info
, rtx x
,
794 machine_mode mode
, bool strict_p
)
796 switch (GET_CODE (x
))
800 info
->type
= ADDRESS_REG
;
802 info
->offset
= const0_rtx
;
803 return riscv_valid_base_register_p (info
->reg
, mode
, strict_p
);
806 info
->type
= ADDRESS_REG
;
807 info
->reg
= XEXP (x
, 0);
808 info
->offset
= XEXP (x
, 1);
809 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
810 && riscv_valid_offset_p (info
->offset
, mode
));
813 info
->type
= ADDRESS_LO_SUM
;
814 info
->reg
= XEXP (x
, 0);
815 info
->offset
= XEXP (x
, 1);
816 /* We have to trust the creator of the LO_SUM to do something vaguely
817 sane. Target-independent code that creates a LO_SUM should also
818 create and verify the matching HIGH. Target-independent code that
819 adds an offset to a LO_SUM must prove that the offset will not
820 induce a carry. Failure to do either of these things would be
821 a bug, and we are not required to check for it here. The RISC-V
822 backend itself should only create LO_SUMs for valid symbolic
823 constants, with the high part being either a HIGH or a copy
826 = riscv_classify_symbolic_expression (info
->offset
);
827 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
828 && riscv_valid_lo_sum_p (info
->symbol_type
, mode
, info
->offset
));
831 /* Small-integer addresses don't occur very often, but they
832 are legitimate if x0 is a valid base register. */
833 info
->type
= ADDRESS_CONST_INT
;
834 return SMALL_OPERAND (INTVAL (x
));
841 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
844 riscv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
846 struct riscv_address_info addr
;
848 return riscv_classify_address (&addr
, x
, mode
, strict_p
);
851 /* Return the number of instructions needed to load or store a value
852 of mode MODE at address X. Return 0 if X isn't valid for MODE.
853 Assume that multiword moves may need to be split into word moves
854 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
858 riscv_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
860 struct riscv_address_info addr
;
863 if (!riscv_classify_address (&addr
, x
, mode
, false))
865 /* This could be a pattern from the pic.md file. In which case we want
866 this address to always have a cost of 3 to make it as expensive as the
867 most expensive symbol. This prevents constant propagation from
868 preferring symbols over register plus offset. */
872 /* BLKmode is used for single unaligned loads and stores and should
873 not count as a multiword mode. */
874 if (mode
!= BLKmode
&& might_split_p
)
875 n
+= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
877 if (addr
.type
== ADDRESS_LO_SUM
)
878 n
+= riscv_symbol_insns (addr
.symbol_type
) - 1;
883 /* Return the number of instructions needed to load constant X.
884 Return 0 if X isn't a valid constant. */
887 riscv_const_insns (rtx x
)
889 enum riscv_symbol_type symbol_type
;
892 switch (GET_CODE (x
))
895 if (!riscv_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
896 || !riscv_split_symbol_type (symbol_type
))
899 /* This is simply an LUI. */
904 int cost
= riscv_integer_cost (INTVAL (x
));
905 /* Force complicated constants to memory. */
906 return cost
< 4 ? cost
: 0;
911 /* We can use x0 to load floating-point zero. */
912 return x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
915 /* See if we can refer to X directly. */
916 if (riscv_symbolic_constant_p (x
, &symbol_type
))
917 return riscv_symbol_insns (symbol_type
);
919 /* Otherwise try splitting the constant into a base and offset. */
920 split_const (x
, &x
, &offset
);
923 int n
= riscv_const_insns (x
);
925 return n
+ riscv_integer_cost (INTVAL (offset
));
931 return riscv_symbol_insns (riscv_classify_symbol (x
));
938 /* X is a doubleword constant that can be handled by splitting it into
939 two words and loading each word separately. Return the number of
940 instructions required to do this. */
943 riscv_split_const_insns (rtx x
)
945 unsigned int low
, high
;
947 low
= riscv_const_insns (riscv_subword (x
, false));
948 high
= riscv_const_insns (riscv_subword (x
, true));
949 gcc_assert (low
> 0 && high
> 0);
953 /* Return the number of instructions needed to implement INSN,
954 given that it loads from or stores to MEM. */
957 riscv_load_store_insns (rtx mem
, rtx_insn
*insn
)
963 gcc_assert (MEM_P (mem
));
964 mode
= GET_MODE (mem
);
966 /* Try to prove that INSN does not need to be split. */
967 might_split_p
= true;
968 if (GET_MODE_BITSIZE (mode
) <= 32)
969 might_split_p
= false;
970 else if (GET_MODE_BITSIZE (mode
) == 64)
972 set
= single_set (insn
);
973 if (set
&& !riscv_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
974 might_split_p
= false;
977 return riscv_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
980 /* Emit a move from SRC to DEST. Assume that the move expanders can
981 handle all moves if !can_create_pseudo_p (). The distinction is
982 important because, unlike emit_move_insn, the move expanders know
983 how to force Pmode objects into the constant pool even when the
984 constant pool address is not itself legitimate. */
987 riscv_emit_move (rtx dest
, rtx src
)
989 return (can_create_pseudo_p ()
990 ? emit_move_insn (dest
, src
)
991 : emit_move_insn_1 (dest
, src
));
994 /* Emit an instruction of the form (set TARGET SRC). */
997 riscv_emit_set (rtx target
, rtx src
)
999 emit_insn (gen_rtx_SET (target
, src
));
1003 /* Emit an instruction of the form (set DEST (CODE X Y)). */
1006 riscv_emit_binary (enum rtx_code code
, rtx dest
, rtx x
, rtx y
)
1008 return riscv_emit_set (dest
, gen_rtx_fmt_ee (code
, GET_MODE (dest
), x
, y
));
1011 /* Compute (CODE X Y) and store the result in a new register
1012 of mode MODE. Return that new register. */
1015 riscv_force_binary (machine_mode mode
, enum rtx_code code
, rtx x
, rtx y
)
1017 return riscv_emit_binary (code
, gen_reg_rtx (mode
), x
, y
);
1020 /* Copy VALUE to a register and return that register. If new pseudos
1021 are allowed, copy it into a new register, otherwise use DEST. */
1024 riscv_force_temporary (rtx dest
, rtx value
)
1026 if (can_create_pseudo_p ())
1027 return force_reg (Pmode
, value
);
1030 riscv_emit_move (dest
, value
);
1035 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
1036 then add CONST_INT OFFSET to the result. */
1039 riscv_unspec_address_offset (rtx base
, rtx offset
,
1040 enum riscv_symbol_type symbol_type
)
1042 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1043 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1044 if (offset
!= const0_rtx
)
1045 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
1046 return gen_rtx_CONST (Pmode
, base
);
1049 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1050 type SYMBOL_TYPE. */
1053 riscv_unspec_address (rtx address
, enum riscv_symbol_type symbol_type
)
1057 split_const (address
, &base
, &offset
);
1058 return riscv_unspec_address_offset (base
, offset
, symbol_type
);
1061 /* If OP is an UNSPEC address, return the address to which it refers,
1062 otherwise return OP itself. */
1065 riscv_strip_unspec_address (rtx op
)
1069 split_const (op
, &base
, &offset
);
1070 if (UNSPEC_ADDRESS_P (base
))
1071 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
1075 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1076 high part to BASE and return the result. Just return BASE otherwise.
1077 TEMP is as for riscv_force_temporary.
1079 The returned expression can be used as the first operand to a LO_SUM. */
1082 riscv_unspec_offset_high (rtx temp
, rtx addr
, enum riscv_symbol_type symbol_type
)
1084 addr
= gen_rtx_HIGH (Pmode
, riscv_unspec_address (addr
, symbol_type
));
1085 return riscv_force_temporary (temp
, addr
);
1088 /* Load an entry from the GOT for a TLS GD access. */
1090 static rtx
riscv_got_load_tls_gd (rtx dest
, rtx sym
)
1092 if (Pmode
== DImode
)
1093 return gen_got_load_tls_gddi (dest
, sym
);
1095 return gen_got_load_tls_gdsi (dest
, sym
);
1098 /* Load an entry from the GOT for a TLS IE access. */
1100 static rtx
riscv_got_load_tls_ie (rtx dest
, rtx sym
)
1102 if (Pmode
== DImode
)
1103 return gen_got_load_tls_iedi (dest
, sym
);
1105 return gen_got_load_tls_iesi (dest
, sym
);
1108 /* Add in the thread pointer for a TLS LE access. */
1110 static rtx
riscv_tls_add_tp_le (rtx dest
, rtx base
, rtx sym
)
1112 rtx tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1113 if (Pmode
== DImode
)
1114 return gen_tls_add_tp_ledi (dest
, base
, tp
, sym
);
1116 return gen_tls_add_tp_lesi (dest
, base
, tp
, sym
);
1119 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1120 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1121 constant in that context and can be split into high and low parts.
1122 If so, and if LOW_OUT is nonnull, emit the high part and store the
1123 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1125 TEMP is as for riscv_force_temporary and is used to load the high
1126 part into a register.
1128 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1129 a legitimize SET_SRC for an .md pattern, otherwise the low part
1130 is guaranteed to be a legitimate address for mode MODE. */
1133 riscv_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
1135 enum riscv_symbol_type symbol_type
;
1137 if ((GET_CODE (addr
) == HIGH
&& mode
== MAX_MACHINE_MODE
)
1138 || !riscv_symbolic_constant_p (addr
, &symbol_type
)
1139 || riscv_symbol_insns (symbol_type
) == 0
1140 || !riscv_split_symbol_type (symbol_type
))
1144 switch (symbol_type
)
1146 case SYMBOL_ABSOLUTE
:
1148 rtx high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
1149 high
= riscv_force_temporary (temp
, high
);
1150 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
1156 static unsigned seqno
;
1160 ssize_t bytes
= snprintf (buf
, sizeof (buf
), ".LA%u", seqno
);
1161 gcc_assert ((size_t) bytes
< sizeof (buf
));
1163 label
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
1164 SYMBOL_REF_FLAGS (label
) |= SYMBOL_FLAG_LOCAL
;
1165 /* ??? Ugly hack to make weak symbols work. May need to change the
1166 RTL for the auipc and/or low patterns to get a better fix for
1168 if (! nonzero_address_p (addr
))
1169 SYMBOL_REF_WEAK (label
) = 1;
1172 temp
= gen_reg_rtx (Pmode
);
1174 if (Pmode
== DImode
)
1175 emit_insn (gen_auipcdi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1177 emit_insn (gen_auipcsi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1179 *low_out
= gen_rtx_LO_SUM (Pmode
, temp
, label
);
1192 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1193 riscv_force_temporary; it is only needed when OFFSET is not a
1197 riscv_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1199 if (!SMALL_OPERAND (offset
))
1203 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1204 The addition inside the macro CONST_HIGH_PART may cause an
1205 overflow, so we need to force a sign-extension check. */
1206 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
1207 offset
= CONST_LOW_PART (offset
);
1208 high
= riscv_force_temporary (temp
, high
);
1209 reg
= riscv_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
1211 return plus_constant (Pmode
, reg
, offset
);
1214 /* The __tls_get_attr symbol. */
1215 static GTY(()) rtx riscv_tls_symbol
;
1217 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1218 the TLS symbol we are referencing and TYPE is the symbol type to use
1219 (either global dynamic or local dynamic). RESULT is an RTX for the
1220 return value location. */
1223 riscv_call_tls_get_addr (rtx sym
, rtx result
)
1225 rtx a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
), func
;
1228 if (!riscv_tls_symbol
)
1229 riscv_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1230 func
= gen_rtx_MEM (FUNCTION_MODE
, riscv_tls_symbol
);
1234 emit_insn (riscv_got_load_tls_gd (a0
, sym
));
1235 insn
= emit_call_insn (gen_call_value (result
, func
, const0_rtx
, NULL
));
1236 RTL_CONST_CALL_P (insn
) = 1;
1237 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1238 insn
= get_insns ();
1245 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1246 its address. The return value will be both a valid address and a valid
1247 SET_SRC (either a REG or a LO_SUM). */
1250 riscv_legitimize_tls_address (rtx loc
)
1253 enum tls_model model
= SYMBOL_REF_TLS_MODEL (loc
);
1255 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1257 model
= TLS_MODEL_LOCAL_EXEC
;
1261 case TLS_MODEL_LOCAL_DYNAMIC
:
1262 /* Rely on section anchors for the optimization that LDM TLS
1263 provides. The anchor's address is loaded with GD TLS. */
1264 case TLS_MODEL_GLOBAL_DYNAMIC
:
1265 tmp
= gen_rtx_REG (Pmode
, GP_RETURN
);
1266 dest
= gen_reg_rtx (Pmode
);
1267 emit_libcall_block (riscv_call_tls_get_addr (loc
, tmp
), dest
, tmp
, loc
);
1270 case TLS_MODEL_INITIAL_EXEC
:
1271 /* la.tls.ie; tp-relative add */
1272 tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1273 tmp
= gen_reg_rtx (Pmode
);
1274 emit_insn (riscv_got_load_tls_ie (tmp
, loc
));
1275 dest
= gen_reg_rtx (Pmode
);
1276 emit_insn (gen_add3_insn (dest
, tmp
, tp
));
1279 case TLS_MODEL_LOCAL_EXEC
:
1280 tmp
= riscv_unspec_offset_high (NULL
, loc
, SYMBOL_TLS_LE
);
1281 dest
= gen_reg_rtx (Pmode
);
1282 emit_insn (riscv_tls_add_tp_le (dest
, tmp
, loc
));
1283 dest
= gen_rtx_LO_SUM (Pmode
, dest
,
1284 riscv_unspec_address (loc
, SYMBOL_TLS_LE
));
1293 /* If X is not a valid address for mode MODE, force it into a register. */
1296 riscv_force_address (rtx x
, machine_mode mode
)
1298 if (!riscv_legitimate_address_p (mode
, x
, false))
1299 x
= force_reg (Pmode
, x
);
1303 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1304 be legitimized in a way that the generic machinery might not expect,
1305 return a new address, otherwise return NULL. MODE is the mode of
1306 the memory being accessed. */
1309 riscv_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1314 if (riscv_tls_symbol_p (x
))
1315 return riscv_legitimize_tls_address (x
);
1317 /* See if the address can split into a high part and a LO_SUM. */
1318 if (riscv_split_symbol (NULL
, x
, mode
, &addr
))
1319 return riscv_force_address (addr
, mode
);
1321 /* Handle BASE + OFFSET using riscv_add_offset. */
1322 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
1323 && INTVAL (XEXP (x
, 1)) != 0)
1325 rtx base
= XEXP (x
, 0);
1326 HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
1328 if (!riscv_valid_base_register_p (base
, mode
, false))
1329 base
= copy_to_mode_reg (Pmode
, base
);
1330 addr
= riscv_add_offset (NULL
, base
, offset
);
1331 return riscv_force_address (addr
, mode
);
1337 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
1338 is the original src mode before promotion. */
1341 riscv_move_integer (rtx temp
, rtx dest
, HOST_WIDE_INT value
,
1342 machine_mode orig_mode
)
1344 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
1349 mode
= GET_MODE (dest
);
1350 /* We use the original mode for the riscv_build_integer call, because HImode
1351 values are given special treatment. */
1352 num_ops
= riscv_build_integer (codes
, value
, orig_mode
);
1354 if (can_create_pseudo_p () && num_ops
> 2 /* not a simple constant */
1355 && num_ops
>= riscv_split_integer_cost (value
))
1356 x
= riscv_split_integer (value
, mode
);
1359 /* Apply each binary operation to X. */
1360 x
= GEN_INT (codes
[0].value
);
1362 for (i
= 1; i
< num_ops
; i
++)
1364 if (!can_create_pseudo_p ())
1365 x
= riscv_emit_set (temp
, x
);
1367 x
= force_reg (mode
, x
);
1369 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1373 riscv_emit_set (dest
, x
);
1376 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1377 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1381 riscv_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
1385 /* Split moves of big integers into smaller pieces. */
1386 if (splittable_const_int_operand (src
, mode
))
1388 riscv_move_integer (dest
, dest
, INTVAL (src
), mode
);
1392 /* Split moves of symbolic constants into high/low pairs. */
1393 if (riscv_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
1395 riscv_emit_set (dest
, src
);
1399 /* Generate the appropriate access sequences for TLS symbols. */
1400 if (riscv_tls_symbol_p (src
))
1402 riscv_emit_move (dest
, riscv_legitimize_tls_address (src
));
1406 /* If we have (const (plus symbol offset)), and that expression cannot
1407 be forced into memory, load the symbol first and add in the offset. Also
1408 prefer to do this even if the constant _can_ be forced into memory, as it
1409 usually produces better code. */
1410 split_const (src
, &base
, &offset
);
1411 if (offset
!= const0_rtx
1412 && (targetm
.cannot_force_const_mem (mode
, src
) || can_create_pseudo_p ()))
1414 base
= riscv_force_temporary (dest
, base
);
1415 riscv_emit_move (dest
, riscv_add_offset (NULL
, base
, INTVAL (offset
)));
1419 src
= force_const_mem (mode
, src
);
1421 /* When using explicit relocs, constant pool references are sometimes
1422 not legitimate addresses. */
1423 riscv_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
1424 riscv_emit_move (dest
, src
);
1427 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1428 sequence that is valid. */
1431 riscv_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
1433 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1437 if (GET_CODE (src
) == CONST_INT
)
1439 /* Apply the equivalent of PROMOTE_MODE here for constants to
1441 machine_mode promoted_mode
= mode
;
1442 if (GET_MODE_CLASS (mode
) == MODE_INT
1443 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
1444 promoted_mode
= word_mode
;
1446 if (splittable_const_int_operand (src
, mode
))
1448 reg
= gen_reg_rtx (promoted_mode
);
1449 riscv_move_integer (reg
, reg
, INTVAL (src
), mode
);
1452 reg
= force_reg (promoted_mode
, src
);
1454 if (promoted_mode
!= mode
)
1455 reg
= gen_lowpart (mode
, reg
);
1458 reg
= force_reg (mode
, src
);
1459 riscv_emit_move (dest
, reg
);
1463 /* We need to deal with constants that would be legitimate
1464 immediate_operands but aren't legitimate move_operands. */
1465 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1467 riscv_legitimize_const_move (mode
, dest
, src
);
1468 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1472 /* RISC-V GCC may generate non-legitimate address due to we provide some
1473 pattern for optimize access PIC local symbol and it's make GCC generate
1474 unrecognizable instruction during optmizing. */
1476 if (MEM_P (dest
) && !riscv_legitimate_address_p (mode
, XEXP (dest
, 0),
1479 XEXP (dest
, 0) = riscv_force_address (XEXP (dest
, 0), mode
);
1482 if (MEM_P (src
) && !riscv_legitimate_address_p (mode
, XEXP (src
, 0),
1485 XEXP (src
, 0) = riscv_force_address (XEXP (src
, 0), mode
);
1491 /* Return true if there is an instruction that implements CODE and accepts
1492 X as an immediate operand. */
1495 riscv_immediate_operand_p (int code
, HOST_WIDE_INT x
)
1502 /* All shift counts are truncated to a valid constant. */
1511 /* These instructions take 12-bit signed immediates. */
1512 return SMALL_OPERAND (x
);
1515 /* We add 1 to the immediate and use SLT. */
1516 return SMALL_OPERAND (x
+ 1);
1519 /* Likewise SLTU, but reject the always-true case. */
1520 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
1524 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1528 /* By default assume that x0 can be used for 0. */
1533 /* Return the cost of binary operation X, given that the instruction
1534 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1535 instructions and that the sequence of a double-word operation takes
1536 DOUBLE_INSNS instructions. */
1539 riscv_binary_cost (rtx x
, int single_insns
, int double_insns
)
1541 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
1542 return COSTS_N_INSNS (double_insns
);
1543 return COSTS_N_INSNS (single_insns
);
1546 /* Return the cost of sign- or zero-extending OP. */
1549 riscv_extend_cost (rtx op
, bool unsigned_p
)
1554 if (unsigned_p
&& GET_MODE (op
) == QImode
)
1555 /* We can use ANDI. */
1556 return COSTS_N_INSNS (1);
1558 if (!unsigned_p
&& GET_MODE (op
) == SImode
)
1559 /* We can use SEXT.W. */
1560 return COSTS_N_INSNS (1);
1562 /* We need to use a shift left and a shift right. */
1563 return COSTS_N_INSNS (2);
1566 /* Implement TARGET_RTX_COSTS. */
1568 #define SINGLE_SHIFT_COST 1
1571 riscv_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1572 int *total
, bool speed
)
1574 bool float_mode_p
= FLOAT_MODE_P (mode
);
1577 switch (GET_CODE (x
))
1580 if (riscv_immediate_operand_p (outer_code
, INTVAL (x
)))
1591 if ((cost
= riscv_const_insns (x
)) > 0)
1593 /* If the constant is likely to be stored in a GPR, SETs of
1594 single-insn constants are as cheap as register sets; we
1595 never want to CSE them. */
1596 if (cost
== 1 && outer_code
== SET
)
1598 /* When we load a constant more than once, it usually is better
1599 to duplicate the last operation in the sequence than to CSE
1600 the constant itself. */
1601 else if (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
)
1602 *total
= COSTS_N_INSNS (1);
1604 else /* The instruction will be fetched from the constant pool. */
1605 *total
= COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE
));
1609 /* If the address is legitimate, return the number of
1610 instructions it needs. */
1611 if ((cost
= riscv_address_insns (XEXP (x
, 0), mode
, true)) > 0)
1613 *total
= COSTS_N_INSNS (cost
+ tune_info
->memory_cost
);
1616 /* Otherwise use the default handling. */
1620 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
1626 /* Double-word operations use two single-word operations. */
1627 *total
= riscv_binary_cost (x
, 1, 2);
1631 /* This is an SImode shift. */
1632 if (outer_code
== SET
&& (INTVAL (XEXP (x
, 2)) > 0)
1633 && (INTVAL (XEXP (x
, 1)) + INTVAL (XEXP (x
, 2)) == 32))
1635 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1643 *total
= riscv_binary_cost (x
, SINGLE_SHIFT_COST
,
1644 CONSTANT_P (XEXP (x
, 1)) ? 4 : 9);
1648 *total
= COSTS_N_INSNS (float_mode_p
? 1 : 3);
1652 *total
= set_src_cost (XEXP (x
, 0), mode
, speed
);
1656 /* This is an SImode shift. */
1657 if (outer_code
== SET
&& GET_MODE (x
) == DImode
1658 && GET_MODE (XEXP (x
, 0)) == SImode
)
1660 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1673 /* Branch comparisons have VOIDmode, so use the first operand's
1675 mode
= GET_MODE (XEXP (x
, 0));
1677 *total
= tune_info
->fp_add
[mode
== DFmode
];
1679 *total
= riscv_binary_cost (x
, 1, 3);
1684 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1685 mode
= GET_MODE (XEXP (x
, 0));
1686 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1691 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1692 mode
= GET_MODE (XEXP (x
, 0));
1693 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (3);
1700 /* FLT or FLE, but guarded by an FFLAGS read and write. */
1701 mode
= GET_MODE (XEXP (x
, 0));
1702 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (4);
1708 *total
= tune_info
->fp_add
[mode
== DFmode
];
1710 *total
= riscv_binary_cost (x
, 1, 4);
1715 rtx op
= XEXP (x
, 0);
1716 if (GET_CODE (op
) == FMA
&& !HONOR_SIGNED_ZEROS (mode
))
1718 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1719 + set_src_cost (XEXP (op
, 0), mode
, speed
)
1720 + set_src_cost (XEXP (op
, 1), mode
, speed
)
1721 + set_src_cost (XEXP (op
, 2), mode
, speed
));
1727 *total
= tune_info
->fp_add
[mode
== DFmode
];
1729 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
1734 *total
= tune_info
->fp_mul
[mode
== DFmode
];
1735 else if (!TARGET_MUL
)
1736 /* Estimate the cost of a library call. */
1737 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1738 else if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
1739 *total
= 3 * tune_info
->int_mul
[0] + COSTS_N_INSNS (2);
1741 *total
= COSTS_N_INSNS (1);
1743 *total
= tune_info
->int_mul
[mode
== DImode
];
1751 *total
= tune_info
->fp_div
[mode
== DFmode
];
1759 /* Estimate the cost of a library call. */
1760 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1762 *total
= tune_info
->int_div
[mode
== DImode
];
1764 *total
= COSTS_N_INSNS (1);
1768 /* This is an SImode shift. */
1769 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
1771 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1776 *total
= riscv_extend_cost (XEXP (x
, 0), GET_CODE (x
) == ZERO_EXTEND
);
1780 case UNSIGNED_FLOAT
:
1783 case FLOAT_TRUNCATE
:
1784 *total
= tune_info
->fp_add
[mode
== DFmode
];
1788 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1789 + set_src_cost (XEXP (x
, 0), mode
, speed
)
1790 + set_src_cost (XEXP (x
, 1), mode
, speed
)
1791 + set_src_cost (XEXP (x
, 2), mode
, speed
));
1795 if (XINT (x
, 1) == UNSPEC_AUIPC
)
1797 /* Make AUIPC cheap to avoid spilling its result to the stack. */
1808 /* Implement TARGET_ADDRESS_COST. */
1811 riscv_address_cost (rtx addr
, machine_mode mode
,
1812 addr_space_t as ATTRIBUTE_UNUSED
,
1813 bool speed ATTRIBUTE_UNUSED
)
1815 return riscv_address_insns (addr
, mode
, false);
1818 /* Return one word of double-word value OP. HIGH_P is true to select the
1819 high part or false to select the low part. */
1822 riscv_subword (rtx op
, bool high_p
)
1824 unsigned int byte
= high_p
? UNITS_PER_WORD
: 0;
1825 machine_mode mode
= GET_MODE (op
);
1827 if (mode
== VOIDmode
)
1828 mode
= TARGET_64BIT
? TImode
: DImode
;
1831 return adjust_address (op
, word_mode
, byte
);
1834 gcc_assert (!FP_REG_RTX_P (op
));
1836 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
1839 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
1842 riscv_split_64bit_move_p (rtx dest
, rtx src
)
1847 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
1848 of zeroing an FPR with FCVT.D.W. */
1849 if (TARGET_DOUBLE_FLOAT
1850 && ((FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
1851 || (FP_REG_RTX_P (dest
) && MEM_P (src
))
1852 || (FP_REG_RTX_P (src
) && MEM_P (dest
))
1853 || (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))))
1859 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
1860 this function handles 64-bit moves for which riscv_split_64bit_move_p
1861 holds. For 64-bit targets, this function handles 128-bit moves. */
1864 riscv_split_doubleword_move (rtx dest
, rtx src
)
1868 /* The operation can be split into two normal moves. Decide in
1869 which order to do them. */
1870 low_dest
= riscv_subword (dest
, false);
1871 if (REG_P (low_dest
) && reg_overlap_mentioned_p (low_dest
, src
))
1873 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1874 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1878 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1879 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1883 /* Return the appropriate instructions to move SRC into DEST. Assume
1884 that SRC is operand 1 and DEST is operand 0. */
1887 riscv_output_move (rtx dest
, rtx src
)
1889 enum rtx_code dest_code
, src_code
;
1893 dest_code
= GET_CODE (dest
);
1894 src_code
= GET_CODE (src
);
1895 mode
= GET_MODE (dest
);
1896 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
1898 if (dbl_p
&& riscv_split_64bit_move_p (dest
, src
))
1901 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
1903 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1904 return dbl_p
? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
1906 if (src_code
== MEM
)
1907 switch (GET_MODE_SIZE (mode
))
1909 case 1: return "lbu\t%0,%1";
1910 case 2: return "lhu\t%0,%1";
1911 case 4: return "lw\t%0,%1";
1912 case 8: return "ld\t%0,%1";
1915 if (src_code
== CONST_INT
)
1918 if (src_code
== HIGH
)
1919 return "lui\t%0,%h1";
1921 if (symbolic_operand (src
, VOIDmode
))
1922 switch (riscv_classify_symbolic_expression (src
))
1924 case SYMBOL_GOT_DISP
: return "la\t%0,%1";
1925 case SYMBOL_ABSOLUTE
: return "lla\t%0,%1";
1926 case SYMBOL_PCREL
: return "lla\t%0,%1";
1927 default: gcc_unreachable ();
1930 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
1931 || (src
== CONST0_RTX (mode
)))
1933 if (dest_code
== REG
)
1935 if (GP_REG_P (REGNO (dest
)))
1936 return "mv\t%0,%z1";
1938 if (FP_REG_P (REGNO (dest
)))
1941 return "fmv.s.x\t%0,%z1";
1943 return "fmv.d.x\t%0,%z1";
1944 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
1945 gcc_assert (src
== CONST0_RTX (mode
));
1946 return "fcvt.d.w\t%0,x0";
1949 if (dest_code
== MEM
)
1950 switch (GET_MODE_SIZE (mode
))
1952 case 1: return "sb\t%z1,%0";
1953 case 2: return "sh\t%z1,%0";
1954 case 4: return "sw\t%z1,%0";
1955 case 8: return "sd\t%z1,%0";
1958 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1960 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1961 return dbl_p
? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
1963 if (dest_code
== MEM
)
1964 return dbl_p
? "fsd\t%1,%0" : "fsw\t%1,%0";
1966 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1968 if (src_code
== MEM
)
1969 return dbl_p
? "fld\t%0,%1" : "flw\t%0,%1";
1975 riscv_output_return ()
1977 if (cfun
->machine
->naked_p
)
1984 /* Return true if CMP1 is a suitable second operand for integer ordering
1985 test CODE. See also the *sCC patterns in riscv.md. */
1988 riscv_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
1994 return reg_or_0_operand (cmp1
, VOIDmode
);
1998 return cmp1
== const1_rtx
;
2002 return arith_operand (cmp1
, VOIDmode
);
2005 return sle_operand (cmp1
, VOIDmode
);
2008 return sleu_operand (cmp1
, VOIDmode
);
2015 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
2016 integer ordering test *CODE, or if an equivalent combination can
2017 be formed by adjusting *CODE and *CMP1. When returning true, update
2018 *CODE and *CMP1 with the chosen code and operand, otherwise leave
2022 riscv_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
2025 HOST_WIDE_INT plus_one
;
2027 if (riscv_int_order_operand_ok_p (*code
, *cmp1
))
2030 if (CONST_INT_P (*cmp1
))
2034 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2035 if (INTVAL (*cmp1
) < plus_one
)
2038 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2044 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2048 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2059 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
2060 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
2061 is nonnull, it's OK to set TARGET to the inverse of the result and
2062 flip *INVERT_PTR instead. */
2065 riscv_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
2066 rtx target
, rtx cmp0
, rtx cmp1
)
2070 /* First see if there is a RISCV instruction that can do this operation.
2071 If not, try doing the same for the inverse operation. If that also
2072 fails, force CMP1 into a register and try again. */
2073 mode
= GET_MODE (cmp0
);
2074 if (riscv_canonicalize_int_order_test (&code
, &cmp1
, mode
))
2075 riscv_emit_binary (code
, target
, cmp0
, cmp1
);
2078 enum rtx_code inv_code
= reverse_condition (code
);
2079 if (!riscv_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
2081 cmp1
= force_reg (mode
, cmp1
);
2082 riscv_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
2084 else if (invert_ptr
== 0)
2086 rtx inv_target
= riscv_force_binary (GET_MODE (target
),
2087 inv_code
, cmp0
, cmp1
);
2088 riscv_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
2092 *invert_ptr
= !*invert_ptr
;
2093 riscv_emit_binary (inv_code
, target
, cmp0
, cmp1
);
2098 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2099 The register will have the same mode as CMP0. */
2102 riscv_zero_if_equal (rtx cmp0
, rtx cmp1
)
2104 if (cmp1
== const0_rtx
)
2107 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2108 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2111 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2114 riscv_extend_comparands (rtx_code code
, rtx
*op0
, rtx
*op1
)
2116 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2117 if (GET_MODE_SIZE (word_mode
) > GET_MODE_SIZE (GET_MODE (*op0
)))
2119 /* It is more profitable to zero-extend QImode values. But not if the
2120 first operand has already been sign-extended, and the second one is
2121 is a constant or has already been sign-extended also. */
2122 if (unsigned_condition (code
) == code
2123 && (GET_MODE (*op0
) == QImode
2124 && ! (GET_CODE (*op0
) == SUBREG
2125 && SUBREG_PROMOTED_VAR_P (*op0
)
2126 && SUBREG_PROMOTED_SIGNED_P (*op0
)
2127 && (CONST_INT_P (*op1
)
2128 || (GET_CODE (*op1
) == SUBREG
2129 && SUBREG_PROMOTED_VAR_P (*op1
)
2130 && SUBREG_PROMOTED_SIGNED_P (*op1
))))))
2132 *op0
= gen_rtx_ZERO_EXTEND (word_mode
, *op0
);
2133 if (CONST_INT_P (*op1
))
2134 *op1
= GEN_INT ((uint8_t) INTVAL (*op1
));
2136 *op1
= gen_rtx_ZERO_EXTEND (word_mode
, *op1
);
2140 *op0
= gen_rtx_SIGN_EXTEND (word_mode
, *op0
);
2141 if (*op1
!= const0_rtx
)
2142 *op1
= gen_rtx_SIGN_EXTEND (word_mode
, *op1
);
2147 /* Convert a comparison into something that can be used in a branch. On
2148 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2149 used to compare them. Update them to describe the final comparison. */
2152 riscv_emit_int_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2154 if (splittable_const_int_operand (*op1
, VOIDmode
))
2156 HOST_WIDE_INT rhs
= INTVAL (*op1
);
2158 if (*code
== EQ
|| *code
== NE
)
2160 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2161 if (SMALL_OPERAND (-rhs
))
2163 *op0
= riscv_force_binary (GET_MODE (*op0
), PLUS
, *op0
,
2170 static const enum rtx_code mag_comparisons
[][2] = {
2171 {LEU
, LTU
}, {GTU
, GEU
}, {LE
, LT
}, {GT
, GE
}
2174 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2175 for (size_t i
= 0; i
< ARRAY_SIZE (mag_comparisons
); i
++)
2177 HOST_WIDE_INT new_rhs
;
2178 bool increment
= *code
== mag_comparisons
[i
][0];
2179 bool decrement
= *code
== mag_comparisons
[i
][1];
2180 if (!increment
&& !decrement
)
2183 new_rhs
= rhs
+ (increment
? 1 : -1);
2184 if (riscv_integer_cost (new_rhs
) < riscv_integer_cost (rhs
)
2185 && (rhs
< 0) == (new_rhs
< 0))
2187 *op1
= GEN_INT (new_rhs
);
2188 *code
= mag_comparisons
[i
][increment
];
2195 riscv_extend_comparands (*code
, op0
, op1
);
2197 *op0
= force_reg (word_mode
, *op0
);
2198 if (*op1
!= const0_rtx
)
2199 *op1
= force_reg (word_mode
, *op1
);
2202 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2205 riscv_emit_float_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2207 rtx tmp0
, tmp1
, cmp_op0
= *op0
, cmp_op1
= *op1
;
2208 enum rtx_code fp_code
= *code
;
2218 /* a == a && b == b */
2219 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2220 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2221 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2227 /* ordered(a, b) > (a == b) */
2228 *code
= fp_code
== LTGT
? GTU
: EQ
;
2229 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2230 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2231 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2232 *op1
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op1
);
2235 #define UNORDERED_COMPARISON(CODE, CMP) \
2238 *op0 = gen_reg_rtx (word_mode); \
2239 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2240 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2241 else if (GET_MODE (cmp_op0) == SFmode) \
2242 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2243 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2244 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2245 else if (GET_MODE (cmp_op0) == DFmode) \
2246 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2248 gcc_unreachable (); \
2249 *op1 = const0_rtx; \
2253 std::swap (cmp_op0
, cmp_op1
);
2256 UNORDERED_COMPARISON(UNGT
, le
)
2259 std::swap (cmp_op0
, cmp_op1
);
2262 UNORDERED_COMPARISON(UNGE
, lt
)
2263 #undef UNORDERED_COMPARISON
2275 /* We have instructions for these cases. */
2276 *op0
= riscv_force_binary (word_mode
, fp_code
, cmp_op0
, cmp_op1
);
2285 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2288 riscv_expand_int_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2290 riscv_extend_comparands (code
, &op0
, &op1
);
2291 op0
= force_reg (word_mode
, op0
);
2293 if (code
== EQ
|| code
== NE
)
2295 rtx zie
= riscv_zero_if_equal (op0
, op1
);
2296 riscv_emit_binary (code
, target
, zie
, const0_rtx
);
2299 riscv_emit_int_order_test (code
, 0, target
, op0
, op1
);
2302 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2305 riscv_expand_float_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2307 riscv_emit_float_compare (&code
, &op0
, &op1
);
2309 rtx cmp
= riscv_force_binary (word_mode
, code
, op0
, op1
);
2310 riscv_emit_set (target
, lowpart_subreg (SImode
, cmp
, word_mode
));
2313 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2316 riscv_expand_conditional_branch (rtx label
, rtx_code code
, rtx op0
, rtx op1
)
2318 if (FLOAT_MODE_P (GET_MODE (op1
)))
2319 riscv_emit_float_compare (&code
, &op0
, &op1
);
2321 riscv_emit_int_compare (&code
, &op0
, &op1
);
2323 rtx condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2324 emit_jump_insn (gen_condjump (condition
, label
));
2327 /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
2330 riscv_expand_conditional_move (rtx dest
, rtx cons
, rtx alt
, rtx_code code
,
2333 riscv_emit_int_compare (&code
, &op0
, &op1
);
2334 rtx cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
2335 emit_insn (gen_rtx_SET (dest
, gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), cond
,
2339 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2340 least PARM_BOUNDARY bits of alignment, but will be given anything up
2341 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2344 riscv_function_arg_boundary (machine_mode mode
, const_tree type
)
2346 unsigned int alignment
;
2348 /* Use natural alignment if the type is not aggregate data. */
2349 if (type
&& !AGGREGATE_TYPE_P (type
))
2350 alignment
= TYPE_ALIGN (TYPE_MAIN_VARIANT (type
));
2352 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2354 return MIN (PREFERRED_STACK_BOUNDARY
, MAX (PARM_BOUNDARY
, alignment
));
2357 /* If MODE represents an argument that can be passed or returned in
2358 floating-point registers, return the number of registers, else 0. */
2361 riscv_pass_mode_in_fpr_p (machine_mode mode
)
2363 if (GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FP_ARG
)
2365 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2368 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
2377 HOST_WIDE_INT offset
;
2378 } riscv_aggregate_field
;
2380 /* Identify subfields of aggregates that are candidates for passing in
2381 floating-point registers. */
2384 riscv_flatten_aggregate_field (const_tree type
,
2385 riscv_aggregate_field fields
[2],
2386 int n
, HOST_WIDE_INT offset
,
2387 bool ignore_zero_width_bit_field_p
)
2389 switch (TREE_CODE (type
))
2392 /* Can't handle incomplete types nor sizes that are not fixed. */
2393 if (!COMPLETE_TYPE_P (type
)
2394 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2395 || !tree_fits_uhwi_p (TYPE_SIZE (type
)))
2398 for (tree f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
2399 if (TREE_CODE (f
) == FIELD_DECL
)
2401 if (!TYPE_P (TREE_TYPE (f
)))
2404 /* The C++ front end strips zero-length bit-fields from structs.
2405 So we need to ignore them in the C front end to make C code
2406 compatible with C++ code. */
2407 if (ignore_zero_width_bit_field_p
2408 && DECL_BIT_FIELD (f
)
2409 && (DECL_SIZE (f
) == NULL_TREE
2410 || integer_zerop (DECL_SIZE (f
))))
2414 HOST_WIDE_INT pos
= offset
+ int_byte_position (f
);
2415 n
= riscv_flatten_aggregate_field (TREE_TYPE (f
),
2417 ignore_zero_width_bit_field_p
);
2426 HOST_WIDE_INT n_elts
;
2427 riscv_aggregate_field subfields
[2];
2428 tree index
= TYPE_DOMAIN (type
);
2429 tree elt_size
= TYPE_SIZE_UNIT (TREE_TYPE (type
));
2430 int n_subfields
= riscv_flatten_aggregate_field (TREE_TYPE (type
),
2431 subfields
, 0, offset
,
2432 ignore_zero_width_bit_field_p
);
2434 /* Can't handle incomplete types nor sizes that are not fixed. */
2435 if (n_subfields
<= 0
2436 || !COMPLETE_TYPE_P (type
)
2437 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2439 || !TYPE_MAX_VALUE (index
)
2440 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
2441 || !TYPE_MIN_VALUE (index
)
2442 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
2443 || !tree_fits_uhwi_p (elt_size
))
2446 n_elts
= 1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
2447 - tree_to_uhwi (TYPE_MIN_VALUE (index
));
2448 gcc_assert (n_elts
>= 0);
2450 for (HOST_WIDE_INT i
= 0; i
< n_elts
; i
++)
2451 for (int j
= 0; j
< n_subfields
; j
++)
2456 fields
[n
] = subfields
[j
];
2457 fields
[n
++].offset
+= i
* tree_to_uhwi (elt_size
);
2465 /* Complex type need consume 2 field, so n must be 0. */
2469 HOST_WIDE_INT elt_size
= GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type
)));
2471 if (elt_size
<= UNITS_PER_FP_ARG
)
2473 fields
[0].type
= TREE_TYPE (type
);
2474 fields
[0].offset
= offset
;
2475 fields
[1].type
= TREE_TYPE (type
);
2476 fields
[1].offset
= offset
+ elt_size
;
2486 && ((SCALAR_FLOAT_TYPE_P (type
)
2487 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FP_ARG
)
2488 || (INTEGRAL_TYPE_P (type
)
2489 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_WORD
)))
2491 fields
[n
].type
= type
;
2492 fields
[n
].offset
= offset
;
2500 /* Identify candidate aggregates for passing in floating-point registers.
2501 Candidates have at most two fields after flattening. */
2504 riscv_flatten_aggregate_argument (const_tree type
,
2505 riscv_aggregate_field fields
[2],
2506 bool ignore_zero_width_bit_field_p
)
2508 if (!type
|| TREE_CODE (type
) != RECORD_TYPE
)
2511 return riscv_flatten_aggregate_field (type
, fields
, 0, 0,
2512 ignore_zero_width_bit_field_p
);
2515 /* See whether TYPE is a record whose fields should be returned in one or
2516 two floating-point registers. If so, populate FIELDS accordingly. */
2519 riscv_pass_aggregate_in_fpr_pair_p (const_tree type
,
2520 riscv_aggregate_field fields
[2])
2522 static int warned
= 0;
2524 /* This is the old ABI, which differs for C++ and C. */
2525 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2526 for (int i
= 0; i
< n_old
; i
++)
2527 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2533 /* This is the new ABI, which is the same for C++ and C. */
2534 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2535 for (int i
= 0; i
< n_new
; i
++)
2536 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2542 if ((n_old
!= n_new
) && (warned
== 0))
2544 warning (0, "ABI for flattened struct with zero-length bit-fields "
2545 "changed in GCC 10");
2549 return n_new
> 0 ? n_new
: 0;
2552 /* See whether TYPE is a record whose fields should be returned in one or
2553 floating-point register and one integer register. If so, populate
2554 FIELDS accordingly. */
2557 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type
,
2558 riscv_aggregate_field fields
[2])
2560 static int warned
= 0;
2562 /* This is the old ABI, which differs for C++ and C. */
2563 unsigned num_int_old
= 0, num_float_old
= 0;
2564 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2565 for (int i
= 0; i
< n_old
; i
++)
2567 num_float_old
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2568 num_int_old
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2571 /* This is the new ABI, which is the same for C++ and C. */
2572 unsigned num_int_new
= 0, num_float_new
= 0;
2573 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2574 for (int i
= 0; i
< n_new
; i
++)
2576 num_float_new
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2577 num_int_new
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2580 if (((num_int_old
== 1 && num_float_old
== 1
2581 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
))
2582 || (num_int_new
== 1 && num_float_new
== 1
2583 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
)))
2586 warning (0, "ABI for flattened struct with zero-length bit-fields "
2587 "changed in GCC 10");
2591 return num_int_new
== 1 && num_float_new
== 1;
2594 /* Return the representation of an argument passed or returned in an FPR
2595 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2596 two modes may be different for structures like:
2598 struct __attribute__((packed)) foo { float f; }
2600 where the SFmode value "f" is passed in REGNO but the struct itself
2601 has mode BLKmode. */
2604 riscv_pass_fpr_single (machine_mode type_mode
, unsigned regno
,
2605 machine_mode value_mode
,
2606 HOST_WIDE_INT offset
)
2608 rtx x
= gen_rtx_REG (value_mode
, regno
);
2610 if (type_mode
!= value_mode
)
2612 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, GEN_INT (offset
));
2613 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
2618 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
2619 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
2620 byte offset for the first value, likewise MODE2 and OFFSET2 for the
2624 riscv_pass_fpr_pair (machine_mode mode
, unsigned regno1
,
2625 machine_mode mode1
, HOST_WIDE_INT offset1
,
2626 unsigned regno2
, machine_mode mode2
,
2627 HOST_WIDE_INT offset2
)
2629 return gen_rtx_PARALLEL
2632 gen_rtx_EXPR_LIST (VOIDmode
,
2633 gen_rtx_REG (mode1
, regno1
),
2635 gen_rtx_EXPR_LIST (VOIDmode
,
2636 gen_rtx_REG (mode2
, regno2
),
2637 GEN_INT (offset2
))));
2640 /* Fill INFO with information about a single argument, and return an
2641 RTL pattern to pass or return the argument. CUM is the cumulative
2642 state for earlier arguments. MODE is the mode of this argument and
2643 TYPE is its type (if known). NAMED is true if this is a named
2644 (fixed) argument rather than a variable one. RETURN_P is true if
2645 returning the argument, or false if passing the argument. */
2648 riscv_get_arg_info (struct riscv_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
2649 machine_mode mode
, const_tree type
, bool named
,
2652 unsigned num_bytes
, num_words
;
2653 unsigned fpr_base
= return_p
? FP_RETURN
: FP_ARG_FIRST
;
2654 unsigned gpr_base
= return_p
? GP_RETURN
: GP_ARG_FIRST
;
2655 unsigned alignment
= riscv_function_arg_boundary (mode
, type
);
2657 memset (info
, 0, sizeof (*info
));
2658 info
->gpr_offset
= cum
->num_gprs
;
2659 info
->fpr_offset
= cum
->num_fprs
;
2663 riscv_aggregate_field fields
[2];
2664 unsigned fregno
= fpr_base
+ info
->fpr_offset
;
2665 unsigned gregno
= gpr_base
+ info
->gpr_offset
;
2667 /* Pass one- or two-element floating-point aggregates in FPRs. */
2668 if ((info
->num_fprs
= riscv_pass_aggregate_in_fpr_pair_p (type
, fields
))
2669 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2670 switch (info
->num_fprs
)
2673 return riscv_pass_fpr_single (mode
, fregno
,
2674 TYPE_MODE (fields
[0].type
),
2678 return riscv_pass_fpr_pair (mode
, fregno
,
2679 TYPE_MODE (fields
[0].type
),
2682 TYPE_MODE (fields
[1].type
),
2689 /* Pass real and complex floating-point numbers in FPRs. */
2690 if ((info
->num_fprs
= riscv_pass_mode_in_fpr_p (mode
))
2691 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2692 switch (GET_MODE_CLASS (mode
))
2695 return gen_rtx_REG (mode
, fregno
);
2697 case MODE_COMPLEX_FLOAT
:
2698 return riscv_pass_fpr_pair (mode
, fregno
, GET_MODE_INNER (mode
), 0,
2699 fregno
+ 1, GET_MODE_INNER (mode
),
2700 GET_MODE_UNIT_SIZE (mode
));
2706 /* Pass structs with one float and one integer in an FPR and a GPR. */
2707 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type
, fields
)
2708 && info
->gpr_offset
< MAX_ARGS_IN_REGISTERS
2709 && info
->fpr_offset
< MAX_ARGS_IN_REGISTERS
)
2714 if (!SCALAR_FLOAT_TYPE_P (fields
[0].type
))
2715 std::swap (fregno
, gregno
);
2717 return riscv_pass_fpr_pair (mode
, fregno
, TYPE_MODE (fields
[0].type
),
2719 gregno
, TYPE_MODE (fields
[1].type
),
2724 /* Work out the size of the argument. */
2725 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2726 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2728 /* Doubleword-aligned varargs start on an even register boundary. */
2729 if (!named
&& num_bytes
!= 0 && alignment
> BITS_PER_WORD
)
2730 info
->gpr_offset
+= info
->gpr_offset
& 1;
2732 /* Partition the argument between registers and stack. */
2734 info
->num_gprs
= MIN (num_words
, MAX_ARGS_IN_REGISTERS
- info
->gpr_offset
);
2735 info
->stack_p
= (num_words
- info
->num_gprs
) != 0;
2737 if (info
->num_gprs
|| return_p
)
2738 return gen_rtx_REG (mode
, gpr_base
+ info
->gpr_offset
);
2743 /* Implement TARGET_FUNCTION_ARG. */
2746 riscv_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
2748 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2749 struct riscv_arg_info info
;
2751 if (arg
.end_marker_p ())
2754 return riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2757 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
2760 riscv_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2761 const_tree type
, bool named
)
2763 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2764 struct riscv_arg_info info
;
2766 riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2768 /* Advance the register count. This has the effect of setting
2769 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
2770 argument required us to skip the final GPR and pass the whole
2771 argument on the stack. */
2772 cum
->num_fprs
= info
.fpr_offset
+ info
.num_fprs
;
2773 cum
->num_gprs
= info
.gpr_offset
+ info
.num_gprs
;
2776 /* Implement TARGET_ARG_PARTIAL_BYTES. */
2779 riscv_arg_partial_bytes (cumulative_args_t cum
,
2780 const function_arg_info
&generic_arg
)
2782 struct riscv_arg_info arg
;
2784 riscv_get_arg_info (&arg
, get_cumulative_args (cum
), generic_arg
.mode
,
2785 generic_arg
.type
, generic_arg
.named
, false);
2786 return arg
.stack_p
? arg
.num_gprs
* UNITS_PER_WORD
: 0;
2789 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
2790 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
2791 VALTYPE is null and MODE is the mode of the return value. */
2794 riscv_function_value (const_tree type
, const_tree func
, machine_mode mode
)
2796 struct riscv_arg_info info
;
2797 CUMULATIVE_ARGS args
;
2801 int unsigned_p
= TYPE_UNSIGNED (type
);
2803 mode
= TYPE_MODE (type
);
2805 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
2806 return values, promote the mode here too. */
2807 mode
= promote_function_mode (type
, mode
, &unsigned_p
, func
, 1);
2810 memset (&args
, 0, sizeof args
);
2811 return riscv_get_arg_info (&info
, &args
, mode
, type
, true, true);
2814 /* Implement TARGET_PASS_BY_REFERENCE. */
2817 riscv_pass_by_reference (cumulative_args_t cum_v
, const function_arg_info
&arg
)
2819 HOST_WIDE_INT size
= arg
.type_size_in_bytes ();
2820 struct riscv_arg_info info
;
2821 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2823 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
2824 never pass variadic arguments in floating-point registers, so we can
2825 avoid the call to riscv_get_arg_info in this case. */
2828 /* Don't pass by reference if we can use a floating-point register. */
2829 riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2834 /* Pass by reference if the data do not fit in two integer registers. */
2835 return !IN_RANGE (size
, 0, 2 * UNITS_PER_WORD
);
2838 /* Implement TARGET_RETURN_IN_MEMORY. */
2841 riscv_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
2843 CUMULATIVE_ARGS args
;
2844 cumulative_args_t cum
= pack_cumulative_args (&args
);
2846 /* The rules for returning in memory are the same as for passing the
2847 first named argument by reference. */
2848 memset (&args
, 0, sizeof args
);
2849 function_arg_info
arg (const_cast<tree
> (type
), /*named=*/true);
2850 return riscv_pass_by_reference (cum
, arg
);
2853 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
2856 riscv_setup_incoming_varargs (cumulative_args_t cum
,
2857 const function_arg_info
&arg
,
2858 int *pretend_size ATTRIBUTE_UNUSED
, int no_rtl
)
2860 CUMULATIVE_ARGS local_cum
;
2863 /* The caller has advanced CUM up to, but not beyond, the last named
2864 argument. Advance a local copy of CUM past the last "real" named
2865 argument, to find out how many registers are left over. */
2866 local_cum
= *get_cumulative_args (cum
);
2867 riscv_function_arg_advance (pack_cumulative_args (&local_cum
),
2868 arg
.mode
, arg
.type
, arg
.named
);
2870 /* Found out how many registers we need to save. */
2871 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
2873 if (!no_rtl
&& gp_saved
> 0)
2875 rtx ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
2876 REG_PARM_STACK_SPACE (cfun
->decl
)
2877 - gp_saved
* UNITS_PER_WORD
);
2878 rtx mem
= gen_frame_mem (BLKmode
, ptr
);
2879 set_mem_alias_set (mem
, get_varargs_alias_set ());
2881 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
2884 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
2885 cfun
->machine
->varargs_size
= gp_saved
* UNITS_PER_WORD
;
2888 /* Handle an attribute requiring a FUNCTION_DECL;
2889 arguments as in struct attribute_spec.handler. */
2891 riscv_handle_fndecl_attribute (tree
*node
, tree name
,
2892 tree args ATTRIBUTE_UNUSED
,
2893 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2895 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2897 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2899 *no_add_attrs
= true;
2905 /* Verify type based attributes. NODE is the what the attribute is being
2906 applied to. NAME is the attribute name. ARGS are the attribute args.
2907 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
2908 the attribute should be ignored. */
2911 riscv_handle_type_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
2912 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2914 /* Check for an argument. */
2915 if (is_attribute_p ("interrupt", name
))
2919 tree cst
= TREE_VALUE (args
);
2922 if (TREE_CODE (cst
) != STRING_CST
)
2924 warning (OPT_Wattributes
,
2925 "%qE attribute requires a string argument",
2927 *no_add_attrs
= true;
2931 string
= TREE_STRING_POINTER (cst
);
2932 if (strcmp (string
, "user") && strcmp (string
, "supervisor")
2933 && strcmp (string
, "machine"))
2935 warning (OPT_Wattributes
,
2936 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"",
2938 *no_add_attrs
= true;
2946 /* Return true if function TYPE is an interrupt function. */
2948 riscv_interrupt_type_p (tree type
)
2950 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
2953 /* Return true if FUNC is a naked function. */
2955 riscv_naked_function_p (tree func
)
2957 tree func_decl
= func
;
2958 if (func
== NULL_TREE
)
2959 func_decl
= current_function_decl
;
2960 return NULL_TREE
!= lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl
));
2963 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
2965 riscv_allocate_stack_slots_for_args ()
2967 /* Naked functions should not allocate stack slots for arguments. */
2968 return !riscv_naked_function_p (current_function_decl
);
2971 /* Implement TARGET_WARN_FUNC_RETURN. */
2973 riscv_warn_func_return (tree decl
)
2975 /* Naked functions are implemented entirely in assembly, including the
2976 return sequence, so suppress warnings about this. */
2977 return !riscv_naked_function_p (decl
);
2980 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
2983 riscv_va_start (tree valist
, rtx nextarg
)
2985 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
2986 std_expand_builtin_va_start (valist
, nextarg
);
2989 /* Make ADDR suitable for use as a call or sibcall target. */
2992 riscv_legitimize_call_address (rtx addr
)
2994 if (!call_insn_operand (addr
, VOIDmode
))
2996 rtx reg
= RISCV_PROLOGUE_TEMP (Pmode
);
2997 riscv_emit_move (reg
, addr
);
3003 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3004 Assume that the areas do not overlap. */
3007 riscv_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
3009 HOST_WIDE_INT offset
, delta
;
3010 unsigned HOST_WIDE_INT bits
;
3012 enum machine_mode mode
;
3015 bits
= MAX (BITS_PER_UNIT
,
3016 MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
))));
3018 mode
= mode_for_size (bits
, MODE_INT
, 0).require ();
3019 delta
= bits
/ BITS_PER_UNIT
;
3021 /* Allocate a buffer for the temporary registers. */
3022 regs
= XALLOCAVEC (rtx
, length
/ delta
);
3024 /* Load as many BITS-sized chunks as possible. Use a normal load if
3025 the source has enough alignment, otherwise use left/right pairs. */
3026 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3028 regs
[i
] = gen_reg_rtx (mode
);
3029 riscv_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
3032 /* Copy the chunks to the destination. */
3033 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3034 riscv_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
3036 /* Mop up any left-over bytes. */
3037 if (offset
< length
)
3039 src
= adjust_address (src
, BLKmode
, offset
);
3040 dest
= adjust_address (dest
, BLKmode
, offset
);
3041 move_by_pieces (dest
, src
, length
- offset
,
3042 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), RETURN_BEGIN
);
3046 /* Helper function for doing a loop-based block operation on memory
3047 reference MEM. Each iteration of the loop will operate on LENGTH
3050 Create a new base register for use within the loop and point it to
3051 the start of MEM. Create a new memory reference that uses this
3052 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3055 riscv_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
3056 rtx
*loop_reg
, rtx
*loop_mem
)
3058 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
3060 /* Although the new mem does not refer to a known location,
3061 it does keep up to LENGTH bytes of alignment. */
3062 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
3063 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
3066 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
3067 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
3068 the memory regions do not overlap. */
3071 riscv_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
3072 HOST_WIDE_INT bytes_per_iter
)
3074 rtx label
, src_reg
, dest_reg
, final_src
, test
;
3075 HOST_WIDE_INT leftover
;
3077 leftover
= length
% bytes_per_iter
;
3080 /* Create registers and memory references for use within the loop. */
3081 riscv_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
3082 riscv_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
3084 /* Calculate the value that SRC_REG should have after the last iteration
3086 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
3089 /* Emit the start of the loop. */
3090 label
= gen_label_rtx ();
3093 /* Emit the loop body. */
3094 riscv_block_move_straight (dest
, src
, bytes_per_iter
);
3096 /* Move on to the next block. */
3097 riscv_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
3098 riscv_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
3100 /* Emit the loop condition. */
3101 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
3102 if (Pmode
== DImode
)
3103 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
3105 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
3107 /* Mop up any left-over bytes. */
3109 riscv_block_move_straight (dest
, src
, leftover
);
3111 emit_insn(gen_nop ());
3114 /* Expand a cpymemsi instruction, which copies LENGTH bytes from
3115 memory reference SRC to memory reference DEST. */
3118 riscv_expand_block_move (rtx dest
, rtx src
, rtx length
)
3120 if (CONST_INT_P (length
))
3122 HOST_WIDE_INT factor
, align
;
3124 align
= MIN (MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), BITS_PER_WORD
);
3125 factor
= BITS_PER_WORD
/ align
;
3127 if (optimize_function_for_size_p (cfun
)
3128 && INTVAL (length
) * factor
* UNITS_PER_WORD
> MOVE_RATIO (false))
3131 if (INTVAL (length
) <= RISCV_MAX_MOVE_BYTES_STRAIGHT
/ factor
)
3133 riscv_block_move_straight (dest
, src
, INTVAL (length
));
3136 else if (optimize
&& align
>= BITS_PER_WORD
)
3138 unsigned min_iter_words
3139 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER
/ UNITS_PER_WORD
;
3140 unsigned iter_words
= min_iter_words
;
3141 HOST_WIDE_INT bytes
= INTVAL (length
), words
= bytes
/ UNITS_PER_WORD
;
3143 /* Lengthen the loop body if it shortens the tail. */
3144 for (unsigned i
= min_iter_words
; i
< min_iter_words
* 2 - 1; i
++)
3146 unsigned cur_cost
= iter_words
+ words
% iter_words
;
3147 unsigned new_cost
= i
+ words
% i
;
3148 if (new_cost
<= cur_cost
)
3152 riscv_block_move_loop (dest
, src
, bytes
, iter_words
* UNITS_PER_WORD
);
3159 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
3160 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
3163 riscv_print_operand_reloc (FILE *file
, rtx op
, bool hi_reloc
)
3167 switch (riscv_classify_symbolic_expression (op
))
3169 case SYMBOL_ABSOLUTE
:
3170 reloc
= hi_reloc
? "%hi" : "%lo";
3174 reloc
= hi_reloc
? "%pcrel_hi" : "%pcrel_lo";
3178 reloc
= hi_reloc
? "%tprel_hi" : "%tprel_lo";
3185 fprintf (file
, "%s(", reloc
);
3186 output_addr_const (file
, riscv_strip_unspec_address (op
));
3190 /* Return true if the .AQ suffix should be added to an AMO to implement the
3191 acquire portion of memory model MODEL. */
3194 riscv_memmodel_needs_amo_acquire (enum memmodel model
)
3198 case MEMMODEL_ACQ_REL
:
3199 case MEMMODEL_SEQ_CST
:
3200 case MEMMODEL_SYNC_SEQ_CST
:
3201 case MEMMODEL_ACQUIRE
:
3202 case MEMMODEL_CONSUME
:
3203 case MEMMODEL_SYNC_ACQUIRE
:
3206 case MEMMODEL_RELEASE
:
3207 case MEMMODEL_SYNC_RELEASE
:
3208 case MEMMODEL_RELAXED
:
3216 /* Return true if a FENCE should be emitted to before a memory access to
3217 implement the release portion of memory model MODEL. */
3220 riscv_memmodel_needs_release_fence (enum memmodel model
)
3224 case MEMMODEL_ACQ_REL
:
3225 case MEMMODEL_SEQ_CST
:
3226 case MEMMODEL_SYNC_SEQ_CST
:
3227 case MEMMODEL_RELEASE
:
3228 case MEMMODEL_SYNC_RELEASE
:
3231 case MEMMODEL_ACQUIRE
:
3232 case MEMMODEL_CONSUME
:
3233 case MEMMODEL_SYNC_ACQUIRE
:
3234 case MEMMODEL_RELAXED
:
3242 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3244 'h' Print the high-part relocation associated with OP, after stripping
3246 'R' Print the low-part relocation associated with OP.
3247 'C' Print the integer branch condition for comparison OP.
3248 'A' Print the atomic operation suffix for memory model OP.
3249 'F' Print a FENCE if the memory model requires a release.
3250 'z' Print x0 if OP is zero, otherwise print OP normally.
3251 'i' Print i if the operand is not a register. */
3254 riscv_print_operand (FILE *file
, rtx op
, int letter
)
3256 machine_mode mode
= GET_MODE (op
);
3257 enum rtx_code code
= GET_CODE (op
);
3264 riscv_print_operand_reloc (file
, op
, true);
3268 riscv_print_operand_reloc (file
, op
, false);
3272 /* The RTL names match the instruction names. */
3273 fputs (GET_RTX_NAME (code
), file
);
3277 if (riscv_memmodel_needs_amo_acquire ((enum memmodel
) INTVAL (op
)))
3278 fputs (".aq", file
);
3282 if (riscv_memmodel_needs_release_fence ((enum memmodel
) INTVAL (op
)))
3283 fputs ("fence iorw,ow; ", file
);
3295 if (letter
&& letter
!= 'z')
3296 output_operand_lossage ("invalid use of '%%%c'", letter
);
3297 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
3301 if (letter
&& letter
!= 'z')
3302 output_operand_lossage ("invalid use of '%%%c'", letter
);
3304 output_address (mode
, XEXP (op
, 0));
3308 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
3309 fputs (reg_names
[GP_REG_FIRST
], file
);
3310 else if (letter
&& letter
!= 'z')
3311 output_operand_lossage ("invalid use of '%%%c'", letter
);
3313 output_addr_const (file
, riscv_strip_unspec_address (op
));
3319 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3322 riscv_print_operand_address (FILE *file
, machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3324 struct riscv_address_info addr
;
3326 if (riscv_classify_address (&addr
, x
, word_mode
, true))
3330 riscv_print_operand (file
, addr
.offset
, 0);
3331 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3334 case ADDRESS_LO_SUM
:
3335 riscv_print_operand_reloc (file
, addr
.offset
, false);
3336 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3339 case ADDRESS_CONST_INT
:
3340 output_addr_const (file
, x
);
3341 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
3344 case ADDRESS_SYMBOLIC
:
3345 output_addr_const (file
, riscv_strip_unspec_address (x
));
3352 riscv_size_ok_for_small_data_p (int size
)
3354 return g_switch_value
&& IN_RANGE (size
, 1, g_switch_value
);
3357 /* Return true if EXP should be placed in the small data section. */
3360 riscv_in_small_data_p (const_tree x
)
3362 if (TREE_CODE (x
) == STRING_CST
|| TREE_CODE (x
) == FUNCTION_DECL
)
3365 if (TREE_CODE (x
) == VAR_DECL
&& DECL_SECTION_NAME (x
))
3367 const char *sec
= DECL_SECTION_NAME (x
);
3368 return strcmp (sec
, ".sdata") == 0 || strcmp (sec
, ".sbss") == 0;
3371 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x
)));
3374 /* Switch to the appropriate section for output of DECL. */
3377 riscv_select_section (tree decl
, int reloc
,
3378 unsigned HOST_WIDE_INT align
)
3380 switch (categorize_decl_for_section (decl
, reloc
))
3382 case SECCAT_SRODATA
:
3383 return get_named_section (decl
, ".srodata", reloc
);
3386 return default_elf_select_section (decl
, reloc
, align
);
3390 /* Return a section for X, handling small data. */
3393 riscv_elf_select_rtx_section (machine_mode mode
, rtx x
,
3394 unsigned HOST_WIDE_INT align
)
3396 section
*s
= default_elf_select_rtx_section (mode
, x
, align
);
3398 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode
)))
3400 if (strncmp (s
->named
.name
, ".rodata.cst", strlen (".rodata.cst")) == 0)
3402 /* Rename .rodata.cst* to .srodata.cst*. */
3403 char *name
= (char *) alloca (strlen (s
->named
.name
) + 2);
3404 sprintf (name
, ".s%s", s
->named
.name
+ 1);
3405 return get_section (name
, s
->named
.common
.flags
, NULL
);
3408 if (s
== data_section
)
3409 return sdata_section
;
3415 /* Make the last instruction frame-related and note that it performs
3416 the operation described by FRAME_PATTERN. */
3419 riscv_set_frame_expr (rtx frame_pattern
)
3423 insn
= get_last_insn ();
3424 RTX_FRAME_RELATED_P (insn
) = 1;
3425 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3430 /* Return a frame-related rtx that stores REG at MEM.
3431 REG must be a single register. */
3434 riscv_frame_set (rtx mem
, rtx reg
)
3436 rtx set
= gen_rtx_SET (mem
, reg
);
3437 RTX_FRAME_RELATED_P (set
) = 1;
3441 /* Return true if the current function must save register REGNO. */
3444 riscv_save_reg_p (unsigned int regno
)
3446 bool call_saved
= !global_regs
[regno
] && !call_used_regs
[regno
];
3447 bool might_clobber
= crtl
->saves_all_registers
3448 || df_regs_ever_live_p (regno
);
3450 if (call_saved
&& might_clobber
)
3453 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
3456 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
3459 /* If this is an interrupt handler, then must save extra registers. */
3460 if (cfun
->machine
->interrupt_handler_p
)
3462 /* zero register is always zero. */
3463 if (regno
== GP_REG_FIRST
)
3466 /* The function will return the stack pointer to its original value. */
3467 if (regno
== STACK_POINTER_REGNUM
)
3470 /* By convention, we assume that gp and tp are safe. */
3471 if (regno
== GP_REGNUM
|| regno
== THREAD_POINTER_REGNUM
)
3474 /* We must save every register used in this function. If this is not a
3475 leaf function, then we must save all temporary registers. */
3476 if (df_regs_ever_live_p (regno
)
3477 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
3484 /* Determine whether to call GPR save/restore routines. */
3486 riscv_use_save_libcall (const struct riscv_frame_info
*frame
)
3488 if (!TARGET_SAVE_RESTORE
|| crtl
->calls_eh_return
|| frame_pointer_needed
3489 || cfun
->machine
->interrupt_handler_p
)
3492 return frame
->save_libcall_adjustment
!= 0;
3495 /* Determine which GPR save/restore routine to call. */
3498 riscv_save_libcall_count (unsigned mask
)
3500 for (unsigned n
= GP_REG_LAST
; n
> GP_REG_FIRST
; n
--)
3501 if (BITSET_P (mask
, n
))
3502 return CALLEE_SAVED_REG_NUMBER (n
) + 1;
3506 /* Populate the current function's riscv_frame_info structure.
3508 RISC-V stack frames grown downward. High addresses are at the top.
3510 +-------------------------------+
3512 | incoming stack arguments |
3514 +-------------------------------+ <-- incoming stack pointer
3516 | callee-allocated save area |
3517 | for arguments that are |
3518 | split between registers and |
3521 +-------------------------------+ <-- arg_pointer_rtx
3523 | callee-allocated save area |
3524 | for register varargs |
3526 +-------------------------------+ <-- hard_frame_pointer_rtx;
3527 | | stack_pointer_rtx + gp_sp_offset
3528 | GPR save area | + UNITS_PER_WORD
3530 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3531 | | + UNITS_PER_HWVALUE
3534 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3538 P +-------------------------------+
3540 | outgoing stack arguments |
3542 +-------------------------------+ <-- stack_pointer_rtx
3544 Dynamic stack allocations such as alloca insert data at point P.
3545 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3546 hard_frame_pointer_rtx unchanged. */
3548 static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info
*frame
);
3551 riscv_compute_frame_info (void)
3553 struct riscv_frame_info
*frame
;
3554 HOST_WIDE_INT offset
;
3555 bool interrupt_save_t1
= false;
3556 unsigned int regno
, i
, num_x_saved
= 0, num_f_saved
= 0;
3558 frame
= &cfun
->machine
->frame
;
3560 /* In an interrupt function, if we have a large frame, then we need to
3561 save/restore t1. We check for this before clearing the frame struct. */
3562 if (cfun
->machine
->interrupt_handler_p
)
3564 HOST_WIDE_INT step1
= riscv_first_stack_step (frame
);
3565 if (! SMALL_OPERAND (frame
->total_size
- step1
))
3566 interrupt_save_t1
= true;
3569 memset (frame
, 0, sizeof (*frame
));
3571 if (!cfun
->machine
->naked_p
)
3573 /* Find out which GPRs we need to save. */
3574 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3575 if (riscv_save_reg_p (regno
)
3576 || (interrupt_save_t1
&& (regno
== T1_REGNUM
)))
3577 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3579 /* If this function calls eh_return, we must also save and restore the
3580 EH data registers. */
3581 if (crtl
->calls_eh_return
)
3582 for (i
= 0; (regno
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
; i
++)
3583 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3585 /* Find out which FPRs we need to save. This loop must iterate over
3586 the same space as its companion in riscv_for_each_saved_reg. */
3587 if (TARGET_HARD_FLOAT
)
3588 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3589 if (riscv_save_reg_p (regno
))
3590 frame
->fmask
|= 1 << (regno
- FP_REG_FIRST
), num_f_saved
++;
3593 /* At the bottom of the frame are any outgoing stack arguments. */
3594 offset
= RISCV_STACK_ALIGN (crtl
->outgoing_args_size
);
3595 /* Next are local stack variables. */
3596 offset
+= RISCV_STACK_ALIGN (get_frame_size ());
3597 /* The virtual frame pointer points above the local variables. */
3598 frame
->frame_pointer_offset
= offset
;
3599 /* Next are the callee-saved FPRs. */
3601 offset
+= RISCV_STACK_ALIGN (num_f_saved
* UNITS_PER_FP_REG
);
3602 frame
->fp_sp_offset
= offset
- UNITS_PER_FP_REG
;
3603 /* Next are the callee-saved GPRs. */
3606 unsigned x_save_size
= RISCV_STACK_ALIGN (num_x_saved
* UNITS_PER_WORD
);
3607 unsigned num_save_restore
= 1 + riscv_save_libcall_count (frame
->mask
);
3609 /* Only use save/restore routines if they don't alter the stack size. */
3610 if (RISCV_STACK_ALIGN (num_save_restore
* UNITS_PER_WORD
) == x_save_size
)
3612 /* Libcall saves/restores 3 registers at once, so we need to
3613 allocate 12 bytes for callee-saved register. */
3615 x_save_size
= 3 * UNITS_PER_WORD
;
3617 frame
->save_libcall_adjustment
= x_save_size
;
3620 offset
+= x_save_size
;
3622 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
3623 /* The hard frame pointer points above the callee-saved GPRs. */
3624 frame
->hard_frame_pointer_offset
= offset
;
3625 /* Above the hard frame pointer is the callee-allocated varags save area. */
3626 offset
+= RISCV_STACK_ALIGN (cfun
->machine
->varargs_size
);
3627 /* Next is the callee-allocated area for pretend stack arguments. */
3628 offset
+= RISCV_STACK_ALIGN (crtl
->args
.pretend_args_size
);
3629 /* Arg pointer must be below pretend args, but must be above alignment
3631 frame
->arg_pointer_offset
= offset
- crtl
->args
.pretend_args_size
;
3632 frame
->total_size
= offset
;
3633 /* Next points the incoming stack pointer and any incoming arguments. */
3635 /* Only use save/restore routines when the GPRs are atop the frame. */
3636 if (frame
->hard_frame_pointer_offset
!= frame
->total_size
)
3637 frame
->save_libcall_adjustment
= 0;
3640 /* Make sure that we're not trying to eliminate to the wrong hard frame
3644 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
3646 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
3649 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
3650 or argument pointer. TO is either the stack pointer or hard frame
3654 riscv_initial_elimination_offset (int from
, int to
)
3656 HOST_WIDE_INT src
, dest
;
3658 riscv_compute_frame_info ();
3660 if (to
== HARD_FRAME_POINTER_REGNUM
)
3661 dest
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
3662 else if (to
== STACK_POINTER_REGNUM
)
3663 dest
= 0; /* The stack pointer is the base of all offsets, hence 0. */
3667 if (from
== FRAME_POINTER_REGNUM
)
3668 src
= cfun
->machine
->frame
.frame_pointer_offset
;
3669 else if (from
== ARG_POINTER_REGNUM
)
3670 src
= cfun
->machine
->frame
.arg_pointer_offset
;
3677 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
3681 riscv_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
3686 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
3689 /* Emit code to change the current function's return address to
3690 ADDRESS. SCRATCH is available as a scratch register, if needed.
3691 ADDRESS and SCRATCH are both word-mode GPRs. */
3694 riscv_set_return_address (rtx address
, rtx scratch
)
3698 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
3699 slot_address
= riscv_add_offset (scratch
, stack_pointer_rtx
,
3700 cfun
->machine
->frame
.gp_sp_offset
);
3701 riscv_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
3704 /* A function to save or store a register. The first argument is the
3705 register and the second is the stack slot. */
3706 typedef void (*riscv_save_restore_fn
) (rtx
, rtx
);
3708 /* Use FN to save or restore register REGNO. MODE is the register's
3709 mode and OFFSET is the offset of its save slot from the current
3713 riscv_save_restore_reg (machine_mode mode
, int regno
,
3714 HOST_WIDE_INT offset
, riscv_save_restore_fn fn
)
3718 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
, offset
));
3719 fn (gen_rtx_REG (mode
, regno
), mem
);
3722 /* Call FN for each register that is saved by the current function.
3723 SP_OFFSET is the offset of the current stack pointer from the start
3727 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset
, riscv_save_restore_fn fn
,
3728 bool epilogue
, bool maybe_eh_return
)
3730 HOST_WIDE_INT offset
;
3732 /* Save the link register and s-registers. */
3733 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
3734 for (unsigned int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3735 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3737 bool handle_reg
= TRUE
;
3739 /* If this is a normal return in a function that calls the eh_return
3740 builtin, then do not restore the eh return data registers as that
3741 would clobber the return value. But we do still need to save them
3742 in the prologue, and restore them for an exception return, so we
3743 need special handling here. */
3744 if (epilogue
&& !maybe_eh_return
&& crtl
->calls_eh_return
)
3746 unsigned int i
, regnum
;
3748 for (i
= 0; (regnum
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
;
3750 if (regno
== regnum
)
3758 riscv_save_restore_reg (word_mode
, regno
, offset
, fn
);
3759 offset
-= UNITS_PER_WORD
;
3762 /* This loop must iterate over the same space as its companion in
3763 riscv_compute_frame_info. */
3764 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
3765 for (unsigned int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3766 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
3768 machine_mode mode
= TARGET_DOUBLE_FLOAT
? DFmode
: SFmode
;
3770 riscv_save_restore_reg (mode
, regno
, offset
, fn
);
3771 offset
-= GET_MODE_SIZE (mode
);
3775 /* Save register REG to MEM. Make the instruction frame-related. */
3778 riscv_save_reg (rtx reg
, rtx mem
)
3780 riscv_emit_move (mem
, reg
);
3781 riscv_set_frame_expr (riscv_frame_set (mem
, reg
));
3784 /* Restore register REG from MEM. */
3787 riscv_restore_reg (rtx reg
, rtx mem
)
3789 rtx insn
= riscv_emit_move (reg
, mem
);
3790 rtx dwarf
= NULL_RTX
;
3791 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3793 if (epilogue_cfa_sp_offset
&& REGNO (reg
) == HARD_FRAME_POINTER_REGNUM
)
3795 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3796 GEN_INT (epilogue_cfa_sp_offset
));
3797 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3800 REG_NOTES (insn
) = dwarf
;
3801 RTX_FRAME_RELATED_P (insn
) = 1;
3804 /* Return the code to invoke the GPR save routine. */
3807 riscv_output_gpr_save (unsigned mask
)
3810 unsigned n
= riscv_save_libcall_count (mask
);
3812 ssize_t bytes
= snprintf (s
, sizeof (s
), "call\tt0,__riscv_save_%u", n
);
3813 gcc_assert ((size_t) bytes
< sizeof (s
));
3818 /* For stack frames that can't be allocated with a single ADDI instruction,
3819 compute the best value to initially allocate. It must at a minimum
3820 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
3821 try to pick a value that will allow compression of the register saves
3822 without adding extra instructions. */
3824 static HOST_WIDE_INT
3825 riscv_first_stack_step (struct riscv_frame_info
*frame
)
3827 if (SMALL_OPERAND (frame
->total_size
))
3828 return frame
->total_size
;
3830 HOST_WIDE_INT min_first_step
=
3831 RISCV_STACK_ALIGN (frame
->total_size
- frame
->fp_sp_offset
);
3832 HOST_WIDE_INT max_first_step
= IMM_REACH
/ 2 - PREFERRED_STACK_BOUNDARY
/ 8;
3833 HOST_WIDE_INT min_second_step
= frame
->total_size
- max_first_step
;
3834 gcc_assert (min_first_step
<= max_first_step
);
3836 /* As an optimization, use the least-significant bits of the total frame
3837 size, so that the second adjustment step is just LUI + ADD. */
3838 if (!SMALL_OPERAND (min_second_step
)
3839 && frame
->total_size
% IMM_REACH
< IMM_REACH
/ 2
3840 && frame
->total_size
% IMM_REACH
>= min_first_step
)
3841 return frame
->total_size
% IMM_REACH
;
3845 /* If we need two subtracts, and one is small enough to allow compressed
3846 loads and stores, then put that one first. */
3847 if (IN_RANGE (min_second_step
, 0,
3848 (TARGET_64BIT
? SDSP_REACH
: SWSP_REACH
)))
3849 return MAX (min_second_step
, min_first_step
);
3851 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
3852 with the minimum first step, so that we can get compressed loads and
3854 else if (!SMALL_OPERAND (min_second_step
))
3855 return min_first_step
;
3858 return max_first_step
;
3862 riscv_adjust_libcall_cfi_prologue ()
3864 rtx dwarf
= NULL_RTX
;
3865 rtx adjust_sp_rtx
, reg
, mem
, insn
;
3866 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3869 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3870 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3872 /* The save order is ra, s0, s1, s2 to s11. */
3873 if (regno
== RETURN_ADDR_REGNUM
)
3874 offset
= saved_size
- UNITS_PER_WORD
;
3875 else if (regno
== S0_REGNUM
)
3876 offset
= saved_size
- UNITS_PER_WORD
* 2;
3877 else if (regno
== S1_REGNUM
)
3878 offset
= saved_size
- UNITS_PER_WORD
* 3;
3880 offset
= saved_size
- ((regno
- S2_REGNUM
+ 4) * UNITS_PER_WORD
);
3882 reg
= gen_rtx_REG (SImode
, regno
);
3883 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3887 insn
= gen_rtx_SET (mem
, reg
);
3888 dwarf
= alloc_reg_note (REG_CFA_OFFSET
, insn
, dwarf
);
3891 /* Debug info for adjust sp. */
3892 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3893 stack_pointer_rtx
, GEN_INT (-saved_size
));
3894 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
3900 riscv_emit_stack_tie (void)
3902 if (Pmode
== SImode
)
3903 emit_insn (gen_stack_tiesi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3905 emit_insn (gen_stack_tiedi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3908 /* Expand the "prologue" pattern. */
3911 riscv_expand_prologue (void)
3913 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
3914 HOST_WIDE_INT size
= frame
->total_size
;
3915 unsigned mask
= frame
->mask
;
3918 if (flag_stack_usage_info
)
3919 current_function_static_stack_size
= size
;
3921 if (cfun
->machine
->naked_p
)
3924 /* When optimizing for size, call a subroutine to save the registers. */
3925 if (riscv_use_save_libcall (frame
))
3927 rtx dwarf
= NULL_RTX
;
3928 dwarf
= riscv_adjust_libcall_cfi_prologue ();
3930 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
3931 size
-= frame
->save_libcall_adjustment
;
3932 insn
= emit_insn (gen_gpr_save (GEN_INT (mask
)));
3934 RTX_FRAME_RELATED_P (insn
) = 1;
3935 REG_NOTES (insn
) = dwarf
;
3938 /* Save the registers. */
3939 if ((frame
->mask
| frame
->fmask
) != 0)
3941 HOST_WIDE_INT step1
= MIN (size
, riscv_first_stack_step (frame
));
3943 insn
= gen_add3_insn (stack_pointer_rtx
,
3946 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3948 riscv_for_each_saved_reg (size
, riscv_save_reg
, false, false);
3951 frame
->mask
= mask
; /* Undo the above fib. */
3953 /* Set up the frame pointer, if we're using one. */
3954 if (frame_pointer_needed
)
3956 insn
= gen_add3_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
,
3957 GEN_INT (frame
->hard_frame_pointer_offset
- size
));
3958 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3960 riscv_emit_stack_tie ();
3963 /* Allocate the rest of the frame. */
3966 if (SMALL_OPERAND (-size
))
3968 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3970 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3974 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), GEN_INT (-size
));
3975 emit_insn (gen_add3_insn (stack_pointer_rtx
,
3977 RISCV_PROLOGUE_TEMP (Pmode
)));
3979 /* Describe the effect of the previous instructions. */
3980 insn
= plus_constant (Pmode
, stack_pointer_rtx
, -size
);
3981 insn
= gen_rtx_SET (stack_pointer_rtx
, insn
);
3982 riscv_set_frame_expr (insn
);
3988 riscv_adjust_libcall_cfi_epilogue ()
3990 rtx dwarf
= NULL_RTX
;
3991 rtx adjust_sp_rtx
, reg
;
3992 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3994 /* Debug info for adjust sp. */
3995 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3996 stack_pointer_rtx
, GEN_INT (saved_size
));
3997 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
4000 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4001 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
4003 reg
= gen_rtx_REG (SImode
, regno
);
4004 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
4010 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
4011 style says which. */
4014 riscv_expand_epilogue (int style
)
4016 /* Split the frame into two. STEP1 is the amount of stack we should
4017 deallocate before restoring the registers. STEP2 is the amount we
4018 should deallocate afterwards.
4020 Start off by assuming that no registers need to be restored. */
4021 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
4022 unsigned mask
= frame
->mask
;
4023 HOST_WIDE_INT step1
= frame
->total_size
;
4024 HOST_WIDE_INT step2
= 0;
4025 bool use_restore_libcall
= ((style
== NORMAL_RETURN
)
4026 && riscv_use_save_libcall (frame
));
4027 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4030 /* We need to add memory barrier to prevent read from deallocated stack. */
4031 bool need_barrier_p
= (get_frame_size ()
4032 + cfun
->machine
->frame
.arg_pointer_offset
) != 0;
4034 if (cfun
->machine
->naked_p
)
4036 gcc_assert (style
== NORMAL_RETURN
);
4038 emit_jump_insn (gen_return ());
4043 if ((style
== NORMAL_RETURN
) && riscv_can_use_return_insn ())
4045 emit_jump_insn (gen_return ());
4049 /* Reset the epilogue cfa info before starting to emit the epilogue. */
4050 epilogue_cfa_sp_offset
= 0;
4052 /* Move past any dynamic stack allocations. */
4053 if (cfun
->calls_alloca
)
4055 /* Emit a barrier to prevent loads from a deallocated stack. */
4056 riscv_emit_stack_tie ();
4057 need_barrier_p
= false;
4059 rtx adjust
= GEN_INT (-frame
->hard_frame_pointer_offset
);
4060 if (!SMALL_OPERAND (INTVAL (adjust
)))
4062 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4063 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4067 gen_add3_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
,
4070 rtx dwarf
= NULL_RTX
;
4071 rtx cfa_adjust_value
= gen_rtx_PLUS (
4072 Pmode
, hard_frame_pointer_rtx
,
4073 GEN_INT (-frame
->hard_frame_pointer_offset
));
4074 rtx cfa_adjust_rtx
= gen_rtx_SET (stack_pointer_rtx
, cfa_adjust_value
);
4075 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, cfa_adjust_rtx
, dwarf
);
4076 RTX_FRAME_RELATED_P (insn
) = 1;
4078 REG_NOTES (insn
) = dwarf
;
4081 /* If we need to restore registers, deallocate as much stack as
4082 possible in the second step without going out of range. */
4083 if ((frame
->mask
| frame
->fmask
) != 0)
4085 step2
= riscv_first_stack_step (frame
);
4089 /* Set TARGET to BASE + STEP1. */
4092 /* Emit a barrier to prevent loads from a deallocated stack. */
4093 riscv_emit_stack_tie ();
4094 need_barrier_p
= false;
4096 /* Get an rtx for STEP1 that we can add to BASE. */
4097 rtx adjust
= GEN_INT (step1
);
4098 if (!SMALL_OPERAND (step1
))
4100 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4101 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4105 gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
, adjust
));
4107 rtx dwarf
= NULL_RTX
;
4108 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4111 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4112 RTX_FRAME_RELATED_P (insn
) = 1;
4114 REG_NOTES (insn
) = dwarf
;
4116 else if (frame_pointer_needed
)
4118 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
4120 epilogue_cfa_sp_offset
= step2
;
4123 if (use_restore_libcall
)
4124 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4126 /* Restore the registers. */
4127 riscv_for_each_saved_reg (frame
->total_size
- step2
, riscv_restore_reg
,
4128 true, style
== EXCEPTION_RETURN
);
4130 if (use_restore_libcall
)
4132 frame
->mask
= mask
; /* Undo the above fib. */
4133 gcc_assert (step2
>= frame
->save_libcall_adjustment
);
4134 step2
-= frame
->save_libcall_adjustment
;
4138 riscv_emit_stack_tie ();
4140 /* Deallocate the final bit of the frame. */
4143 insn
= emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4146 rtx dwarf
= NULL_RTX
;
4147 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4149 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4150 RTX_FRAME_RELATED_P (insn
) = 1;
4152 REG_NOTES (insn
) = dwarf
;
4155 if (use_restore_libcall
)
4157 rtx dwarf
= riscv_adjust_libcall_cfi_epilogue ();
4158 insn
= emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask
))));
4159 RTX_FRAME_RELATED_P (insn
) = 1;
4160 REG_NOTES (insn
) = dwarf
;
4162 emit_jump_insn (gen_gpr_restore_return (ra
));
4166 /* Add in the __builtin_eh_return stack adjustment. */
4167 if ((style
== EXCEPTION_RETURN
) && crtl
->calls_eh_return
)
4168 emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4169 EH_RETURN_STACKADJ_RTX
));
4171 /* Return from interrupt. */
4172 if (cfun
->machine
->interrupt_handler_p
)
4174 enum riscv_privilege_levels mode
= cfun
->machine
->interrupt_mode
;
4176 gcc_assert (mode
!= UNKNOWN_MODE
);
4178 if (mode
== MACHINE_MODE
)
4179 emit_jump_insn (gen_riscv_mret ());
4180 else if (mode
== SUPERVISOR_MODE
)
4181 emit_jump_insn (gen_riscv_sret ());
4183 emit_jump_insn (gen_riscv_uret ());
4185 else if (style
!= SIBCALL_RETURN
)
4186 emit_jump_insn (gen_simple_return_internal (ra
));
4189 /* Implement EPILOGUE_USES. */
4192 riscv_epilogue_uses (unsigned int regno
)
4194 if (regno
== RETURN_ADDR_REGNUM
)
4197 if (epilogue_completed
&& cfun
->machine
->interrupt_handler_p
)
4199 /* An interrupt function restores temp regs, so we must indicate that
4200 they are live at function end. */
4201 if (df_regs_ever_live_p (regno
)
4202 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
4209 /* Return nonzero if this function is known to have a null epilogue.
4210 This allows the optimizer to omit jumps to jumps if no stack
4214 riscv_can_use_return_insn (void)
4216 return (reload_completed
&& cfun
->machine
->frame
.total_size
== 0
4217 && ! cfun
->machine
->interrupt_handler_p
);
4220 /* Given that there exists at least one variable that is set (produced)
4221 by OUT_INSN and read (consumed) by IN_INSN, return true iff
4222 IN_INSN represents one or more memory store operations and none of
4223 the variables set by OUT_INSN is used by IN_INSN as the address of a
4224 store operation. If either IN_INSN or OUT_INSN does not represent
4225 a "single" RTL SET expression (as loosely defined by the
4226 implementation of the single_set function) or a PARALLEL with only
4227 SETs, CLOBBERs, and USEs inside, this function returns false.
4229 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
4230 conditions that result in assertion failures in the generic
4231 store_data_bypass_p function and returns FALSE in such cases.
4233 This is required to make -msave-restore work with the sifive-7
4234 pipeline description. */
4237 riscv_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
4239 rtx out_set
, in_set
;
4240 rtx out_pat
, in_pat
;
4241 rtx out_exp
, in_exp
;
4244 in_set
= single_set (in_insn
);
4247 if (MEM_P (SET_DEST (in_set
)))
4249 out_set
= single_set (out_insn
);
4252 out_pat
= PATTERN (out_insn
);
4253 if (GET_CODE (out_pat
) == PARALLEL
)
4255 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
4257 out_exp
= XVECEXP (out_pat
, 0, i
);
4258 if ((GET_CODE (out_exp
) == CLOBBER
)
4259 || (GET_CODE (out_exp
) == USE
))
4261 else if (GET_CODE (out_exp
) != SET
)
4270 in_pat
= PATTERN (in_insn
);
4271 if (GET_CODE (in_pat
) != PARALLEL
)
4274 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
4276 in_exp
= XVECEXP (in_pat
, 0, i
);
4277 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
4279 else if (GET_CODE (in_exp
) != SET
)
4282 if (MEM_P (SET_DEST (in_exp
)))
4284 out_set
= single_set (out_insn
);
4287 out_pat
= PATTERN (out_insn
);
4288 if (GET_CODE (out_pat
) != PARALLEL
)
4290 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
4292 out_exp
= XVECEXP (out_pat
, 0, j
);
4293 if ((GET_CODE (out_exp
) == CLOBBER
)
4294 || (GET_CODE (out_exp
) == USE
))
4296 else if (GET_CODE (out_exp
) != SET
)
4304 return store_data_bypass_p (out_insn
, in_insn
);
4307 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4309 When floating-point registers are wider than integer ones, moves between
4310 them must go through memory. */
4313 riscv_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
4316 return (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4317 && (class1
== FP_REGS
) != (class2
== FP_REGS
));
4320 /* Implement TARGET_REGISTER_MOVE_COST. */
4323 riscv_register_move_cost (machine_mode mode
,
4324 reg_class_t from
, reg_class_t to
)
4326 return riscv_secondary_memory_needed (mode
, from
, to
) ? 8 : 2;
4329 /* Implement TARGET_HARD_REGNO_NREGS. */
4332 riscv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
4334 if (FP_REG_P (regno
))
4335 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_REG
- 1) / UNITS_PER_FP_REG
;
4337 /* All other registers are word-sized. */
4338 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4341 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4344 riscv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4346 unsigned int nregs
= riscv_hard_regno_nregs (regno
, mode
);
4348 if (GP_REG_P (regno
))
4350 if (!GP_REG_P (regno
+ nregs
- 1))
4353 else if (FP_REG_P (regno
))
4355 if (!FP_REG_P (regno
+ nregs
- 1))
4358 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4359 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4362 /* Only use callee-saved registers if a potential callee is guaranteed
4363 to spill the requisite width. */
4364 if (GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_REG
4365 || (!call_used_regs
[regno
]
4366 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_ARG
))
4372 /* Require same callee-savedness for all registers. */
4373 for (unsigned i
= 1; i
< nregs
; i
++)
4374 if (call_used_regs
[regno
] != call_used_regs
[regno
+ i
])
4380 /* Implement TARGET_MODES_TIEABLE_P.
4382 Don't allow floating-point modes to be tied, since type punning of
4383 single-precision and double-precision is implementation defined. */
4386 riscv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4388 return (mode1
== mode2
4389 || !(GET_MODE_CLASS (mode1
) == MODE_FLOAT
4390 && GET_MODE_CLASS (mode2
) == MODE_FLOAT
));
4393 /* Implement CLASS_MAX_NREGS. */
4395 static unsigned char
4396 riscv_class_max_nregs (reg_class_t rclass
, machine_mode mode
)
4398 if (reg_class_subset_p (FP_REGS
, rclass
))
4399 return riscv_hard_regno_nregs (FP_REG_FIRST
, mode
);
4401 if (reg_class_subset_p (GR_REGS
, rclass
))
4402 return riscv_hard_regno_nregs (GP_REG_FIRST
, mode
);
4407 /* Implement TARGET_MEMORY_MOVE_COST. */
4410 riscv_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
4412 return (tune_info
->memory_cost
4413 + memory_move_secondary_cost (mode
, rclass
, in
));
4416 /* Return the number of instructions that can be issued per cycle. */
4419 riscv_issue_rate (void)
4421 return tune_info
->issue_rate
;
4424 /* Auxiliary function to emit RISC-V ELF attribute. */
4426 riscv_emit_attribute ()
4428 fprintf (asm_out_file
, "\t.attribute arch, \"%s\"\n",
4429 riscv_arch_str ().c_str ());
4431 fprintf (asm_out_file
, "\t.attribute unaligned_access, %d\n",
4432 TARGET_STRICT_ALIGN
? 0 : 1);
4434 fprintf (asm_out_file
, "\t.attribute stack_align, %d\n",
4435 riscv_stack_boundary
/ 8);
4438 /* Implement TARGET_ASM_FILE_START. */
4441 riscv_file_start (void)
4443 default_file_start ();
4445 /* Instruct GAS to generate position-[in]dependent code. */
4446 fprintf (asm_out_file
, "\t.option %spic\n", (flag_pic
? "" : "no"));
4448 /* If the user specifies "-mno-relax" on the command line then disable linker
4449 relaxation in the assembler. */
4451 fprintf (asm_out_file
, "\t.option norelax\n");
4453 if (riscv_emit_attribute_p
)
4454 riscv_emit_attribute ();
4457 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4458 in order to avoid duplicating too much logic from elsewhere. */
4461 riscv_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
4462 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4465 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
4466 rtx this_rtx
, temp1
, temp2
, fnaddr
;
4469 /* Pretend to be a post-reload pass while generating rtl. */
4470 reload_completed
= 1;
4472 /* Mark the end of the (empty) prologue. */
4473 emit_note (NOTE_INSN_PROLOGUE_END
);
4475 /* Determine if we can use a sibcall to call FUNCTION directly. */
4476 fnaddr
= gen_rtx_MEM (FUNCTION_MODE
, XEXP (DECL_RTL (function
), 0));
4478 /* We need two temporary registers in some cases. */
4479 temp1
= gen_rtx_REG (Pmode
, RISCV_PROLOGUE_TEMP_REGNUM
);
4480 temp2
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
4482 /* Find out which register contains the "this" pointer. */
4483 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
4484 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
4486 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
4488 /* Add DELTA to THIS_RTX. */
4491 rtx offset
= GEN_INT (delta
);
4492 if (!SMALL_OPERAND (delta
))
4494 riscv_emit_move (temp1
, offset
);
4497 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
4500 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4501 if (vcall_offset
!= 0)
4505 /* Set TEMP1 to *THIS_RTX. */
4506 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
4508 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4509 addr
= riscv_add_offset (temp2
, temp1
, vcall_offset
);
4511 /* Load the offset and add it to THIS_RTX. */
4512 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
4513 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
4516 /* Jump to the target function. */
4517 insn
= emit_call_insn (gen_sibcall (fnaddr
, const0_rtx
, NULL
, const0_rtx
));
4518 SIBLING_CALL_P (insn
) = 1;
4520 /* Run just enough of rest_of_compilation. This sequence was
4521 "borrowed" from alpha.c. */
4522 insn
= get_insns ();
4523 split_all_insns_noflow ();
4524 shorten_branches (insn
);
4525 assemble_start_function (thunk_fndecl
, fnname
);
4526 final_start_function (insn
, file
, 1);
4527 final (insn
, file
, 1);
4528 final_end_function ();
4529 assemble_end_function (thunk_fndecl
, fnname
);
4531 /* Clean up the vars set above. Note that final_end_function resets
4532 the global pointer for us. */
4533 reload_completed
= 0;
4536 /* Allocate a chunk of memory for per-function machine-dependent data. */
4538 static struct machine_function
*
4539 riscv_init_machine_status (void)
4541 return ggc_cleared_alloc
<machine_function
> ();
4544 /* Implement TARGET_OPTION_OVERRIDE. */
4547 riscv_option_override (void)
4549 const struct riscv_cpu_info
*cpu
;
4551 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4552 SUBTARGET_OVERRIDE_OPTIONS
;
4555 flag_pcc_struct_return
= 0;
4560 /* The presence of the M extension implies that division instructions
4561 are present, so include them unless explicitly disabled. */
4562 if (TARGET_MUL
&& (target_flags_explicit
& MASK_DIV
) == 0)
4563 target_flags
|= MASK_DIV
;
4564 else if (!TARGET_MUL
&& TARGET_DIV
)
4565 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
4567 /* Likewise floating-point division and square root. */
4568 if (TARGET_HARD_FLOAT
&& (target_flags_explicit
& MASK_FDIV
) == 0)
4569 target_flags
|= MASK_FDIV
;
4571 /* Handle -mtune. */
4572 cpu
= riscv_parse_cpu (riscv_tune_string
? riscv_tune_string
:
4573 RISCV_TUNE_STRING_DEFAULT
);
4574 riscv_microarchitecture
= cpu
->microarchitecture
;
4575 tune_info
= optimize_size
? &optimize_size_tune_info
: cpu
->tune_info
;
4577 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
4578 for size. For architectures that trap and emulate unaligned accesses,
4579 the performance cost is too great, even for -Os. Similarly, if
4580 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
4581 riscv_slow_unaligned_access_p
= (cpu
->tune_info
->slow_unaligned_access
4582 || TARGET_STRICT_ALIGN
);
4583 if ((target_flags_explicit
& MASK_STRICT_ALIGN
) == 0
4584 && cpu
->tune_info
->slow_unaligned_access
)
4585 target_flags
|= MASK_STRICT_ALIGN
;
4587 /* If the user hasn't specified a branch cost, use the processor's
4589 if (riscv_branch_cost
== 0)
4590 riscv_branch_cost
= tune_info
->branch_cost
;
4592 /* Function to allocate machine-dependent function status. */
4593 init_machine_status
= &riscv_init_machine_status
;
4596 riscv_cmodel
= CM_PIC
;
4598 /* We get better code with explicit relocs for CM_MEDLOW, but
4599 worse code for the others (for now). Pick the best default. */
4600 if ((target_flags_explicit
& MASK_EXPLICIT_RELOCS
) == 0)
4601 if (riscv_cmodel
== CM_MEDLOW
)
4602 target_flags
|= MASK_EXPLICIT_RELOCS
;
4604 /* Require that the ISA supports the requested floating-point ABI. */
4605 if (UNITS_PER_FP_ARG
> (TARGET_HARD_FLOAT
? UNITS_PER_FP_REG
: 0))
4606 error ("requested ABI requires %<-march%> to subsume the %qc extension",
4607 UNITS_PER_FP_ARG
> 8 ? 'Q' : (UNITS_PER_FP_ARG
> 4 ? 'D' : 'F'));
4609 if (TARGET_RVE
&& riscv_abi
!= ABI_ILP32E
)
4610 error ("rv32e requires ilp32e ABI");
4612 /* We do not yet support ILP32 on RV64. */
4613 if (BITS_PER_WORD
!= POINTER_SIZE
)
4614 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE
);
4616 /* Validate -mpreferred-stack-boundary= value. */
4617 riscv_stack_boundary
= ABI_STACK_BOUNDARY
;
4618 if (riscv_preferred_stack_boundary_arg
)
4620 int min
= ctz_hwi (STACK_BOUNDARY
/ 8);
4623 if (!IN_RANGE (riscv_preferred_stack_boundary_arg
, min
, max
))
4624 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d",
4625 riscv_preferred_stack_boundary_arg
, min
, max
);
4627 riscv_stack_boundary
= 8 << riscv_preferred_stack_boundary_arg
;
4630 if (riscv_emit_attribute_p
< 0)
4631 #ifdef HAVE_AS_RISCV_ATTRIBUTE
4632 riscv_emit_attribute_p
= TARGET_RISCV_ATTRIBUTE
;
4634 riscv_emit_attribute_p
= 0;
4636 if (riscv_emit_attribute_p
)
4637 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"
4638 " [%<-mriscv-attribute%>]");
4642 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4645 riscv_conditional_register_usage (void)
4647 /* We have only x0~x15 on RV32E. */
4650 for (int r
= 16; r
<= 31; r
++)
4654 if (riscv_abi
== ABI_ILP32E
)
4656 for (int r
= 16; r
<= 31; r
++)
4657 call_used_regs
[r
] = 1;
4660 if (!TARGET_HARD_FLOAT
)
4662 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4663 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4666 /* In the soft-float ABI, there are no callee-saved FP registers. */
4667 if (UNITS_PER_FP_ARG
== 0)
4669 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4670 call_used_regs
[regno
] = 1;
4674 /* Return a register priority for hard reg REGNO. */
4677 riscv_register_priority (int regno
)
4679 /* Favor x8-x15/f8-f15 to improve the odds of RVC instruction selection. */
4680 if (TARGET_RVC
&& (IN_RANGE (regno
, GP_REG_FIRST
+ 8, GP_REG_FIRST
+ 15)
4681 || IN_RANGE (regno
, FP_REG_FIRST
+ 8, FP_REG_FIRST
+ 15)))
4687 /* Implement TARGET_TRAMPOLINE_INIT. */
4690 riscv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4692 rtx addr
, end_addr
, mem
;
4693 uint32_t trampoline
[4];
4695 HOST_WIDE_INT static_chain_offset
, target_function_offset
;
4697 /* Work out the offsets of the pointers from the start of the
4699 gcc_assert (ARRAY_SIZE (trampoline
) * 4 == TRAMPOLINE_CODE_SIZE
);
4701 /* Get pointers to the beginning and end of the code block. */
4702 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
4703 end_addr
= riscv_force_binary (Pmode
, PLUS
, addr
,
4704 GEN_INT (TRAMPOLINE_CODE_SIZE
));
4707 if (Pmode
== SImode
)
4709 chain_value
= force_reg (Pmode
, chain_value
);
4711 rtx target_function
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
4712 /* lui t2, hi(chain)
4714 addi t2, t2, lo(chain)
4717 unsigned HOST_WIDE_INT lui_hi_chain_code
, lui_hi_func_code
;
4718 unsigned HOST_WIDE_INT lo_chain_code
, lo_func_code
;
4720 rtx uimm_mask
= force_reg (SImode
, gen_int_mode (-IMM_REACH
, SImode
));
4723 rtx imm12_mask
= gen_reg_rtx (SImode
);
4724 emit_insn (gen_one_cmplsi2 (imm12_mask
, uimm_mask
));
4726 rtx fixup_value
= force_reg (SImode
, gen_int_mode (IMM_REACH
/2, SImode
));
4728 /* Gen lui t2, hi(chain). */
4729 rtx hi_chain
= riscv_force_binary (SImode
, PLUS
, chain_value
,
4731 hi_chain
= riscv_force_binary (SImode
, AND
, hi_chain
,
4733 lui_hi_chain_code
= OPCODE_LUI
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4734 rtx lui_hi_chain
= riscv_force_binary (SImode
, IOR
, hi_chain
,
4735 gen_int_mode (lui_hi_chain_code
, SImode
));
4737 mem
= adjust_address (m_tramp
, SImode
, 0);
4738 riscv_emit_move (mem
, lui_hi_chain
);
4740 /* Gen lui t1, hi(func). */
4741 rtx hi_func
= riscv_force_binary (SImode
, PLUS
, target_function
,
4743 hi_func
= riscv_force_binary (SImode
, AND
, hi_func
,
4745 lui_hi_func_code
= OPCODE_LUI
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
);
4746 rtx lui_hi_func
= riscv_force_binary (SImode
, IOR
, hi_func
,
4747 gen_int_mode (lui_hi_func_code
, SImode
));
4749 mem
= adjust_address (m_tramp
, SImode
, 1 * GET_MODE_SIZE (SImode
));
4750 riscv_emit_move (mem
, lui_hi_func
);
4752 /* Gen addi t2, t2, lo(chain). */
4753 rtx lo_chain
= riscv_force_binary (SImode
, AND
, chain_value
,
4755 lo_chain
= riscv_force_binary (SImode
, ASHIFT
, lo_chain
, GEN_INT (20));
4757 lo_chain_code
= OPCODE_ADDI
4758 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4759 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
);
4761 rtx addi_lo_chain
= riscv_force_binary (SImode
, IOR
, lo_chain
,
4762 force_reg (SImode
, GEN_INT (lo_chain_code
)));
4764 mem
= adjust_address (m_tramp
, SImode
, 2 * GET_MODE_SIZE (SImode
));
4765 riscv_emit_move (mem
, addi_lo_chain
);
4767 /* Gen jr r1, lo(func). */
4768 rtx lo_func
= riscv_force_binary (SImode
, AND
, target_function
,
4770 lo_func
= riscv_force_binary (SImode
, ASHIFT
, lo_func
, GEN_INT (20));
4772 lo_func_code
= OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4774 rtx jr_lo_func
= riscv_force_binary (SImode
, IOR
, lo_func
,
4775 force_reg (SImode
, GEN_INT (lo_func_code
)));
4777 mem
= adjust_address (m_tramp
, SImode
, 3 * GET_MODE_SIZE (SImode
));
4778 riscv_emit_move (mem
, jr_lo_func
);
4782 static_chain_offset
= TRAMPOLINE_CODE_SIZE
;
4783 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
4786 l[wd] t1, target_function_offset(t2)
4787 l[wd] t2, static_chain_offset(t2)
4790 trampoline
[0] = OPCODE_AUIPC
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4791 trampoline
[1] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4792 | (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
)
4793 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4794 | (target_function_offset
<< SHIFT_IMM
);
4795 trampoline
[2] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4796 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4797 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4798 | (static_chain_offset
<< SHIFT_IMM
);
4799 trampoline
[3] = OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4801 /* Copy the trampoline code. */
4802 for (i
= 0; i
< ARRAY_SIZE (trampoline
); i
++)
4804 mem
= adjust_address (m_tramp
, SImode
, i
* GET_MODE_SIZE (SImode
));
4805 riscv_emit_move (mem
, gen_int_mode (trampoline
[i
], SImode
));
4808 /* Set up the static chain pointer field. */
4809 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
4810 riscv_emit_move (mem
, chain_value
);
4812 /* Set up the target function field. */
4813 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
4814 riscv_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
4817 /* Flush the code part of the trampoline. */
4818 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
4819 emit_insn (gen_clear_cache (addr
, end_addr
));
4822 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
4825 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
4826 tree exp ATTRIBUTE_UNUSED
)
4828 /* Don't use sibcalls when use save-restore routine. */
4829 if (TARGET_SAVE_RESTORE
)
4832 /* Don't use sibcall for naked functions. */
4833 if (cfun
->machine
->naked_p
)
4836 /* Don't use sibcall for interrupt functions. */
4837 if (cfun
->machine
->interrupt_handler_p
)
4843 /* Get the interrupt type, return UNKNOWN_MODE if it's not
4844 interrupt function. */
4845 static enum riscv_privilege_levels
4846 riscv_get_interrupt_type (tree decl
)
4848 gcc_assert (decl
!= NULL_TREE
);
4850 if ((TREE_CODE(decl
) != FUNCTION_DECL
)
4851 || (!riscv_interrupt_type_p (TREE_TYPE (decl
))))
4852 return UNKNOWN_MODE
;
4855 = TREE_VALUE (lookup_attribute ("interrupt",
4856 TYPE_ATTRIBUTES (TREE_TYPE (decl
))));
4858 if (attr_args
&& TREE_CODE (TREE_VALUE (attr_args
)) != VOID_TYPE
)
4860 const char *string
= TREE_STRING_POINTER (TREE_VALUE (attr_args
));
4862 if (!strcmp (string
, "user"))
4864 else if (!strcmp (string
, "supervisor"))
4865 return SUPERVISOR_MODE
;
4866 else /* Must be "machine". */
4867 return MACHINE_MODE
;
4870 /* Interrupt attributes are machine mode by default. */
4871 return MACHINE_MODE
;
4874 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
4875 /* Sanity cheching for above function attributes. */
4877 riscv_set_current_function (tree decl
)
4879 if (decl
== NULL_TREE
4880 || current_function_decl
== NULL_TREE
4881 || current_function_decl
== error_mark_node
4883 || cfun
->machine
->attributes_checked_p
)
4886 cfun
->machine
->naked_p
= riscv_naked_function_p (decl
);
4887 cfun
->machine
->interrupt_handler_p
4888 = riscv_interrupt_type_p (TREE_TYPE (decl
));
4890 if (cfun
->machine
->naked_p
&& cfun
->machine
->interrupt_handler_p
)
4891 error ("function attributes %qs and %qs are mutually exclusive",
4892 "interrupt", "naked");
4894 if (cfun
->machine
->interrupt_handler_p
)
4896 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
4897 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
4899 if (TREE_CODE (ret
) != VOID_TYPE
)
4900 error ("%qs function cannot return a value", "interrupt");
4902 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
4903 error ("%qs function cannot have arguments", "interrupt");
4905 cfun
->machine
->interrupt_mode
= riscv_get_interrupt_type (decl
);
4907 gcc_assert (cfun
->machine
->interrupt_mode
!= UNKNOWN_MODE
);
4910 /* Don't print the above diagnostics more than once. */
4911 cfun
->machine
->attributes_checked_p
= 1;
4914 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
4916 riscv_merge_decl_attributes (tree olddecl
, tree newdecl
)
4918 tree combined_attrs
;
4920 enum riscv_privilege_levels old_interrupt_type
4921 = riscv_get_interrupt_type (olddecl
);
4922 enum riscv_privilege_levels new_interrupt_type
4923 = riscv_get_interrupt_type (newdecl
);
4925 /* Check old and new has same interrupt type. */
4926 if ((old_interrupt_type
!= UNKNOWN_MODE
)
4927 && (new_interrupt_type
!= UNKNOWN_MODE
)
4928 && (old_interrupt_type
!= new_interrupt_type
))
4929 error ("%qs function cannot have different interrupt type", "interrupt");
4931 /* Create combined attributes. */
4932 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
4933 DECL_ATTRIBUTES (newdecl
));
4935 return combined_attrs
;
4938 /* Implement TARGET_CANNOT_COPY_INSN_P. */
4941 riscv_cannot_copy_insn_p (rtx_insn
*insn
)
4943 return recog_memoized (insn
) >= 0 && get_attr_cannot_copy (insn
);
4946 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
4949 riscv_slow_unaligned_access (machine_mode
, unsigned int)
4951 return riscv_slow_unaligned_access_p
;
4954 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
4957 riscv_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t rclass
)
4959 return !reg_classes_intersect_p (FP_REGS
, rclass
);
4963 /* Implement TARGET_CONSTANT_ALIGNMENT. */
4965 static HOST_WIDE_INT
4966 riscv_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
4968 if ((TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
4969 && (riscv_align_data_type
== riscv_align_data_type_xlen
))
4970 return MAX (align
, BITS_PER_WORD
);
4974 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
4976 /* This function is equivalent to default_promote_function_mode_always_promote
4977 except that it returns a promoted mode even if type is NULL_TREE. This is
4978 needed by libcalls which have no type (only a mode) such as fixed conversion
4979 routines that take a signed or unsigned char/short/int argument and convert
4980 it to a fixed type. */
4983 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4985 int *punsignedp ATTRIBUTE_UNUSED
,
4986 const_tree fntype ATTRIBUTE_UNUSED
,
4987 int for_return ATTRIBUTE_UNUSED
)
4991 if (type
!= NULL_TREE
)
4992 return promote_mode (type
, mode
, punsignedp
);
4994 unsignedp
= *punsignedp
;
4995 PROMOTE_MODE (mode
, unsignedp
, type
);
4996 *punsignedp
= unsignedp
;
5000 /* Initialize the GCC target structure. */
5001 #undef TARGET_ASM_ALIGNED_HI_OP
5002 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
5003 #undef TARGET_ASM_ALIGNED_SI_OP
5004 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
5005 #undef TARGET_ASM_ALIGNED_DI_OP
5006 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
5008 #undef TARGET_OPTION_OVERRIDE
5009 #define TARGET_OPTION_OVERRIDE riscv_option_override
5011 #undef TARGET_LEGITIMIZE_ADDRESS
5012 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
5014 #undef TARGET_SCHED_ISSUE_RATE
5015 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
5017 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5018 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
5020 #undef TARGET_SET_CURRENT_FUNCTION
5021 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
5023 #undef TARGET_REGISTER_MOVE_COST
5024 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
5025 #undef TARGET_MEMORY_MOVE_COST
5026 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
5027 #undef TARGET_RTX_COSTS
5028 #define TARGET_RTX_COSTS riscv_rtx_costs
5029 #undef TARGET_ADDRESS_COST
5030 #define TARGET_ADDRESS_COST riscv_address_cost
5032 #undef TARGET_ASM_FILE_START
5033 #define TARGET_ASM_FILE_START riscv_file_start
5034 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5035 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5037 #undef TARGET_EXPAND_BUILTIN_VA_START
5038 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
5040 #undef TARGET_PROMOTE_FUNCTION_MODE
5041 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
5043 #undef TARGET_RETURN_IN_MEMORY
5044 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
5046 #undef TARGET_ASM_OUTPUT_MI_THUNK
5047 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
5048 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5049 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5051 #undef TARGET_PRINT_OPERAND
5052 #define TARGET_PRINT_OPERAND riscv_print_operand
5053 #undef TARGET_PRINT_OPERAND_ADDRESS
5054 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
5056 #undef TARGET_SETUP_INCOMING_VARARGS
5057 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
5058 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
5059 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
5060 #undef TARGET_STRICT_ARGUMENT_NAMING
5061 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
5062 #undef TARGET_MUST_PASS_IN_STACK
5063 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
5064 #undef TARGET_PASS_BY_REFERENCE
5065 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
5066 #undef TARGET_ARG_PARTIAL_BYTES
5067 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
5068 #undef TARGET_FUNCTION_ARG
5069 #define TARGET_FUNCTION_ARG riscv_function_arg
5070 #undef TARGET_FUNCTION_ARG_ADVANCE
5071 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
5072 #undef TARGET_FUNCTION_ARG_BOUNDARY
5073 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
5075 /* The generic ELF target does not always have TLS support. */
5077 #undef TARGET_HAVE_TLS
5078 #define TARGET_HAVE_TLS true
5081 #undef TARGET_CANNOT_FORCE_CONST_MEM
5082 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
5084 #undef TARGET_LEGITIMATE_CONSTANT_P
5085 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
5087 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5088 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
5090 #undef TARGET_LEGITIMATE_ADDRESS_P
5091 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
5093 #undef TARGET_CAN_ELIMINATE
5094 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
5096 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5097 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
5099 #undef TARGET_CLASS_MAX_NREGS
5100 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
5102 #undef TARGET_TRAMPOLINE_INIT
5103 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
5105 #undef TARGET_IN_SMALL_DATA_P
5106 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
5108 #undef TARGET_HAVE_SRODATA_SECTION
5109 #define TARGET_HAVE_SRODATA_SECTION true
5111 #undef TARGET_ASM_SELECT_SECTION
5112 #define TARGET_ASM_SELECT_SECTION riscv_select_section
5114 #undef TARGET_ASM_SELECT_RTX_SECTION
5115 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
5117 #undef TARGET_MIN_ANCHOR_OFFSET
5118 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
5120 #undef TARGET_MAX_ANCHOR_OFFSET
5121 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
5123 #undef TARGET_REGISTER_PRIORITY
5124 #define TARGET_REGISTER_PRIORITY riscv_register_priority
5126 #undef TARGET_CANNOT_COPY_INSN_P
5127 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
5129 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
5130 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
5132 #undef TARGET_INIT_BUILTINS
5133 #define TARGET_INIT_BUILTINS riscv_init_builtins
5135 #undef TARGET_BUILTIN_DECL
5136 #define TARGET_BUILTIN_DECL riscv_builtin_decl
5138 #undef TARGET_EXPAND_BUILTIN
5139 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
5141 #undef TARGET_HARD_REGNO_NREGS
5142 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
5143 #undef TARGET_HARD_REGNO_MODE_OK
5144 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
5146 #undef TARGET_MODES_TIEABLE_P
5147 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
5149 #undef TARGET_SLOW_UNALIGNED_ACCESS
5150 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
5152 #undef TARGET_SECONDARY_MEMORY_NEEDED
5153 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
5155 #undef TARGET_CAN_CHANGE_MODE_CLASS
5156 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
5158 #undef TARGET_CONSTANT_ALIGNMENT
5159 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
5161 #undef TARGET_MERGE_DECL_ATTRIBUTES
5162 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
5164 #undef TARGET_ATTRIBUTE_TABLE
5165 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
5167 #undef TARGET_WARN_FUNC_RETURN
5168 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
5170 /* The low bit is ignored by jump instructions so is safe to use. */
5171 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
5172 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
5174 struct gcc_target targetm
= TARGET_INITIALIZER
;
5176 #include "gt-riscv.h"