1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
27 #include "coretypes.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
37 #include "stringpool.h"
40 #include "stor-layout.h"
49 #include "target-def.h"
50 #include "basic-block.h"
55 #include "diagnostic.h"
58 #include "tree-pass.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* True if bit BIT is set in VALUE. */
76 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
78 /* Classifies an address.
81 A natural register + offset address. The register satisfies
82 riscv_valid_base_register_p and the offset is a const_arith_operand.
85 A LO_SUM rtx. The first operand is a valid base register and
86 the second operand is a symbolic address.
89 A signed 16-bit constant address.
92 A constant symbolic address. */
93 enum riscv_address_type
{
100 /* Information about a function's frame layout. */
101 struct GTY(()) riscv_frame_info
{
102 /* The size of the frame in bytes. */
103 HOST_WIDE_INT total_size
;
105 /* Bit X is set if the function saves or restores GPR X. */
108 /* Likewise FPR X. */
111 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
112 unsigned save_libcall_adjustment
;
114 /* Offsets of fixed-point and floating-point save areas from frame bottom */
115 HOST_WIDE_INT gp_sp_offset
;
116 HOST_WIDE_INT fp_sp_offset
;
118 /* Offset of virtual frame pointer from stack pointer/frame bottom */
119 HOST_WIDE_INT frame_pointer_offset
;
121 /* Offset of hard frame pointer from stack pointer/frame bottom */
122 HOST_WIDE_INT hard_frame_pointer_offset
;
124 /* The offset of arg_pointer_rtx from the bottom of the frame. */
125 HOST_WIDE_INT arg_pointer_offset
;
128 enum riscv_privilege_levels
{
129 UNKNOWN_MODE
, USER_MODE
, SUPERVISOR_MODE
, MACHINE_MODE
132 struct GTY(()) machine_function
{
133 /* The number of extra stack bytes taken up by register varargs.
134 This area is allocated by the callee at the very top of the frame. */
137 /* True if current function is a naked function. */
140 /* True if current function is an interrupt function. */
141 bool interrupt_handler_p
;
142 /* For an interrupt handler, indicates the privilege level. */
143 enum riscv_privilege_levels interrupt_mode
;
145 /* True if attributes on current function have been checked. */
146 bool attributes_checked_p
;
148 /* The current frame information, calculated by riscv_compute_frame_info. */
149 struct riscv_frame_info frame
;
152 /* Information about a single argument. */
153 struct riscv_arg_info
{
154 /* True if the argument is at least partially passed on the stack. */
157 /* The number of integer registers allocated to this argument. */
158 unsigned int num_gprs
;
160 /* The offset of the first register used, provided num_gprs is nonzero.
161 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
162 unsigned int gpr_offset
;
164 /* The number of floating-point registers allocated to this argument. */
165 unsigned int num_fprs
;
167 /* The offset of the first register used, provided num_fprs is nonzero. */
168 unsigned int fpr_offset
;
171 /* Information about an address described by riscv_address_type.
177 REG is the base register and OFFSET is the constant offset.
180 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
181 is the type of symbol it references.
184 SYMBOL_TYPE is the type of symbol that the address references. */
185 struct riscv_address_info
{
186 enum riscv_address_type type
;
189 enum riscv_symbol_type symbol_type
;
192 /* One stage in a constant building sequence. These sequences have
196 A = A CODE[1] VALUE[1]
197 A = A CODE[2] VALUE[2]
200 where A is an accumulator, each CODE[i] is a binary rtl operation
201 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
202 struct riscv_integer_op
{
204 unsigned HOST_WIDE_INT value
;
207 /* The largest number of operations needed to load an integer constant.
208 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
209 #define RISCV_MAX_INTEGER_OPS 8
211 /* Costs of various operations on the different architectures. */
213 struct riscv_tune_param
215 unsigned short fp_add
[2];
216 unsigned short fp_mul
[2];
217 unsigned short fp_div
[2];
218 unsigned short int_mul
[2];
219 unsigned short int_div
[2];
220 unsigned short issue_rate
;
221 unsigned short branch_cost
;
222 unsigned short memory_cost
;
223 bool slow_unaligned_access
;
226 /* Information about one micro-arch we know about. */
227 struct riscv_tune_info
{
228 /* This micro-arch canonical name. */
231 /* Which automaton to use for tuning. */
232 enum riscv_microarchitecture_type microarchitecture
;
234 /* Tuning parameters for this micro-arch. */
235 const struct riscv_tune_param
*tune_param
;
238 /* Global variables for machine-dependent things. */
240 /* Whether unaligned accesses execute very slowly. */
241 bool riscv_slow_unaligned_access_p
;
243 /* Stack alignment to assume/maintain. */
244 unsigned riscv_stack_boundary
;
246 /* If non-zero, this is an offset to be added to SP to redefine the CFA
247 when restoring the FP register from the stack. Only valid when generating
249 static int epilogue_cfa_sp_offset
;
251 /* Which tuning parameters to use. */
252 static const struct riscv_tune_param
*tune_param
;
254 /* Which automaton to use for tuning. */
255 enum riscv_microarchitecture_type riscv_microarchitecture
;
257 /* Index R is the smallest register class that contains register R. */
258 const enum reg_class riscv_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
259 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
260 GR_REGS
, GR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
261 JALR_REGS
, JALR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
262 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
263 SIBCALL_REGS
, SIBCALL_REGS
, JALR_REGS
, JALR_REGS
,
264 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
265 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
266 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
267 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
268 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
269 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
270 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
271 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
272 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
273 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
274 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
275 FRAME_REGS
, FRAME_REGS
,
278 /* Costs to use when optimizing for rocket. */
279 static const struct riscv_tune_param rocket_tune_info
= {
280 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
281 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
282 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
283 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
284 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
288 true, /* slow_unaligned_access */
291 /* Costs to use when optimizing for Sifive 7 Series. */
292 static const struct riscv_tune_param sifive_7_tune_info
= {
293 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
294 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
295 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
296 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
297 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
301 true, /* slow_unaligned_access */
304 /* Costs to use when optimizing for T-HEAD c906. */
305 static const struct riscv_tune_param thead_c906_tune_info
= {
306 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
307 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
308 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
309 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
310 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
314 false, /* slow_unaligned_access */
317 /* Costs to use when optimizing for size. */
318 static const struct riscv_tune_param optimize_size_tune_info
= {
319 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
320 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
321 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
322 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
323 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
327 false, /* slow_unaligned_access */
330 static tree
riscv_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
331 static tree
riscv_handle_type_attribute (tree
*, tree
, tree
, int, bool *);
333 /* Defining target-specific uses of __attribute__. */
334 static const struct attribute_spec riscv_attribute_table
[] =
336 /* Syntax: { name, min_len, max_len, decl_required, type_required,
337 function_type_required, affects_type_identity, handler,
340 /* The attribute telling no prologue/epilogue. */
341 { "naked", 0, 0, true, false, false, false,
342 riscv_handle_fndecl_attribute
, NULL
},
343 /* This attribute generates prologue/epilogue for interrupt handlers. */
344 { "interrupt", 0, 1, false, true, true, false,
345 riscv_handle_type_attribute
, NULL
},
347 /* The last attribute spec is set to be NULL. */
348 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
351 /* Order for the CLOBBERs/USEs of gpr_save. */
352 static const unsigned gpr_save_reg_order
[] = {
353 INVALID_REGNUM
, T0_REGNUM
, T1_REGNUM
, RETURN_ADDR_REGNUM
,
354 S0_REGNUM
, S1_REGNUM
, S2_REGNUM
, S3_REGNUM
, S4_REGNUM
,
355 S5_REGNUM
, S6_REGNUM
, S7_REGNUM
, S8_REGNUM
, S9_REGNUM
,
356 S10_REGNUM
, S11_REGNUM
359 /* A table describing all the processors GCC knows about. */
360 static const struct riscv_tune_info riscv_tune_info_table
[] = {
361 { "rocket", generic
, &rocket_tune_info
},
362 { "sifive-3-series", generic
, &rocket_tune_info
},
363 { "sifive-5-series", generic
, &rocket_tune_info
},
364 { "sifive-7-series", sifive_7
, &sifive_7_tune_info
},
365 { "thead-c906", generic
, &thead_c906_tune_info
},
366 { "size", generic
, &optimize_size_tune_info
},
369 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
372 riscv_min_arithmetic_precision (void)
377 /* Return the riscv_tune_info entry for the given name string. */
379 static const struct riscv_tune_info
*
380 riscv_parse_tune (const char *tune_string
)
382 const riscv_cpu_info
*cpu
= riscv_find_cpu (tune_string
);
385 tune_string
= cpu
->tune
;
387 for (unsigned i
= 0; i
< ARRAY_SIZE (riscv_tune_info_table
); i
++)
388 if (strcmp (riscv_tune_info_table
[i
].name
, tune_string
) == 0)
389 return riscv_tune_info_table
+ i
;
391 error ("unknown cpu %qs for %<-mtune%>", tune_string
);
392 return riscv_tune_info_table
;
395 /* Helper function for riscv_build_integer; arguments are as for
396 riscv_build_integer. */
399 riscv_build_integer_1 (struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
],
400 HOST_WIDE_INT value
, machine_mode mode
)
402 HOST_WIDE_INT low_part
= CONST_LOW_PART (value
);
403 int cost
= RISCV_MAX_INTEGER_OPS
+ 1, alt_cost
;
404 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
406 if (SMALL_OPERAND (value
) || LUI_OPERAND (value
))
408 /* Simply ADDI or LUI. */
409 codes
[0].code
= UNKNOWN
;
410 codes
[0].value
= value
;
414 /* End with ADDI. When constructing HImode constants, do not generate any
415 intermediate value that is not itself a valid HImode constant. The
416 XORI case below will handle those remaining HImode constants. */
419 || value
- low_part
<= ((1 << (GET_MODE_BITSIZE (HImode
) - 1)) - 1)))
421 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
- low_part
, mode
);
424 alt_codes
[alt_cost
-1].code
= PLUS
;
425 alt_codes
[alt_cost
-1].value
= low_part
;
426 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
432 if (cost
> 2 && (low_part
< 0 || mode
== HImode
))
434 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
^ low_part
, mode
);
437 alt_codes
[alt_cost
-1].code
= XOR
;
438 alt_codes
[alt_cost
-1].value
= low_part
;
439 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
444 /* Eliminate trailing zeros and end with SLLI. */
445 if (cost
> 2 && (value
& 1) == 0)
447 int shift
= ctz_hwi (value
);
448 unsigned HOST_WIDE_INT x
= value
;
449 x
= sext_hwi (x
>> shift
, HOST_BITS_PER_WIDE_INT
- shift
);
451 /* Don't eliminate the lower 12 bits if LUI might apply. */
452 if (shift
> IMM_BITS
&& !SMALL_OPERAND (x
) && LUI_OPERAND (x
<< IMM_BITS
))
453 shift
-= IMM_BITS
, x
<<= IMM_BITS
;
455 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, x
, mode
);
458 alt_codes
[alt_cost
-1].code
= ASHIFT
;
459 alt_codes
[alt_cost
-1].value
= shift
;
460 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
465 gcc_assert (cost
<= RISCV_MAX_INTEGER_OPS
);
469 /* Fill CODES with a sequence of rtl operations to load VALUE.
470 Return the number of operations needed. */
473 riscv_build_integer (struct riscv_integer_op
*codes
, HOST_WIDE_INT value
,
476 int cost
= riscv_build_integer_1 (codes
, value
, mode
);
478 /* Eliminate leading zeros and end with SRLI. */
479 if (value
> 0 && cost
> 2)
481 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
482 int alt_cost
, shift
= clz_hwi (value
);
483 HOST_WIDE_INT shifted_val
;
485 /* Try filling trailing bits with 1s. */
486 shifted_val
= (value
<< shift
) | ((((HOST_WIDE_INT
) 1) << shift
) - 1);
487 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
490 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
491 alt_codes
[alt_cost
-1].value
= shift
;
492 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
496 /* Try filling trailing bits with 0s. */
497 shifted_val
= value
<< shift
;
498 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
501 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
502 alt_codes
[alt_cost
-1].value
= shift
;
503 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
511 /* Return the cost of constructing VAL in the event that a scratch
512 register is available. */
515 riscv_split_integer_cost (HOST_WIDE_INT val
)
518 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
519 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
520 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
522 cost
= 2 + riscv_build_integer (codes
, loval
, VOIDmode
);
524 cost
+= riscv_build_integer (codes
, hival
, VOIDmode
);
529 /* Return the cost of constructing the integer constant VAL. */
532 riscv_integer_cost (HOST_WIDE_INT val
)
534 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
535 return MIN (riscv_build_integer (codes
, val
, VOIDmode
),
536 riscv_split_integer_cost (val
));
539 /* Try to split a 64b integer into 32b parts, then reassemble. */
542 riscv_split_integer (HOST_WIDE_INT val
, machine_mode mode
)
544 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
545 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
546 rtx hi
= gen_reg_rtx (mode
), lo
= gen_reg_rtx (mode
);
548 riscv_move_integer (hi
, hi
, hival
, mode
, FALSE
);
549 riscv_move_integer (lo
, lo
, loval
, mode
, FALSE
);
551 hi
= gen_rtx_fmt_ee (ASHIFT
, mode
, hi
, GEN_INT (32));
552 hi
= force_reg (mode
, hi
);
554 return gen_rtx_fmt_ee (PLUS
, mode
, hi
, lo
);
557 /* Return true if X is a thread-local symbol. */
560 riscv_tls_symbol_p (const_rtx x
)
562 return SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0;
565 /* Return true if symbol X binds locally. */
568 riscv_symbol_binds_local_p (const_rtx x
)
570 if (SYMBOL_REF_P (x
))
571 return (SYMBOL_REF_DECL (x
)
572 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
573 : SYMBOL_REF_LOCAL_P (x
));
578 /* Return the method that should be used to access SYMBOL_REF or
581 static enum riscv_symbol_type
582 riscv_classify_symbol (const_rtx x
)
584 if (riscv_tls_symbol_p (x
))
587 if (GET_CODE (x
) == SYMBOL_REF
&& flag_pic
&& !riscv_symbol_binds_local_p (x
))
588 return SYMBOL_GOT_DISP
;
590 return riscv_cmodel
== CM_MEDLOW
? SYMBOL_ABSOLUTE
: SYMBOL_PCREL
;
593 /* Classify the base of symbolic expression X. */
595 enum riscv_symbol_type
596 riscv_classify_symbolic_expression (rtx x
)
600 split_const (x
, &x
, &offset
);
601 if (UNSPEC_ADDRESS_P (x
))
602 return UNSPEC_ADDRESS_TYPE (x
);
604 return riscv_classify_symbol (x
);
607 /* Return true if X is a symbolic constant. If it is, store the type of
608 the symbol in *SYMBOL_TYPE. */
611 riscv_symbolic_constant_p (rtx x
, enum riscv_symbol_type
*symbol_type
)
615 split_const (x
, &x
, &offset
);
616 if (UNSPEC_ADDRESS_P (x
))
618 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
619 x
= UNSPEC_ADDRESS (x
);
621 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
622 *symbol_type
= riscv_classify_symbol (x
);
626 if (offset
== const0_rtx
)
629 /* Nonzero offsets are only valid for references that don't use the GOT. */
630 switch (*symbol_type
)
632 case SYMBOL_ABSOLUTE
:
635 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
636 return sext_hwi (INTVAL (offset
), 32) == INTVAL (offset
);
643 /* Returns the number of instructions necessary to reference a symbol. */
645 static int riscv_symbol_insns (enum riscv_symbol_type type
)
649 case SYMBOL_TLS
: return 0; /* Depends on the TLS model. */
650 case SYMBOL_ABSOLUTE
: return 2; /* LUI + the reference. */
651 case SYMBOL_PCREL
: return 2; /* AUIPC + the reference. */
652 case SYMBOL_TLS_LE
: return 3; /* LUI + ADD TP + the reference. */
653 case SYMBOL_GOT_DISP
: return 3; /* AUIPC + LD GOT + the reference. */
654 default: gcc_unreachable ();
658 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
661 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
663 return riscv_const_insns (x
) > 0;
666 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
669 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
671 enum riscv_symbol_type type
;
674 /* There is no assembler syntax for expressing an address-sized
676 if (GET_CODE (x
) == HIGH
)
679 split_const (x
, &base
, &offset
);
680 if (riscv_symbolic_constant_p (base
, &type
))
682 /* As an optimization, don't spill symbolic constants that are as
683 cheap to rematerialize as to access in the constant pool. */
684 if (SMALL_OPERAND (INTVAL (offset
)) && riscv_symbol_insns (type
) > 0)
687 /* As an optimization, avoid needlessly generate dynamic relocations. */
692 /* TLS symbols must be computed by riscv_legitimize_move. */
693 if (tls_referenced_p (x
))
699 /* Return true if register REGNO is a valid base register for mode MODE.
700 STRICT_P is true if REG_OK_STRICT is in effect. */
703 riscv_regno_mode_ok_for_base_p (int regno
,
704 machine_mode mode ATTRIBUTE_UNUSED
,
707 if (!HARD_REGISTER_NUM_P (regno
))
711 regno
= reg_renumber
[regno
];
714 /* These fake registers will be eliminated to either the stack or
715 hard frame pointer, both of which are usually valid base registers.
716 Reload deals with the cases where the eliminated form isn't valid. */
717 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
720 return GP_REG_P (regno
);
723 /* Return true if X is a valid base register for mode MODE.
724 STRICT_P is true if REG_OK_STRICT is in effect. */
727 riscv_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
729 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
733 && riscv_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
736 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
737 can address a value of mode MODE. */
740 riscv_valid_offset_p (rtx x
, machine_mode mode
)
742 /* Check that X is a signed 12-bit number. */
743 if (!const_arith_operand (x
, Pmode
))
746 /* We may need to split multiword moves, so make sure that every word
748 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
749 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
755 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
758 riscv_split_symbol_type (enum riscv_symbol_type symbol_type
)
760 if (symbol_type
== SYMBOL_TLS_LE
)
763 if (!TARGET_EXPLICIT_RELOCS
)
766 return symbol_type
== SYMBOL_ABSOLUTE
|| symbol_type
== SYMBOL_PCREL
;
769 /* Return true if a LO_SUM can address a value of mode MODE when the
770 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
771 is used when the mode is BLKmode. */
774 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type
, machine_mode mode
,
779 /* Check that symbols of type SYMBOL_TYPE can be used to access values
781 if (riscv_symbol_insns (sym_type
) == 0)
784 /* Check that there is a known low-part relocation. */
785 if (!riscv_split_symbol_type (sym_type
))
788 /* We can't tell size or alignment when we have BLKmode, so try extracing a
789 decl from the symbol if possible. */
794 /* Extract the symbol from the LO_SUM operand, if any. */
795 split_const (x
, &x
, &offset
);
797 /* Might be a CODE_LABEL. We can compute align but not size for that,
798 so don't bother trying to handle it. */
799 if (!SYMBOL_REF_P (x
))
802 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
803 align
= (SYMBOL_REF_DECL (x
)
804 ? DECL_ALIGN (SYMBOL_REF_DECL (x
))
806 size
= (SYMBOL_REF_DECL (x
) && DECL_SIZE (SYMBOL_REF_DECL (x
))
807 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x
)))
812 align
= GET_MODE_ALIGNMENT (mode
);
813 size
= GET_MODE_BITSIZE (mode
);
816 /* We may need to split multiword moves, so make sure that each word
817 can be accessed without inducing a carry. */
818 if (size
> BITS_PER_WORD
819 && (!TARGET_STRICT_ALIGN
|| size
> align
))
825 /* Return true if X is a valid address for machine mode MODE. If it is,
826 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
830 riscv_classify_address (struct riscv_address_info
*info
, rtx x
,
831 machine_mode mode
, bool strict_p
)
833 switch (GET_CODE (x
))
837 info
->type
= ADDRESS_REG
;
839 info
->offset
= const0_rtx
;
840 return riscv_valid_base_register_p (info
->reg
, mode
, strict_p
);
843 info
->type
= ADDRESS_REG
;
844 info
->reg
= XEXP (x
, 0);
845 info
->offset
= XEXP (x
, 1);
846 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
847 && riscv_valid_offset_p (info
->offset
, mode
));
850 info
->type
= ADDRESS_LO_SUM
;
851 info
->reg
= XEXP (x
, 0);
852 info
->offset
= XEXP (x
, 1);
853 /* We have to trust the creator of the LO_SUM to do something vaguely
854 sane. Target-independent code that creates a LO_SUM should also
855 create and verify the matching HIGH. Target-independent code that
856 adds an offset to a LO_SUM must prove that the offset will not
857 induce a carry. Failure to do either of these things would be
858 a bug, and we are not required to check for it here. The RISC-V
859 backend itself should only create LO_SUMs for valid symbolic
860 constants, with the high part being either a HIGH or a copy
863 = riscv_classify_symbolic_expression (info
->offset
);
864 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
865 && riscv_valid_lo_sum_p (info
->symbol_type
, mode
, info
->offset
));
868 /* Small-integer addresses don't occur very often, but they
869 are legitimate if x0 is a valid base register. */
870 info
->type
= ADDRESS_CONST_INT
;
871 return SMALL_OPERAND (INTVAL (x
));
878 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
881 riscv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
883 struct riscv_address_info addr
;
885 return riscv_classify_address (&addr
, x
, mode
, strict_p
);
888 /* Return true if hard reg REGNO can be used in compressed instructions. */
891 riscv_compressed_reg_p (int regno
)
893 /* x8-x15/f8-f15 are compressible registers. */
894 return (TARGET_RVC
&& (IN_RANGE (regno
, GP_REG_FIRST
+ 8, GP_REG_FIRST
+ 15)
895 || IN_RANGE (regno
, FP_REG_FIRST
+ 8, FP_REG_FIRST
+ 15)));
898 /* Return true if x is an unsigned 5-bit immediate scaled by 4. */
901 riscv_compressed_lw_offset_p (rtx x
)
903 return (CONST_INT_P (x
)
904 && (INTVAL (x
) & 3) == 0
905 && IN_RANGE (INTVAL (x
), 0, CSW_MAX_OFFSET
));
908 /* Return true if load/store from/to address x can be compressed. */
911 riscv_compressed_lw_address_p (rtx x
)
913 struct riscv_address_info addr
;
914 bool result
= riscv_classify_address (&addr
, x
, GET_MODE (x
),
917 /* Return false if address is not compressed_reg + small_offset. */
919 || addr
.type
!= ADDRESS_REG
920 /* Before reload, assume all registers are OK. */
922 && !riscv_compressed_reg_p (REGNO (addr
.reg
))
923 && addr
.reg
!= stack_pointer_rtx
)
924 || !riscv_compressed_lw_offset_p (addr
.offset
))
930 /* Return the number of instructions needed to load or store a value
931 of mode MODE at address X. Return 0 if X isn't valid for MODE.
932 Assume that multiword moves may need to be split into word moves
933 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
937 riscv_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
939 struct riscv_address_info addr
= {};
942 if (!riscv_classify_address (&addr
, x
, mode
, false))
944 /* This could be a pattern from the pic.md file. In which case we want
945 this address to always have a cost of 3 to make it as expensive as the
946 most expensive symbol. This prevents constant propagation from
947 preferring symbols over register plus offset. */
951 /* BLKmode is used for single unaligned loads and stores and should
952 not count as a multiword mode. */
953 if (mode
!= BLKmode
&& might_split_p
)
954 n
+= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
956 if (addr
.type
== ADDRESS_LO_SUM
)
957 n
+= riscv_symbol_insns (addr
.symbol_type
) - 1;
962 /* Return the number of instructions needed to load constant X.
963 Return 0 if X isn't a valid constant. */
966 riscv_const_insns (rtx x
)
968 enum riscv_symbol_type symbol_type
;
971 switch (GET_CODE (x
))
974 if (!riscv_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
975 || !riscv_split_symbol_type (symbol_type
))
978 /* This is simply an LUI. */
983 int cost
= riscv_integer_cost (INTVAL (x
));
984 /* Force complicated constants to memory. */
985 return cost
< 4 ? cost
: 0;
990 /* We can use x0 to load floating-point zero. */
991 return x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
994 /* See if we can refer to X directly. */
995 if (riscv_symbolic_constant_p (x
, &symbol_type
))
996 return riscv_symbol_insns (symbol_type
);
998 /* Otherwise try splitting the constant into a base and offset. */
999 split_const (x
, &x
, &offset
);
1002 int n
= riscv_const_insns (x
);
1004 return n
+ riscv_integer_cost (INTVAL (offset
));
1010 return riscv_symbol_insns (riscv_classify_symbol (x
));
1017 /* X is a doubleword constant that can be handled by splitting it into
1018 two words and loading each word separately. Return the number of
1019 instructions required to do this. */
1022 riscv_split_const_insns (rtx x
)
1024 unsigned int low
, high
;
1026 low
= riscv_const_insns (riscv_subword (x
, false));
1027 high
= riscv_const_insns (riscv_subword (x
, true));
1028 gcc_assert (low
> 0 && high
> 0);
1032 /* Return the number of instructions needed to implement INSN,
1033 given that it loads from or stores to MEM. */
1036 riscv_load_store_insns (rtx mem
, rtx_insn
*insn
)
1042 gcc_assert (MEM_P (mem
));
1043 mode
= GET_MODE (mem
);
1045 /* Try to prove that INSN does not need to be split. */
1046 might_split_p
= true;
1047 if (GET_MODE_BITSIZE (mode
) <= 32)
1048 might_split_p
= false;
1049 else if (GET_MODE_BITSIZE (mode
) == 64)
1051 set
= single_set (insn
);
1052 if (set
&& !riscv_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
1053 might_split_p
= false;
1056 return riscv_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
1059 /* Emit a move from SRC to DEST. Assume that the move expanders can
1060 handle all moves if !can_create_pseudo_p (). The distinction is
1061 important because, unlike emit_move_insn, the move expanders know
1062 how to force Pmode objects into the constant pool even when the
1063 constant pool address is not itself legitimate. */
1066 riscv_emit_move (rtx dest
, rtx src
)
1068 return (can_create_pseudo_p ()
1069 ? emit_move_insn (dest
, src
)
1070 : emit_move_insn_1 (dest
, src
));
1073 /* Emit an instruction of the form (set TARGET SRC). */
1076 riscv_emit_set (rtx target
, rtx src
)
1078 emit_insn (gen_rtx_SET (target
, src
));
1082 /* Emit an instruction of the form (set DEST (CODE X Y)). */
1085 riscv_emit_binary (enum rtx_code code
, rtx dest
, rtx x
, rtx y
)
1087 return riscv_emit_set (dest
, gen_rtx_fmt_ee (code
, GET_MODE (dest
), x
, y
));
1090 /* Compute (CODE X Y) and store the result in a new register
1091 of mode MODE. Return that new register. */
1094 riscv_force_binary (machine_mode mode
, enum rtx_code code
, rtx x
, rtx y
)
1096 return riscv_emit_binary (code
, gen_reg_rtx (mode
), x
, y
);
1100 riscv_swap_instruction (rtx inst
)
1102 gcc_assert (GET_MODE (inst
) == SImode
);
1103 if (BYTES_BIG_ENDIAN
)
1104 inst
= expand_unop (SImode
, bswap_optab
, inst
, gen_reg_rtx (SImode
), 1);
1108 /* Copy VALUE to a register and return that register. If new pseudos
1109 are allowed, copy it into a new register, otherwise use DEST. */
1112 riscv_force_temporary (rtx dest
, rtx value
, bool in_splitter
)
1114 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1115 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1116 combine undo buffer. */
1117 if (can_create_pseudo_p () && !in_splitter
)
1118 return force_reg (Pmode
, value
);
1121 riscv_emit_move (dest
, value
);
1126 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
1127 then add CONST_INT OFFSET to the result. */
1130 riscv_unspec_address_offset (rtx base
, rtx offset
,
1131 enum riscv_symbol_type symbol_type
)
1133 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1134 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1135 if (offset
!= const0_rtx
)
1136 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
1137 return gen_rtx_CONST (Pmode
, base
);
1140 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1141 type SYMBOL_TYPE. */
1144 riscv_unspec_address (rtx address
, enum riscv_symbol_type symbol_type
)
1148 split_const (address
, &base
, &offset
);
1149 return riscv_unspec_address_offset (base
, offset
, symbol_type
);
1152 /* If OP is an UNSPEC address, return the address to which it refers,
1153 otherwise return OP itself. */
1156 riscv_strip_unspec_address (rtx op
)
1160 split_const (op
, &base
, &offset
);
1161 if (UNSPEC_ADDRESS_P (base
))
1162 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
1166 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1167 high part to BASE and return the result. Just return BASE otherwise.
1168 TEMP is as for riscv_force_temporary.
1170 The returned expression can be used as the first operand to a LO_SUM. */
1173 riscv_unspec_offset_high (rtx temp
, rtx addr
, enum riscv_symbol_type symbol_type
)
1175 addr
= gen_rtx_HIGH (Pmode
, riscv_unspec_address (addr
, symbol_type
));
1176 return riscv_force_temporary (temp
, addr
, FALSE
);
1179 /* Load an entry from the GOT for a TLS GD access. */
1181 static rtx
riscv_got_load_tls_gd (rtx dest
, rtx sym
)
1183 if (Pmode
== DImode
)
1184 return gen_got_load_tls_gddi (dest
, sym
);
1186 return gen_got_load_tls_gdsi (dest
, sym
);
1189 /* Load an entry from the GOT for a TLS IE access. */
1191 static rtx
riscv_got_load_tls_ie (rtx dest
, rtx sym
)
1193 if (Pmode
== DImode
)
1194 return gen_got_load_tls_iedi (dest
, sym
);
1196 return gen_got_load_tls_iesi (dest
, sym
);
1199 /* Add in the thread pointer for a TLS LE access. */
1201 static rtx
riscv_tls_add_tp_le (rtx dest
, rtx base
, rtx sym
)
1203 rtx tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1204 if (Pmode
== DImode
)
1205 return gen_tls_add_tp_ledi (dest
, base
, tp
, sym
);
1207 return gen_tls_add_tp_lesi (dest
, base
, tp
, sym
);
1210 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1211 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1212 constant in that context and can be split into high and low parts.
1213 If so, and if LOW_OUT is nonnull, emit the high part and store the
1214 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1216 TEMP is as for riscv_force_temporary and is used to load the high
1217 part into a register.
1219 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1220 a legitimize SET_SRC for an .md pattern, otherwise the low part
1221 is guaranteed to be a legitimate address for mode MODE. */
1224 riscv_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
,
1227 enum riscv_symbol_type symbol_type
;
1229 if ((GET_CODE (addr
) == HIGH
&& mode
== MAX_MACHINE_MODE
)
1230 || !riscv_symbolic_constant_p (addr
, &symbol_type
)
1231 || riscv_symbol_insns (symbol_type
) == 0
1232 || !riscv_split_symbol_type (symbol_type
))
1236 switch (symbol_type
)
1238 case SYMBOL_ABSOLUTE
:
1240 rtx high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
1241 high
= riscv_force_temporary (temp
, high
, in_splitter
);
1242 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
1248 static unsigned seqno
;
1252 ssize_t bytes
= snprintf (buf
, sizeof (buf
), ".LA%u", seqno
);
1253 gcc_assert ((size_t) bytes
< sizeof (buf
));
1255 label
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
1256 SYMBOL_REF_FLAGS (label
) |= SYMBOL_FLAG_LOCAL
;
1257 /* ??? Ugly hack to make weak symbols work. May need to change the
1258 RTL for the auipc and/or low patterns to get a better fix for
1260 if (! nonzero_address_p (addr
))
1261 SYMBOL_REF_WEAK (label
) = 1;
1264 temp
= gen_reg_rtx (Pmode
);
1266 if (Pmode
== DImode
)
1267 emit_insn (gen_auipcdi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1269 emit_insn (gen_auipcsi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1271 *low_out
= gen_rtx_LO_SUM (Pmode
, temp
, label
);
1284 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1285 riscv_force_temporary; it is only needed when OFFSET is not a
1289 riscv_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1291 if (!SMALL_OPERAND (offset
))
1295 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1296 The addition inside the macro CONST_HIGH_PART may cause an
1297 overflow, so we need to force a sign-extension check. */
1298 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
1299 offset
= CONST_LOW_PART (offset
);
1300 high
= riscv_force_temporary (temp
, high
, FALSE
);
1301 reg
= riscv_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
),
1304 return plus_constant (Pmode
, reg
, offset
);
1307 /* The __tls_get_attr symbol. */
1308 static GTY(()) rtx riscv_tls_symbol
;
1310 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1311 the TLS symbol we are referencing and TYPE is the symbol type to use
1312 (either global dynamic or local dynamic). RESULT is an RTX for the
1313 return value location. */
1316 riscv_call_tls_get_addr (rtx sym
, rtx result
)
1318 rtx a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
), func
;
1321 if (!riscv_tls_symbol
)
1322 riscv_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1323 func
= gen_rtx_MEM (FUNCTION_MODE
, riscv_tls_symbol
);
1327 emit_insn (riscv_got_load_tls_gd (a0
, sym
));
1328 insn
= emit_call_insn (gen_call_value (result
, func
, const0_rtx
, NULL
));
1329 RTL_CONST_CALL_P (insn
) = 1;
1330 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1331 insn
= get_insns ();
1338 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1339 its address. The return value will be both a valid address and a valid
1340 SET_SRC (either a REG or a LO_SUM). */
1343 riscv_legitimize_tls_address (rtx loc
)
1346 enum tls_model model
= SYMBOL_REF_TLS_MODEL (loc
);
1349 /* TLS copy relocs are now deprecated and should not be used. */
1350 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1352 model
= TLS_MODEL_LOCAL_EXEC
;
1357 case TLS_MODEL_LOCAL_DYNAMIC
:
1358 /* Rely on section anchors for the optimization that LDM TLS
1359 provides. The anchor's address is loaded with GD TLS. */
1360 case TLS_MODEL_GLOBAL_DYNAMIC
:
1361 tmp
= gen_rtx_REG (Pmode
, GP_RETURN
);
1362 dest
= gen_reg_rtx (Pmode
);
1363 emit_libcall_block (riscv_call_tls_get_addr (loc
, tmp
), dest
, tmp
, loc
);
1366 case TLS_MODEL_INITIAL_EXEC
:
1367 /* la.tls.ie; tp-relative add */
1368 tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1369 tmp
= gen_reg_rtx (Pmode
);
1370 emit_insn (riscv_got_load_tls_ie (tmp
, loc
));
1371 dest
= gen_reg_rtx (Pmode
);
1372 emit_insn (gen_add3_insn (dest
, tmp
, tp
));
1375 case TLS_MODEL_LOCAL_EXEC
:
1376 tmp
= riscv_unspec_offset_high (NULL
, loc
, SYMBOL_TLS_LE
);
1377 dest
= gen_reg_rtx (Pmode
);
1378 emit_insn (riscv_tls_add_tp_le (dest
, tmp
, loc
));
1379 dest
= gen_rtx_LO_SUM (Pmode
, dest
,
1380 riscv_unspec_address (loc
, SYMBOL_TLS_LE
));
1389 /* If X is not a valid address for mode MODE, force it into a register. */
1392 riscv_force_address (rtx x
, machine_mode mode
)
1394 if (!riscv_legitimate_address_p (mode
, x
, false))
1395 x
= force_reg (Pmode
, x
);
1399 /* Modify base + offset so that offset fits within a compressed load/store insn
1400 and the excess is added to base. */
1403 riscv_shorten_lw_offset (rtx base
, HOST_WIDE_INT offset
)
1406 /* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess
1408 high
= GEN_INT (offset
& ~CSW_MAX_OFFSET
);
1409 offset
&= CSW_MAX_OFFSET
;
1410 if (!SMALL_OPERAND (INTVAL (high
)))
1411 high
= force_reg (Pmode
, high
);
1412 base
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, high
, base
));
1413 addr
= plus_constant (Pmode
, base
, offset
);
1417 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1418 be legitimized in a way that the generic machinery might not expect,
1419 return a new address, otherwise return NULL. MODE is the mode of
1420 the memory being accessed. */
1423 riscv_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1428 if (riscv_tls_symbol_p (x
))
1429 return riscv_legitimize_tls_address (x
);
1431 /* See if the address can split into a high part and a LO_SUM. */
1432 if (riscv_split_symbol (NULL
, x
, mode
, &addr
, FALSE
))
1433 return riscv_force_address (addr
, mode
);
1435 /* Handle BASE + OFFSET. */
1436 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
1437 && INTVAL (XEXP (x
, 1)) != 0)
1439 rtx base
= XEXP (x
, 0);
1440 HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
1442 if (!riscv_valid_base_register_p (base
, mode
, false))
1443 base
= copy_to_mode_reg (Pmode
, base
);
1444 if (optimize_function_for_size_p (cfun
)
1445 && (strcmp (current_pass
->name
, "shorten_memrefs") == 0)
1447 /* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow
1448 possible compressed load/store. */
1449 addr
= riscv_shorten_lw_offset (base
, offset
);
1451 addr
= riscv_add_offset (NULL
, base
, offset
);
1452 return riscv_force_address (addr
, mode
);
1458 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
1459 is the original src mode before promotion. */
1462 riscv_move_integer (rtx temp
, rtx dest
, HOST_WIDE_INT value
,
1463 machine_mode orig_mode
, bool in_splitter
)
1465 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
1470 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1471 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1472 combine undo buffer. */
1473 bool can_create_pseudo
= can_create_pseudo_p () && ! in_splitter
;
1475 mode
= GET_MODE (dest
);
1476 /* We use the original mode for the riscv_build_integer call, because HImode
1477 values are given special treatment. */
1478 num_ops
= riscv_build_integer (codes
, value
, orig_mode
);
1480 if (can_create_pseudo
&& num_ops
> 2 /* not a simple constant */
1481 && num_ops
>= riscv_split_integer_cost (value
))
1482 x
= riscv_split_integer (value
, mode
);
1485 /* Apply each binary operation to X. */
1486 x
= GEN_INT (codes
[0].value
);
1488 for (i
= 1; i
< num_ops
; i
++)
1490 if (!can_create_pseudo
)
1491 x
= riscv_emit_set (temp
, x
);
1493 x
= force_reg (mode
, x
);
1495 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1499 riscv_emit_set (dest
, x
);
1502 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1503 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1507 riscv_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
1511 /* Split moves of big integers into smaller pieces. */
1512 if (splittable_const_int_operand (src
, mode
))
1514 riscv_move_integer (dest
, dest
, INTVAL (src
), mode
, FALSE
);
1518 /* Split moves of symbolic constants into high/low pairs. */
1519 if (riscv_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
, FALSE
))
1521 riscv_emit_set (dest
, src
);
1525 /* Generate the appropriate access sequences for TLS symbols. */
1526 if (riscv_tls_symbol_p (src
))
1528 riscv_emit_move (dest
, riscv_legitimize_tls_address (src
));
1532 /* If we have (const (plus symbol offset)), and that expression cannot
1533 be forced into memory, load the symbol first and add in the offset. Also
1534 prefer to do this even if the constant _can_ be forced into memory, as it
1535 usually produces better code. */
1536 split_const (src
, &base
, &offset
);
1537 if (offset
!= const0_rtx
1538 && (targetm
.cannot_force_const_mem (mode
, src
) || can_create_pseudo_p ()))
1540 base
= riscv_force_temporary (dest
, base
, FALSE
);
1541 riscv_emit_move (dest
, riscv_add_offset (NULL
, base
, INTVAL (offset
)));
1545 src
= force_const_mem (mode
, src
);
1547 /* When using explicit relocs, constant pool references are sometimes
1548 not legitimate addresses. */
1549 riscv_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0), FALSE
);
1550 riscv_emit_move (dest
, src
);
1553 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1554 sequence that is valid. */
1557 riscv_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
1560 (set (reg:QI target) (mem:QI (address)))
1562 (set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
1563 (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
1564 with auto-sign/zero extend. */
1565 if (GET_MODE_CLASS (mode
) == MODE_INT
1566 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
1567 && can_create_pseudo_p ()
1573 temp_reg
= gen_reg_rtx (word_mode
);
1574 zero_extend_p
= (LOAD_EXTEND_OP (mode
) == ZERO_EXTEND
);
1575 emit_insn (gen_extend_insn (temp_reg
, src
, word_mode
, mode
,
1577 riscv_emit_move (dest
, gen_lowpart (mode
, temp_reg
));
1581 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1585 if (GET_CODE (src
) == CONST_INT
)
1587 /* Apply the equivalent of PROMOTE_MODE here for constants to
1589 machine_mode promoted_mode
= mode
;
1590 if (GET_MODE_CLASS (mode
) == MODE_INT
1591 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
1592 promoted_mode
= word_mode
;
1594 if (splittable_const_int_operand (src
, mode
))
1596 reg
= gen_reg_rtx (promoted_mode
);
1597 riscv_move_integer (reg
, reg
, INTVAL (src
), mode
, FALSE
);
1600 reg
= force_reg (promoted_mode
, src
);
1602 if (promoted_mode
!= mode
)
1603 reg
= gen_lowpart (mode
, reg
);
1606 reg
= force_reg (mode
, src
);
1607 riscv_emit_move (dest
, reg
);
1611 /* We need to deal with constants that would be legitimate
1612 immediate_operands but aren't legitimate move_operands. */
1613 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1615 riscv_legitimize_const_move (mode
, dest
, src
);
1616 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1620 /* RISC-V GCC may generate non-legitimate address due to we provide some
1621 pattern for optimize access PIC local symbol and it's make GCC generate
1622 unrecognizable instruction during optmizing. */
1624 if (MEM_P (dest
) && !riscv_legitimate_address_p (mode
, XEXP (dest
, 0),
1627 XEXP (dest
, 0) = riscv_force_address (XEXP (dest
, 0), mode
);
1630 if (MEM_P (src
) && !riscv_legitimate_address_p (mode
, XEXP (src
, 0),
1633 XEXP (src
, 0) = riscv_force_address (XEXP (src
, 0), mode
);
1639 /* Return true if there is an instruction that implements CODE and accepts
1640 X as an immediate operand. */
1643 riscv_immediate_operand_p (int code
, HOST_WIDE_INT x
)
1650 /* All shift counts are truncated to a valid constant. */
1659 /* These instructions take 12-bit signed immediates. */
1660 return SMALL_OPERAND (x
);
1663 /* We add 1 to the immediate and use SLT. */
1664 return SMALL_OPERAND (x
+ 1);
1667 /* Likewise SLTU, but reject the always-true case. */
1668 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
1672 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1676 /* By default assume that x0 can be used for 0. */
1681 /* Return the cost of binary operation X, given that the instruction
1682 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1683 instructions and that the sequence of a double-word operation takes
1684 DOUBLE_INSNS instructions. */
1687 riscv_binary_cost (rtx x
, int single_insns
, int double_insns
)
1689 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
1690 return COSTS_N_INSNS (double_insns
);
1691 return COSTS_N_INSNS (single_insns
);
1694 /* Return the cost of sign- or zero-extending OP. */
1697 riscv_extend_cost (rtx op
, bool unsigned_p
)
1702 if (unsigned_p
&& GET_MODE (op
) == QImode
)
1703 /* We can use ANDI. */
1704 return COSTS_N_INSNS (1);
1706 /* ZBA provide zext.w. */
1707 if (TARGET_ZBA
&& TARGET_64BIT
&& unsigned_p
&& GET_MODE (op
) == SImode
)
1708 return COSTS_N_INSNS (1);
1710 /* ZBB provide zext.h, sext.b and sext.h. */
1713 if (!unsigned_p
&& GET_MODE (op
) == QImode
)
1714 return COSTS_N_INSNS (1);
1716 if (GET_MODE (op
) == HImode
)
1717 return COSTS_N_INSNS (1);
1720 if (!unsigned_p
&& GET_MODE (op
) == SImode
)
1721 /* We can use SEXT.W. */
1722 return COSTS_N_INSNS (1);
1724 /* We need to use a shift left and a shift right. */
1725 return COSTS_N_INSNS (2);
1728 /* Implement TARGET_RTX_COSTS. */
1730 #define SINGLE_SHIFT_COST 1
1733 riscv_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1734 int *total
, bool speed
)
1736 bool float_mode_p
= FLOAT_MODE_P (mode
);
1739 switch (GET_CODE (x
))
1742 if (riscv_immediate_operand_p (outer_code
, INTVAL (x
)))
1753 if ((cost
= riscv_const_insns (x
)) > 0)
1755 /* If the constant is likely to be stored in a GPR, SETs of
1756 single-insn constants are as cheap as register sets; we
1757 never want to CSE them. */
1758 if (cost
== 1 && outer_code
== SET
)
1760 /* When we load a constant more than once, it usually is better
1761 to duplicate the last operation in the sequence than to CSE
1762 the constant itself. */
1763 else if (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
)
1764 *total
= COSTS_N_INSNS (1);
1766 else /* The instruction will be fetched from the constant pool. */
1767 *total
= COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE
));
1771 /* If the address is legitimate, return the number of
1772 instructions it needs. */
1773 if ((cost
= riscv_address_insns (XEXP (x
, 0), mode
, true)) > 0)
1775 /* When optimizing for size, make uncompressible 32-bit addresses
1776 more expensive so that compressible 32-bit addresses are
1778 if (TARGET_RVC
&& !speed
&& riscv_mshorten_memrefs
&& mode
== SImode
1779 && !riscv_compressed_lw_address_p (XEXP (x
, 0)))
1782 *total
= COSTS_N_INSNS (cost
+ tune_param
->memory_cost
);
1785 /* Otherwise use the default handling. */
1789 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
1793 /* slli.uw pattern for zba. */
1794 if (TARGET_ZBA
&& TARGET_64BIT
&& mode
== DImode
1795 && GET_CODE (XEXP (x
, 0)) == ASHIFT
)
1797 rtx and_rhs
= XEXP (x
, 1);
1798 rtx ashift_lhs
= XEXP (XEXP (x
, 0), 0);
1799 rtx ashift_rhs
= XEXP (XEXP (x
, 0), 1);
1800 if (REG_P (ashift_lhs
)
1801 && CONST_INT_P (ashift_rhs
)
1802 && CONST_INT_P (and_rhs
)
1803 && ((INTVAL (and_rhs
) >> INTVAL (ashift_rhs
)) == 0xffffffff))
1804 *total
= COSTS_N_INSNS (1);
1810 /* orn, andn and xorn pattern for zbb. */
1812 && GET_CODE (XEXP (x
, 0)) == NOT
)
1814 *total
= riscv_binary_cost (x
, 1, 2);
1817 /* Double-word operations use two single-word operations. */
1818 *total
= riscv_binary_cost (x
, 1, 2);
1822 /* This is an SImode shift. */
1823 if (outer_code
== SET
1824 && CONST_INT_P (XEXP (x
, 1))
1825 && CONST_INT_P (XEXP (x
, 2))
1826 && (INTVAL (XEXP (x
, 2)) > 0)
1827 && (INTVAL (XEXP (x
, 1)) + INTVAL (XEXP (x
, 2)) == 32))
1829 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1837 *total
= riscv_binary_cost (x
, SINGLE_SHIFT_COST
,
1838 CONSTANT_P (XEXP (x
, 1)) ? 4 : 9);
1842 *total
= COSTS_N_INSNS (float_mode_p
? 1 : 3);
1846 *total
= set_src_cost (XEXP (x
, 0), mode
, speed
);
1850 /* This is an SImode shift. */
1851 if (outer_code
== SET
&& GET_MODE (x
) == DImode
1852 && GET_MODE (XEXP (x
, 0)) == SImode
)
1854 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1867 /* Branch comparisons have VOIDmode, so use the first operand's
1869 mode
= GET_MODE (XEXP (x
, 0));
1871 *total
= tune_param
->fp_add
[mode
== DFmode
];
1873 *total
= riscv_binary_cost (x
, 1, 3);
1878 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1879 mode
= GET_MODE (XEXP (x
, 0));
1880 *total
= tune_param
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1884 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1885 mode
= GET_MODE (XEXP (x
, 0));
1886 *total
= tune_param
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (3);
1890 /* (FLT(A, A) || FGT(B, B)). */
1891 mode
= GET_MODE (XEXP (x
, 0));
1892 *total
= tune_param
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1899 /* FLT or FLE, but guarded by an FFLAGS read and write. */
1900 mode
= GET_MODE (XEXP (x
, 0));
1901 *total
= tune_param
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (4);
1906 /* add.uw pattern for zba. */
1908 && (TARGET_64BIT
&& (mode
== DImode
))
1909 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1910 && REG_P (XEXP (XEXP (x
, 0), 0))
1911 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == SImode
)
1913 *total
= COSTS_N_INSNS (1);
1916 /* shNadd pattern for zba. */
1918 && ((!TARGET_64BIT
&& (mode
== SImode
)) ||
1919 (TARGET_64BIT
&& (mode
== DImode
)))
1920 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
1921 && REG_P (XEXP (XEXP (x
, 0), 0))
1922 && CONST_INT_P (XEXP (XEXP (x
, 0), 0))
1923 && IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 0)), 1, 3))
1925 *total
= COSTS_N_INSNS (1);
1928 /* shNadd.uw pattern for zba.
1929 [(set (match_operand:DI 0 "register_operand" "=r")
1931 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1932 (match_operand:QI 2 "immediate_operand" "I"))
1933 (match_operand 3 "immediate_operand" ""))
1934 (match_operand:DI 4 "register_operand" "r")))]
1935 "TARGET_64BIT && TARGET_ZBA
1936 && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
1937 && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
1940 && (TARGET_64BIT
&& (mode
== DImode
))
1941 && (GET_CODE (XEXP (x
, 0)) == AND
)
1942 && (REG_P (XEXP (x
, 1))))
1945 rtx and_lhs
= XEXP (XEXP (x
, 0), 0);
1946 rtx and_rhs
= XEXP (XEXP (x
, 0), 1);
1947 if (GET_CODE (and_lhs
) != ASHIFT
)
1949 if (!CONST_INT_P (and_rhs
))
1952 rtx ashift_lhs
= XEXP (and_lhs
, 0);
1953 rtx ashift_rhs
= XEXP (and_lhs
, 1);
1955 if (!CONST_INT_P (ashift_rhs
)
1956 || !IN_RANGE (INTVAL (ashift_rhs
), 1, 3))
1959 if (CONST_INT_P (and_rhs
)
1960 && ((INTVAL (and_rhs
) >> INTVAL (ashift_rhs
)) == 0xffffffff))
1962 *total
= COSTS_N_INSNS (1);
1969 *total
= tune_param
->fp_add
[mode
== DFmode
];
1971 *total
= riscv_binary_cost (x
, 1, 4);
1976 rtx op
= XEXP (x
, 0);
1977 if (GET_CODE (op
) == FMA
&& !HONOR_SIGNED_ZEROS (mode
))
1979 *total
= (tune_param
->fp_mul
[mode
== DFmode
]
1980 + set_src_cost (XEXP (op
, 0), mode
, speed
)
1981 + set_src_cost (XEXP (op
, 1), mode
, speed
)
1982 + set_src_cost (XEXP (op
, 2), mode
, speed
));
1988 *total
= tune_param
->fp_add
[mode
== DFmode
];
1990 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
1995 *total
= tune_param
->fp_mul
[mode
== DFmode
];
1996 else if (!TARGET_MUL
)
1997 /* Estimate the cost of a library call. */
1998 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1999 else if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
2000 *total
= 3 * tune_param
->int_mul
[0] + COSTS_N_INSNS (2);
2002 *total
= COSTS_N_INSNS (1);
2004 *total
= tune_param
->int_mul
[mode
== DImode
];
2012 *total
= tune_param
->fp_div
[mode
== DFmode
];
2020 /* Estimate the cost of a library call. */
2021 *total
= COSTS_N_INSNS (speed
? 32 : 6);
2023 *total
= tune_param
->int_div
[mode
== DImode
];
2025 *total
= COSTS_N_INSNS (1);
2029 /* This is an SImode shift. */
2030 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
2032 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
2037 *total
= riscv_extend_cost (XEXP (x
, 0), GET_CODE (x
) == ZERO_EXTEND
);
2041 case UNSIGNED_FLOAT
:
2044 case FLOAT_TRUNCATE
:
2045 *total
= tune_param
->fp_add
[mode
== DFmode
];
2049 *total
= (tune_param
->fp_mul
[mode
== DFmode
]
2050 + set_src_cost (XEXP (x
, 0), mode
, speed
)
2051 + set_src_cost (XEXP (x
, 1), mode
, speed
)
2052 + set_src_cost (XEXP (x
, 2), mode
, speed
));
2056 if (XINT (x
, 1) == UNSPEC_AUIPC
)
2058 /* Make AUIPC cheap to avoid spilling its result to the stack. */
2069 /* Implement TARGET_ADDRESS_COST. */
2072 riscv_address_cost (rtx addr
, machine_mode mode
,
2073 addr_space_t as ATTRIBUTE_UNUSED
,
2074 bool speed ATTRIBUTE_UNUSED
)
2076 /* When optimizing for size, make uncompressible 32-bit addresses more
2077 * expensive so that compressible 32-bit addresses are preferred. */
2078 if (TARGET_RVC
&& !speed
&& riscv_mshorten_memrefs
&& mode
== SImode
2079 && !riscv_compressed_lw_address_p (addr
))
2080 return riscv_address_insns (addr
, mode
, false) + 1;
2081 return riscv_address_insns (addr
, mode
, false);
2084 /* Return one word of double-word value OP. HIGH_P is true to select the
2085 high part or false to select the low part. */
2088 riscv_subword (rtx op
, bool high_p
)
2090 unsigned int byte
= (high_p
!= BYTES_BIG_ENDIAN
) ? UNITS_PER_WORD
: 0;
2091 machine_mode mode
= GET_MODE (op
);
2093 if (mode
== VOIDmode
)
2094 mode
= TARGET_64BIT
? TImode
: DImode
;
2097 return adjust_address (op
, word_mode
, byte
);
2100 gcc_assert (!FP_REG_RTX_P (op
));
2102 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
2105 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2108 riscv_split_64bit_move_p (rtx dest
, rtx src
)
2113 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
2114 of zeroing an FPR with FCVT.D.W. */
2115 if (TARGET_DOUBLE_FLOAT
2116 && ((FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
2117 || (FP_REG_RTX_P (dest
) && MEM_P (src
))
2118 || (FP_REG_RTX_P (src
) && MEM_P (dest
))
2119 || (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))))
2125 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
2126 this function handles 64-bit moves for which riscv_split_64bit_move_p
2127 holds. For 64-bit targets, this function handles 128-bit moves. */
2130 riscv_split_doubleword_move (rtx dest
, rtx src
)
2134 /* The operation can be split into two normal moves. Decide in
2135 which order to do them. */
2136 low_dest
= riscv_subword (dest
, false);
2137 if (REG_P (low_dest
) && reg_overlap_mentioned_p (low_dest
, src
))
2139 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
2140 riscv_emit_move (low_dest
, riscv_subword (src
, false));
2144 riscv_emit_move (low_dest
, riscv_subword (src
, false));
2145 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
2149 /* Return the appropriate instructions to move SRC into DEST. Assume
2150 that SRC is operand 1 and DEST is operand 0. */
2153 riscv_output_move (rtx dest
, rtx src
)
2155 enum rtx_code dest_code
, src_code
;
2159 dest_code
= GET_CODE (dest
);
2160 src_code
= GET_CODE (src
);
2161 mode
= GET_MODE (dest
);
2162 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
2164 if (dbl_p
&& riscv_split_64bit_move_p (dest
, src
))
2167 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
2169 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2170 return dbl_p
? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1";
2172 if (src_code
== MEM
)
2173 switch (GET_MODE_SIZE (mode
))
2175 case 1: return "lbu\t%0,%1";
2176 case 2: return "lhu\t%0,%1";
2177 case 4: return "lw\t%0,%1";
2178 case 8: return "ld\t%0,%1";
2181 if (src_code
== CONST_INT
)
2184 if (src_code
== HIGH
)
2185 return "lui\t%0,%h1";
2187 if (symbolic_operand (src
, VOIDmode
))
2188 switch (riscv_classify_symbolic_expression (src
))
2190 case SYMBOL_GOT_DISP
: return "la\t%0,%1";
2191 case SYMBOL_ABSOLUTE
: return "lla\t%0,%1";
2192 case SYMBOL_PCREL
: return "lla\t%0,%1";
2193 default: gcc_unreachable ();
2196 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
2197 || (src
== CONST0_RTX (mode
)))
2199 if (dest_code
== REG
)
2201 if (GP_REG_P (REGNO (dest
)))
2202 return "mv\t%0,%z1";
2204 if (FP_REG_P (REGNO (dest
)))
2207 return "fmv.w.x\t%0,%z1";
2209 return "fmv.d.x\t%0,%z1";
2210 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
2211 gcc_assert (src
== CONST0_RTX (mode
));
2212 return "fcvt.d.w\t%0,x0";
2215 if (dest_code
== MEM
)
2216 switch (GET_MODE_SIZE (mode
))
2218 case 1: return "sb\t%z1,%0";
2219 case 2: return "sh\t%z1,%0";
2220 case 4: return "sw\t%z1,%0";
2221 case 8: return "sd\t%z1,%0";
2224 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2226 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2227 return dbl_p
? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
2229 if (dest_code
== MEM
)
2230 return dbl_p
? "fsd\t%1,%0" : "fsw\t%1,%0";
2232 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2234 if (src_code
== MEM
)
2235 return dbl_p
? "fld\t%0,%1" : "flw\t%0,%1";
2241 riscv_output_return ()
2243 if (cfun
->machine
->naked_p
)
2250 /* Return true if CMP1 is a suitable second operand for integer ordering
2251 test CODE. See also the *sCC patterns in riscv.md. */
2254 riscv_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
2260 return reg_or_0_operand (cmp1
, VOIDmode
);
2264 return cmp1
== const1_rtx
;
2268 return arith_operand (cmp1
, VOIDmode
);
2271 return sle_operand (cmp1
, VOIDmode
);
2274 return sleu_operand (cmp1
, VOIDmode
);
2281 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
2282 integer ordering test *CODE, or if an equivalent combination can
2283 be formed by adjusting *CODE and *CMP1. When returning true, update
2284 *CODE and *CMP1 with the chosen code and operand, otherwise leave
2288 riscv_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
2291 HOST_WIDE_INT plus_one
;
2293 if (riscv_int_order_operand_ok_p (*code
, *cmp1
))
2296 if (CONST_INT_P (*cmp1
))
2300 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2301 if (INTVAL (*cmp1
) < plus_one
)
2304 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2310 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2314 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2325 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
2326 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
2327 is nonnull, it's OK to set TARGET to the inverse of the result and
2328 flip *INVERT_PTR instead. */
2331 riscv_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
2332 rtx target
, rtx cmp0
, rtx cmp1
)
2336 /* First see if there is a RISCV instruction that can do this operation.
2337 If not, try doing the same for the inverse operation. If that also
2338 fails, force CMP1 into a register and try again. */
2339 mode
= GET_MODE (cmp0
);
2340 if (riscv_canonicalize_int_order_test (&code
, &cmp1
, mode
))
2341 riscv_emit_binary (code
, target
, cmp0
, cmp1
);
2344 enum rtx_code inv_code
= reverse_condition (code
);
2345 if (!riscv_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
2347 cmp1
= force_reg (mode
, cmp1
);
2348 riscv_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
2350 else if (invert_ptr
== 0)
2352 rtx inv_target
= riscv_force_binary (GET_MODE (target
),
2353 inv_code
, cmp0
, cmp1
);
2354 riscv_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
2358 *invert_ptr
= !*invert_ptr
;
2359 riscv_emit_binary (inv_code
, target
, cmp0
, cmp1
);
2364 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2365 The register will have the same mode as CMP0. */
2368 riscv_zero_if_equal (rtx cmp0
, rtx cmp1
)
2370 if (cmp1
== const0_rtx
)
2373 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2374 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2377 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2380 riscv_extend_comparands (rtx_code code
, rtx
*op0
, rtx
*op1
)
2382 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2383 if (GET_MODE_SIZE (word_mode
) > GET_MODE_SIZE (GET_MODE (*op0
)))
2385 /* It is more profitable to zero-extend QImode values. But not if the
2386 first operand has already been sign-extended, and the second one is
2387 is a constant or has already been sign-extended also. */
2388 if (unsigned_condition (code
) == code
2389 && (GET_MODE (*op0
) == QImode
2390 && ! (GET_CODE (*op0
) == SUBREG
2391 && SUBREG_PROMOTED_VAR_P (*op0
)
2392 && SUBREG_PROMOTED_SIGNED_P (*op0
)
2393 && (CONST_INT_P (*op1
)
2394 || (GET_CODE (*op1
) == SUBREG
2395 && SUBREG_PROMOTED_VAR_P (*op1
)
2396 && SUBREG_PROMOTED_SIGNED_P (*op1
))))))
2398 *op0
= gen_rtx_ZERO_EXTEND (word_mode
, *op0
);
2399 if (CONST_INT_P (*op1
))
2400 *op1
= GEN_INT ((uint8_t) INTVAL (*op1
));
2402 *op1
= gen_rtx_ZERO_EXTEND (word_mode
, *op1
);
2406 *op0
= gen_rtx_SIGN_EXTEND (word_mode
, *op0
);
2407 if (*op1
!= const0_rtx
)
2408 *op1
= gen_rtx_SIGN_EXTEND (word_mode
, *op1
);
2413 /* Convert a comparison into something that can be used in a branch. On
2414 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2415 used to compare them. Update them to describe the final comparison. */
2418 riscv_emit_int_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2420 if (splittable_const_int_operand (*op1
, VOIDmode
))
2422 HOST_WIDE_INT rhs
= INTVAL (*op1
);
2424 if (*code
== EQ
|| *code
== NE
)
2426 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2427 if (SMALL_OPERAND (-rhs
))
2429 *op0
= riscv_force_binary (GET_MODE (*op0
), PLUS
, *op0
,
2436 static const enum rtx_code mag_comparisons
[][2] = {
2437 {LEU
, LTU
}, {GTU
, GEU
}, {LE
, LT
}, {GT
, GE
}
2440 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2441 for (size_t i
= 0; i
< ARRAY_SIZE (mag_comparisons
); i
++)
2443 HOST_WIDE_INT new_rhs
;
2444 bool increment
= *code
== mag_comparisons
[i
][0];
2445 bool decrement
= *code
== mag_comparisons
[i
][1];
2446 if (!increment
&& !decrement
)
2449 new_rhs
= rhs
+ (increment
? 1 : -1);
2450 if (riscv_integer_cost (new_rhs
) < riscv_integer_cost (rhs
)
2451 && (rhs
< 0) == (new_rhs
< 0))
2453 *op1
= GEN_INT (new_rhs
);
2454 *code
= mag_comparisons
[i
][increment
];
2461 riscv_extend_comparands (*code
, op0
, op1
);
2463 *op0
= force_reg (word_mode
, *op0
);
2464 if (*op1
!= const0_rtx
)
2465 *op1
= force_reg (word_mode
, *op1
);
2468 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2471 riscv_emit_float_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2473 rtx tmp0
, tmp1
, cmp_op0
= *op0
, cmp_op1
= *op1
;
2474 enum rtx_code fp_code
= *code
;
2484 /* a == a && b == b */
2485 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2486 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2487 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2492 /* ordered(a, b) > (a == b) */
2494 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2495 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2496 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2497 *op1
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op1
);
2500 #define UNORDERED_COMPARISON(CODE, CMP) \
2503 *op0 = gen_reg_rtx (word_mode); \
2504 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2505 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2506 else if (GET_MODE (cmp_op0) == SFmode) \
2507 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2508 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2509 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2510 else if (GET_MODE (cmp_op0) == DFmode) \
2511 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2513 gcc_unreachable (); \
2514 *op1 = const0_rtx; \
2518 std::swap (cmp_op0
, cmp_op1
);
2521 UNORDERED_COMPARISON(UNGT
, le
)
2524 std::swap (cmp_op0
, cmp_op1
);
2527 UNORDERED_COMPARISON(UNGE
, lt
)
2528 #undef UNORDERED_COMPARISON
2540 /* We have instructions for these cases. */
2541 *op0
= riscv_force_binary (word_mode
, fp_code
, cmp_op0
, cmp_op1
);
2546 /* (a < b) | (a > b) */
2547 tmp0
= riscv_force_binary (word_mode
, LT
, cmp_op0
, cmp_op1
);
2548 tmp1
= riscv_force_binary (word_mode
, GT
, cmp_op0
, cmp_op1
);
2549 *op0
= riscv_force_binary (word_mode
, IOR
, tmp0
, tmp1
);
2558 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2561 riscv_expand_int_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2563 riscv_extend_comparands (code
, &op0
, &op1
);
2564 op0
= force_reg (word_mode
, op0
);
2566 if (code
== EQ
|| code
== NE
)
2568 rtx zie
= riscv_zero_if_equal (op0
, op1
);
2569 riscv_emit_binary (code
, target
, zie
, const0_rtx
);
2572 riscv_emit_int_order_test (code
, 0, target
, op0
, op1
);
2575 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2578 riscv_expand_float_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2580 riscv_emit_float_compare (&code
, &op0
, &op1
);
2582 rtx cmp
= riscv_force_binary (word_mode
, code
, op0
, op1
);
2583 riscv_emit_set (target
, lowpart_subreg (SImode
, cmp
, word_mode
));
2586 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2589 riscv_expand_conditional_branch (rtx label
, rtx_code code
, rtx op0
, rtx op1
)
2591 if (FLOAT_MODE_P (GET_MODE (op1
)))
2592 riscv_emit_float_compare (&code
, &op0
, &op1
);
2594 riscv_emit_int_compare (&code
, &op0
, &op1
);
2596 rtx condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2597 emit_jump_insn (gen_condjump (condition
, label
));
2600 /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
2603 riscv_expand_conditional_move (rtx dest
, rtx cons
, rtx alt
, rtx_code code
,
2606 riscv_emit_int_compare (&code
, &op0
, &op1
);
2607 rtx cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
2608 emit_insn (gen_rtx_SET (dest
, gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), cond
,
2612 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2613 least PARM_BOUNDARY bits of alignment, but will be given anything up
2614 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2617 riscv_function_arg_boundary (machine_mode mode
, const_tree type
)
2619 unsigned int alignment
;
2621 /* Use natural alignment if the type is not aggregate data. */
2622 if (type
&& !AGGREGATE_TYPE_P (type
))
2623 alignment
= TYPE_ALIGN (TYPE_MAIN_VARIANT (type
));
2625 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2627 return MIN (PREFERRED_STACK_BOUNDARY
, MAX (PARM_BOUNDARY
, alignment
));
2630 /* If MODE represents an argument that can be passed or returned in
2631 floating-point registers, return the number of registers, else 0. */
2634 riscv_pass_mode_in_fpr_p (machine_mode mode
)
2636 if (GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FP_ARG
)
2638 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2641 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
2650 HOST_WIDE_INT offset
;
2651 } riscv_aggregate_field
;
2653 /* Identify subfields of aggregates that are candidates for passing in
2654 floating-point registers. */
2657 riscv_flatten_aggregate_field (const_tree type
,
2658 riscv_aggregate_field fields
[2],
2659 int n
, HOST_WIDE_INT offset
,
2660 bool ignore_zero_width_bit_field_p
)
2662 switch (TREE_CODE (type
))
2665 /* Can't handle incomplete types nor sizes that are not fixed. */
2666 if (!COMPLETE_TYPE_P (type
)
2667 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2668 || !tree_fits_uhwi_p (TYPE_SIZE (type
)))
2671 for (tree f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
2672 if (TREE_CODE (f
) == FIELD_DECL
)
2674 if (!TYPE_P (TREE_TYPE (f
)))
2677 /* The C++ front end strips zero-length bit-fields from structs.
2678 So we need to ignore them in the C front end to make C code
2679 compatible with C++ code. */
2680 if (ignore_zero_width_bit_field_p
2681 && DECL_BIT_FIELD (f
)
2682 && (DECL_SIZE (f
) == NULL_TREE
2683 || integer_zerop (DECL_SIZE (f
))))
2687 HOST_WIDE_INT pos
= offset
+ int_byte_position (f
);
2688 n
= riscv_flatten_aggregate_field (TREE_TYPE (f
),
2690 ignore_zero_width_bit_field_p
);
2699 HOST_WIDE_INT n_elts
;
2700 riscv_aggregate_field subfields
[2];
2701 tree index
= TYPE_DOMAIN (type
);
2702 tree elt_size
= TYPE_SIZE_UNIT (TREE_TYPE (type
));
2703 int n_subfields
= riscv_flatten_aggregate_field (TREE_TYPE (type
),
2704 subfields
, 0, offset
,
2705 ignore_zero_width_bit_field_p
);
2707 /* Can't handle incomplete types nor sizes that are not fixed. */
2708 if (n_subfields
<= 0
2709 || !COMPLETE_TYPE_P (type
)
2710 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2712 || !TYPE_MAX_VALUE (index
)
2713 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
2714 || !TYPE_MIN_VALUE (index
)
2715 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
2716 || !tree_fits_uhwi_p (elt_size
))
2719 n_elts
= 1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
2720 - tree_to_uhwi (TYPE_MIN_VALUE (index
));
2721 gcc_assert (n_elts
>= 0);
2723 for (HOST_WIDE_INT i
= 0; i
< n_elts
; i
++)
2724 for (int j
= 0; j
< n_subfields
; j
++)
2729 fields
[n
] = subfields
[j
];
2730 fields
[n
++].offset
+= i
* tree_to_uhwi (elt_size
);
2738 /* Complex type need consume 2 field, so n must be 0. */
2742 HOST_WIDE_INT elt_size
= GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type
)));
2744 if (elt_size
<= UNITS_PER_FP_ARG
)
2746 fields
[0].type
= TREE_TYPE (type
);
2747 fields
[0].offset
= offset
;
2748 fields
[1].type
= TREE_TYPE (type
);
2749 fields
[1].offset
= offset
+ elt_size
;
2759 && ((SCALAR_FLOAT_TYPE_P (type
)
2760 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FP_ARG
)
2761 || (INTEGRAL_TYPE_P (type
)
2762 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_WORD
)))
2764 fields
[n
].type
= type
;
2765 fields
[n
].offset
= offset
;
2773 /* Identify candidate aggregates for passing in floating-point registers.
2774 Candidates have at most two fields after flattening. */
2777 riscv_flatten_aggregate_argument (const_tree type
,
2778 riscv_aggregate_field fields
[2],
2779 bool ignore_zero_width_bit_field_p
)
2781 if (!type
|| TREE_CODE (type
) != RECORD_TYPE
)
2784 return riscv_flatten_aggregate_field (type
, fields
, 0, 0,
2785 ignore_zero_width_bit_field_p
);
2788 /* See whether TYPE is a record whose fields should be returned in one or
2789 two floating-point registers. If so, populate FIELDS accordingly. */
2792 riscv_pass_aggregate_in_fpr_pair_p (const_tree type
,
2793 riscv_aggregate_field fields
[2])
2795 static int warned
= 0;
2797 /* This is the old ABI, which differs for C++ and C. */
2798 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2799 for (int i
= 0; i
< n_old
; i
++)
2800 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2806 /* This is the new ABI, which is the same for C++ and C. */
2807 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2808 for (int i
= 0; i
< n_new
; i
++)
2809 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2815 if ((n_old
!= n_new
) && (warned
== 0))
2817 warning (0, "ABI for flattened struct with zero-length bit-fields "
2818 "changed in GCC 10");
2822 return n_new
> 0 ? n_new
: 0;
2825 /* See whether TYPE is a record whose fields should be returned in one or
2826 floating-point register and one integer register. If so, populate
2827 FIELDS accordingly. */
2830 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type
,
2831 riscv_aggregate_field fields
[2])
2833 static int warned
= 0;
2835 /* This is the old ABI, which differs for C++ and C. */
2836 unsigned num_int_old
= 0, num_float_old
= 0;
2837 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2838 for (int i
= 0; i
< n_old
; i
++)
2840 num_float_old
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2841 num_int_old
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2844 /* This is the new ABI, which is the same for C++ and C. */
2845 unsigned num_int_new
= 0, num_float_new
= 0;
2846 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2847 for (int i
= 0; i
< n_new
; i
++)
2849 num_float_new
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2850 num_int_new
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2853 if (((num_int_old
== 1 && num_float_old
== 1
2854 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
))
2855 || (num_int_new
== 1 && num_float_new
== 1
2856 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
)))
2859 warning (0, "ABI for flattened struct with zero-length bit-fields "
2860 "changed in GCC 10");
2864 return num_int_new
== 1 && num_float_new
== 1;
2867 /* Return the representation of an argument passed or returned in an FPR
2868 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2869 two modes may be different for structures like:
2871 struct __attribute__((packed)) foo { float f; }
2873 where the SFmode value "f" is passed in REGNO but the struct itself
2874 has mode BLKmode. */
2877 riscv_pass_fpr_single (machine_mode type_mode
, unsigned regno
,
2878 machine_mode value_mode
,
2879 HOST_WIDE_INT offset
)
2881 rtx x
= gen_rtx_REG (value_mode
, regno
);
2883 if (type_mode
!= value_mode
)
2885 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, GEN_INT (offset
));
2886 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
2891 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
2892 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
2893 byte offset for the first value, likewise MODE2 and OFFSET2 for the
2897 riscv_pass_fpr_pair (machine_mode mode
, unsigned regno1
,
2898 machine_mode mode1
, HOST_WIDE_INT offset1
,
2899 unsigned regno2
, machine_mode mode2
,
2900 HOST_WIDE_INT offset2
)
2902 return gen_rtx_PARALLEL
2905 gen_rtx_EXPR_LIST (VOIDmode
,
2906 gen_rtx_REG (mode1
, regno1
),
2908 gen_rtx_EXPR_LIST (VOIDmode
,
2909 gen_rtx_REG (mode2
, regno2
),
2910 GEN_INT (offset2
))));
2913 /* Fill INFO with information about a single argument, and return an
2914 RTL pattern to pass or return the argument. CUM is the cumulative
2915 state for earlier arguments. MODE is the mode of this argument and
2916 TYPE is its type (if known). NAMED is true if this is a named
2917 (fixed) argument rather than a variable one. RETURN_P is true if
2918 returning the argument, or false if passing the argument. */
2921 riscv_get_arg_info (struct riscv_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
2922 machine_mode mode
, const_tree type
, bool named
,
2925 unsigned num_bytes
, num_words
;
2926 unsigned fpr_base
= return_p
? FP_RETURN
: FP_ARG_FIRST
;
2927 unsigned gpr_base
= return_p
? GP_RETURN
: GP_ARG_FIRST
;
2928 unsigned alignment
= riscv_function_arg_boundary (mode
, type
);
2930 memset (info
, 0, sizeof (*info
));
2931 info
->gpr_offset
= cum
->num_gprs
;
2932 info
->fpr_offset
= cum
->num_fprs
;
2936 riscv_aggregate_field fields
[2];
2937 unsigned fregno
= fpr_base
+ info
->fpr_offset
;
2938 unsigned gregno
= gpr_base
+ info
->gpr_offset
;
2940 /* Pass one- or two-element floating-point aggregates in FPRs. */
2941 if ((info
->num_fprs
= riscv_pass_aggregate_in_fpr_pair_p (type
, fields
))
2942 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2943 switch (info
->num_fprs
)
2946 return riscv_pass_fpr_single (mode
, fregno
,
2947 TYPE_MODE (fields
[0].type
),
2951 return riscv_pass_fpr_pair (mode
, fregno
,
2952 TYPE_MODE (fields
[0].type
),
2955 TYPE_MODE (fields
[1].type
),
2962 /* Pass real and complex floating-point numbers in FPRs. */
2963 if ((info
->num_fprs
= riscv_pass_mode_in_fpr_p (mode
))
2964 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2965 switch (GET_MODE_CLASS (mode
))
2968 return gen_rtx_REG (mode
, fregno
);
2970 case MODE_COMPLEX_FLOAT
:
2971 return riscv_pass_fpr_pair (mode
, fregno
, GET_MODE_INNER (mode
), 0,
2972 fregno
+ 1, GET_MODE_INNER (mode
),
2973 GET_MODE_UNIT_SIZE (mode
));
2979 /* Pass structs with one float and one integer in an FPR and a GPR. */
2980 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type
, fields
)
2981 && info
->gpr_offset
< MAX_ARGS_IN_REGISTERS
2982 && info
->fpr_offset
< MAX_ARGS_IN_REGISTERS
)
2987 if (!SCALAR_FLOAT_TYPE_P (fields
[0].type
))
2988 std::swap (fregno
, gregno
);
2990 return riscv_pass_fpr_pair (mode
, fregno
, TYPE_MODE (fields
[0].type
),
2992 gregno
, TYPE_MODE (fields
[1].type
),
2997 /* Work out the size of the argument. */
2998 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2999 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3001 /* Doubleword-aligned varargs start on an even register boundary. */
3002 if (!named
&& num_bytes
!= 0 && alignment
> BITS_PER_WORD
)
3003 info
->gpr_offset
+= info
->gpr_offset
& 1;
3005 /* Partition the argument between registers and stack. */
3007 info
->num_gprs
= MIN (num_words
, MAX_ARGS_IN_REGISTERS
- info
->gpr_offset
);
3008 info
->stack_p
= (num_words
- info
->num_gprs
) != 0;
3010 if (info
->num_gprs
|| return_p
)
3011 return gen_rtx_REG (mode
, gpr_base
+ info
->gpr_offset
);
3016 /* Implement TARGET_FUNCTION_ARG. */
3019 riscv_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
3021 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3022 struct riscv_arg_info info
;
3024 if (arg
.end_marker_p ())
3027 return riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
3030 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
3033 riscv_function_arg_advance (cumulative_args_t cum_v
,
3034 const function_arg_info
&arg
)
3036 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3037 struct riscv_arg_info info
;
3039 riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
3041 /* Advance the register count. This has the effect of setting
3042 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
3043 argument required us to skip the final GPR and pass the whole
3044 argument on the stack. */
3045 cum
->num_fprs
= info
.fpr_offset
+ info
.num_fprs
;
3046 cum
->num_gprs
= info
.gpr_offset
+ info
.num_gprs
;
3049 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3052 riscv_arg_partial_bytes (cumulative_args_t cum
,
3053 const function_arg_info
&generic_arg
)
3055 struct riscv_arg_info arg
;
3057 riscv_get_arg_info (&arg
, get_cumulative_args (cum
), generic_arg
.mode
,
3058 generic_arg
.type
, generic_arg
.named
, false);
3059 return arg
.stack_p
? arg
.num_gprs
* UNITS_PER_WORD
: 0;
3062 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
3063 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
3064 VALTYPE is null and MODE is the mode of the return value. */
3067 riscv_function_value (const_tree type
, const_tree func
, machine_mode mode
)
3069 struct riscv_arg_info info
;
3070 CUMULATIVE_ARGS args
;
3074 int unsigned_p
= TYPE_UNSIGNED (type
);
3076 mode
= TYPE_MODE (type
);
3078 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
3079 return values, promote the mode here too. */
3080 mode
= promote_function_mode (type
, mode
, &unsigned_p
, func
, 1);
3083 memset (&args
, 0, sizeof args
);
3084 return riscv_get_arg_info (&info
, &args
, mode
, type
, true, true);
3087 /* Implement TARGET_PASS_BY_REFERENCE. */
3090 riscv_pass_by_reference (cumulative_args_t cum_v
, const function_arg_info
&arg
)
3092 HOST_WIDE_INT size
= arg
.type_size_in_bytes ();
3093 struct riscv_arg_info info
;
3094 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3096 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
3097 never pass variadic arguments in floating-point registers, so we can
3098 avoid the call to riscv_get_arg_info in this case. */
3101 /* Don't pass by reference if we can use a floating-point register. */
3102 riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
3107 /* Pass by reference if the data do not fit in two integer registers. */
3108 return !IN_RANGE (size
, 0, 2 * UNITS_PER_WORD
);
3111 /* Implement TARGET_RETURN_IN_MEMORY. */
3114 riscv_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
3116 CUMULATIVE_ARGS args
;
3117 cumulative_args_t cum
= pack_cumulative_args (&args
);
3119 /* The rules for returning in memory are the same as for passing the
3120 first named argument by reference. */
3121 memset (&args
, 0, sizeof args
);
3122 function_arg_info
arg (const_cast<tree
> (type
), /*named=*/true);
3123 return riscv_pass_by_reference (cum
, arg
);
3126 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
3129 riscv_setup_incoming_varargs (cumulative_args_t cum
,
3130 const function_arg_info
&arg
,
3131 int *pretend_size ATTRIBUTE_UNUSED
, int no_rtl
)
3133 CUMULATIVE_ARGS local_cum
;
3136 /* The caller has advanced CUM up to, but not beyond, the last named
3137 argument. Advance a local copy of CUM past the last "real" named
3138 argument, to find out how many registers are left over. */
3139 local_cum
= *get_cumulative_args (cum
);
3140 riscv_function_arg_advance (pack_cumulative_args (&local_cum
), arg
);
3142 /* Found out how many registers we need to save. */
3143 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
3145 if (!no_rtl
&& gp_saved
> 0)
3147 rtx ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
3148 REG_PARM_STACK_SPACE (cfun
->decl
)
3149 - gp_saved
* UNITS_PER_WORD
);
3150 rtx mem
= gen_frame_mem (BLKmode
, ptr
);
3151 set_mem_alias_set (mem
, get_varargs_alias_set ());
3153 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
3156 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
3157 cfun
->machine
->varargs_size
= gp_saved
* UNITS_PER_WORD
;
3160 /* Handle an attribute requiring a FUNCTION_DECL;
3161 arguments as in struct attribute_spec.handler. */
3163 riscv_handle_fndecl_attribute (tree
*node
, tree name
,
3164 tree args ATTRIBUTE_UNUSED
,
3165 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
3167 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3169 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3171 *no_add_attrs
= true;
3177 /* Verify type based attributes. NODE is the what the attribute is being
3178 applied to. NAME is the attribute name. ARGS are the attribute args.
3179 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
3180 the attribute should be ignored. */
3183 riscv_handle_type_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
3184 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
3186 /* Check for an argument. */
3187 if (is_attribute_p ("interrupt", name
))
3191 tree cst
= TREE_VALUE (args
);
3194 if (TREE_CODE (cst
) != STRING_CST
)
3196 warning (OPT_Wattributes
,
3197 "%qE attribute requires a string argument",
3199 *no_add_attrs
= true;
3203 string
= TREE_STRING_POINTER (cst
);
3204 if (strcmp (string
, "user") && strcmp (string
, "supervisor")
3205 && strcmp (string
, "machine"))
3207 warning (OPT_Wattributes
,
3208 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"",
3210 *no_add_attrs
= true;
3218 /* Return true if function TYPE is an interrupt function. */
3220 riscv_interrupt_type_p (tree type
)
3222 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
3225 /* Return true if FUNC is a naked function. */
3227 riscv_naked_function_p (tree func
)
3229 tree func_decl
= func
;
3230 if (func
== NULL_TREE
)
3231 func_decl
= current_function_decl
;
3232 return NULL_TREE
!= lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl
));
3235 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
3237 riscv_allocate_stack_slots_for_args ()
3239 /* Naked functions should not allocate stack slots for arguments. */
3240 return !riscv_naked_function_p (current_function_decl
);
3243 /* Implement TARGET_WARN_FUNC_RETURN. */
3245 riscv_warn_func_return (tree decl
)
3247 /* Naked functions are implemented entirely in assembly, including the
3248 return sequence, so suppress warnings about this. */
3249 return !riscv_naked_function_p (decl
);
3252 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
3255 riscv_va_start (tree valist
, rtx nextarg
)
3257 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
3258 std_expand_builtin_va_start (valist
, nextarg
);
3261 /* Make ADDR suitable for use as a call or sibcall target. */
3264 riscv_legitimize_call_address (rtx addr
)
3266 if (!call_insn_operand (addr
, VOIDmode
))
3268 rtx reg
= RISCV_CALL_ADDRESS_TEMP (Pmode
);
3269 riscv_emit_move (reg
, addr
);
3275 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3276 Assume that the areas do not overlap. */
3279 riscv_block_move_straight (rtx dest
, rtx src
, unsigned HOST_WIDE_INT length
)
3281 unsigned HOST_WIDE_INT offset
, delta
;
3282 unsigned HOST_WIDE_INT bits
;
3284 enum machine_mode mode
;
3287 bits
= MAX (BITS_PER_UNIT
,
3288 MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
))));
3290 mode
= mode_for_size (bits
, MODE_INT
, 0).require ();
3291 delta
= bits
/ BITS_PER_UNIT
;
3293 /* Allocate a buffer for the temporary registers. */
3294 regs
= XALLOCAVEC (rtx
, length
/ delta
);
3296 /* Load as many BITS-sized chunks as possible. Use a normal load if
3297 the source has enough alignment, otherwise use left/right pairs. */
3298 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3300 regs
[i
] = gen_reg_rtx (mode
);
3301 riscv_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
3304 /* Copy the chunks to the destination. */
3305 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3306 riscv_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
3308 /* Mop up any left-over bytes. */
3309 if (offset
< length
)
3311 src
= adjust_address (src
, BLKmode
, offset
);
3312 dest
= adjust_address (dest
, BLKmode
, offset
);
3313 move_by_pieces (dest
, src
, length
- offset
,
3314 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), RETURN_BEGIN
);
3318 /* Helper function for doing a loop-based block operation on memory
3319 reference MEM. Each iteration of the loop will operate on LENGTH
3322 Create a new base register for use within the loop and point it to
3323 the start of MEM. Create a new memory reference that uses this
3324 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3327 riscv_adjust_block_mem (rtx mem
, unsigned HOST_WIDE_INT length
,
3328 rtx
*loop_reg
, rtx
*loop_mem
)
3330 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
3332 /* Although the new mem does not refer to a known location,
3333 it does keep up to LENGTH bytes of alignment. */
3334 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
3335 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
3338 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
3339 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
3340 the memory regions do not overlap. */
3343 riscv_block_move_loop (rtx dest
, rtx src
, unsigned HOST_WIDE_INT length
,
3344 unsigned HOST_WIDE_INT bytes_per_iter
)
3346 rtx label
, src_reg
, dest_reg
, final_src
, test
;
3347 unsigned HOST_WIDE_INT leftover
;
3349 leftover
= length
% bytes_per_iter
;
3352 /* Create registers and memory references for use within the loop. */
3353 riscv_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
3354 riscv_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
3356 /* Calculate the value that SRC_REG should have after the last iteration
3358 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
3361 /* Emit the start of the loop. */
3362 label
= gen_label_rtx ();
3365 /* Emit the loop body. */
3366 riscv_block_move_straight (dest
, src
, bytes_per_iter
);
3368 /* Move on to the next block. */
3369 riscv_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
3370 riscv_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
3372 /* Emit the loop condition. */
3373 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
3374 emit_jump_insn (gen_cbranch4 (Pmode
, test
, src_reg
, final_src
, label
));
3376 /* Mop up any left-over bytes. */
3378 riscv_block_move_straight (dest
, src
, leftover
);
3380 emit_insn(gen_nop ());
3383 /* Expand a cpymemsi instruction, which copies LENGTH bytes from
3384 memory reference SRC to memory reference DEST. */
3387 riscv_expand_block_move (rtx dest
, rtx src
, rtx length
)
3389 if (CONST_INT_P (length
))
3391 unsigned HOST_WIDE_INT hwi_length
= UINTVAL (length
);
3392 unsigned HOST_WIDE_INT factor
, align
;
3394 align
= MIN (MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), BITS_PER_WORD
);
3395 factor
= BITS_PER_WORD
/ align
;
3397 if (optimize_function_for_size_p (cfun
)
3398 && hwi_length
* factor
* UNITS_PER_WORD
> MOVE_RATIO (false))
3401 if (hwi_length
<= (RISCV_MAX_MOVE_BYTES_STRAIGHT
/ factor
))
3403 riscv_block_move_straight (dest
, src
, INTVAL (length
));
3406 else if (optimize
&& align
>= BITS_PER_WORD
)
3408 unsigned min_iter_words
3409 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER
/ UNITS_PER_WORD
;
3410 unsigned iter_words
= min_iter_words
;
3411 unsigned HOST_WIDE_INT bytes
= hwi_length
;
3412 unsigned HOST_WIDE_INT words
= bytes
/ UNITS_PER_WORD
;
3414 /* Lengthen the loop body if it shortens the tail. */
3415 for (unsigned i
= min_iter_words
; i
< min_iter_words
* 2 - 1; i
++)
3417 unsigned cur_cost
= iter_words
+ words
% iter_words
;
3418 unsigned new_cost
= i
+ words
% i
;
3419 if (new_cost
<= cur_cost
)
3423 riscv_block_move_loop (dest
, src
, bytes
, iter_words
* UNITS_PER_WORD
);
3430 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
3431 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
3434 riscv_print_operand_reloc (FILE *file
, rtx op
, bool hi_reloc
)
3438 switch (riscv_classify_symbolic_expression (op
))
3440 case SYMBOL_ABSOLUTE
:
3441 reloc
= hi_reloc
? "%hi" : "%lo";
3445 reloc
= hi_reloc
? "%pcrel_hi" : "%pcrel_lo";
3449 reloc
= hi_reloc
? "%tprel_hi" : "%tprel_lo";
3453 output_operand_lossage ("invalid use of '%%%c'", hi_reloc
? 'h' : 'R');
3457 fprintf (file
, "%s(", reloc
);
3458 output_addr_const (file
, riscv_strip_unspec_address (op
));
3462 /* Return true if the .AQ suffix should be added to an AMO to implement the
3463 acquire portion of memory model MODEL. */
3466 riscv_memmodel_needs_amo_acquire (enum memmodel model
)
3470 case MEMMODEL_ACQ_REL
:
3471 case MEMMODEL_SEQ_CST
:
3472 case MEMMODEL_SYNC_SEQ_CST
:
3473 case MEMMODEL_ACQUIRE
:
3474 case MEMMODEL_CONSUME
:
3475 case MEMMODEL_SYNC_ACQUIRE
:
3478 case MEMMODEL_RELEASE
:
3479 case MEMMODEL_SYNC_RELEASE
:
3480 case MEMMODEL_RELAXED
:
3488 /* Return true if a FENCE should be emitted to before a memory access to
3489 implement the release portion of memory model MODEL. */
3492 riscv_memmodel_needs_release_fence (enum memmodel model
)
3496 case MEMMODEL_ACQ_REL
:
3497 case MEMMODEL_SEQ_CST
:
3498 case MEMMODEL_SYNC_SEQ_CST
:
3499 case MEMMODEL_RELEASE
:
3500 case MEMMODEL_SYNC_RELEASE
:
3503 case MEMMODEL_ACQUIRE
:
3504 case MEMMODEL_CONSUME
:
3505 case MEMMODEL_SYNC_ACQUIRE
:
3506 case MEMMODEL_RELAXED
:
3514 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3516 'h' Print the high-part relocation associated with OP, after stripping
3518 'R' Print the low-part relocation associated with OP.
3519 'C' Print the integer branch condition for comparison OP.
3520 'A' Print the atomic operation suffix for memory model OP.
3521 'F' Print a FENCE if the memory model requires a release.
3522 'z' Print x0 if OP is zero, otherwise print OP normally.
3523 'i' Print i if the operand is not a register. */
3526 riscv_print_operand (FILE *file
, rtx op
, int letter
)
3528 machine_mode mode
= GET_MODE (op
);
3529 enum rtx_code code
= GET_CODE (op
);
3536 riscv_print_operand_reloc (file
, op
, true);
3540 riscv_print_operand_reloc (file
, op
, false);
3544 /* The RTL names match the instruction names. */
3545 fputs (GET_RTX_NAME (code
), file
);
3549 if (riscv_memmodel_needs_amo_acquire ((enum memmodel
) INTVAL (op
)))
3550 fputs (".aq", file
);
3554 if (riscv_memmodel_needs_release_fence ((enum memmodel
) INTVAL (op
)))
3555 fputs ("fence iorw,ow; ", file
);
3567 if (letter
&& letter
!= 'z')
3568 output_operand_lossage ("invalid use of '%%%c'", letter
);
3569 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
3573 if (letter
&& letter
!= 'z')
3574 output_operand_lossage ("invalid use of '%%%c'", letter
);
3576 output_address (mode
, XEXP (op
, 0));
3580 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
3581 fputs (reg_names
[GP_REG_FIRST
], file
);
3582 else if (letter
&& letter
!= 'z')
3583 output_operand_lossage ("invalid use of '%%%c'", letter
);
3585 output_addr_const (file
, riscv_strip_unspec_address (op
));
3591 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3594 riscv_print_operand_address (FILE *file
, machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3596 struct riscv_address_info addr
;
3598 if (riscv_classify_address (&addr
, x
, word_mode
, true))
3602 riscv_print_operand (file
, addr
.offset
, 0);
3603 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3606 case ADDRESS_LO_SUM
:
3607 riscv_print_operand_reloc (file
, addr
.offset
, false);
3608 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3611 case ADDRESS_CONST_INT
:
3612 output_addr_const (file
, x
);
3613 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
3616 case ADDRESS_SYMBOLIC
:
3617 output_addr_const (file
, riscv_strip_unspec_address (x
));
3624 riscv_size_ok_for_small_data_p (int size
)
3626 return g_switch_value
&& IN_RANGE (size
, 1, g_switch_value
);
3629 /* Return true if EXP should be placed in the small data section. */
3632 riscv_in_small_data_p (const_tree x
)
3634 if (TREE_CODE (x
) == STRING_CST
|| TREE_CODE (x
) == FUNCTION_DECL
)
3637 if (TREE_CODE (x
) == VAR_DECL
&& DECL_SECTION_NAME (x
))
3639 const char *sec
= DECL_SECTION_NAME (x
);
3640 return strcmp (sec
, ".sdata") == 0 || strcmp (sec
, ".sbss") == 0;
3643 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x
)));
3646 /* Switch to the appropriate section for output of DECL. */
3649 riscv_select_section (tree decl
, int reloc
,
3650 unsigned HOST_WIDE_INT align
)
3652 switch (categorize_decl_for_section (decl
, reloc
))
3654 case SECCAT_SRODATA
:
3655 return get_named_section (decl
, ".srodata", reloc
);
3658 return default_elf_select_section (decl
, reloc
, align
);
3662 /* Switch to the appropriate section for output of DECL. */
3665 riscv_unique_section (tree decl
, int reloc
)
3667 const char *prefix
= NULL
;
3668 bool one_only
= DECL_ONE_ONLY (decl
) && !HAVE_COMDAT_GROUP
;
3670 switch (categorize_decl_for_section (decl
, reloc
))
3672 case SECCAT_SRODATA
:
3673 prefix
= one_only
? ".sr" : ".srodata";
3681 const char *name
, *linkonce
;
3684 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3685 name
= targetm
.strip_name_encoding (name
);
3687 /* If we're using one_only, then there needs to be a .gnu.linkonce
3688 prefix to the section name. */
3689 linkonce
= one_only
? ".gnu.linkonce" : "";
3691 string
= ACONCAT ((linkonce
, prefix
, ".", name
, NULL
));
3693 set_decl_section_name (decl
, string
);
3696 default_unique_section (decl
, reloc
);
3699 /* Return a section for X, handling small data. */
3702 riscv_elf_select_rtx_section (machine_mode mode
, rtx x
,
3703 unsigned HOST_WIDE_INT align
)
3705 section
*s
= default_elf_select_rtx_section (mode
, x
, align
);
3707 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode
)))
3709 if (startswith (s
->named
.name
, ".rodata.cst"))
3711 /* Rename .rodata.cst* to .srodata.cst*. */
3712 char *name
= (char *) alloca (strlen (s
->named
.name
) + 2);
3713 sprintf (name
, ".s%s", s
->named
.name
+ 1);
3714 return get_section (name
, s
->named
.common
.flags
, NULL
);
3717 if (s
== data_section
)
3718 return sdata_section
;
3724 /* Make the last instruction frame-related and note that it performs
3725 the operation described by FRAME_PATTERN. */
3728 riscv_set_frame_expr (rtx frame_pattern
)
3732 insn
= get_last_insn ();
3733 RTX_FRAME_RELATED_P (insn
) = 1;
3734 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3739 /* Return a frame-related rtx that stores REG at MEM.
3740 REG must be a single register. */
3743 riscv_frame_set (rtx mem
, rtx reg
)
3745 rtx set
= gen_rtx_SET (mem
, reg
);
3746 RTX_FRAME_RELATED_P (set
) = 1;
3750 /* Return true if the current function must save register REGNO. */
3753 riscv_save_reg_p (unsigned int regno
)
3755 bool call_saved
= !global_regs
[regno
] && !call_used_or_fixed_reg_p (regno
);
3756 bool might_clobber
= crtl
->saves_all_registers
3757 || df_regs_ever_live_p (regno
);
3759 if (call_saved
&& might_clobber
)
3762 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
3765 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
3768 /* If this is an interrupt handler, then must save extra registers. */
3769 if (cfun
->machine
->interrupt_handler_p
)
3771 /* zero register is always zero. */
3772 if (regno
== GP_REG_FIRST
)
3775 /* The function will return the stack pointer to its original value. */
3776 if (regno
== STACK_POINTER_REGNUM
)
3779 /* By convention, we assume that gp and tp are safe. */
3780 if (regno
== GP_REGNUM
|| regno
== THREAD_POINTER_REGNUM
)
3783 /* We must save every register used in this function. If this is not a
3784 leaf function, then we must save all temporary registers. */
3785 if (df_regs_ever_live_p (regno
)
3786 || (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
)))
3793 /* Determine whether to call GPR save/restore routines. */
3795 riscv_use_save_libcall (const struct riscv_frame_info
*frame
)
3797 if (!TARGET_SAVE_RESTORE
|| crtl
->calls_eh_return
|| frame_pointer_needed
3798 || cfun
->machine
->interrupt_handler_p
)
3801 return frame
->save_libcall_adjustment
!= 0;
3804 /* Determine which GPR save/restore routine to call. */
3807 riscv_save_libcall_count (unsigned mask
)
3809 for (unsigned n
= GP_REG_LAST
; n
> GP_REG_FIRST
; n
--)
3810 if (BITSET_P (mask
, n
))
3811 return CALLEE_SAVED_REG_NUMBER (n
) + 1;
3815 /* Populate the current function's riscv_frame_info structure.
3817 RISC-V stack frames grown downward. High addresses are at the top.
3819 +-------------------------------+
3821 | incoming stack arguments |
3823 +-------------------------------+ <-- incoming stack pointer
3825 | callee-allocated save area |
3826 | for arguments that are |
3827 | split between registers and |
3830 +-------------------------------+ <-- arg_pointer_rtx
3832 | callee-allocated save area |
3833 | for register varargs |
3835 +-------------------------------+ <-- hard_frame_pointer_rtx;
3836 | | stack_pointer_rtx + gp_sp_offset
3837 | GPR save area | + UNITS_PER_WORD
3839 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3840 | | + UNITS_PER_HWVALUE
3843 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3847 P +-------------------------------+
3849 | outgoing stack arguments |
3851 +-------------------------------+ <-- stack_pointer_rtx
3853 Dynamic stack allocations such as alloca insert data at point P.
3854 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3855 hard_frame_pointer_rtx unchanged. */
3857 static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info
*frame
);
3860 riscv_compute_frame_info (void)
3862 struct riscv_frame_info
*frame
;
3863 HOST_WIDE_INT offset
;
3864 bool interrupt_save_prologue_temp
= false;
3865 unsigned int regno
, i
, num_x_saved
= 0, num_f_saved
= 0;
3867 frame
= &cfun
->machine
->frame
;
3869 /* In an interrupt function, if we have a large frame, then we need to
3870 save/restore t0. We check for this before clearing the frame struct. */
3871 if (cfun
->machine
->interrupt_handler_p
)
3873 HOST_WIDE_INT step1
= riscv_first_stack_step (frame
);
3874 if (! SMALL_OPERAND (frame
->total_size
- step1
))
3875 interrupt_save_prologue_temp
= true;
3878 memset (frame
, 0, sizeof (*frame
));
3880 if (!cfun
->machine
->naked_p
)
3882 /* Find out which GPRs we need to save. */
3883 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3884 if (riscv_save_reg_p (regno
)
3885 || (interrupt_save_prologue_temp
3886 && (regno
== RISCV_PROLOGUE_TEMP_REGNUM
)))
3887 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3889 /* If this function calls eh_return, we must also save and restore the
3890 EH data registers. */
3891 if (crtl
->calls_eh_return
)
3892 for (i
= 0; (regno
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
; i
++)
3893 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3895 /* Find out which FPRs we need to save. This loop must iterate over
3896 the same space as its companion in riscv_for_each_saved_reg. */
3897 if (TARGET_HARD_FLOAT
)
3898 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3899 if (riscv_save_reg_p (regno
))
3900 frame
->fmask
|= 1 << (regno
- FP_REG_FIRST
), num_f_saved
++;
3903 /* At the bottom of the frame are any outgoing stack arguments. */
3904 offset
= RISCV_STACK_ALIGN (crtl
->outgoing_args_size
);
3905 /* Next are local stack variables. */
3906 offset
+= RISCV_STACK_ALIGN (get_frame_size ());
3907 /* The virtual frame pointer points above the local variables. */
3908 frame
->frame_pointer_offset
= offset
;
3909 /* Next are the callee-saved FPRs. */
3911 offset
+= RISCV_STACK_ALIGN (num_f_saved
* UNITS_PER_FP_REG
);
3912 frame
->fp_sp_offset
= offset
- UNITS_PER_FP_REG
;
3913 /* Next are the callee-saved GPRs. */
3916 unsigned x_save_size
= RISCV_STACK_ALIGN (num_x_saved
* UNITS_PER_WORD
);
3917 unsigned num_save_restore
= 1 + riscv_save_libcall_count (frame
->mask
);
3919 /* Only use save/restore routines if they don't alter the stack size. */
3920 if (RISCV_STACK_ALIGN (num_save_restore
* UNITS_PER_WORD
) == x_save_size
)
3922 /* Libcall saves/restores 3 registers at once, so we need to
3923 allocate 12 bytes for callee-saved register. */
3925 x_save_size
= 3 * UNITS_PER_WORD
;
3927 frame
->save_libcall_adjustment
= x_save_size
;
3930 offset
+= x_save_size
;
3932 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
3933 /* The hard frame pointer points above the callee-saved GPRs. */
3934 frame
->hard_frame_pointer_offset
= offset
;
3935 /* Above the hard frame pointer is the callee-allocated varags save area. */
3936 offset
+= RISCV_STACK_ALIGN (cfun
->machine
->varargs_size
);
3937 /* Next is the callee-allocated area for pretend stack arguments. */
3938 offset
+= RISCV_STACK_ALIGN (crtl
->args
.pretend_args_size
);
3939 /* Arg pointer must be below pretend args, but must be above alignment
3941 frame
->arg_pointer_offset
= offset
- crtl
->args
.pretend_args_size
;
3942 frame
->total_size
= offset
;
3943 /* Next points the incoming stack pointer and any incoming arguments. */
3945 /* Only use save/restore routines when the GPRs are atop the frame. */
3946 if (frame
->hard_frame_pointer_offset
!= frame
->total_size
)
3947 frame
->save_libcall_adjustment
= 0;
3950 /* Make sure that we're not trying to eliminate to the wrong hard frame
3954 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
3956 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
3959 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
3960 or argument pointer. TO is either the stack pointer or hard frame
3964 riscv_initial_elimination_offset (int from
, int to
)
3966 HOST_WIDE_INT src
, dest
;
3968 riscv_compute_frame_info ();
3970 if (to
== HARD_FRAME_POINTER_REGNUM
)
3971 dest
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
3972 else if (to
== STACK_POINTER_REGNUM
)
3973 dest
= 0; /* The stack pointer is the base of all offsets, hence 0. */
3977 if (from
== FRAME_POINTER_REGNUM
)
3978 src
= cfun
->machine
->frame
.frame_pointer_offset
;
3979 else if (from
== ARG_POINTER_REGNUM
)
3980 src
= cfun
->machine
->frame
.arg_pointer_offset
;
3987 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
3991 riscv_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
3996 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
3999 /* Emit code to change the current function's return address to
4000 ADDRESS. SCRATCH is available as a scratch register, if needed.
4001 ADDRESS and SCRATCH are both word-mode GPRs. */
4004 riscv_set_return_address (rtx address
, rtx scratch
)
4008 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
4009 slot_address
= riscv_add_offset (scratch
, stack_pointer_rtx
,
4010 cfun
->machine
->frame
.gp_sp_offset
);
4011 riscv_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
4014 /* A function to save or store a register. The first argument is the
4015 register and the second is the stack slot. */
4016 typedef void (*riscv_save_restore_fn
) (rtx
, rtx
);
4018 /* Use FN to save or restore register REGNO. MODE is the register's
4019 mode and OFFSET is the offset of its save slot from the current
4023 riscv_save_restore_reg (machine_mode mode
, int regno
,
4024 HOST_WIDE_INT offset
, riscv_save_restore_fn fn
)
4028 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
, offset
));
4029 fn (gen_rtx_REG (mode
, regno
), mem
);
4032 /* Call FN for each register that is saved by the current function.
4033 SP_OFFSET is the offset of the current stack pointer from the start
4037 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset
, riscv_save_restore_fn fn
,
4038 bool epilogue
, bool maybe_eh_return
)
4040 HOST_WIDE_INT offset
;
4042 /* Save the link register and s-registers. */
4043 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
4044 for (unsigned int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4045 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
4047 bool handle_reg
= TRUE
;
4049 /* If this is a normal return in a function that calls the eh_return
4050 builtin, then do not restore the eh return data registers as that
4051 would clobber the return value. But we do still need to save them
4052 in the prologue, and restore them for an exception return, so we
4053 need special handling here. */
4054 if (epilogue
&& !maybe_eh_return
&& crtl
->calls_eh_return
)
4056 unsigned int i
, regnum
;
4058 for (i
= 0; (regnum
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
;
4060 if (regno
== regnum
)
4068 riscv_save_restore_reg (word_mode
, regno
, offset
, fn
);
4069 offset
-= UNITS_PER_WORD
;
4072 /* This loop must iterate over the same space as its companion in
4073 riscv_compute_frame_info. */
4074 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
4075 for (unsigned int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4076 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
4078 machine_mode mode
= TARGET_DOUBLE_FLOAT
? DFmode
: SFmode
;
4080 riscv_save_restore_reg (mode
, regno
, offset
, fn
);
4081 offset
-= GET_MODE_SIZE (mode
);
4085 /* Save register REG to MEM. Make the instruction frame-related. */
4088 riscv_save_reg (rtx reg
, rtx mem
)
4090 riscv_emit_move (mem
, reg
);
4091 riscv_set_frame_expr (riscv_frame_set (mem
, reg
));
4094 /* Restore register REG from MEM. */
4097 riscv_restore_reg (rtx reg
, rtx mem
)
4099 rtx insn
= riscv_emit_move (reg
, mem
);
4100 rtx dwarf
= NULL_RTX
;
4101 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
4103 if (epilogue_cfa_sp_offset
&& REGNO (reg
) == HARD_FRAME_POINTER_REGNUM
)
4105 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4106 GEN_INT (epilogue_cfa_sp_offset
));
4107 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4110 REG_NOTES (insn
) = dwarf
;
4111 RTX_FRAME_RELATED_P (insn
) = 1;
4114 /* For stack frames that can't be allocated with a single ADDI instruction,
4115 compute the best value to initially allocate. It must at a minimum
4116 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
4117 try to pick a value that will allow compression of the register saves
4118 without adding extra instructions. */
4120 static HOST_WIDE_INT
4121 riscv_first_stack_step (struct riscv_frame_info
*frame
)
4123 if (SMALL_OPERAND (frame
->total_size
))
4124 return frame
->total_size
;
4126 HOST_WIDE_INT min_first_step
=
4127 RISCV_STACK_ALIGN (frame
->total_size
- frame
->fp_sp_offset
);
4128 HOST_WIDE_INT max_first_step
= IMM_REACH
/ 2 - PREFERRED_STACK_BOUNDARY
/ 8;
4129 HOST_WIDE_INT min_second_step
= frame
->total_size
- max_first_step
;
4130 gcc_assert (min_first_step
<= max_first_step
);
4132 /* As an optimization, use the least-significant bits of the total frame
4133 size, so that the second adjustment step is just LUI + ADD. */
4134 if (!SMALL_OPERAND (min_second_step
)
4135 && frame
->total_size
% IMM_REACH
< IMM_REACH
/ 2
4136 && frame
->total_size
% IMM_REACH
>= min_first_step
)
4137 return frame
->total_size
% IMM_REACH
;
4141 /* If we need two subtracts, and one is small enough to allow compressed
4142 loads and stores, then put that one first. */
4143 if (IN_RANGE (min_second_step
, 0,
4144 (TARGET_64BIT
? SDSP_REACH
: SWSP_REACH
)))
4145 return MAX (min_second_step
, min_first_step
);
4147 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
4148 with the minimum first step, so that we can get compressed loads and
4150 else if (!SMALL_OPERAND (min_second_step
))
4151 return min_first_step
;
4154 return max_first_step
;
4158 riscv_adjust_libcall_cfi_prologue ()
4160 rtx dwarf
= NULL_RTX
;
4161 rtx adjust_sp_rtx
, reg
, mem
, insn
;
4162 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
4165 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4166 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
4168 /* The save order is ra, s0, s1, s2 to s11. */
4169 if (regno
== RETURN_ADDR_REGNUM
)
4170 offset
= saved_size
- UNITS_PER_WORD
;
4171 else if (regno
== S0_REGNUM
)
4172 offset
= saved_size
- UNITS_PER_WORD
* 2;
4173 else if (regno
== S1_REGNUM
)
4174 offset
= saved_size
- UNITS_PER_WORD
* 3;
4176 offset
= saved_size
- ((regno
- S2_REGNUM
+ 4) * UNITS_PER_WORD
);
4178 reg
= gen_rtx_REG (SImode
, regno
);
4179 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
4183 insn
= gen_rtx_SET (mem
, reg
);
4184 dwarf
= alloc_reg_note (REG_CFA_OFFSET
, insn
, dwarf
);
4187 /* Debug info for adjust sp. */
4188 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
4189 stack_pointer_rtx
, GEN_INT (-saved_size
));
4190 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
4196 riscv_emit_stack_tie (void)
4198 if (Pmode
== SImode
)
4199 emit_insn (gen_stack_tiesi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
4201 emit_insn (gen_stack_tiedi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
4204 /* Expand the "prologue" pattern. */
4207 riscv_expand_prologue (void)
4209 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
4210 HOST_WIDE_INT size
= frame
->total_size
;
4211 unsigned mask
= frame
->mask
;
4214 if (flag_stack_usage_info
)
4215 current_function_static_stack_size
= size
;
4217 if (cfun
->machine
->naked_p
)
4220 /* When optimizing for size, call a subroutine to save the registers. */
4221 if (riscv_use_save_libcall (frame
))
4223 rtx dwarf
= NULL_RTX
;
4224 dwarf
= riscv_adjust_libcall_cfi_prologue ();
4226 size
-= frame
->save_libcall_adjustment
;
4227 insn
= emit_insn (riscv_gen_gpr_save_insn (frame
));
4228 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4230 RTX_FRAME_RELATED_P (insn
) = 1;
4231 REG_NOTES (insn
) = dwarf
;
4234 /* Save the registers. */
4235 if ((frame
->mask
| frame
->fmask
) != 0)
4237 HOST_WIDE_INT step1
= MIN (size
, riscv_first_stack_step (frame
));
4239 insn
= gen_add3_insn (stack_pointer_rtx
,
4242 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4244 riscv_for_each_saved_reg (size
, riscv_save_reg
, false, false);
4247 frame
->mask
= mask
; /* Undo the above fib. */
4249 /* Set up the frame pointer, if we're using one. */
4250 if (frame_pointer_needed
)
4252 insn
= gen_add3_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
,
4253 GEN_INT (frame
->hard_frame_pointer_offset
- size
));
4254 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4256 riscv_emit_stack_tie ();
4259 /* Allocate the rest of the frame. */
4262 if (SMALL_OPERAND (-size
))
4264 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4266 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4270 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), GEN_INT (-size
));
4271 emit_insn (gen_add3_insn (stack_pointer_rtx
,
4273 RISCV_PROLOGUE_TEMP (Pmode
)));
4275 /* Describe the effect of the previous instructions. */
4276 insn
= plus_constant (Pmode
, stack_pointer_rtx
, -size
);
4277 insn
= gen_rtx_SET (stack_pointer_rtx
, insn
);
4278 riscv_set_frame_expr (insn
);
4284 riscv_adjust_libcall_cfi_epilogue ()
4286 rtx dwarf
= NULL_RTX
;
4287 rtx adjust_sp_rtx
, reg
;
4288 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
4290 /* Debug info for adjust sp. */
4291 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
4292 stack_pointer_rtx
, GEN_INT (saved_size
));
4293 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
4296 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4297 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
4299 reg
= gen_rtx_REG (SImode
, regno
);
4300 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
4306 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
4307 style says which. */
4310 riscv_expand_epilogue (int style
)
4312 /* Split the frame into two. STEP1 is the amount of stack we should
4313 deallocate before restoring the registers. STEP2 is the amount we
4314 should deallocate afterwards.
4316 Start off by assuming that no registers need to be restored. */
4317 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
4318 unsigned mask
= frame
->mask
;
4319 HOST_WIDE_INT step1
= frame
->total_size
;
4320 HOST_WIDE_INT step2
= 0;
4321 bool use_restore_libcall
= ((style
== NORMAL_RETURN
)
4322 && riscv_use_save_libcall (frame
));
4323 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4326 /* We need to add memory barrier to prevent read from deallocated stack. */
4327 bool need_barrier_p
= (get_frame_size ()
4328 + cfun
->machine
->frame
.arg_pointer_offset
) != 0;
4330 if (cfun
->machine
->naked_p
)
4332 gcc_assert (style
== NORMAL_RETURN
);
4334 emit_jump_insn (gen_return ());
4339 if ((style
== NORMAL_RETURN
) && riscv_can_use_return_insn ())
4341 emit_jump_insn (gen_return ());
4345 /* Reset the epilogue cfa info before starting to emit the epilogue. */
4346 epilogue_cfa_sp_offset
= 0;
4348 /* Move past any dynamic stack allocations. */
4349 if (cfun
->calls_alloca
)
4351 /* Emit a barrier to prevent loads from a deallocated stack. */
4352 riscv_emit_stack_tie ();
4353 need_barrier_p
= false;
4355 rtx adjust
= GEN_INT (-frame
->hard_frame_pointer_offset
);
4356 if (!SMALL_OPERAND (INTVAL (adjust
)))
4358 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4359 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4363 gen_add3_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
,
4366 rtx dwarf
= NULL_RTX
;
4367 rtx cfa_adjust_value
= gen_rtx_PLUS (
4368 Pmode
, hard_frame_pointer_rtx
,
4369 GEN_INT (-frame
->hard_frame_pointer_offset
));
4370 rtx cfa_adjust_rtx
= gen_rtx_SET (stack_pointer_rtx
, cfa_adjust_value
);
4371 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, cfa_adjust_rtx
, dwarf
);
4372 RTX_FRAME_RELATED_P (insn
) = 1;
4374 REG_NOTES (insn
) = dwarf
;
4377 /* If we need to restore registers, deallocate as much stack as
4378 possible in the second step without going out of range. */
4379 if ((frame
->mask
| frame
->fmask
) != 0)
4381 step2
= riscv_first_stack_step (frame
);
4385 /* Set TARGET to BASE + STEP1. */
4388 /* Emit a barrier to prevent loads from a deallocated stack. */
4389 riscv_emit_stack_tie ();
4390 need_barrier_p
= false;
4392 /* Get an rtx for STEP1 that we can add to BASE. */
4393 rtx adjust
= GEN_INT (step1
);
4394 if (!SMALL_OPERAND (step1
))
4396 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4397 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4401 gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
, adjust
));
4403 rtx dwarf
= NULL_RTX
;
4404 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4407 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4408 RTX_FRAME_RELATED_P (insn
) = 1;
4410 REG_NOTES (insn
) = dwarf
;
4412 else if (frame_pointer_needed
)
4414 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
4416 epilogue_cfa_sp_offset
= step2
;
4419 if (use_restore_libcall
)
4420 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4422 /* Restore the registers. */
4423 riscv_for_each_saved_reg (frame
->total_size
- step2
, riscv_restore_reg
,
4424 true, style
== EXCEPTION_RETURN
);
4426 if (use_restore_libcall
)
4428 frame
->mask
= mask
; /* Undo the above fib. */
4429 gcc_assert (step2
>= frame
->save_libcall_adjustment
);
4430 step2
-= frame
->save_libcall_adjustment
;
4434 riscv_emit_stack_tie ();
4436 /* Deallocate the final bit of the frame. */
4439 insn
= emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4442 rtx dwarf
= NULL_RTX
;
4443 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4445 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4446 RTX_FRAME_RELATED_P (insn
) = 1;
4448 REG_NOTES (insn
) = dwarf
;
4451 if (use_restore_libcall
)
4453 rtx dwarf
= riscv_adjust_libcall_cfi_epilogue ();
4454 insn
= emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask
))));
4455 RTX_FRAME_RELATED_P (insn
) = 1;
4456 REG_NOTES (insn
) = dwarf
;
4458 emit_jump_insn (gen_gpr_restore_return (ra
));
4462 /* Add in the __builtin_eh_return stack adjustment. */
4463 if ((style
== EXCEPTION_RETURN
) && crtl
->calls_eh_return
)
4464 emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4465 EH_RETURN_STACKADJ_RTX
));
4467 /* Return from interrupt. */
4468 if (cfun
->machine
->interrupt_handler_p
)
4470 enum riscv_privilege_levels mode
= cfun
->machine
->interrupt_mode
;
4472 gcc_assert (mode
!= UNKNOWN_MODE
);
4474 if (mode
== MACHINE_MODE
)
4475 emit_jump_insn (gen_riscv_mret ());
4476 else if (mode
== SUPERVISOR_MODE
)
4477 emit_jump_insn (gen_riscv_sret ());
4479 emit_jump_insn (gen_riscv_uret ());
4481 else if (style
!= SIBCALL_RETURN
)
4482 emit_jump_insn (gen_simple_return_internal (ra
));
4485 /* Implement EPILOGUE_USES. */
4488 riscv_epilogue_uses (unsigned int regno
)
4490 if (regno
== RETURN_ADDR_REGNUM
)
4493 if (epilogue_completed
&& cfun
->machine
->interrupt_handler_p
)
4495 /* An interrupt function restores temp regs, so we must indicate that
4496 they are live at function end. */
4497 if (df_regs_ever_live_p (regno
)
4498 || (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
)))
4505 /* Return nonzero if this function is known to have a null epilogue.
4506 This allows the optimizer to omit jumps to jumps if no stack
4510 riscv_can_use_return_insn (void)
4512 return (reload_completed
&& cfun
->machine
->frame
.total_size
== 0
4513 && ! cfun
->machine
->interrupt_handler_p
);
4516 /* Given that there exists at least one variable that is set (produced)
4517 by OUT_INSN and read (consumed) by IN_INSN, return true iff
4518 IN_INSN represents one or more memory store operations and none of
4519 the variables set by OUT_INSN is used by IN_INSN as the address of a
4520 store operation. If either IN_INSN or OUT_INSN does not represent
4521 a "single" RTL SET expression (as loosely defined by the
4522 implementation of the single_set function) or a PARALLEL with only
4523 SETs, CLOBBERs, and USEs inside, this function returns false.
4525 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
4526 conditions that result in assertion failures in the generic
4527 store_data_bypass_p function and returns FALSE in such cases.
4529 This is required to make -msave-restore work with the sifive-7
4530 pipeline description. */
4533 riscv_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
4535 rtx out_set
, in_set
;
4536 rtx out_pat
, in_pat
;
4537 rtx out_exp
, in_exp
;
4540 in_set
= single_set (in_insn
);
4543 if (MEM_P (SET_DEST (in_set
)))
4545 out_set
= single_set (out_insn
);
4548 out_pat
= PATTERN (out_insn
);
4549 if (GET_CODE (out_pat
) == PARALLEL
)
4551 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
4553 out_exp
= XVECEXP (out_pat
, 0, i
);
4554 if ((GET_CODE (out_exp
) == CLOBBER
)
4555 || (GET_CODE (out_exp
) == USE
))
4557 else if (GET_CODE (out_exp
) != SET
)
4566 in_pat
= PATTERN (in_insn
);
4567 if (GET_CODE (in_pat
) != PARALLEL
)
4570 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
4572 in_exp
= XVECEXP (in_pat
, 0, i
);
4573 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
4575 else if (GET_CODE (in_exp
) != SET
)
4578 if (MEM_P (SET_DEST (in_exp
)))
4580 out_set
= single_set (out_insn
);
4583 out_pat
= PATTERN (out_insn
);
4584 if (GET_CODE (out_pat
) != PARALLEL
)
4586 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
4588 out_exp
= XVECEXP (out_pat
, 0, j
);
4589 if ((GET_CODE (out_exp
) == CLOBBER
)
4590 || (GET_CODE (out_exp
) == USE
))
4592 else if (GET_CODE (out_exp
) != SET
)
4600 return store_data_bypass_p (out_insn
, in_insn
);
4603 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4605 When floating-point registers are wider than integer ones, moves between
4606 them must go through memory. */
4609 riscv_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
4612 return (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4613 && (class1
== FP_REGS
) != (class2
== FP_REGS
));
4616 /* Implement TARGET_REGISTER_MOVE_COST. */
4619 riscv_register_move_cost (machine_mode mode
,
4620 reg_class_t from
, reg_class_t to
)
4622 return riscv_secondary_memory_needed (mode
, from
, to
) ? 8 : 2;
4625 /* Implement TARGET_HARD_REGNO_NREGS. */
4628 riscv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
4630 if (FP_REG_P (regno
))
4631 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_REG
- 1) / UNITS_PER_FP_REG
;
4633 /* All other registers are word-sized. */
4634 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4637 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4640 riscv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4642 unsigned int nregs
= riscv_hard_regno_nregs (regno
, mode
);
4644 if (GP_REG_P (regno
))
4646 if (!GP_REG_P (regno
+ nregs
- 1))
4649 else if (FP_REG_P (regno
))
4651 if (!FP_REG_P (regno
+ nregs
- 1))
4654 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4655 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4658 /* Only use callee-saved registers if a potential callee is guaranteed
4659 to spill the requisite width. */
4660 if (GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_REG
4661 || (!call_used_or_fixed_reg_p (regno
)
4662 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_ARG
))
4668 /* Require same callee-savedness for all registers. */
4669 for (unsigned i
= 1; i
< nregs
; i
++)
4670 if (call_used_or_fixed_reg_p (regno
)
4671 != call_used_or_fixed_reg_p (regno
+ i
))
4677 /* Implement TARGET_MODES_TIEABLE_P.
4679 Don't allow floating-point modes to be tied, since type punning of
4680 single-precision and double-precision is implementation defined. */
4683 riscv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4685 return (mode1
== mode2
4686 || !(GET_MODE_CLASS (mode1
) == MODE_FLOAT
4687 && GET_MODE_CLASS (mode2
) == MODE_FLOAT
));
4690 /* Implement CLASS_MAX_NREGS. */
4692 static unsigned char
4693 riscv_class_max_nregs (reg_class_t rclass
, machine_mode mode
)
4695 if (reg_class_subset_p (FP_REGS
, rclass
))
4696 return riscv_hard_regno_nregs (FP_REG_FIRST
, mode
);
4698 if (reg_class_subset_p (GR_REGS
, rclass
))
4699 return riscv_hard_regno_nregs (GP_REG_FIRST
, mode
);
4704 /* Implement TARGET_MEMORY_MOVE_COST. */
4707 riscv_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
4709 return (tune_param
->memory_cost
4710 + memory_move_secondary_cost (mode
, rclass
, in
));
4713 /* Return the number of instructions that can be issued per cycle. */
4716 riscv_issue_rate (void)
4718 return tune_param
->issue_rate
;
4721 /* Auxiliary function to emit RISC-V ELF attribute. */
4723 riscv_emit_attribute ()
4725 fprintf (asm_out_file
, "\t.attribute arch, \"%s\"\n",
4726 riscv_arch_str ().c_str ());
4728 fprintf (asm_out_file
, "\t.attribute unaligned_access, %d\n",
4729 TARGET_STRICT_ALIGN
? 0 : 1);
4731 fprintf (asm_out_file
, "\t.attribute stack_align, %d\n",
4732 riscv_stack_boundary
/ 8);
4735 /* Implement TARGET_ASM_FILE_START. */
4738 riscv_file_start (void)
4740 default_file_start ();
4742 /* Instruct GAS to generate position-[in]dependent code. */
4743 fprintf (asm_out_file
, "\t.option %spic\n", (flag_pic
? "" : "no"));
4745 /* If the user specifies "-mno-relax" on the command line then disable linker
4746 relaxation in the assembler. */
4748 fprintf (asm_out_file
, "\t.option norelax\n");
4750 if (riscv_emit_attribute_p
)
4751 riscv_emit_attribute ();
4754 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4755 in order to avoid duplicating too much logic from elsewhere. */
4758 riscv_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
4759 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4762 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
4763 rtx this_rtx
, temp1
, temp2
, fnaddr
;
4766 /* Pretend to be a post-reload pass while generating rtl. */
4767 reload_completed
= 1;
4769 /* Mark the end of the (empty) prologue. */
4770 emit_note (NOTE_INSN_PROLOGUE_END
);
4772 /* Determine if we can use a sibcall to call FUNCTION directly. */
4773 fnaddr
= gen_rtx_MEM (FUNCTION_MODE
, XEXP (DECL_RTL (function
), 0));
4775 /* We need two temporary registers in some cases. */
4776 temp1
= gen_rtx_REG (Pmode
, RISCV_PROLOGUE_TEMP_REGNUM
);
4777 temp2
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
4779 /* Find out which register contains the "this" pointer. */
4780 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
4781 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
4783 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
4785 /* Add DELTA to THIS_RTX. */
4788 rtx offset
= GEN_INT (delta
);
4789 if (!SMALL_OPERAND (delta
))
4791 riscv_emit_move (temp1
, offset
);
4794 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
4797 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4798 if (vcall_offset
!= 0)
4802 /* Set TEMP1 to *THIS_RTX. */
4803 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
4805 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4806 addr
= riscv_add_offset (temp2
, temp1
, vcall_offset
);
4808 /* Load the offset and add it to THIS_RTX. */
4809 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
4810 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
4813 /* Jump to the target function. */
4814 insn
= emit_call_insn (gen_sibcall (fnaddr
, const0_rtx
, NULL
, const0_rtx
));
4815 SIBLING_CALL_P (insn
) = 1;
4817 /* Run just enough of rest_of_compilation. This sequence was
4818 "borrowed" from alpha.c. */
4819 insn
= get_insns ();
4820 split_all_insns_noflow ();
4821 shorten_branches (insn
);
4822 assemble_start_function (thunk_fndecl
, fnname
);
4823 final_start_function (insn
, file
, 1);
4824 final (insn
, file
, 1);
4825 final_end_function ();
4826 assemble_end_function (thunk_fndecl
, fnname
);
4828 /* Clean up the vars set above. Note that final_end_function resets
4829 the global pointer for us. */
4830 reload_completed
= 0;
4833 /* Allocate a chunk of memory for per-function machine-dependent data. */
4835 static struct machine_function
*
4836 riscv_init_machine_status (void)
4838 return ggc_cleared_alloc
<machine_function
> ();
4841 /* Implement TARGET_OPTION_OVERRIDE. */
4844 riscv_option_override (void)
4846 const struct riscv_tune_info
*cpu
;
4848 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4849 SUBTARGET_OVERRIDE_OPTIONS
;
4852 flag_pcc_struct_return
= 0;
4857 /* The presence of the M extension implies that division instructions
4858 are present, so include them unless explicitly disabled. */
4859 if (TARGET_MUL
&& (target_flags_explicit
& MASK_DIV
) == 0)
4860 target_flags
|= MASK_DIV
;
4861 else if (!TARGET_MUL
&& TARGET_DIV
)
4862 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
4864 /* Likewise floating-point division and square root. */
4865 if (TARGET_HARD_FLOAT
&& (target_flags_explicit
& MASK_FDIV
) == 0)
4866 target_flags
|= MASK_FDIV
;
4868 /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
4869 if -mtune and -mcpu both not not given. */
4870 cpu
= riscv_parse_tune (riscv_tune_string
? riscv_tune_string
:
4871 (riscv_cpu_string
? riscv_cpu_string
:
4872 RISCV_TUNE_STRING_DEFAULT
));
4873 riscv_microarchitecture
= cpu
->microarchitecture
;
4874 tune_param
= optimize_size
? &optimize_size_tune_info
: cpu
->tune_param
;
4876 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
4877 for size. For architectures that trap and emulate unaligned accesses,
4878 the performance cost is too great, even for -Os. Similarly, if
4879 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
4880 riscv_slow_unaligned_access_p
= (cpu
->tune_param
->slow_unaligned_access
4881 || TARGET_STRICT_ALIGN
);
4882 if ((target_flags_explicit
& MASK_STRICT_ALIGN
) == 0
4883 && cpu
->tune_param
->slow_unaligned_access
)
4884 target_flags
|= MASK_STRICT_ALIGN
;
4886 /* If the user hasn't specified a branch cost, use the processor's
4888 if (riscv_branch_cost
== 0)
4889 riscv_branch_cost
= tune_param
->branch_cost
;
4891 /* Function to allocate machine-dependent function status. */
4892 init_machine_status
= &riscv_init_machine_status
;
4895 riscv_cmodel
= CM_PIC
;
4897 /* We get better code with explicit relocs for CM_MEDLOW, but
4898 worse code for the others (for now). Pick the best default. */
4899 if ((target_flags_explicit
& MASK_EXPLICIT_RELOCS
) == 0)
4900 if (riscv_cmodel
== CM_MEDLOW
)
4901 target_flags
|= MASK_EXPLICIT_RELOCS
;
4903 /* Require that the ISA supports the requested floating-point ABI. */
4904 if (UNITS_PER_FP_ARG
> (TARGET_HARD_FLOAT
? UNITS_PER_FP_REG
: 0))
4905 error ("requested ABI requires %<-march%> to subsume the %qc extension",
4906 UNITS_PER_FP_ARG
> 8 ? 'Q' : (UNITS_PER_FP_ARG
> 4 ? 'D' : 'F'));
4908 if (TARGET_RVE
&& riscv_abi
!= ABI_ILP32E
)
4909 error ("rv32e requires ilp32e ABI");
4911 /* We do not yet support ILP32 on RV64. */
4912 if (BITS_PER_WORD
!= POINTER_SIZE
)
4913 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE
);
4915 /* Validate -mpreferred-stack-boundary= value. */
4916 riscv_stack_boundary
= ABI_STACK_BOUNDARY
;
4917 if (riscv_preferred_stack_boundary_arg
)
4919 int min
= ctz_hwi (STACK_BOUNDARY
/ 8);
4922 if (!IN_RANGE (riscv_preferred_stack_boundary_arg
, min
, max
))
4923 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d",
4924 riscv_preferred_stack_boundary_arg
, min
, max
);
4926 riscv_stack_boundary
= 8 << riscv_preferred_stack_boundary_arg
;
4929 if (riscv_emit_attribute_p
< 0)
4930 #ifdef HAVE_AS_RISCV_ATTRIBUTE
4931 riscv_emit_attribute_p
= TARGET_RISCV_ATTRIBUTE
;
4933 riscv_emit_attribute_p
= 0;
4935 if (riscv_emit_attribute_p
)
4936 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"
4937 " [%<-mriscv-attribute%>]");
4940 if (riscv_stack_protector_guard
== SSP_GLOBAL
4941 && OPTION_SET_P (riscv_stack_protector_guard_offset_str
))
4943 error ("incompatible options %<-mstack-protector-guard=global%> and "
4944 "%<-mstack-protector-guard-offset=%s%>",
4945 riscv_stack_protector_guard_offset_str
);
4948 if (riscv_stack_protector_guard
== SSP_TLS
4949 && !(OPTION_SET_P (riscv_stack_protector_guard_offset_str
)
4950 && OPTION_SET_P (riscv_stack_protector_guard_reg_str
)))
4952 error ("both %<-mstack-protector-guard-offset%> and "
4953 "%<-mstack-protector-guard-reg%> must be used "
4954 "with %<-mstack-protector-guard=sysreg%>");
4957 if (OPTION_SET_P (riscv_stack_protector_guard_reg_str
))
4959 const char *str
= riscv_stack_protector_guard_reg_str
;
4960 int reg
= decode_reg_name (str
);
4962 if (!IN_RANGE (reg
, GP_REG_FIRST
+ 1, GP_REG_LAST
))
4963 error ("%qs is not a valid base register in %qs", str
,
4964 "-mstack-protector-guard-reg=");
4966 riscv_stack_protector_guard_reg
= reg
;
4969 if (OPTION_SET_P (riscv_stack_protector_guard_offset_str
))
4972 const char *str
= riscv_stack_protector_guard_offset_str
;
4974 long offs
= strtol (riscv_stack_protector_guard_offset_str
, &end
, 0);
4976 if (!*str
|| *end
|| errno
)
4977 error ("%qs is not a valid number in %qs", str
,
4978 "-mstack-protector-guard-offset=");
4980 if (!SMALL_OPERAND (offs
))
4981 error ("%qs is not a valid offset in %qs", str
,
4982 "-mstack-protector-guard-offset=");
4984 riscv_stack_protector_guard_offset
= offs
;
4989 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4992 riscv_conditional_register_usage (void)
4994 /* We have only x0~x15 on RV32E. */
4997 for (int r
= 16; r
<= 31; r
++)
5001 if (riscv_abi
== ABI_ILP32E
)
5003 for (int r
= 16; r
<= 31; r
++)
5004 call_used_regs
[r
] = 1;
5007 if (!TARGET_HARD_FLOAT
)
5009 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
5010 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5013 /* In the soft-float ABI, there are no callee-saved FP registers. */
5014 if (UNITS_PER_FP_ARG
== 0)
5016 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
5017 call_used_regs
[regno
] = 1;
5021 /* Return a register priority for hard reg REGNO. */
5024 riscv_register_priority (int regno
)
5026 /* Favor compressed registers to improve the odds of RVC instruction
5028 if (riscv_compressed_reg_p (regno
))
5034 /* Implement TARGET_TRAMPOLINE_INIT. */
5037 riscv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
5039 rtx addr
, end_addr
, mem
;
5040 uint32_t trampoline
[4];
5042 HOST_WIDE_INT static_chain_offset
, target_function_offset
;
5044 /* Work out the offsets of the pointers from the start of the
5046 gcc_assert (ARRAY_SIZE (trampoline
) * 4 == TRAMPOLINE_CODE_SIZE
);
5048 /* Get pointers to the beginning and end of the code block. */
5049 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
5050 end_addr
= riscv_force_binary (Pmode
, PLUS
, addr
,
5051 GEN_INT (TRAMPOLINE_CODE_SIZE
));
5054 if (Pmode
== SImode
)
5056 chain_value
= force_reg (Pmode
, chain_value
);
5058 rtx target_function
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
5059 /* lui t2, hi(chain)
5061 addi t2, t2, lo(chain)
5064 unsigned HOST_WIDE_INT lui_hi_chain_code
, lui_hi_func_code
;
5065 unsigned HOST_WIDE_INT lo_chain_code
, lo_func_code
;
5067 rtx uimm_mask
= force_reg (SImode
, gen_int_mode (-IMM_REACH
, SImode
));
5070 rtx imm12_mask
= gen_reg_rtx (SImode
);
5071 emit_insn (gen_one_cmplsi2 (imm12_mask
, uimm_mask
));
5073 rtx fixup_value
= force_reg (SImode
, gen_int_mode (IMM_REACH
/2, SImode
));
5075 /* Gen lui t2, hi(chain). */
5076 rtx hi_chain
= riscv_force_binary (SImode
, PLUS
, chain_value
,
5078 hi_chain
= riscv_force_binary (SImode
, AND
, hi_chain
,
5080 lui_hi_chain_code
= OPCODE_LUI
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
5081 rtx lui_hi_chain
= riscv_force_binary (SImode
, IOR
, hi_chain
,
5082 gen_int_mode (lui_hi_chain_code
, SImode
));
5084 mem
= adjust_address (m_tramp
, SImode
, 0);
5085 riscv_emit_move (mem
, riscv_swap_instruction (lui_hi_chain
));
5087 /* Gen lui t0, hi(func). */
5088 rtx hi_func
= riscv_force_binary (SImode
, PLUS
, target_function
,
5090 hi_func
= riscv_force_binary (SImode
, AND
, hi_func
,
5092 lui_hi_func_code
= OPCODE_LUI
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
);
5093 rtx lui_hi_func
= riscv_force_binary (SImode
, IOR
, hi_func
,
5094 gen_int_mode (lui_hi_func_code
, SImode
));
5096 mem
= adjust_address (m_tramp
, SImode
, 1 * GET_MODE_SIZE (SImode
));
5097 riscv_emit_move (mem
, riscv_swap_instruction (lui_hi_func
));
5099 /* Gen addi t2, t2, lo(chain). */
5100 rtx lo_chain
= riscv_force_binary (SImode
, AND
, chain_value
,
5102 lo_chain
= riscv_force_binary (SImode
, ASHIFT
, lo_chain
, GEN_INT (20));
5104 lo_chain_code
= OPCODE_ADDI
5105 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
5106 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
);
5108 rtx addi_lo_chain
= riscv_force_binary (SImode
, IOR
, lo_chain
,
5109 force_reg (SImode
, GEN_INT (lo_chain_code
)));
5111 mem
= adjust_address (m_tramp
, SImode
, 2 * GET_MODE_SIZE (SImode
));
5112 riscv_emit_move (mem
, riscv_swap_instruction (addi_lo_chain
));
5114 /* Gen jr t0, lo(func). */
5115 rtx lo_func
= riscv_force_binary (SImode
, AND
, target_function
,
5117 lo_func
= riscv_force_binary (SImode
, ASHIFT
, lo_func
, GEN_INT (20));
5119 lo_func_code
= OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
5121 rtx jr_lo_func
= riscv_force_binary (SImode
, IOR
, lo_func
,
5122 force_reg (SImode
, GEN_INT (lo_func_code
)));
5124 mem
= adjust_address (m_tramp
, SImode
, 3 * GET_MODE_SIZE (SImode
));
5125 riscv_emit_move (mem
, riscv_swap_instruction (jr_lo_func
));
5129 static_chain_offset
= TRAMPOLINE_CODE_SIZE
;
5130 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
5133 l[wd] t0, target_function_offset(t2)
5134 l[wd] t2, static_chain_offset(t2)
5137 trampoline
[0] = OPCODE_AUIPC
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
5138 trampoline
[1] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
5139 | (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
)
5140 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
5141 | (target_function_offset
<< SHIFT_IMM
);
5142 trampoline
[2] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
5143 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
5144 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
5145 | (static_chain_offset
<< SHIFT_IMM
);
5146 trampoline
[3] = OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
5148 /* Copy the trampoline code. */
5149 for (i
= 0; i
< ARRAY_SIZE (trampoline
); i
++)
5151 if (BYTES_BIG_ENDIAN
)
5152 trampoline
[i
] = __builtin_bswap32(trampoline
[i
]);
5153 mem
= adjust_address (m_tramp
, SImode
, i
* GET_MODE_SIZE (SImode
));
5154 riscv_emit_move (mem
, gen_int_mode (trampoline
[i
], SImode
));
5157 /* Set up the static chain pointer field. */
5158 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
5159 riscv_emit_move (mem
, chain_value
);
5161 /* Set up the target function field. */
5162 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
5163 riscv_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
5166 /* Flush the code part of the trampoline. */
5167 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
5168 emit_insn (gen_clear_cache (addr
, end_addr
));
5171 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5174 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
5175 tree exp ATTRIBUTE_UNUSED
)
5177 /* Don't use sibcalls when use save-restore routine. */
5178 if (TARGET_SAVE_RESTORE
)
5181 /* Don't use sibcall for naked functions. */
5182 if (cfun
->machine
->naked_p
)
5185 /* Don't use sibcall for interrupt functions. */
5186 if (cfun
->machine
->interrupt_handler_p
)
5192 /* Get the interrupt type, return UNKNOWN_MODE if it's not
5193 interrupt function. */
5194 static enum riscv_privilege_levels
5195 riscv_get_interrupt_type (tree decl
)
5197 gcc_assert (decl
!= NULL_TREE
);
5199 if ((TREE_CODE(decl
) != FUNCTION_DECL
)
5200 || (!riscv_interrupt_type_p (TREE_TYPE (decl
))))
5201 return UNKNOWN_MODE
;
5204 = TREE_VALUE (lookup_attribute ("interrupt",
5205 TYPE_ATTRIBUTES (TREE_TYPE (decl
))));
5207 if (attr_args
&& TREE_CODE (TREE_VALUE (attr_args
)) != VOID_TYPE
)
5209 const char *string
= TREE_STRING_POINTER (TREE_VALUE (attr_args
));
5211 if (!strcmp (string
, "user"))
5213 else if (!strcmp (string
, "supervisor"))
5214 return SUPERVISOR_MODE
;
5215 else /* Must be "machine". */
5216 return MACHINE_MODE
;
5219 /* Interrupt attributes are machine mode by default. */
5220 return MACHINE_MODE
;
5223 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
5224 /* Sanity cheching for above function attributes. */
5226 riscv_set_current_function (tree decl
)
5228 if (decl
== NULL_TREE
5229 || current_function_decl
== NULL_TREE
5230 || current_function_decl
== error_mark_node
5232 || cfun
->machine
->attributes_checked_p
)
5235 cfun
->machine
->naked_p
= riscv_naked_function_p (decl
);
5236 cfun
->machine
->interrupt_handler_p
5237 = riscv_interrupt_type_p (TREE_TYPE (decl
));
5239 if (cfun
->machine
->naked_p
&& cfun
->machine
->interrupt_handler_p
)
5240 error ("function attributes %qs and %qs are mutually exclusive",
5241 "interrupt", "naked");
5243 if (cfun
->machine
->interrupt_handler_p
)
5245 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
5246 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
5248 if (TREE_CODE (ret
) != VOID_TYPE
)
5249 error ("%qs function cannot return a value", "interrupt");
5251 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
5252 error ("%qs function cannot have arguments", "interrupt");
5254 cfun
->machine
->interrupt_mode
= riscv_get_interrupt_type (decl
);
5256 gcc_assert (cfun
->machine
->interrupt_mode
!= UNKNOWN_MODE
);
5259 /* Don't print the above diagnostics more than once. */
5260 cfun
->machine
->attributes_checked_p
= 1;
5263 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
5265 riscv_merge_decl_attributes (tree olddecl
, tree newdecl
)
5267 tree combined_attrs
;
5269 enum riscv_privilege_levels old_interrupt_type
5270 = riscv_get_interrupt_type (olddecl
);
5271 enum riscv_privilege_levels new_interrupt_type
5272 = riscv_get_interrupt_type (newdecl
);
5274 /* Check old and new has same interrupt type. */
5275 if ((old_interrupt_type
!= UNKNOWN_MODE
)
5276 && (new_interrupt_type
!= UNKNOWN_MODE
)
5277 && (old_interrupt_type
!= new_interrupt_type
))
5278 error ("%qs function cannot have different interrupt type", "interrupt");
5280 /* Create combined attributes. */
5281 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
5282 DECL_ATTRIBUTES (newdecl
));
5284 return combined_attrs
;
5287 /* Implement TARGET_CANNOT_COPY_INSN_P. */
5290 riscv_cannot_copy_insn_p (rtx_insn
*insn
)
5292 return recog_memoized (insn
) >= 0 && get_attr_cannot_copy (insn
);
5295 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
5298 riscv_slow_unaligned_access (machine_mode
, unsigned int)
5300 return riscv_slow_unaligned_access_p
;
5303 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
5306 riscv_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t rclass
)
5308 return !reg_classes_intersect_p (FP_REGS
, rclass
);
5312 /* Implement TARGET_CONSTANT_ALIGNMENT. */
5314 static HOST_WIDE_INT
5315 riscv_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
5317 if ((TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
5318 && (riscv_align_data_type
== riscv_align_data_type_xlen
))
5319 return MAX (align
, BITS_PER_WORD
);
5323 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
5325 /* This function is equivalent to default_promote_function_mode_always_promote
5326 except that it returns a promoted mode even if type is NULL_TREE. This is
5327 needed by libcalls which have no type (only a mode) such as fixed conversion
5328 routines that take a signed or unsigned char/short/int argument and convert
5329 it to a fixed type. */
5332 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
5334 int *punsignedp ATTRIBUTE_UNUSED
,
5335 const_tree fntype ATTRIBUTE_UNUSED
,
5336 int for_return ATTRIBUTE_UNUSED
)
5340 if (type
!= NULL_TREE
)
5341 return promote_mode (type
, mode
, punsignedp
);
5343 unsignedp
= *punsignedp
;
5344 PROMOTE_MODE (mode
, unsignedp
, type
);
5345 *punsignedp
= unsignedp
;
5349 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
5354 /* Do nothing unless we have -msave-restore */
5355 if (TARGET_SAVE_RESTORE
)
5356 riscv_remove_unneeded_save_restore_calls ();
5359 /* Return nonzero if register FROM_REGNO can be renamed to register
5363 riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED
,
5366 /* Interrupt functions can only use registers that have already been
5367 saved by the prologue, even if they would normally be
5369 return !cfun
->machine
->interrupt_handler_p
|| df_regs_ever_live_p (to_regno
);
5372 /* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */
5375 riscv_new_address_profitable_p (rtx memref
, rtx_insn
*insn
, rtx new_addr
)
5377 /* Prefer old address if it is less expensive. */
5378 addr_space_t as
= MEM_ADDR_SPACE (memref
);
5379 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
5380 int old_cost
= address_cost (XEXP (memref
, 0), GET_MODE (memref
), as
, speed
);
5381 int new_cost
= address_cost (new_addr
, GET_MODE (memref
), as
, speed
);
5382 return new_cost
<= old_cost
;
5385 /* Helper function for generating gpr_save pattern. */
5388 riscv_gen_gpr_save_insn (struct riscv_frame_info
*frame
)
5390 unsigned count
= riscv_save_libcall_count (frame
->mask
);
5391 /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */
5392 unsigned veclen
= 1 + 2 + 1 + count
;
5393 rtvec vec
= rtvec_alloc (veclen
);
5395 gcc_assert (veclen
<= ARRAY_SIZE (gpr_save_reg_order
));
5397 RTVEC_ELT (vec
, 0) =
5398 gen_rtx_UNSPEC_VOLATILE (VOIDmode
,
5399 gen_rtvec (1, GEN_INT (count
)), UNSPECV_GPR_SAVE
);
5401 for (unsigned i
= 1; i
< veclen
; ++i
)
5403 unsigned regno
= gpr_save_reg_order
[i
];
5404 rtx reg
= gen_rtx_REG (Pmode
, regno
);
5407 /* t0 and t1 are CLOBBERs, others are USEs. */
5409 elt
= gen_rtx_CLOBBER (Pmode
, reg
);
5411 elt
= gen_rtx_USE (Pmode
, reg
);
5413 RTVEC_ELT (vec
, i
) = elt
;
5416 /* Largest number of caller-save register must set in mask if we are
5417 not using __riscv_save_0. */
5418 gcc_assert ((count
== 0) ||
5419 BITSET_P (frame
->mask
, gpr_save_reg_order
[veclen
- 1]));
5421 return gen_rtx_PARALLEL (VOIDmode
, vec
);
5424 /* Return true if it's valid gpr_save pattern. */
5427 riscv_gpr_save_operation_p (rtx op
)
5429 unsigned len
= XVECLEN (op
, 0);
5431 if (len
> ARRAY_SIZE (gpr_save_reg_order
))
5434 for (unsigned i
= 0; i
< len
; i
++)
5436 rtx elt
= XVECEXP (op
, 0, i
);
5439 /* First element in parallel is unspec. */
5440 if (GET_CODE (elt
) != UNSPEC_VOLATILE
5441 || GET_CODE (XVECEXP (elt
, 0, 0)) != CONST_INT
5442 || XINT (elt
, 1) != UNSPECV_GPR_SAVE
)
5447 /* Two CLOBBER and USEs, must check the order. */
5448 unsigned expect_code
= i
< 3 ? CLOBBER
: USE
;
5449 if (GET_CODE (elt
) != expect_code
5450 || !REG_P (XEXP (elt
, 1))
5451 || (REGNO (XEXP (elt
, 1)) != gpr_save_reg_order
[i
]))
5459 /* Implement TARGET_ASAN_SHADOW_OFFSET. */
5461 static unsigned HOST_WIDE_INT
5462 riscv_asan_shadow_offset (void)
5464 /* We only have libsanitizer support for RV64 at present.
5466 This number must match kRiscv*_ShadowOffset* in the file
5467 libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
5468 even though 1<<36 makes more sense. */
5469 return TARGET_64BIT
? (HOST_WIDE_INT_1
<< 29) : 0;
5472 /* Initialize the GCC target structure. */
5473 #undef TARGET_ASM_ALIGNED_HI_OP
5474 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
5475 #undef TARGET_ASM_ALIGNED_SI_OP
5476 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
5477 #undef TARGET_ASM_ALIGNED_DI_OP
5478 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
5480 #undef TARGET_OPTION_OVERRIDE
5481 #define TARGET_OPTION_OVERRIDE riscv_option_override
5483 #undef TARGET_LEGITIMIZE_ADDRESS
5484 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
5486 #undef TARGET_SCHED_ISSUE_RATE
5487 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
5489 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5490 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
5492 #undef TARGET_SET_CURRENT_FUNCTION
5493 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
5495 #undef TARGET_REGISTER_MOVE_COST
5496 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
5497 #undef TARGET_MEMORY_MOVE_COST
5498 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
5499 #undef TARGET_RTX_COSTS
5500 #define TARGET_RTX_COSTS riscv_rtx_costs
5501 #undef TARGET_ADDRESS_COST
5502 #define TARGET_ADDRESS_COST riscv_address_cost
5504 #undef TARGET_ASM_FILE_START
5505 #define TARGET_ASM_FILE_START riscv_file_start
5506 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5507 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5509 #undef TARGET_EXPAND_BUILTIN_VA_START
5510 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
5512 #undef TARGET_PROMOTE_FUNCTION_MODE
5513 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
5515 #undef TARGET_RETURN_IN_MEMORY
5516 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
5518 #undef TARGET_ASM_OUTPUT_MI_THUNK
5519 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
5520 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5521 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5523 #undef TARGET_PRINT_OPERAND
5524 #define TARGET_PRINT_OPERAND riscv_print_operand
5525 #undef TARGET_PRINT_OPERAND_ADDRESS
5526 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
5528 #undef TARGET_SETUP_INCOMING_VARARGS
5529 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
5530 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
5531 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
5532 #undef TARGET_STRICT_ARGUMENT_NAMING
5533 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
5534 #undef TARGET_MUST_PASS_IN_STACK
5535 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
5536 #undef TARGET_PASS_BY_REFERENCE
5537 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
5538 #undef TARGET_ARG_PARTIAL_BYTES
5539 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
5540 #undef TARGET_FUNCTION_ARG
5541 #define TARGET_FUNCTION_ARG riscv_function_arg
5542 #undef TARGET_FUNCTION_ARG_ADVANCE
5543 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
5544 #undef TARGET_FUNCTION_ARG_BOUNDARY
5545 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
5547 /* The generic ELF target does not always have TLS support. */
5549 #undef TARGET_HAVE_TLS
5550 #define TARGET_HAVE_TLS true
5553 #undef TARGET_CANNOT_FORCE_CONST_MEM
5554 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
5556 #undef TARGET_LEGITIMATE_CONSTANT_P
5557 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
5559 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5560 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
5562 #undef TARGET_LEGITIMATE_ADDRESS_P
5563 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
5565 #undef TARGET_CAN_ELIMINATE
5566 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
5568 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5569 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
5571 #undef TARGET_CLASS_MAX_NREGS
5572 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
5574 #undef TARGET_TRAMPOLINE_INIT
5575 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
5577 #undef TARGET_IN_SMALL_DATA_P
5578 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
5580 #undef TARGET_HAVE_SRODATA_SECTION
5581 #define TARGET_HAVE_SRODATA_SECTION true
5583 #undef TARGET_ASM_SELECT_SECTION
5584 #define TARGET_ASM_SELECT_SECTION riscv_select_section
5586 #undef TARGET_ASM_UNIQUE_SECTION
5587 #define TARGET_ASM_UNIQUE_SECTION riscv_unique_section
5589 #undef TARGET_ASM_SELECT_RTX_SECTION
5590 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
5592 #undef TARGET_MIN_ANCHOR_OFFSET
5593 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
5595 #undef TARGET_MAX_ANCHOR_OFFSET
5596 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
5598 #undef TARGET_REGISTER_PRIORITY
5599 #define TARGET_REGISTER_PRIORITY riscv_register_priority
5601 #undef TARGET_CANNOT_COPY_INSN_P
5602 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
5604 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
5605 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
5607 #undef TARGET_INIT_BUILTINS
5608 #define TARGET_INIT_BUILTINS riscv_init_builtins
5610 #undef TARGET_BUILTIN_DECL
5611 #define TARGET_BUILTIN_DECL riscv_builtin_decl
5613 #undef TARGET_EXPAND_BUILTIN
5614 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
5616 #undef TARGET_HARD_REGNO_NREGS
5617 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
5618 #undef TARGET_HARD_REGNO_MODE_OK
5619 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
5621 #undef TARGET_MODES_TIEABLE_P
5622 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
5624 #undef TARGET_SLOW_UNALIGNED_ACCESS
5625 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
5627 #undef TARGET_SECONDARY_MEMORY_NEEDED
5628 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
5630 #undef TARGET_CAN_CHANGE_MODE_CLASS
5631 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
5633 #undef TARGET_CONSTANT_ALIGNMENT
5634 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
5636 #undef TARGET_MERGE_DECL_ATTRIBUTES
5637 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
5639 #undef TARGET_ATTRIBUTE_TABLE
5640 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
5642 #undef TARGET_WARN_FUNC_RETURN
5643 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
5645 /* The low bit is ignored by jump instructions so is safe to use. */
5646 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
5647 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
5649 #undef TARGET_MACHINE_DEPENDENT_REORG
5650 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg
5652 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
5653 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
5655 #undef TARGET_ASAN_SHADOW_OFFSET
5656 #define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
5658 #ifdef TARGET_BIG_ENDIAN_DEFAULT
5659 #undef TARGET_DEFAULT_TARGET_FLAGS
5660 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
5663 struct gcc_target targetm
= TARGET_INITIALIZER
;
5665 #include "gt-riscv.h"