1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
27 #include "coretypes.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
37 #include "stringpool.h"
40 #include "stor-layout.h"
49 #include "target-def.h"
50 #include "basic-block.h"
55 #include "diagnostic.h"
58 #include "tree-pass.h"
60 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* True if bit BIT is set in VALUE. */
75 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
77 /* Classifies an address.
80 A natural register + offset address. The register satisfies
81 riscv_valid_base_register_p and the offset is a const_arith_operand.
84 A LO_SUM rtx. The first operand is a valid base register and
85 the second operand is a symbolic address.
88 A signed 16-bit constant address.
91 A constant symbolic address. */
92 enum riscv_address_type
{
99 /* Information about a function's frame layout. */
100 struct GTY(()) riscv_frame_info
{
101 /* The size of the frame in bytes. */
102 HOST_WIDE_INT total_size
;
104 /* Bit X is set if the function saves or restores GPR X. */
107 /* Likewise FPR X. */
110 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
111 unsigned save_libcall_adjustment
;
113 /* Offsets of fixed-point and floating-point save areas from frame bottom */
114 HOST_WIDE_INT gp_sp_offset
;
115 HOST_WIDE_INT fp_sp_offset
;
117 /* Offset of virtual frame pointer from stack pointer/frame bottom */
118 HOST_WIDE_INT frame_pointer_offset
;
120 /* Offset of hard frame pointer from stack pointer/frame bottom */
121 HOST_WIDE_INT hard_frame_pointer_offset
;
123 /* The offset of arg_pointer_rtx from the bottom of the frame. */
124 HOST_WIDE_INT arg_pointer_offset
;
127 enum riscv_privilege_levels
{
128 UNKNOWN_MODE
, USER_MODE
, SUPERVISOR_MODE
, MACHINE_MODE
131 struct GTY(()) machine_function
{
132 /* The number of extra stack bytes taken up by register varargs.
133 This area is allocated by the callee at the very top of the frame. */
136 /* True if current function is a naked function. */
139 /* True if current function is an interrupt function. */
140 bool interrupt_handler_p
;
141 /* For an interrupt handler, indicates the privilege level. */
142 enum riscv_privilege_levels interrupt_mode
;
144 /* True if attributes on current function have been checked. */
145 bool attributes_checked_p
;
147 /* The current frame information, calculated by riscv_compute_frame_info. */
148 struct riscv_frame_info frame
;
151 /* Information about a single argument. */
152 struct riscv_arg_info
{
153 /* True if the argument is at least partially passed on the stack. */
156 /* The number of integer registers allocated to this argument. */
157 unsigned int num_gprs
;
159 /* The offset of the first register used, provided num_gprs is nonzero.
160 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
161 unsigned int gpr_offset
;
163 /* The number of floating-point registers allocated to this argument. */
164 unsigned int num_fprs
;
166 /* The offset of the first register used, provided num_fprs is nonzero. */
167 unsigned int fpr_offset
;
170 /* Information about an address described by riscv_address_type.
176 REG is the base register and OFFSET is the constant offset.
179 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
180 is the type of symbol it references.
183 SYMBOL_TYPE is the type of symbol that the address references. */
184 struct riscv_address_info
{
185 enum riscv_address_type type
;
188 enum riscv_symbol_type symbol_type
;
191 /* One stage in a constant building sequence. These sequences have
195 A = A CODE[1] VALUE[1]
196 A = A CODE[2] VALUE[2]
199 where A is an accumulator, each CODE[i] is a binary rtl operation
200 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
201 struct riscv_integer_op
{
203 unsigned HOST_WIDE_INT value
;
206 /* The largest number of operations needed to load an integer constant.
207 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
208 #define RISCV_MAX_INTEGER_OPS 8
210 /* Costs of various operations on the different architectures. */
212 struct riscv_tune_info
214 unsigned short fp_add
[2];
215 unsigned short fp_mul
[2];
216 unsigned short fp_div
[2];
217 unsigned short int_mul
[2];
218 unsigned short int_div
[2];
219 unsigned short issue_rate
;
220 unsigned short branch_cost
;
221 unsigned short memory_cost
;
222 bool slow_unaligned_access
;
225 /* Information about one CPU we know about. */
226 struct riscv_cpu_info
{
227 /* This CPU's canonical name. */
230 /* Which automaton to use for tuning. */
231 enum riscv_microarchitecture_type microarchitecture
;
233 /* Tuning parameters for this CPU. */
234 const struct riscv_tune_info
*tune_info
;
237 /* Global variables for machine-dependent things. */
239 /* Whether unaligned accesses execute very slowly. */
240 bool riscv_slow_unaligned_access_p
;
242 /* Stack alignment to assume/maintain. */
243 unsigned riscv_stack_boundary
;
245 /* If non-zero, this is an offset to be added to SP to redefine the CFA
246 when restoring the FP register from the stack. Only valid when generating
248 static int epilogue_cfa_sp_offset
;
250 /* Which tuning parameters to use. */
251 static const struct riscv_tune_info
*tune_info
;
253 /* Which automaton to use for tuning. */
254 enum riscv_microarchitecture_type riscv_microarchitecture
;
256 /* Index R is the smallest register class that contains register R. */
257 const enum reg_class riscv_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
258 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
259 GR_REGS
, GR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
260 JALR_REGS
, JALR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
261 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
262 SIBCALL_REGS
, SIBCALL_REGS
, JALR_REGS
, JALR_REGS
,
263 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
264 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
265 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
266 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
267 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
268 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
269 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
270 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
271 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
272 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
273 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
274 FRAME_REGS
, FRAME_REGS
,
277 /* Costs to use when optimizing for rocket. */
278 static const struct riscv_tune_info rocket_tune_info
= {
279 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
280 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
281 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
282 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
283 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
287 true, /* slow_unaligned_access */
290 /* Costs to use when optimizing for Sifive 7 Series. */
291 static const struct riscv_tune_info sifive_7_tune_info
= {
292 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
293 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
294 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
295 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
296 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
300 true, /* slow_unaligned_access */
303 /* Costs to use when optimizing for size. */
304 static const struct riscv_tune_info optimize_size_tune_info
= {
305 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
306 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
307 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
308 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
309 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
313 false, /* slow_unaligned_access */
316 static tree
riscv_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
317 static tree
riscv_handle_type_attribute (tree
*, tree
, tree
, int, bool *);
319 /* Defining target-specific uses of __attribute__. */
320 static const struct attribute_spec riscv_attribute_table
[] =
322 /* Syntax: { name, min_len, max_len, decl_required, type_required,
323 function_type_required, affects_type_identity, handler,
326 /* The attribute telling no prologue/epilogue. */
327 { "naked", 0, 0, true, false, false, false,
328 riscv_handle_fndecl_attribute
, NULL
},
329 /* This attribute generates prologue/epilogue for interrupt handlers. */
330 { "interrupt", 0, 1, false, true, true, false,
331 riscv_handle_type_attribute
, NULL
},
333 /* The last attribute spec is set to be NULL. */
334 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
337 /* A table describing all the processors GCC knows about. */
338 static const struct riscv_cpu_info riscv_cpu_info_table
[] = {
339 { "rocket", generic
, &rocket_tune_info
},
340 { "sifive-3-series", generic
, &rocket_tune_info
},
341 { "sifive-5-series", generic
, &rocket_tune_info
},
342 { "sifive-7-series", sifive_7
, &sifive_7_tune_info
},
343 { "size", generic
, &optimize_size_tune_info
},
346 /* Return the riscv_cpu_info entry for the given name string. */
348 static const struct riscv_cpu_info
*
349 riscv_parse_cpu (const char *cpu_string
)
351 for (unsigned i
= 0; i
< ARRAY_SIZE (riscv_cpu_info_table
); i
++)
352 if (strcmp (riscv_cpu_info_table
[i
].name
, cpu_string
) == 0)
353 return riscv_cpu_info_table
+ i
;
355 error ("unknown cpu %qs for %<-mtune%>", cpu_string
);
356 return riscv_cpu_info_table
;
359 /* Helper function for riscv_build_integer; arguments are as for
360 riscv_build_integer. */
363 riscv_build_integer_1 (struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
],
364 HOST_WIDE_INT value
, machine_mode mode
)
366 HOST_WIDE_INT low_part
= CONST_LOW_PART (value
);
367 int cost
= RISCV_MAX_INTEGER_OPS
+ 1, alt_cost
;
368 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
370 if (SMALL_OPERAND (value
) || LUI_OPERAND (value
))
372 /* Simply ADDI or LUI. */
373 codes
[0].code
= UNKNOWN
;
374 codes
[0].value
= value
;
378 /* End with ADDI. When constructing HImode constants, do not generate any
379 intermediate value that is not itself a valid HImode constant. The
380 XORI case below will handle those remaining HImode constants. */
383 || value
- low_part
<= ((1 << (GET_MODE_BITSIZE (HImode
) - 1)) - 1)))
385 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
- low_part
, mode
);
388 alt_codes
[alt_cost
-1].code
= PLUS
;
389 alt_codes
[alt_cost
-1].value
= low_part
;
390 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
396 if (cost
> 2 && (low_part
< 0 || mode
== HImode
))
398 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
^ low_part
, mode
);
401 alt_codes
[alt_cost
-1].code
= XOR
;
402 alt_codes
[alt_cost
-1].value
= low_part
;
403 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
408 /* Eliminate trailing zeros and end with SLLI. */
409 if (cost
> 2 && (value
& 1) == 0)
411 int shift
= ctz_hwi (value
);
412 unsigned HOST_WIDE_INT x
= value
;
413 x
= sext_hwi (x
>> shift
, HOST_BITS_PER_WIDE_INT
- shift
);
415 /* Don't eliminate the lower 12 bits if LUI might apply. */
416 if (shift
> IMM_BITS
&& !SMALL_OPERAND (x
) && LUI_OPERAND (x
<< IMM_BITS
))
417 shift
-= IMM_BITS
, x
<<= IMM_BITS
;
419 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, x
, mode
);
422 alt_codes
[alt_cost
-1].code
= ASHIFT
;
423 alt_codes
[alt_cost
-1].value
= shift
;
424 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
429 gcc_assert (cost
<= RISCV_MAX_INTEGER_OPS
);
433 /* Fill CODES with a sequence of rtl operations to load VALUE.
434 Return the number of operations needed. */
437 riscv_build_integer (struct riscv_integer_op
*codes
, HOST_WIDE_INT value
,
440 int cost
= riscv_build_integer_1 (codes
, value
, mode
);
442 /* Eliminate leading zeros and end with SRLI. */
443 if (value
> 0 && cost
> 2)
445 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
446 int alt_cost
, shift
= clz_hwi (value
);
447 HOST_WIDE_INT shifted_val
;
449 /* Try filling trailing bits with 1s. */
450 shifted_val
= (value
<< shift
) | ((((HOST_WIDE_INT
) 1) << shift
) - 1);
451 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
454 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
455 alt_codes
[alt_cost
-1].value
= shift
;
456 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
460 /* Try filling trailing bits with 0s. */
461 shifted_val
= value
<< shift
;
462 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
465 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
466 alt_codes
[alt_cost
-1].value
= shift
;
467 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
475 /* Return the cost of constructing VAL in the event that a scratch
476 register is available. */
479 riscv_split_integer_cost (HOST_WIDE_INT val
)
482 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
483 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
484 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
486 cost
= 2 + riscv_build_integer (codes
, loval
, VOIDmode
);
488 cost
+= riscv_build_integer (codes
, hival
, VOIDmode
);
493 /* Return the cost of constructing the integer constant VAL. */
496 riscv_integer_cost (HOST_WIDE_INT val
)
498 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
499 return MIN (riscv_build_integer (codes
, val
, VOIDmode
),
500 riscv_split_integer_cost (val
));
503 /* Try to split a 64b integer into 32b parts, then reassemble. */
506 riscv_split_integer (HOST_WIDE_INT val
, machine_mode mode
)
508 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
509 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
510 rtx hi
= gen_reg_rtx (mode
), lo
= gen_reg_rtx (mode
);
512 riscv_move_integer (hi
, hi
, hival
, mode
, FALSE
);
513 riscv_move_integer (lo
, lo
, loval
, mode
, FALSE
);
515 hi
= gen_rtx_fmt_ee (ASHIFT
, mode
, hi
, GEN_INT (32));
516 hi
= force_reg (mode
, hi
);
518 return gen_rtx_fmt_ee (PLUS
, mode
, hi
, lo
);
521 /* Return true if X is a thread-local symbol. */
524 riscv_tls_symbol_p (const_rtx x
)
526 return SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0;
529 /* Return true if symbol X binds locally. */
532 riscv_symbol_binds_local_p (const_rtx x
)
534 if (SYMBOL_REF_P (x
))
535 return (SYMBOL_REF_DECL (x
)
536 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
537 : SYMBOL_REF_LOCAL_P (x
));
542 /* Return the method that should be used to access SYMBOL_REF or
545 static enum riscv_symbol_type
546 riscv_classify_symbol (const_rtx x
)
548 if (riscv_tls_symbol_p (x
))
551 if (GET_CODE (x
) == SYMBOL_REF
&& flag_pic
&& !riscv_symbol_binds_local_p (x
))
552 return SYMBOL_GOT_DISP
;
554 return riscv_cmodel
== CM_MEDLOW
? SYMBOL_ABSOLUTE
: SYMBOL_PCREL
;
557 /* Classify the base of symbolic expression X. */
559 enum riscv_symbol_type
560 riscv_classify_symbolic_expression (rtx x
)
564 split_const (x
, &x
, &offset
);
565 if (UNSPEC_ADDRESS_P (x
))
566 return UNSPEC_ADDRESS_TYPE (x
);
568 return riscv_classify_symbol (x
);
571 /* Return true if X is a symbolic constant. If it is, store the type of
572 the symbol in *SYMBOL_TYPE. */
575 riscv_symbolic_constant_p (rtx x
, enum riscv_symbol_type
*symbol_type
)
579 split_const (x
, &x
, &offset
);
580 if (UNSPEC_ADDRESS_P (x
))
582 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
583 x
= UNSPEC_ADDRESS (x
);
585 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
586 *symbol_type
= riscv_classify_symbol (x
);
590 if (offset
== const0_rtx
)
593 /* Nonzero offsets are only valid for references that don't use the GOT. */
594 switch (*symbol_type
)
596 case SYMBOL_ABSOLUTE
:
599 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
600 return sext_hwi (INTVAL (offset
), 32) == INTVAL (offset
);
607 /* Returns the number of instructions necessary to reference a symbol. */
609 static int riscv_symbol_insns (enum riscv_symbol_type type
)
613 case SYMBOL_TLS
: return 0; /* Depends on the TLS model. */
614 case SYMBOL_ABSOLUTE
: return 2; /* LUI + the reference. */
615 case SYMBOL_PCREL
: return 2; /* AUIPC + the reference. */
616 case SYMBOL_TLS_LE
: return 3; /* LUI + ADD TP + the reference. */
617 case SYMBOL_GOT_DISP
: return 3; /* AUIPC + LD GOT + the reference. */
618 default: gcc_unreachable ();
622 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
625 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
627 return riscv_const_insns (x
) > 0;
630 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
633 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
635 enum riscv_symbol_type type
;
638 /* There is no assembler syntax for expressing an address-sized
640 if (GET_CODE (x
) == HIGH
)
643 split_const (x
, &base
, &offset
);
644 if (riscv_symbolic_constant_p (base
, &type
))
646 /* As an optimization, don't spill symbolic constants that are as
647 cheap to rematerialize as to access in the constant pool. */
648 if (SMALL_OPERAND (INTVAL (offset
)) && riscv_symbol_insns (type
) > 0)
651 /* As an optimization, avoid needlessly generate dynamic relocations. */
656 /* TLS symbols must be computed by riscv_legitimize_move. */
657 if (tls_referenced_p (x
))
663 /* Return true if register REGNO is a valid base register for mode MODE.
664 STRICT_P is true if REG_OK_STRICT is in effect. */
667 riscv_regno_mode_ok_for_base_p (int regno
,
668 machine_mode mode ATTRIBUTE_UNUSED
,
671 if (!HARD_REGISTER_NUM_P (regno
))
675 regno
= reg_renumber
[regno
];
678 /* These fake registers will be eliminated to either the stack or
679 hard frame pointer, both of which are usually valid base registers.
680 Reload deals with the cases where the eliminated form isn't valid. */
681 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
684 return GP_REG_P (regno
);
687 /* Return true if X is a valid base register for mode MODE.
688 STRICT_P is true if REG_OK_STRICT is in effect. */
691 riscv_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
693 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
697 && riscv_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
700 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
701 can address a value of mode MODE. */
704 riscv_valid_offset_p (rtx x
, machine_mode mode
)
706 /* Check that X is a signed 12-bit number. */
707 if (!const_arith_operand (x
, Pmode
))
710 /* We may need to split multiword moves, so make sure that every word
712 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
713 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
719 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
722 riscv_split_symbol_type (enum riscv_symbol_type symbol_type
)
724 if (symbol_type
== SYMBOL_TLS_LE
)
727 if (!TARGET_EXPLICIT_RELOCS
)
730 return symbol_type
== SYMBOL_ABSOLUTE
|| symbol_type
== SYMBOL_PCREL
;
733 /* Return true if a LO_SUM can address a value of mode MODE when the
734 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
735 is used when the mode is BLKmode. */
738 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type
, machine_mode mode
,
743 /* Check that symbols of type SYMBOL_TYPE can be used to access values
745 if (riscv_symbol_insns (sym_type
) == 0)
748 /* Check that there is a known low-part relocation. */
749 if (!riscv_split_symbol_type (sym_type
))
752 /* We can't tell size or alignment when we have BLKmode, so try extracing a
753 decl from the symbol if possible. */
758 /* Extract the symbol from the LO_SUM operand, if any. */
759 split_const (x
, &x
, &offset
);
761 /* Might be a CODE_LABEL. We can compute align but not size for that,
762 so don't bother trying to handle it. */
763 if (!SYMBOL_REF_P (x
))
766 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
767 align
= (SYMBOL_REF_DECL (x
)
768 ? DECL_ALIGN (SYMBOL_REF_DECL (x
))
770 size
= (SYMBOL_REF_DECL (x
) && DECL_SIZE (SYMBOL_REF_DECL (x
))
771 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x
)))
776 align
= GET_MODE_ALIGNMENT (mode
);
777 size
= GET_MODE_BITSIZE (mode
);
780 /* We may need to split multiword moves, so make sure that each word
781 can be accessed without inducing a carry. */
782 if (size
> BITS_PER_WORD
783 && (!TARGET_STRICT_ALIGN
|| size
> align
))
789 /* Return true if X is a valid address for machine mode MODE. If it is,
790 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
794 riscv_classify_address (struct riscv_address_info
*info
, rtx x
,
795 machine_mode mode
, bool strict_p
)
797 switch (GET_CODE (x
))
801 info
->type
= ADDRESS_REG
;
803 info
->offset
= const0_rtx
;
804 return riscv_valid_base_register_p (info
->reg
, mode
, strict_p
);
807 info
->type
= ADDRESS_REG
;
808 info
->reg
= XEXP (x
, 0);
809 info
->offset
= XEXP (x
, 1);
810 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
811 && riscv_valid_offset_p (info
->offset
, mode
));
814 info
->type
= ADDRESS_LO_SUM
;
815 info
->reg
= XEXP (x
, 0);
816 info
->offset
= XEXP (x
, 1);
817 /* We have to trust the creator of the LO_SUM to do something vaguely
818 sane. Target-independent code that creates a LO_SUM should also
819 create and verify the matching HIGH. Target-independent code that
820 adds an offset to a LO_SUM must prove that the offset will not
821 induce a carry. Failure to do either of these things would be
822 a bug, and we are not required to check for it here. The RISC-V
823 backend itself should only create LO_SUMs for valid symbolic
824 constants, with the high part being either a HIGH or a copy
827 = riscv_classify_symbolic_expression (info
->offset
);
828 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
829 && riscv_valid_lo_sum_p (info
->symbol_type
, mode
, info
->offset
));
832 /* Small-integer addresses don't occur very often, but they
833 are legitimate if x0 is a valid base register. */
834 info
->type
= ADDRESS_CONST_INT
;
835 return SMALL_OPERAND (INTVAL (x
));
842 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
845 riscv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
847 struct riscv_address_info addr
;
849 return riscv_classify_address (&addr
, x
, mode
, strict_p
);
852 /* Return true if hard reg REGNO can be used in compressed instructions. */
855 riscv_compressed_reg_p (int regno
)
857 /* x8-x15/f8-f15 are compressible registers. */
858 return (TARGET_RVC
&& (IN_RANGE (regno
, GP_REG_FIRST
+ 8, GP_REG_FIRST
+ 15)
859 || IN_RANGE (regno
, FP_REG_FIRST
+ 8, FP_REG_FIRST
+ 15)));
862 /* Return true if x is an unsigned 5-bit immediate scaled by 4. */
865 riscv_compressed_lw_offset_p (rtx x
)
867 return (CONST_INT_P (x
)
868 && (INTVAL (x
) & 3) == 0
869 && IN_RANGE (INTVAL (x
), 0, CSW_MAX_OFFSET
));
872 /* Return true if load/store from/to address x can be compressed. */
875 riscv_compressed_lw_address_p (rtx x
)
877 struct riscv_address_info addr
;
878 bool result
= riscv_classify_address (&addr
, x
, GET_MODE (x
),
881 /* Before reload, assuming all load/stores of valid addresses get compressed
882 gives better code size than checking if the address is reg + small_offset
884 if (result
&& !reload_completed
)
887 /* Return false if address is not compressed_reg + small_offset. */
889 || addr
.type
!= ADDRESS_REG
890 || (!riscv_compressed_reg_p (REGNO (addr
.reg
))
891 && addr
.reg
!= stack_pointer_rtx
)
892 || !riscv_compressed_lw_offset_p (addr
.offset
))
898 /* Return the number of instructions needed to load or store a value
899 of mode MODE at address X. Return 0 if X isn't valid for MODE.
900 Assume that multiword moves may need to be split into word moves
901 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
905 riscv_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
907 struct riscv_address_info addr
= {};
910 if (!riscv_classify_address (&addr
, x
, mode
, false))
912 /* This could be a pattern from the pic.md file. In which case we want
913 this address to always have a cost of 3 to make it as expensive as the
914 most expensive symbol. This prevents constant propagation from
915 preferring symbols over register plus offset. */
919 /* BLKmode is used for single unaligned loads and stores and should
920 not count as a multiword mode. */
921 if (mode
!= BLKmode
&& might_split_p
)
922 n
+= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
924 if (addr
.type
== ADDRESS_LO_SUM
)
925 n
+= riscv_symbol_insns (addr
.symbol_type
) - 1;
930 /* Return the number of instructions needed to load constant X.
931 Return 0 if X isn't a valid constant. */
934 riscv_const_insns (rtx x
)
936 enum riscv_symbol_type symbol_type
;
939 switch (GET_CODE (x
))
942 if (!riscv_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
943 || !riscv_split_symbol_type (symbol_type
))
946 /* This is simply an LUI. */
951 int cost
= riscv_integer_cost (INTVAL (x
));
952 /* Force complicated constants to memory. */
953 return cost
< 4 ? cost
: 0;
958 /* We can use x0 to load floating-point zero. */
959 return x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
962 /* See if we can refer to X directly. */
963 if (riscv_symbolic_constant_p (x
, &symbol_type
))
964 return riscv_symbol_insns (symbol_type
);
966 /* Otherwise try splitting the constant into a base and offset. */
967 split_const (x
, &x
, &offset
);
970 int n
= riscv_const_insns (x
);
972 return n
+ riscv_integer_cost (INTVAL (offset
));
978 return riscv_symbol_insns (riscv_classify_symbol (x
));
985 /* X is a doubleword constant that can be handled by splitting it into
986 two words and loading each word separately. Return the number of
987 instructions required to do this. */
990 riscv_split_const_insns (rtx x
)
992 unsigned int low
, high
;
994 low
= riscv_const_insns (riscv_subword (x
, false));
995 high
= riscv_const_insns (riscv_subword (x
, true));
996 gcc_assert (low
> 0 && high
> 0);
1000 /* Return the number of instructions needed to implement INSN,
1001 given that it loads from or stores to MEM. */
1004 riscv_load_store_insns (rtx mem
, rtx_insn
*insn
)
1010 gcc_assert (MEM_P (mem
));
1011 mode
= GET_MODE (mem
);
1013 /* Try to prove that INSN does not need to be split. */
1014 might_split_p
= true;
1015 if (GET_MODE_BITSIZE (mode
) <= 32)
1016 might_split_p
= false;
1017 else if (GET_MODE_BITSIZE (mode
) == 64)
1019 set
= single_set (insn
);
1020 if (set
&& !riscv_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
1021 might_split_p
= false;
1024 return riscv_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
1027 /* Emit a move from SRC to DEST. Assume that the move expanders can
1028 handle all moves if !can_create_pseudo_p (). The distinction is
1029 important because, unlike emit_move_insn, the move expanders know
1030 how to force Pmode objects into the constant pool even when the
1031 constant pool address is not itself legitimate. */
1034 riscv_emit_move (rtx dest
, rtx src
)
1036 return (can_create_pseudo_p ()
1037 ? emit_move_insn (dest
, src
)
1038 : emit_move_insn_1 (dest
, src
));
1041 /* Emit an instruction of the form (set TARGET SRC). */
1044 riscv_emit_set (rtx target
, rtx src
)
1046 emit_insn (gen_rtx_SET (target
, src
));
1050 /* Emit an instruction of the form (set DEST (CODE X Y)). */
1053 riscv_emit_binary (enum rtx_code code
, rtx dest
, rtx x
, rtx y
)
1055 return riscv_emit_set (dest
, gen_rtx_fmt_ee (code
, GET_MODE (dest
), x
, y
));
1058 /* Compute (CODE X Y) and store the result in a new register
1059 of mode MODE. Return that new register. */
1062 riscv_force_binary (machine_mode mode
, enum rtx_code code
, rtx x
, rtx y
)
1064 return riscv_emit_binary (code
, gen_reg_rtx (mode
), x
, y
);
1067 /* Copy VALUE to a register and return that register. If new pseudos
1068 are allowed, copy it into a new register, otherwise use DEST. */
1071 riscv_force_temporary (rtx dest
, rtx value
, bool in_splitter
)
1073 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1074 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1075 combine undo buffer. */
1076 if (can_create_pseudo_p () && !in_splitter
)
1077 return force_reg (Pmode
, value
);
1080 riscv_emit_move (dest
, value
);
1085 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
1086 then add CONST_INT OFFSET to the result. */
1089 riscv_unspec_address_offset (rtx base
, rtx offset
,
1090 enum riscv_symbol_type symbol_type
)
1092 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1093 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1094 if (offset
!= const0_rtx
)
1095 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
1096 return gen_rtx_CONST (Pmode
, base
);
1099 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1100 type SYMBOL_TYPE. */
1103 riscv_unspec_address (rtx address
, enum riscv_symbol_type symbol_type
)
1107 split_const (address
, &base
, &offset
);
1108 return riscv_unspec_address_offset (base
, offset
, symbol_type
);
1111 /* If OP is an UNSPEC address, return the address to which it refers,
1112 otherwise return OP itself. */
1115 riscv_strip_unspec_address (rtx op
)
1119 split_const (op
, &base
, &offset
);
1120 if (UNSPEC_ADDRESS_P (base
))
1121 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
1125 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1126 high part to BASE and return the result. Just return BASE otherwise.
1127 TEMP is as for riscv_force_temporary.
1129 The returned expression can be used as the first operand to a LO_SUM. */
1132 riscv_unspec_offset_high (rtx temp
, rtx addr
, enum riscv_symbol_type symbol_type
)
1134 addr
= gen_rtx_HIGH (Pmode
, riscv_unspec_address (addr
, symbol_type
));
1135 return riscv_force_temporary (temp
, addr
, FALSE
);
1138 /* Load an entry from the GOT for a TLS GD access. */
1140 static rtx
riscv_got_load_tls_gd (rtx dest
, rtx sym
)
1142 if (Pmode
== DImode
)
1143 return gen_got_load_tls_gddi (dest
, sym
);
1145 return gen_got_load_tls_gdsi (dest
, sym
);
1148 /* Load an entry from the GOT for a TLS IE access. */
1150 static rtx
riscv_got_load_tls_ie (rtx dest
, rtx sym
)
1152 if (Pmode
== DImode
)
1153 return gen_got_load_tls_iedi (dest
, sym
);
1155 return gen_got_load_tls_iesi (dest
, sym
);
1158 /* Add in the thread pointer for a TLS LE access. */
1160 static rtx
riscv_tls_add_tp_le (rtx dest
, rtx base
, rtx sym
)
1162 rtx tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1163 if (Pmode
== DImode
)
1164 return gen_tls_add_tp_ledi (dest
, base
, tp
, sym
);
1166 return gen_tls_add_tp_lesi (dest
, base
, tp
, sym
);
1169 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1170 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1171 constant in that context and can be split into high and low parts.
1172 If so, and if LOW_OUT is nonnull, emit the high part and store the
1173 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1175 TEMP is as for riscv_force_temporary and is used to load the high
1176 part into a register.
1178 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1179 a legitimize SET_SRC for an .md pattern, otherwise the low part
1180 is guaranteed to be a legitimate address for mode MODE. */
1183 riscv_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
,
1186 enum riscv_symbol_type symbol_type
;
1188 if ((GET_CODE (addr
) == HIGH
&& mode
== MAX_MACHINE_MODE
)
1189 || !riscv_symbolic_constant_p (addr
, &symbol_type
)
1190 || riscv_symbol_insns (symbol_type
) == 0
1191 || !riscv_split_symbol_type (symbol_type
))
1195 switch (symbol_type
)
1197 case SYMBOL_ABSOLUTE
:
1199 rtx high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
1200 high
= riscv_force_temporary (temp
, high
, in_splitter
);
1201 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
1207 static unsigned seqno
;
1211 ssize_t bytes
= snprintf (buf
, sizeof (buf
), ".LA%u", seqno
);
1212 gcc_assert ((size_t) bytes
< sizeof (buf
));
1214 label
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
1215 SYMBOL_REF_FLAGS (label
) |= SYMBOL_FLAG_LOCAL
;
1216 /* ??? Ugly hack to make weak symbols work. May need to change the
1217 RTL for the auipc and/or low patterns to get a better fix for
1219 if (! nonzero_address_p (addr
))
1220 SYMBOL_REF_WEAK (label
) = 1;
1223 temp
= gen_reg_rtx (Pmode
);
1225 if (Pmode
== DImode
)
1226 emit_insn (gen_auipcdi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1228 emit_insn (gen_auipcsi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1230 *low_out
= gen_rtx_LO_SUM (Pmode
, temp
, label
);
1243 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1244 riscv_force_temporary; it is only needed when OFFSET is not a
1248 riscv_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1250 if (!SMALL_OPERAND (offset
))
1254 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1255 The addition inside the macro CONST_HIGH_PART may cause an
1256 overflow, so we need to force a sign-extension check. */
1257 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
1258 offset
= CONST_LOW_PART (offset
);
1259 high
= riscv_force_temporary (temp
, high
, FALSE
);
1260 reg
= riscv_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
),
1263 return plus_constant (Pmode
, reg
, offset
);
1266 /* The __tls_get_attr symbol. */
1267 static GTY(()) rtx riscv_tls_symbol
;
1269 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1270 the TLS symbol we are referencing and TYPE is the symbol type to use
1271 (either global dynamic or local dynamic). RESULT is an RTX for the
1272 return value location. */
1275 riscv_call_tls_get_addr (rtx sym
, rtx result
)
1277 rtx a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
), func
;
1280 if (!riscv_tls_symbol
)
1281 riscv_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1282 func
= gen_rtx_MEM (FUNCTION_MODE
, riscv_tls_symbol
);
1286 emit_insn (riscv_got_load_tls_gd (a0
, sym
));
1287 insn
= emit_call_insn (gen_call_value (result
, func
, const0_rtx
, NULL
));
1288 RTL_CONST_CALL_P (insn
) = 1;
1289 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1290 insn
= get_insns ();
1297 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1298 its address. The return value will be both a valid address and a valid
1299 SET_SRC (either a REG or a LO_SUM). */
1302 riscv_legitimize_tls_address (rtx loc
)
1305 enum tls_model model
= SYMBOL_REF_TLS_MODEL (loc
);
1308 /* TLS copy relocs are now deprecated and should not be used. */
1309 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1311 model
= TLS_MODEL_LOCAL_EXEC
;
1316 case TLS_MODEL_LOCAL_DYNAMIC
:
1317 /* Rely on section anchors for the optimization that LDM TLS
1318 provides. The anchor's address is loaded with GD TLS. */
1319 case TLS_MODEL_GLOBAL_DYNAMIC
:
1320 tmp
= gen_rtx_REG (Pmode
, GP_RETURN
);
1321 dest
= gen_reg_rtx (Pmode
);
1322 emit_libcall_block (riscv_call_tls_get_addr (loc
, tmp
), dest
, tmp
, loc
);
1325 case TLS_MODEL_INITIAL_EXEC
:
1326 /* la.tls.ie; tp-relative add */
1327 tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1328 tmp
= gen_reg_rtx (Pmode
);
1329 emit_insn (riscv_got_load_tls_ie (tmp
, loc
));
1330 dest
= gen_reg_rtx (Pmode
);
1331 emit_insn (gen_add3_insn (dest
, tmp
, tp
));
1334 case TLS_MODEL_LOCAL_EXEC
:
1335 tmp
= riscv_unspec_offset_high (NULL
, loc
, SYMBOL_TLS_LE
);
1336 dest
= gen_reg_rtx (Pmode
);
1337 emit_insn (riscv_tls_add_tp_le (dest
, tmp
, loc
));
1338 dest
= gen_rtx_LO_SUM (Pmode
, dest
,
1339 riscv_unspec_address (loc
, SYMBOL_TLS_LE
));
1348 /* If X is not a valid address for mode MODE, force it into a register. */
1351 riscv_force_address (rtx x
, machine_mode mode
)
1353 if (!riscv_legitimate_address_p (mode
, x
, false))
1354 x
= force_reg (Pmode
, x
);
1358 /* Modify base + offset so that offset fits within a compressed load/store insn
1359 and the excess is added to base. */
1362 riscv_shorten_lw_offset (rtx base
, HOST_WIDE_INT offset
)
1365 /* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess
1367 high
= GEN_INT (offset
& ~CSW_MAX_OFFSET
);
1368 offset
&= CSW_MAX_OFFSET
;
1369 if (!SMALL_OPERAND (INTVAL (high
)))
1370 high
= force_reg (Pmode
, high
);
1371 base
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, high
, base
));
1372 addr
= plus_constant (Pmode
, base
, offset
);
1376 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1377 be legitimized in a way that the generic machinery might not expect,
1378 return a new address, otherwise return NULL. MODE is the mode of
1379 the memory being accessed. */
1382 riscv_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1387 if (riscv_tls_symbol_p (x
))
1388 return riscv_legitimize_tls_address (x
);
1390 /* See if the address can split into a high part and a LO_SUM. */
1391 if (riscv_split_symbol (NULL
, x
, mode
, &addr
, FALSE
))
1392 return riscv_force_address (addr
, mode
);
1394 /* Handle BASE + OFFSET. */
1395 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
1396 && INTVAL (XEXP (x
, 1)) != 0)
1398 rtx base
= XEXP (x
, 0);
1399 HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
1401 if (!riscv_valid_base_register_p (base
, mode
, false))
1402 base
= copy_to_mode_reg (Pmode
, base
);
1403 if (optimize_function_for_size_p (cfun
)
1404 && (strcmp (current_pass
->name
, "shorten_memrefs") == 0)
1406 /* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow
1407 possible compressed load/store. */
1408 addr
= riscv_shorten_lw_offset (base
, offset
);
1410 addr
= riscv_add_offset (NULL
, base
, offset
);
1411 return riscv_force_address (addr
, mode
);
1417 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
1418 is the original src mode before promotion. */
1421 riscv_move_integer (rtx temp
, rtx dest
, HOST_WIDE_INT value
,
1422 machine_mode orig_mode
, bool in_splitter
)
1424 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
1429 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1430 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1431 combine undo buffer. */
1432 bool can_create_pseudo
= can_create_pseudo_p () && ! in_splitter
;
1434 mode
= GET_MODE (dest
);
1435 /* We use the original mode for the riscv_build_integer call, because HImode
1436 values are given special treatment. */
1437 num_ops
= riscv_build_integer (codes
, value
, orig_mode
);
1439 if (can_create_pseudo
&& num_ops
> 2 /* not a simple constant */
1440 && num_ops
>= riscv_split_integer_cost (value
))
1441 x
= riscv_split_integer (value
, mode
);
1444 /* Apply each binary operation to X. */
1445 x
= GEN_INT (codes
[0].value
);
1447 for (i
= 1; i
< num_ops
; i
++)
1449 if (!can_create_pseudo
)
1450 x
= riscv_emit_set (temp
, x
);
1452 x
= force_reg (mode
, x
);
1454 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1458 riscv_emit_set (dest
, x
);
1461 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1462 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1466 riscv_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
1470 /* Split moves of big integers into smaller pieces. */
1471 if (splittable_const_int_operand (src
, mode
))
1473 riscv_move_integer (dest
, dest
, INTVAL (src
), mode
, FALSE
);
1477 /* Split moves of symbolic constants into high/low pairs. */
1478 if (riscv_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
, FALSE
))
1480 riscv_emit_set (dest
, src
);
1484 /* Generate the appropriate access sequences for TLS symbols. */
1485 if (riscv_tls_symbol_p (src
))
1487 riscv_emit_move (dest
, riscv_legitimize_tls_address (src
));
1491 /* If we have (const (plus symbol offset)), and that expression cannot
1492 be forced into memory, load the symbol first and add in the offset. Also
1493 prefer to do this even if the constant _can_ be forced into memory, as it
1494 usually produces better code. */
1495 split_const (src
, &base
, &offset
);
1496 if (offset
!= const0_rtx
1497 && (targetm
.cannot_force_const_mem (mode
, src
) || can_create_pseudo_p ()))
1499 base
= riscv_force_temporary (dest
, base
, FALSE
);
1500 riscv_emit_move (dest
, riscv_add_offset (NULL
, base
, INTVAL (offset
)));
1504 src
= force_const_mem (mode
, src
);
1506 /* When using explicit relocs, constant pool references are sometimes
1507 not legitimate addresses. */
1508 riscv_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0), FALSE
);
1509 riscv_emit_move (dest
, src
);
1512 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1513 sequence that is valid. */
1516 riscv_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
1518 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1522 if (GET_CODE (src
) == CONST_INT
)
1524 /* Apply the equivalent of PROMOTE_MODE here for constants to
1526 machine_mode promoted_mode
= mode
;
1527 if (GET_MODE_CLASS (mode
) == MODE_INT
1528 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
1529 promoted_mode
= word_mode
;
1531 if (splittable_const_int_operand (src
, mode
))
1533 reg
= gen_reg_rtx (promoted_mode
);
1534 riscv_move_integer (reg
, reg
, INTVAL (src
), mode
, FALSE
);
1537 reg
= force_reg (promoted_mode
, src
);
1539 if (promoted_mode
!= mode
)
1540 reg
= gen_lowpart (mode
, reg
);
1543 reg
= force_reg (mode
, src
);
1544 riscv_emit_move (dest
, reg
);
1548 /* We need to deal with constants that would be legitimate
1549 immediate_operands but aren't legitimate move_operands. */
1550 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1552 riscv_legitimize_const_move (mode
, dest
, src
);
1553 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1557 /* RISC-V GCC may generate non-legitimate address due to we provide some
1558 pattern for optimize access PIC local symbol and it's make GCC generate
1559 unrecognizable instruction during optmizing. */
1561 if (MEM_P (dest
) && !riscv_legitimate_address_p (mode
, XEXP (dest
, 0),
1564 XEXP (dest
, 0) = riscv_force_address (XEXP (dest
, 0), mode
);
1567 if (MEM_P (src
) && !riscv_legitimate_address_p (mode
, XEXP (src
, 0),
1570 XEXP (src
, 0) = riscv_force_address (XEXP (src
, 0), mode
);
1576 /* Return true if there is an instruction that implements CODE and accepts
1577 X as an immediate operand. */
1580 riscv_immediate_operand_p (int code
, HOST_WIDE_INT x
)
1587 /* All shift counts are truncated to a valid constant. */
1596 /* These instructions take 12-bit signed immediates. */
1597 return SMALL_OPERAND (x
);
1600 /* We add 1 to the immediate and use SLT. */
1601 return SMALL_OPERAND (x
+ 1);
1604 /* Likewise SLTU, but reject the always-true case. */
1605 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
1609 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1613 /* By default assume that x0 can be used for 0. */
1618 /* Return the cost of binary operation X, given that the instruction
1619 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1620 instructions and that the sequence of a double-word operation takes
1621 DOUBLE_INSNS instructions. */
1624 riscv_binary_cost (rtx x
, int single_insns
, int double_insns
)
1626 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
1627 return COSTS_N_INSNS (double_insns
);
1628 return COSTS_N_INSNS (single_insns
);
1631 /* Return the cost of sign- or zero-extending OP. */
1634 riscv_extend_cost (rtx op
, bool unsigned_p
)
1639 if (unsigned_p
&& GET_MODE (op
) == QImode
)
1640 /* We can use ANDI. */
1641 return COSTS_N_INSNS (1);
1643 if (!unsigned_p
&& GET_MODE (op
) == SImode
)
1644 /* We can use SEXT.W. */
1645 return COSTS_N_INSNS (1);
1647 /* We need to use a shift left and a shift right. */
1648 return COSTS_N_INSNS (2);
1651 /* Implement TARGET_RTX_COSTS. */
1653 #define SINGLE_SHIFT_COST 1
1656 riscv_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1657 int *total
, bool speed
)
1659 bool float_mode_p
= FLOAT_MODE_P (mode
);
1662 switch (GET_CODE (x
))
1665 if (riscv_immediate_operand_p (outer_code
, INTVAL (x
)))
1676 if ((cost
= riscv_const_insns (x
)) > 0)
1678 /* If the constant is likely to be stored in a GPR, SETs of
1679 single-insn constants are as cheap as register sets; we
1680 never want to CSE them. */
1681 if (cost
== 1 && outer_code
== SET
)
1683 /* When we load a constant more than once, it usually is better
1684 to duplicate the last operation in the sequence than to CSE
1685 the constant itself. */
1686 else if (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
)
1687 *total
= COSTS_N_INSNS (1);
1689 else /* The instruction will be fetched from the constant pool. */
1690 *total
= COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE
));
1694 /* If the address is legitimate, return the number of
1695 instructions it needs. */
1696 if ((cost
= riscv_address_insns (XEXP (x
, 0), mode
, true)) > 0)
1698 *total
= COSTS_N_INSNS (cost
+ tune_info
->memory_cost
);
1701 /* Otherwise use the default handling. */
1705 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
1711 /* Double-word operations use two single-word operations. */
1712 *total
= riscv_binary_cost (x
, 1, 2);
1716 /* This is an SImode shift. */
1717 if (outer_code
== SET
1718 && CONST_INT_P (XEXP (x
, 1))
1719 && CONST_INT_P (XEXP (x
, 2))
1720 && (INTVAL (XEXP (x
, 2)) > 0)
1721 && (INTVAL (XEXP (x
, 1)) + INTVAL (XEXP (x
, 2)) == 32))
1723 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1731 *total
= riscv_binary_cost (x
, SINGLE_SHIFT_COST
,
1732 CONSTANT_P (XEXP (x
, 1)) ? 4 : 9);
1736 *total
= COSTS_N_INSNS (float_mode_p
? 1 : 3);
1740 *total
= set_src_cost (XEXP (x
, 0), mode
, speed
);
1744 /* This is an SImode shift. */
1745 if (outer_code
== SET
&& GET_MODE (x
) == DImode
1746 && GET_MODE (XEXP (x
, 0)) == SImode
)
1748 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1761 /* Branch comparisons have VOIDmode, so use the first operand's
1763 mode
= GET_MODE (XEXP (x
, 0));
1765 *total
= tune_info
->fp_add
[mode
== DFmode
];
1767 *total
= riscv_binary_cost (x
, 1, 3);
1772 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1773 mode
= GET_MODE (XEXP (x
, 0));
1774 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1778 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1779 mode
= GET_MODE (XEXP (x
, 0));
1780 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (3);
1784 /* (FLT(A, A) || FGT(B, B)). */
1785 mode
= GET_MODE (XEXP (x
, 0));
1786 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1793 /* FLT or FLE, but guarded by an FFLAGS read and write. */
1794 mode
= GET_MODE (XEXP (x
, 0));
1795 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (4);
1801 *total
= tune_info
->fp_add
[mode
== DFmode
];
1803 *total
= riscv_binary_cost (x
, 1, 4);
1808 rtx op
= XEXP (x
, 0);
1809 if (GET_CODE (op
) == FMA
&& !HONOR_SIGNED_ZEROS (mode
))
1811 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1812 + set_src_cost (XEXP (op
, 0), mode
, speed
)
1813 + set_src_cost (XEXP (op
, 1), mode
, speed
)
1814 + set_src_cost (XEXP (op
, 2), mode
, speed
));
1820 *total
= tune_info
->fp_add
[mode
== DFmode
];
1822 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
1827 *total
= tune_info
->fp_mul
[mode
== DFmode
];
1828 else if (!TARGET_MUL
)
1829 /* Estimate the cost of a library call. */
1830 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1831 else if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
1832 *total
= 3 * tune_info
->int_mul
[0] + COSTS_N_INSNS (2);
1834 *total
= COSTS_N_INSNS (1);
1836 *total
= tune_info
->int_mul
[mode
== DImode
];
1844 *total
= tune_info
->fp_div
[mode
== DFmode
];
1852 /* Estimate the cost of a library call. */
1853 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1855 *total
= tune_info
->int_div
[mode
== DImode
];
1857 *total
= COSTS_N_INSNS (1);
1861 /* This is an SImode shift. */
1862 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
1864 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1869 *total
= riscv_extend_cost (XEXP (x
, 0), GET_CODE (x
) == ZERO_EXTEND
);
1873 case UNSIGNED_FLOAT
:
1876 case FLOAT_TRUNCATE
:
1877 *total
= tune_info
->fp_add
[mode
== DFmode
];
1881 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1882 + set_src_cost (XEXP (x
, 0), mode
, speed
)
1883 + set_src_cost (XEXP (x
, 1), mode
, speed
)
1884 + set_src_cost (XEXP (x
, 2), mode
, speed
));
1888 if (XINT (x
, 1) == UNSPEC_AUIPC
)
1890 /* Make AUIPC cheap to avoid spilling its result to the stack. */
1901 /* Implement TARGET_ADDRESS_COST. */
1904 riscv_address_cost (rtx addr
, machine_mode mode
,
1905 addr_space_t as ATTRIBUTE_UNUSED
,
1906 bool speed ATTRIBUTE_UNUSED
)
1908 /* When optimizing for size, make uncompressible 32-bit addresses more
1909 * expensive so that compressible 32-bit addresses are preferred. */
1910 if (TARGET_RVC
&& !speed
&& riscv_mshorten_memrefs
&& mode
== SImode
1911 && !riscv_compressed_lw_address_p (addr
))
1912 return riscv_address_insns (addr
, mode
, false) + 1;
1913 return riscv_address_insns (addr
, mode
, false);
1916 /* Return one word of double-word value OP. HIGH_P is true to select the
1917 high part or false to select the low part. */
1920 riscv_subword (rtx op
, bool high_p
)
1922 unsigned int byte
= high_p
? UNITS_PER_WORD
: 0;
1923 machine_mode mode
= GET_MODE (op
);
1925 if (mode
== VOIDmode
)
1926 mode
= TARGET_64BIT
? TImode
: DImode
;
1929 return adjust_address (op
, word_mode
, byte
);
1932 gcc_assert (!FP_REG_RTX_P (op
));
1934 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
1937 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
1940 riscv_split_64bit_move_p (rtx dest
, rtx src
)
1945 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
1946 of zeroing an FPR with FCVT.D.W. */
1947 if (TARGET_DOUBLE_FLOAT
1948 && ((FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
1949 || (FP_REG_RTX_P (dest
) && MEM_P (src
))
1950 || (FP_REG_RTX_P (src
) && MEM_P (dest
))
1951 || (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))))
1957 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
1958 this function handles 64-bit moves for which riscv_split_64bit_move_p
1959 holds. For 64-bit targets, this function handles 128-bit moves. */
1962 riscv_split_doubleword_move (rtx dest
, rtx src
)
1966 /* The operation can be split into two normal moves. Decide in
1967 which order to do them. */
1968 low_dest
= riscv_subword (dest
, false);
1969 if (REG_P (low_dest
) && reg_overlap_mentioned_p (low_dest
, src
))
1971 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1972 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1976 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1977 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1981 /* Return the appropriate instructions to move SRC into DEST. Assume
1982 that SRC is operand 1 and DEST is operand 0. */
1985 riscv_output_move (rtx dest
, rtx src
)
1987 enum rtx_code dest_code
, src_code
;
1991 dest_code
= GET_CODE (dest
);
1992 src_code
= GET_CODE (src
);
1993 mode
= GET_MODE (dest
);
1994 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
1996 if (dbl_p
&& riscv_split_64bit_move_p (dest
, src
))
1999 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
2001 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2002 return dbl_p
? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1";
2004 if (src_code
== MEM
)
2005 switch (GET_MODE_SIZE (mode
))
2007 case 1: return "lbu\t%0,%1";
2008 case 2: return "lhu\t%0,%1";
2009 case 4: return "lw\t%0,%1";
2010 case 8: return "ld\t%0,%1";
2013 if (src_code
== CONST_INT
)
2016 if (src_code
== HIGH
)
2017 return "lui\t%0,%h1";
2019 if (symbolic_operand (src
, VOIDmode
))
2020 switch (riscv_classify_symbolic_expression (src
))
2022 case SYMBOL_GOT_DISP
: return "la\t%0,%1";
2023 case SYMBOL_ABSOLUTE
: return "lla\t%0,%1";
2024 case SYMBOL_PCREL
: return "lla\t%0,%1";
2025 default: gcc_unreachable ();
2028 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
2029 || (src
== CONST0_RTX (mode
)))
2031 if (dest_code
== REG
)
2033 if (GP_REG_P (REGNO (dest
)))
2034 return "mv\t%0,%z1";
2036 if (FP_REG_P (REGNO (dest
)))
2039 return "fmv.w.x\t%0,%z1";
2041 return "fmv.d.x\t%0,%z1";
2042 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
2043 gcc_assert (src
== CONST0_RTX (mode
));
2044 return "fcvt.d.w\t%0,x0";
2047 if (dest_code
== MEM
)
2048 switch (GET_MODE_SIZE (mode
))
2050 case 1: return "sb\t%z1,%0";
2051 case 2: return "sh\t%z1,%0";
2052 case 4: return "sw\t%z1,%0";
2053 case 8: return "sd\t%z1,%0";
2056 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2058 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2059 return dbl_p
? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
2061 if (dest_code
== MEM
)
2062 return dbl_p
? "fsd\t%1,%0" : "fsw\t%1,%0";
2064 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2066 if (src_code
== MEM
)
2067 return dbl_p
? "fld\t%0,%1" : "flw\t%0,%1";
2073 riscv_output_return ()
2075 if (cfun
->machine
->naked_p
)
2082 /* Return true if CMP1 is a suitable second operand for integer ordering
2083 test CODE. See also the *sCC patterns in riscv.md. */
2086 riscv_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
2092 return reg_or_0_operand (cmp1
, VOIDmode
);
2096 return cmp1
== const1_rtx
;
2100 return arith_operand (cmp1
, VOIDmode
);
2103 return sle_operand (cmp1
, VOIDmode
);
2106 return sleu_operand (cmp1
, VOIDmode
);
2113 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
2114 integer ordering test *CODE, or if an equivalent combination can
2115 be formed by adjusting *CODE and *CMP1. When returning true, update
2116 *CODE and *CMP1 with the chosen code and operand, otherwise leave
2120 riscv_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
2123 HOST_WIDE_INT plus_one
;
2125 if (riscv_int_order_operand_ok_p (*code
, *cmp1
))
2128 if (CONST_INT_P (*cmp1
))
2132 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2133 if (INTVAL (*cmp1
) < plus_one
)
2136 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2142 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
2146 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
2157 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
2158 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
2159 is nonnull, it's OK to set TARGET to the inverse of the result and
2160 flip *INVERT_PTR instead. */
2163 riscv_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
2164 rtx target
, rtx cmp0
, rtx cmp1
)
2168 /* First see if there is a RISCV instruction that can do this operation.
2169 If not, try doing the same for the inverse operation. If that also
2170 fails, force CMP1 into a register and try again. */
2171 mode
= GET_MODE (cmp0
);
2172 if (riscv_canonicalize_int_order_test (&code
, &cmp1
, mode
))
2173 riscv_emit_binary (code
, target
, cmp0
, cmp1
);
2176 enum rtx_code inv_code
= reverse_condition (code
);
2177 if (!riscv_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
2179 cmp1
= force_reg (mode
, cmp1
);
2180 riscv_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
2182 else if (invert_ptr
== 0)
2184 rtx inv_target
= riscv_force_binary (GET_MODE (target
),
2185 inv_code
, cmp0
, cmp1
);
2186 riscv_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
2190 *invert_ptr
= !*invert_ptr
;
2191 riscv_emit_binary (inv_code
, target
, cmp0
, cmp1
);
2196 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2197 The register will have the same mode as CMP0. */
2200 riscv_zero_if_equal (rtx cmp0
, rtx cmp1
)
2202 if (cmp1
== const0_rtx
)
2205 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2206 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2209 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2212 riscv_extend_comparands (rtx_code code
, rtx
*op0
, rtx
*op1
)
2214 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2215 if (GET_MODE_SIZE (word_mode
) > GET_MODE_SIZE (GET_MODE (*op0
)))
2217 /* It is more profitable to zero-extend QImode values. But not if the
2218 first operand has already been sign-extended, and the second one is
2219 is a constant or has already been sign-extended also. */
2220 if (unsigned_condition (code
) == code
2221 && (GET_MODE (*op0
) == QImode
2222 && ! (GET_CODE (*op0
) == SUBREG
2223 && SUBREG_PROMOTED_VAR_P (*op0
)
2224 && SUBREG_PROMOTED_SIGNED_P (*op0
)
2225 && (CONST_INT_P (*op1
)
2226 || (GET_CODE (*op1
) == SUBREG
2227 && SUBREG_PROMOTED_VAR_P (*op1
)
2228 && SUBREG_PROMOTED_SIGNED_P (*op1
))))))
2230 *op0
= gen_rtx_ZERO_EXTEND (word_mode
, *op0
);
2231 if (CONST_INT_P (*op1
))
2232 *op1
= GEN_INT ((uint8_t) INTVAL (*op1
));
2234 *op1
= gen_rtx_ZERO_EXTEND (word_mode
, *op1
);
2238 *op0
= gen_rtx_SIGN_EXTEND (word_mode
, *op0
);
2239 if (*op1
!= const0_rtx
)
2240 *op1
= gen_rtx_SIGN_EXTEND (word_mode
, *op1
);
2245 /* Convert a comparison into something that can be used in a branch. On
2246 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2247 used to compare them. Update them to describe the final comparison. */
2250 riscv_emit_int_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2252 if (splittable_const_int_operand (*op1
, VOIDmode
))
2254 HOST_WIDE_INT rhs
= INTVAL (*op1
);
2256 if (*code
== EQ
|| *code
== NE
)
2258 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2259 if (SMALL_OPERAND (-rhs
))
2261 *op0
= riscv_force_binary (GET_MODE (*op0
), PLUS
, *op0
,
2268 static const enum rtx_code mag_comparisons
[][2] = {
2269 {LEU
, LTU
}, {GTU
, GEU
}, {LE
, LT
}, {GT
, GE
}
2272 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2273 for (size_t i
= 0; i
< ARRAY_SIZE (mag_comparisons
); i
++)
2275 HOST_WIDE_INT new_rhs
;
2276 bool increment
= *code
== mag_comparisons
[i
][0];
2277 bool decrement
= *code
== mag_comparisons
[i
][1];
2278 if (!increment
&& !decrement
)
2281 new_rhs
= rhs
+ (increment
? 1 : -1);
2282 if (riscv_integer_cost (new_rhs
) < riscv_integer_cost (rhs
)
2283 && (rhs
< 0) == (new_rhs
< 0))
2285 *op1
= GEN_INT (new_rhs
);
2286 *code
= mag_comparisons
[i
][increment
];
2293 riscv_extend_comparands (*code
, op0
, op1
);
2295 *op0
= force_reg (word_mode
, *op0
);
2296 if (*op1
!= const0_rtx
)
2297 *op1
= force_reg (word_mode
, *op1
);
2300 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2303 riscv_emit_float_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2305 rtx tmp0
, tmp1
, cmp_op0
= *op0
, cmp_op1
= *op1
;
2306 enum rtx_code fp_code
= *code
;
2316 /* a == a && b == b */
2317 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2318 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2319 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2324 /* ordered(a, b) > (a == b) */
2326 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2327 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2328 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2329 *op1
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op1
);
2332 #define UNORDERED_COMPARISON(CODE, CMP) \
2335 *op0 = gen_reg_rtx (word_mode); \
2336 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2337 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2338 else if (GET_MODE (cmp_op0) == SFmode) \
2339 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2340 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2341 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2342 else if (GET_MODE (cmp_op0) == DFmode) \
2343 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2345 gcc_unreachable (); \
2346 *op1 = const0_rtx; \
2350 std::swap (cmp_op0
, cmp_op1
);
2353 UNORDERED_COMPARISON(UNGT
, le
)
2356 std::swap (cmp_op0
, cmp_op1
);
2359 UNORDERED_COMPARISON(UNGE
, lt
)
2360 #undef UNORDERED_COMPARISON
2372 /* We have instructions for these cases. */
2373 *op0
= riscv_force_binary (word_mode
, fp_code
, cmp_op0
, cmp_op1
);
2378 /* (a < b) | (a > b) */
2379 tmp0
= riscv_force_binary (word_mode
, LT
, cmp_op0
, cmp_op1
);
2380 tmp1
= riscv_force_binary (word_mode
, GT
, cmp_op0
, cmp_op1
);
2381 *op0
= riscv_force_binary (word_mode
, IOR
, tmp0
, tmp1
);
2390 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2393 riscv_expand_int_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2395 riscv_extend_comparands (code
, &op0
, &op1
);
2396 op0
= force_reg (word_mode
, op0
);
2398 if (code
== EQ
|| code
== NE
)
2400 rtx zie
= riscv_zero_if_equal (op0
, op1
);
2401 riscv_emit_binary (code
, target
, zie
, const0_rtx
);
2404 riscv_emit_int_order_test (code
, 0, target
, op0
, op1
);
2407 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2410 riscv_expand_float_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2412 riscv_emit_float_compare (&code
, &op0
, &op1
);
2414 rtx cmp
= riscv_force_binary (word_mode
, code
, op0
, op1
);
2415 riscv_emit_set (target
, lowpart_subreg (SImode
, cmp
, word_mode
));
2418 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2421 riscv_expand_conditional_branch (rtx label
, rtx_code code
, rtx op0
, rtx op1
)
2423 if (FLOAT_MODE_P (GET_MODE (op1
)))
2424 riscv_emit_float_compare (&code
, &op0
, &op1
);
2426 riscv_emit_int_compare (&code
, &op0
, &op1
);
2428 rtx condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2429 emit_jump_insn (gen_condjump (condition
, label
));
2432 /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
2435 riscv_expand_conditional_move (rtx dest
, rtx cons
, rtx alt
, rtx_code code
,
2438 riscv_emit_int_compare (&code
, &op0
, &op1
);
2439 rtx cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
2440 emit_insn (gen_rtx_SET (dest
, gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), cond
,
2444 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2445 least PARM_BOUNDARY bits of alignment, but will be given anything up
2446 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2449 riscv_function_arg_boundary (machine_mode mode
, const_tree type
)
2451 unsigned int alignment
;
2453 /* Use natural alignment if the type is not aggregate data. */
2454 if (type
&& !AGGREGATE_TYPE_P (type
))
2455 alignment
= TYPE_ALIGN (TYPE_MAIN_VARIANT (type
));
2457 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2459 return MIN (PREFERRED_STACK_BOUNDARY
, MAX (PARM_BOUNDARY
, alignment
));
2462 /* If MODE represents an argument that can be passed or returned in
2463 floating-point registers, return the number of registers, else 0. */
2466 riscv_pass_mode_in_fpr_p (machine_mode mode
)
2468 if (GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FP_ARG
)
2470 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2473 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
2482 HOST_WIDE_INT offset
;
2483 } riscv_aggregate_field
;
2485 /* Identify subfields of aggregates that are candidates for passing in
2486 floating-point registers. */
2489 riscv_flatten_aggregate_field (const_tree type
,
2490 riscv_aggregate_field fields
[2],
2491 int n
, HOST_WIDE_INT offset
,
2492 bool ignore_zero_width_bit_field_p
)
2494 switch (TREE_CODE (type
))
2497 /* Can't handle incomplete types nor sizes that are not fixed. */
2498 if (!COMPLETE_TYPE_P (type
)
2499 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2500 || !tree_fits_uhwi_p (TYPE_SIZE (type
)))
2503 for (tree f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
2504 if (TREE_CODE (f
) == FIELD_DECL
)
2506 if (!TYPE_P (TREE_TYPE (f
)))
2509 /* The C++ front end strips zero-length bit-fields from structs.
2510 So we need to ignore them in the C front end to make C code
2511 compatible with C++ code. */
2512 if (ignore_zero_width_bit_field_p
2513 && DECL_BIT_FIELD (f
)
2514 && (DECL_SIZE (f
) == NULL_TREE
2515 || integer_zerop (DECL_SIZE (f
))))
2519 HOST_WIDE_INT pos
= offset
+ int_byte_position (f
);
2520 n
= riscv_flatten_aggregate_field (TREE_TYPE (f
),
2522 ignore_zero_width_bit_field_p
);
2531 HOST_WIDE_INT n_elts
;
2532 riscv_aggregate_field subfields
[2];
2533 tree index
= TYPE_DOMAIN (type
);
2534 tree elt_size
= TYPE_SIZE_UNIT (TREE_TYPE (type
));
2535 int n_subfields
= riscv_flatten_aggregate_field (TREE_TYPE (type
),
2536 subfields
, 0, offset
,
2537 ignore_zero_width_bit_field_p
);
2539 /* Can't handle incomplete types nor sizes that are not fixed. */
2540 if (n_subfields
<= 0
2541 || !COMPLETE_TYPE_P (type
)
2542 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2544 || !TYPE_MAX_VALUE (index
)
2545 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
2546 || !TYPE_MIN_VALUE (index
)
2547 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
2548 || !tree_fits_uhwi_p (elt_size
))
2551 n_elts
= 1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
2552 - tree_to_uhwi (TYPE_MIN_VALUE (index
));
2553 gcc_assert (n_elts
>= 0);
2555 for (HOST_WIDE_INT i
= 0; i
< n_elts
; i
++)
2556 for (int j
= 0; j
< n_subfields
; j
++)
2561 fields
[n
] = subfields
[j
];
2562 fields
[n
++].offset
+= i
* tree_to_uhwi (elt_size
);
2570 /* Complex type need consume 2 field, so n must be 0. */
2574 HOST_WIDE_INT elt_size
= GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type
)));
2576 if (elt_size
<= UNITS_PER_FP_ARG
)
2578 fields
[0].type
= TREE_TYPE (type
);
2579 fields
[0].offset
= offset
;
2580 fields
[1].type
= TREE_TYPE (type
);
2581 fields
[1].offset
= offset
+ elt_size
;
2591 && ((SCALAR_FLOAT_TYPE_P (type
)
2592 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FP_ARG
)
2593 || (INTEGRAL_TYPE_P (type
)
2594 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_WORD
)))
2596 fields
[n
].type
= type
;
2597 fields
[n
].offset
= offset
;
2605 /* Identify candidate aggregates for passing in floating-point registers.
2606 Candidates have at most two fields after flattening. */
2609 riscv_flatten_aggregate_argument (const_tree type
,
2610 riscv_aggregate_field fields
[2],
2611 bool ignore_zero_width_bit_field_p
)
2613 if (!type
|| TREE_CODE (type
) != RECORD_TYPE
)
2616 return riscv_flatten_aggregate_field (type
, fields
, 0, 0,
2617 ignore_zero_width_bit_field_p
);
2620 /* See whether TYPE is a record whose fields should be returned in one or
2621 two floating-point registers. If so, populate FIELDS accordingly. */
2624 riscv_pass_aggregate_in_fpr_pair_p (const_tree type
,
2625 riscv_aggregate_field fields
[2])
2627 static int warned
= 0;
2629 /* This is the old ABI, which differs for C++ and C. */
2630 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2631 for (int i
= 0; i
< n_old
; i
++)
2632 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2638 /* This is the new ABI, which is the same for C++ and C. */
2639 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2640 for (int i
= 0; i
< n_new
; i
++)
2641 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2647 if ((n_old
!= n_new
) && (warned
== 0))
2649 warning (0, "ABI for flattened struct with zero-length bit-fields "
2650 "changed in GCC 10");
2654 return n_new
> 0 ? n_new
: 0;
2657 /* See whether TYPE is a record whose fields should be returned in one or
2658 floating-point register and one integer register. If so, populate
2659 FIELDS accordingly. */
2662 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type
,
2663 riscv_aggregate_field fields
[2])
2665 static int warned
= 0;
2667 /* This is the old ABI, which differs for C++ and C. */
2668 unsigned num_int_old
= 0, num_float_old
= 0;
2669 int n_old
= riscv_flatten_aggregate_argument (type
, fields
, false);
2670 for (int i
= 0; i
< n_old
; i
++)
2672 num_float_old
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2673 num_int_old
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2676 /* This is the new ABI, which is the same for C++ and C. */
2677 unsigned num_int_new
= 0, num_float_new
= 0;
2678 int n_new
= riscv_flatten_aggregate_argument (type
, fields
, true);
2679 for (int i
= 0; i
< n_new
; i
++)
2681 num_float_new
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2682 num_int_new
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2685 if (((num_int_old
== 1 && num_float_old
== 1
2686 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
))
2687 || (num_int_new
== 1 && num_float_new
== 1
2688 && (num_int_old
!= num_int_new
|| num_float_old
!= num_float_new
)))
2691 warning (0, "ABI for flattened struct with zero-length bit-fields "
2692 "changed in GCC 10");
2696 return num_int_new
== 1 && num_float_new
== 1;
2699 /* Return the representation of an argument passed or returned in an FPR
2700 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2701 two modes may be different for structures like:
2703 struct __attribute__((packed)) foo { float f; }
2705 where the SFmode value "f" is passed in REGNO but the struct itself
2706 has mode BLKmode. */
2709 riscv_pass_fpr_single (machine_mode type_mode
, unsigned regno
,
2710 machine_mode value_mode
,
2711 HOST_WIDE_INT offset
)
2713 rtx x
= gen_rtx_REG (value_mode
, regno
);
2715 if (type_mode
!= value_mode
)
2717 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, GEN_INT (offset
));
2718 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
2723 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
2724 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
2725 byte offset for the first value, likewise MODE2 and OFFSET2 for the
2729 riscv_pass_fpr_pair (machine_mode mode
, unsigned regno1
,
2730 machine_mode mode1
, HOST_WIDE_INT offset1
,
2731 unsigned regno2
, machine_mode mode2
,
2732 HOST_WIDE_INT offset2
)
2734 return gen_rtx_PARALLEL
2737 gen_rtx_EXPR_LIST (VOIDmode
,
2738 gen_rtx_REG (mode1
, regno1
),
2740 gen_rtx_EXPR_LIST (VOIDmode
,
2741 gen_rtx_REG (mode2
, regno2
),
2742 GEN_INT (offset2
))));
2745 /* Fill INFO with information about a single argument, and return an
2746 RTL pattern to pass or return the argument. CUM is the cumulative
2747 state for earlier arguments. MODE is the mode of this argument and
2748 TYPE is its type (if known). NAMED is true if this is a named
2749 (fixed) argument rather than a variable one. RETURN_P is true if
2750 returning the argument, or false if passing the argument. */
2753 riscv_get_arg_info (struct riscv_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
2754 machine_mode mode
, const_tree type
, bool named
,
2757 unsigned num_bytes
, num_words
;
2758 unsigned fpr_base
= return_p
? FP_RETURN
: FP_ARG_FIRST
;
2759 unsigned gpr_base
= return_p
? GP_RETURN
: GP_ARG_FIRST
;
2760 unsigned alignment
= riscv_function_arg_boundary (mode
, type
);
2762 memset (info
, 0, sizeof (*info
));
2763 info
->gpr_offset
= cum
->num_gprs
;
2764 info
->fpr_offset
= cum
->num_fprs
;
2768 riscv_aggregate_field fields
[2];
2769 unsigned fregno
= fpr_base
+ info
->fpr_offset
;
2770 unsigned gregno
= gpr_base
+ info
->gpr_offset
;
2772 /* Pass one- or two-element floating-point aggregates in FPRs. */
2773 if ((info
->num_fprs
= riscv_pass_aggregate_in_fpr_pair_p (type
, fields
))
2774 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2775 switch (info
->num_fprs
)
2778 return riscv_pass_fpr_single (mode
, fregno
,
2779 TYPE_MODE (fields
[0].type
),
2783 return riscv_pass_fpr_pair (mode
, fregno
,
2784 TYPE_MODE (fields
[0].type
),
2787 TYPE_MODE (fields
[1].type
),
2794 /* Pass real and complex floating-point numbers in FPRs. */
2795 if ((info
->num_fprs
= riscv_pass_mode_in_fpr_p (mode
))
2796 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2797 switch (GET_MODE_CLASS (mode
))
2800 return gen_rtx_REG (mode
, fregno
);
2802 case MODE_COMPLEX_FLOAT
:
2803 return riscv_pass_fpr_pair (mode
, fregno
, GET_MODE_INNER (mode
), 0,
2804 fregno
+ 1, GET_MODE_INNER (mode
),
2805 GET_MODE_UNIT_SIZE (mode
));
2811 /* Pass structs with one float and one integer in an FPR and a GPR. */
2812 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type
, fields
)
2813 && info
->gpr_offset
< MAX_ARGS_IN_REGISTERS
2814 && info
->fpr_offset
< MAX_ARGS_IN_REGISTERS
)
2819 if (!SCALAR_FLOAT_TYPE_P (fields
[0].type
))
2820 std::swap (fregno
, gregno
);
2822 return riscv_pass_fpr_pair (mode
, fregno
, TYPE_MODE (fields
[0].type
),
2824 gregno
, TYPE_MODE (fields
[1].type
),
2829 /* Work out the size of the argument. */
2830 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2831 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2833 /* Doubleword-aligned varargs start on an even register boundary. */
2834 if (!named
&& num_bytes
!= 0 && alignment
> BITS_PER_WORD
)
2835 info
->gpr_offset
+= info
->gpr_offset
& 1;
2837 /* Partition the argument between registers and stack. */
2839 info
->num_gprs
= MIN (num_words
, MAX_ARGS_IN_REGISTERS
- info
->gpr_offset
);
2840 info
->stack_p
= (num_words
- info
->num_gprs
) != 0;
2842 if (info
->num_gprs
|| return_p
)
2843 return gen_rtx_REG (mode
, gpr_base
+ info
->gpr_offset
);
2848 /* Implement TARGET_FUNCTION_ARG. */
2851 riscv_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
2853 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2854 struct riscv_arg_info info
;
2856 if (arg
.end_marker_p ())
2859 return riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2862 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
2865 riscv_function_arg_advance (cumulative_args_t cum_v
,
2866 const function_arg_info
&arg
)
2868 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2869 struct riscv_arg_info info
;
2871 riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2873 /* Advance the register count. This has the effect of setting
2874 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
2875 argument required us to skip the final GPR and pass the whole
2876 argument on the stack. */
2877 cum
->num_fprs
= info
.fpr_offset
+ info
.num_fprs
;
2878 cum
->num_gprs
= info
.gpr_offset
+ info
.num_gprs
;
2881 /* Implement TARGET_ARG_PARTIAL_BYTES. */
2884 riscv_arg_partial_bytes (cumulative_args_t cum
,
2885 const function_arg_info
&generic_arg
)
2887 struct riscv_arg_info arg
;
2889 riscv_get_arg_info (&arg
, get_cumulative_args (cum
), generic_arg
.mode
,
2890 generic_arg
.type
, generic_arg
.named
, false);
2891 return arg
.stack_p
? arg
.num_gprs
* UNITS_PER_WORD
: 0;
2894 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
2895 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
2896 VALTYPE is null and MODE is the mode of the return value. */
2899 riscv_function_value (const_tree type
, const_tree func
, machine_mode mode
)
2901 struct riscv_arg_info info
;
2902 CUMULATIVE_ARGS args
;
2906 int unsigned_p
= TYPE_UNSIGNED (type
);
2908 mode
= TYPE_MODE (type
);
2910 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
2911 return values, promote the mode here too. */
2912 mode
= promote_function_mode (type
, mode
, &unsigned_p
, func
, 1);
2915 memset (&args
, 0, sizeof args
);
2916 return riscv_get_arg_info (&info
, &args
, mode
, type
, true, true);
2919 /* Implement TARGET_PASS_BY_REFERENCE. */
2922 riscv_pass_by_reference (cumulative_args_t cum_v
, const function_arg_info
&arg
)
2924 HOST_WIDE_INT size
= arg
.type_size_in_bytes ();
2925 struct riscv_arg_info info
;
2926 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2928 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
2929 never pass variadic arguments in floating-point registers, so we can
2930 avoid the call to riscv_get_arg_info in this case. */
2933 /* Don't pass by reference if we can use a floating-point register. */
2934 riscv_get_arg_info (&info
, cum
, arg
.mode
, arg
.type
, arg
.named
, false);
2939 /* Pass by reference if the data do not fit in two integer registers. */
2940 return !IN_RANGE (size
, 0, 2 * UNITS_PER_WORD
);
2943 /* Implement TARGET_RETURN_IN_MEMORY. */
2946 riscv_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
2948 CUMULATIVE_ARGS args
;
2949 cumulative_args_t cum
= pack_cumulative_args (&args
);
2951 /* The rules for returning in memory are the same as for passing the
2952 first named argument by reference. */
2953 memset (&args
, 0, sizeof args
);
2954 function_arg_info
arg (const_cast<tree
> (type
), /*named=*/true);
2955 return riscv_pass_by_reference (cum
, arg
);
2958 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
2961 riscv_setup_incoming_varargs (cumulative_args_t cum
,
2962 const function_arg_info
&arg
,
2963 int *pretend_size ATTRIBUTE_UNUSED
, int no_rtl
)
2965 CUMULATIVE_ARGS local_cum
;
2968 /* The caller has advanced CUM up to, but not beyond, the last named
2969 argument. Advance a local copy of CUM past the last "real" named
2970 argument, to find out how many registers are left over. */
2971 local_cum
= *get_cumulative_args (cum
);
2972 riscv_function_arg_advance (pack_cumulative_args (&local_cum
), arg
);
2974 /* Found out how many registers we need to save. */
2975 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
2977 if (!no_rtl
&& gp_saved
> 0)
2979 rtx ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
2980 REG_PARM_STACK_SPACE (cfun
->decl
)
2981 - gp_saved
* UNITS_PER_WORD
);
2982 rtx mem
= gen_frame_mem (BLKmode
, ptr
);
2983 set_mem_alias_set (mem
, get_varargs_alias_set ());
2985 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
2988 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
2989 cfun
->machine
->varargs_size
= gp_saved
* UNITS_PER_WORD
;
2992 /* Handle an attribute requiring a FUNCTION_DECL;
2993 arguments as in struct attribute_spec.handler. */
2995 riscv_handle_fndecl_attribute (tree
*node
, tree name
,
2996 tree args ATTRIBUTE_UNUSED
,
2997 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2999 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3001 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3003 *no_add_attrs
= true;
3009 /* Verify type based attributes. NODE is the what the attribute is being
3010 applied to. NAME is the attribute name. ARGS are the attribute args.
3011 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
3012 the attribute should be ignored. */
3015 riscv_handle_type_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
3016 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
3018 /* Check for an argument. */
3019 if (is_attribute_p ("interrupt", name
))
3023 tree cst
= TREE_VALUE (args
);
3026 if (TREE_CODE (cst
) != STRING_CST
)
3028 warning (OPT_Wattributes
,
3029 "%qE attribute requires a string argument",
3031 *no_add_attrs
= true;
3035 string
= TREE_STRING_POINTER (cst
);
3036 if (strcmp (string
, "user") && strcmp (string
, "supervisor")
3037 && strcmp (string
, "machine"))
3039 warning (OPT_Wattributes
,
3040 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"",
3042 *no_add_attrs
= true;
3050 /* Return true if function TYPE is an interrupt function. */
3052 riscv_interrupt_type_p (tree type
)
3054 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
3057 /* Return true if FUNC is a naked function. */
3059 riscv_naked_function_p (tree func
)
3061 tree func_decl
= func
;
3062 if (func
== NULL_TREE
)
3063 func_decl
= current_function_decl
;
3064 return NULL_TREE
!= lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl
));
3067 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
3069 riscv_allocate_stack_slots_for_args ()
3071 /* Naked functions should not allocate stack slots for arguments. */
3072 return !riscv_naked_function_p (current_function_decl
);
3075 /* Implement TARGET_WARN_FUNC_RETURN. */
3077 riscv_warn_func_return (tree decl
)
3079 /* Naked functions are implemented entirely in assembly, including the
3080 return sequence, so suppress warnings about this. */
3081 return !riscv_naked_function_p (decl
);
3084 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
3087 riscv_va_start (tree valist
, rtx nextarg
)
3089 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
3090 std_expand_builtin_va_start (valist
, nextarg
);
3093 /* Make ADDR suitable for use as a call or sibcall target. */
3096 riscv_legitimize_call_address (rtx addr
)
3098 if (!call_insn_operand (addr
, VOIDmode
))
3100 rtx reg
= RISCV_PROLOGUE_TEMP (Pmode
);
3101 riscv_emit_move (reg
, addr
);
3107 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3108 Assume that the areas do not overlap. */
3111 riscv_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
3113 HOST_WIDE_INT offset
, delta
;
3114 unsigned HOST_WIDE_INT bits
;
3116 enum machine_mode mode
;
3119 bits
= MAX (BITS_PER_UNIT
,
3120 MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
))));
3122 mode
= mode_for_size (bits
, MODE_INT
, 0).require ();
3123 delta
= bits
/ BITS_PER_UNIT
;
3125 /* Allocate a buffer for the temporary registers. */
3126 regs
= XALLOCAVEC (rtx
, length
/ delta
);
3128 /* Load as many BITS-sized chunks as possible. Use a normal load if
3129 the source has enough alignment, otherwise use left/right pairs. */
3130 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3132 regs
[i
] = gen_reg_rtx (mode
);
3133 riscv_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
3136 /* Copy the chunks to the destination. */
3137 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3138 riscv_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
3140 /* Mop up any left-over bytes. */
3141 if (offset
< length
)
3143 src
= adjust_address (src
, BLKmode
, offset
);
3144 dest
= adjust_address (dest
, BLKmode
, offset
);
3145 move_by_pieces (dest
, src
, length
- offset
,
3146 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), RETURN_BEGIN
);
3150 /* Helper function for doing a loop-based block operation on memory
3151 reference MEM. Each iteration of the loop will operate on LENGTH
3154 Create a new base register for use within the loop and point it to
3155 the start of MEM. Create a new memory reference that uses this
3156 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3159 riscv_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
3160 rtx
*loop_reg
, rtx
*loop_mem
)
3162 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
3164 /* Although the new mem does not refer to a known location,
3165 it does keep up to LENGTH bytes of alignment. */
3166 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
3167 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
3170 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
3171 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
3172 the memory regions do not overlap. */
3175 riscv_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
3176 HOST_WIDE_INT bytes_per_iter
)
3178 rtx label
, src_reg
, dest_reg
, final_src
, test
;
3179 HOST_WIDE_INT leftover
;
3181 leftover
= length
% bytes_per_iter
;
3184 /* Create registers and memory references for use within the loop. */
3185 riscv_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
3186 riscv_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
3188 /* Calculate the value that SRC_REG should have after the last iteration
3190 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
3193 /* Emit the start of the loop. */
3194 label
= gen_label_rtx ();
3197 /* Emit the loop body. */
3198 riscv_block_move_straight (dest
, src
, bytes_per_iter
);
3200 /* Move on to the next block. */
3201 riscv_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
3202 riscv_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
3204 /* Emit the loop condition. */
3205 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
3206 if (Pmode
== DImode
)
3207 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
3209 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
3211 /* Mop up any left-over bytes. */
3213 riscv_block_move_straight (dest
, src
, leftover
);
3215 emit_insn(gen_nop ());
3218 /* Expand a cpymemsi instruction, which copies LENGTH bytes from
3219 memory reference SRC to memory reference DEST. */
3222 riscv_expand_block_move (rtx dest
, rtx src
, rtx length
)
3224 if (CONST_INT_P (length
))
3226 HOST_WIDE_INT factor
, align
;
3228 align
= MIN (MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), BITS_PER_WORD
);
3229 factor
= BITS_PER_WORD
/ align
;
3231 if (optimize_function_for_size_p (cfun
)
3232 && INTVAL (length
) * factor
* UNITS_PER_WORD
> MOVE_RATIO (false))
3235 if (INTVAL (length
) <= RISCV_MAX_MOVE_BYTES_STRAIGHT
/ factor
)
3237 riscv_block_move_straight (dest
, src
, INTVAL (length
));
3240 else if (optimize
&& align
>= BITS_PER_WORD
)
3242 unsigned min_iter_words
3243 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER
/ UNITS_PER_WORD
;
3244 unsigned iter_words
= min_iter_words
;
3245 HOST_WIDE_INT bytes
= INTVAL (length
), words
= bytes
/ UNITS_PER_WORD
;
3247 /* Lengthen the loop body if it shortens the tail. */
3248 for (unsigned i
= min_iter_words
; i
< min_iter_words
* 2 - 1; i
++)
3250 unsigned cur_cost
= iter_words
+ words
% iter_words
;
3251 unsigned new_cost
= i
+ words
% i
;
3252 if (new_cost
<= cur_cost
)
3256 riscv_block_move_loop (dest
, src
, bytes
, iter_words
* UNITS_PER_WORD
);
3263 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
3264 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
3267 riscv_print_operand_reloc (FILE *file
, rtx op
, bool hi_reloc
)
3271 switch (riscv_classify_symbolic_expression (op
))
3273 case SYMBOL_ABSOLUTE
:
3274 reloc
= hi_reloc
? "%hi" : "%lo";
3278 reloc
= hi_reloc
? "%pcrel_hi" : "%pcrel_lo";
3282 reloc
= hi_reloc
? "%tprel_hi" : "%tprel_lo";
3286 output_operand_lossage ("invalid use of '%%%c'", hi_reloc
? 'h' : 'R');
3290 fprintf (file
, "%s(", reloc
);
3291 output_addr_const (file
, riscv_strip_unspec_address (op
));
3295 /* Return true if the .AQ suffix should be added to an AMO to implement the
3296 acquire portion of memory model MODEL. */
3299 riscv_memmodel_needs_amo_acquire (enum memmodel model
)
3303 case MEMMODEL_ACQ_REL
:
3304 case MEMMODEL_SEQ_CST
:
3305 case MEMMODEL_SYNC_SEQ_CST
:
3306 case MEMMODEL_ACQUIRE
:
3307 case MEMMODEL_CONSUME
:
3308 case MEMMODEL_SYNC_ACQUIRE
:
3311 case MEMMODEL_RELEASE
:
3312 case MEMMODEL_SYNC_RELEASE
:
3313 case MEMMODEL_RELAXED
:
3321 /* Return true if a FENCE should be emitted to before a memory access to
3322 implement the release portion of memory model MODEL. */
3325 riscv_memmodel_needs_release_fence (enum memmodel model
)
3329 case MEMMODEL_ACQ_REL
:
3330 case MEMMODEL_SEQ_CST
:
3331 case MEMMODEL_SYNC_SEQ_CST
:
3332 case MEMMODEL_RELEASE
:
3333 case MEMMODEL_SYNC_RELEASE
:
3336 case MEMMODEL_ACQUIRE
:
3337 case MEMMODEL_CONSUME
:
3338 case MEMMODEL_SYNC_ACQUIRE
:
3339 case MEMMODEL_RELAXED
:
3347 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3349 'h' Print the high-part relocation associated with OP, after stripping
3351 'R' Print the low-part relocation associated with OP.
3352 'C' Print the integer branch condition for comparison OP.
3353 'A' Print the atomic operation suffix for memory model OP.
3354 'F' Print a FENCE if the memory model requires a release.
3355 'z' Print x0 if OP is zero, otherwise print OP normally.
3356 'i' Print i if the operand is not a register. */
3359 riscv_print_operand (FILE *file
, rtx op
, int letter
)
3361 machine_mode mode
= GET_MODE (op
);
3362 enum rtx_code code
= GET_CODE (op
);
3369 riscv_print_operand_reloc (file
, op
, true);
3373 riscv_print_operand_reloc (file
, op
, false);
3377 /* The RTL names match the instruction names. */
3378 fputs (GET_RTX_NAME (code
), file
);
3382 if (riscv_memmodel_needs_amo_acquire ((enum memmodel
) INTVAL (op
)))
3383 fputs (".aq", file
);
3387 if (riscv_memmodel_needs_release_fence ((enum memmodel
) INTVAL (op
)))
3388 fputs ("fence iorw,ow; ", file
);
3400 if (letter
&& letter
!= 'z')
3401 output_operand_lossage ("invalid use of '%%%c'", letter
);
3402 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
3406 if (letter
&& letter
!= 'z')
3407 output_operand_lossage ("invalid use of '%%%c'", letter
);
3409 output_address (mode
, XEXP (op
, 0));
3413 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
3414 fputs (reg_names
[GP_REG_FIRST
], file
);
3415 else if (letter
&& letter
!= 'z')
3416 output_operand_lossage ("invalid use of '%%%c'", letter
);
3418 output_addr_const (file
, riscv_strip_unspec_address (op
));
3424 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3427 riscv_print_operand_address (FILE *file
, machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3429 struct riscv_address_info addr
;
3431 if (riscv_classify_address (&addr
, x
, word_mode
, true))
3435 riscv_print_operand (file
, addr
.offset
, 0);
3436 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3439 case ADDRESS_LO_SUM
:
3440 riscv_print_operand_reloc (file
, addr
.offset
, false);
3441 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3444 case ADDRESS_CONST_INT
:
3445 output_addr_const (file
, x
);
3446 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
3449 case ADDRESS_SYMBOLIC
:
3450 output_addr_const (file
, riscv_strip_unspec_address (x
));
3457 riscv_size_ok_for_small_data_p (int size
)
3459 return g_switch_value
&& IN_RANGE (size
, 1, g_switch_value
);
3462 /* Return true if EXP should be placed in the small data section. */
3465 riscv_in_small_data_p (const_tree x
)
3467 if (TREE_CODE (x
) == STRING_CST
|| TREE_CODE (x
) == FUNCTION_DECL
)
3470 if (TREE_CODE (x
) == VAR_DECL
&& DECL_SECTION_NAME (x
))
3472 const char *sec
= DECL_SECTION_NAME (x
);
3473 return strcmp (sec
, ".sdata") == 0 || strcmp (sec
, ".sbss") == 0;
3476 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x
)));
3479 /* Switch to the appropriate section for output of DECL. */
3482 riscv_select_section (tree decl
, int reloc
,
3483 unsigned HOST_WIDE_INT align
)
3485 switch (categorize_decl_for_section (decl
, reloc
))
3487 case SECCAT_SRODATA
:
3488 return get_named_section (decl
, ".srodata", reloc
);
3491 return default_elf_select_section (decl
, reloc
, align
);
3495 /* Return a section for X, handling small data. */
3498 riscv_elf_select_rtx_section (machine_mode mode
, rtx x
,
3499 unsigned HOST_WIDE_INT align
)
3501 section
*s
= default_elf_select_rtx_section (mode
, x
, align
);
3503 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode
)))
3505 if (strncmp (s
->named
.name
, ".rodata.cst", strlen (".rodata.cst")) == 0)
3507 /* Rename .rodata.cst* to .srodata.cst*. */
3508 char *name
= (char *) alloca (strlen (s
->named
.name
) + 2);
3509 sprintf (name
, ".s%s", s
->named
.name
+ 1);
3510 return get_section (name
, s
->named
.common
.flags
, NULL
);
3513 if (s
== data_section
)
3514 return sdata_section
;
3520 /* Make the last instruction frame-related and note that it performs
3521 the operation described by FRAME_PATTERN. */
3524 riscv_set_frame_expr (rtx frame_pattern
)
3528 insn
= get_last_insn ();
3529 RTX_FRAME_RELATED_P (insn
) = 1;
3530 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3535 /* Return a frame-related rtx that stores REG at MEM.
3536 REG must be a single register. */
3539 riscv_frame_set (rtx mem
, rtx reg
)
3541 rtx set
= gen_rtx_SET (mem
, reg
);
3542 RTX_FRAME_RELATED_P (set
) = 1;
3546 /* Return true if the current function must save register REGNO. */
3549 riscv_save_reg_p (unsigned int regno
)
3551 bool call_saved
= !global_regs
[regno
] && !call_used_or_fixed_reg_p (regno
);
3552 bool might_clobber
= crtl
->saves_all_registers
3553 || df_regs_ever_live_p (regno
);
3555 if (call_saved
&& might_clobber
)
3558 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
3561 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
3564 /* If this is an interrupt handler, then must save extra registers. */
3565 if (cfun
->machine
->interrupt_handler_p
)
3567 /* zero register is always zero. */
3568 if (regno
== GP_REG_FIRST
)
3571 /* The function will return the stack pointer to its original value. */
3572 if (regno
== STACK_POINTER_REGNUM
)
3575 /* By convention, we assume that gp and tp are safe. */
3576 if (regno
== GP_REGNUM
|| regno
== THREAD_POINTER_REGNUM
)
3579 /* We must save every register used in this function. If this is not a
3580 leaf function, then we must save all temporary registers. */
3581 if (df_regs_ever_live_p (regno
)
3582 || (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
)))
3589 /* Determine whether to call GPR save/restore routines. */
3591 riscv_use_save_libcall (const struct riscv_frame_info
*frame
)
3593 if (!TARGET_SAVE_RESTORE
|| crtl
->calls_eh_return
|| frame_pointer_needed
3594 || cfun
->machine
->interrupt_handler_p
)
3597 return frame
->save_libcall_adjustment
!= 0;
3600 /* Determine which GPR save/restore routine to call. */
3603 riscv_save_libcall_count (unsigned mask
)
3605 for (unsigned n
= GP_REG_LAST
; n
> GP_REG_FIRST
; n
--)
3606 if (BITSET_P (mask
, n
))
3607 return CALLEE_SAVED_REG_NUMBER (n
) + 1;
3611 /* Populate the current function's riscv_frame_info structure.
3613 RISC-V stack frames grown downward. High addresses are at the top.
3615 +-------------------------------+
3617 | incoming stack arguments |
3619 +-------------------------------+ <-- incoming stack pointer
3621 | callee-allocated save area |
3622 | for arguments that are |
3623 | split between registers and |
3626 +-------------------------------+ <-- arg_pointer_rtx
3628 | callee-allocated save area |
3629 | for register varargs |
3631 +-------------------------------+ <-- hard_frame_pointer_rtx;
3632 | | stack_pointer_rtx + gp_sp_offset
3633 | GPR save area | + UNITS_PER_WORD
3635 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3636 | | + UNITS_PER_HWVALUE
3639 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3643 P +-------------------------------+
3645 | outgoing stack arguments |
3647 +-------------------------------+ <-- stack_pointer_rtx
3649 Dynamic stack allocations such as alloca insert data at point P.
3650 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3651 hard_frame_pointer_rtx unchanged. */
3653 static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info
*frame
);
3656 riscv_compute_frame_info (void)
3658 struct riscv_frame_info
*frame
;
3659 HOST_WIDE_INT offset
;
3660 bool interrupt_save_t1
= false;
3661 unsigned int regno
, i
, num_x_saved
= 0, num_f_saved
= 0;
3663 frame
= &cfun
->machine
->frame
;
3665 /* In an interrupt function, if we have a large frame, then we need to
3666 save/restore t1. We check for this before clearing the frame struct. */
3667 if (cfun
->machine
->interrupt_handler_p
)
3669 HOST_WIDE_INT step1
= riscv_first_stack_step (frame
);
3670 if (! SMALL_OPERAND (frame
->total_size
- step1
))
3671 interrupt_save_t1
= true;
3674 memset (frame
, 0, sizeof (*frame
));
3676 if (!cfun
->machine
->naked_p
)
3678 /* Find out which GPRs we need to save. */
3679 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3680 if (riscv_save_reg_p (regno
)
3681 || (interrupt_save_t1
&& (regno
== T1_REGNUM
)))
3682 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3684 /* If this function calls eh_return, we must also save and restore the
3685 EH data registers. */
3686 if (crtl
->calls_eh_return
)
3687 for (i
= 0; (regno
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
; i
++)
3688 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3690 /* Find out which FPRs we need to save. This loop must iterate over
3691 the same space as its companion in riscv_for_each_saved_reg. */
3692 if (TARGET_HARD_FLOAT
)
3693 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3694 if (riscv_save_reg_p (regno
))
3695 frame
->fmask
|= 1 << (regno
- FP_REG_FIRST
), num_f_saved
++;
3698 /* At the bottom of the frame are any outgoing stack arguments. */
3699 offset
= RISCV_STACK_ALIGN (crtl
->outgoing_args_size
);
3700 /* Next are local stack variables. */
3701 offset
+= RISCV_STACK_ALIGN (get_frame_size ());
3702 /* The virtual frame pointer points above the local variables. */
3703 frame
->frame_pointer_offset
= offset
;
3704 /* Next are the callee-saved FPRs. */
3706 offset
+= RISCV_STACK_ALIGN (num_f_saved
* UNITS_PER_FP_REG
);
3707 frame
->fp_sp_offset
= offset
- UNITS_PER_FP_REG
;
3708 /* Next are the callee-saved GPRs. */
3711 unsigned x_save_size
= RISCV_STACK_ALIGN (num_x_saved
* UNITS_PER_WORD
);
3712 unsigned num_save_restore
= 1 + riscv_save_libcall_count (frame
->mask
);
3714 /* Only use save/restore routines if they don't alter the stack size. */
3715 if (RISCV_STACK_ALIGN (num_save_restore
* UNITS_PER_WORD
) == x_save_size
)
3717 /* Libcall saves/restores 3 registers at once, so we need to
3718 allocate 12 bytes for callee-saved register. */
3720 x_save_size
= 3 * UNITS_PER_WORD
;
3722 frame
->save_libcall_adjustment
= x_save_size
;
3725 offset
+= x_save_size
;
3727 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
3728 /* The hard frame pointer points above the callee-saved GPRs. */
3729 frame
->hard_frame_pointer_offset
= offset
;
3730 /* Above the hard frame pointer is the callee-allocated varags save area. */
3731 offset
+= RISCV_STACK_ALIGN (cfun
->machine
->varargs_size
);
3732 /* Next is the callee-allocated area for pretend stack arguments. */
3733 offset
+= RISCV_STACK_ALIGN (crtl
->args
.pretend_args_size
);
3734 /* Arg pointer must be below pretend args, but must be above alignment
3736 frame
->arg_pointer_offset
= offset
- crtl
->args
.pretend_args_size
;
3737 frame
->total_size
= offset
;
3738 /* Next points the incoming stack pointer and any incoming arguments. */
3740 /* Only use save/restore routines when the GPRs are atop the frame. */
3741 if (frame
->hard_frame_pointer_offset
!= frame
->total_size
)
3742 frame
->save_libcall_adjustment
= 0;
3745 /* Make sure that we're not trying to eliminate to the wrong hard frame
3749 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
3751 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
3754 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
3755 or argument pointer. TO is either the stack pointer or hard frame
3759 riscv_initial_elimination_offset (int from
, int to
)
3761 HOST_WIDE_INT src
, dest
;
3763 riscv_compute_frame_info ();
3765 if (to
== HARD_FRAME_POINTER_REGNUM
)
3766 dest
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
3767 else if (to
== STACK_POINTER_REGNUM
)
3768 dest
= 0; /* The stack pointer is the base of all offsets, hence 0. */
3772 if (from
== FRAME_POINTER_REGNUM
)
3773 src
= cfun
->machine
->frame
.frame_pointer_offset
;
3774 else if (from
== ARG_POINTER_REGNUM
)
3775 src
= cfun
->machine
->frame
.arg_pointer_offset
;
3782 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
3786 riscv_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
3791 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
3794 /* Emit code to change the current function's return address to
3795 ADDRESS. SCRATCH is available as a scratch register, if needed.
3796 ADDRESS and SCRATCH are both word-mode GPRs. */
3799 riscv_set_return_address (rtx address
, rtx scratch
)
3803 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
3804 slot_address
= riscv_add_offset (scratch
, stack_pointer_rtx
,
3805 cfun
->machine
->frame
.gp_sp_offset
);
3806 riscv_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
3809 /* A function to save or store a register. The first argument is the
3810 register and the second is the stack slot. */
3811 typedef void (*riscv_save_restore_fn
) (rtx
, rtx
);
3813 /* Use FN to save or restore register REGNO. MODE is the register's
3814 mode and OFFSET is the offset of its save slot from the current
3818 riscv_save_restore_reg (machine_mode mode
, int regno
,
3819 HOST_WIDE_INT offset
, riscv_save_restore_fn fn
)
3823 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
, offset
));
3824 fn (gen_rtx_REG (mode
, regno
), mem
);
3827 /* Call FN for each register that is saved by the current function.
3828 SP_OFFSET is the offset of the current stack pointer from the start
3832 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset
, riscv_save_restore_fn fn
,
3833 bool epilogue
, bool maybe_eh_return
)
3835 HOST_WIDE_INT offset
;
3837 /* Save the link register and s-registers. */
3838 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
3839 for (unsigned int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3840 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3842 bool handle_reg
= TRUE
;
3844 /* If this is a normal return in a function that calls the eh_return
3845 builtin, then do not restore the eh return data registers as that
3846 would clobber the return value. But we do still need to save them
3847 in the prologue, and restore them for an exception return, so we
3848 need special handling here. */
3849 if (epilogue
&& !maybe_eh_return
&& crtl
->calls_eh_return
)
3851 unsigned int i
, regnum
;
3853 for (i
= 0; (regnum
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
;
3855 if (regno
== regnum
)
3863 riscv_save_restore_reg (word_mode
, regno
, offset
, fn
);
3864 offset
-= UNITS_PER_WORD
;
3867 /* This loop must iterate over the same space as its companion in
3868 riscv_compute_frame_info. */
3869 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
3870 for (unsigned int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3871 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
3873 machine_mode mode
= TARGET_DOUBLE_FLOAT
? DFmode
: SFmode
;
3875 riscv_save_restore_reg (mode
, regno
, offset
, fn
);
3876 offset
-= GET_MODE_SIZE (mode
);
3880 /* Save register REG to MEM. Make the instruction frame-related. */
3883 riscv_save_reg (rtx reg
, rtx mem
)
3885 riscv_emit_move (mem
, reg
);
3886 riscv_set_frame_expr (riscv_frame_set (mem
, reg
));
3889 /* Restore register REG from MEM. */
3892 riscv_restore_reg (rtx reg
, rtx mem
)
3894 rtx insn
= riscv_emit_move (reg
, mem
);
3895 rtx dwarf
= NULL_RTX
;
3896 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3898 if (epilogue_cfa_sp_offset
&& REGNO (reg
) == HARD_FRAME_POINTER_REGNUM
)
3900 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3901 GEN_INT (epilogue_cfa_sp_offset
));
3902 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3905 REG_NOTES (insn
) = dwarf
;
3906 RTX_FRAME_RELATED_P (insn
) = 1;
3909 /* Return the code to invoke the GPR save routine. */
3912 riscv_output_gpr_save (unsigned mask
)
3915 unsigned n
= riscv_save_libcall_count (mask
);
3917 ssize_t bytes
= snprintf (s
, sizeof (s
), "call\tt0,__riscv_save_%u", n
);
3918 gcc_assert ((size_t) bytes
< sizeof (s
));
3923 /* For stack frames that can't be allocated with a single ADDI instruction,
3924 compute the best value to initially allocate. It must at a minimum
3925 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
3926 try to pick a value that will allow compression of the register saves
3927 without adding extra instructions. */
3929 static HOST_WIDE_INT
3930 riscv_first_stack_step (struct riscv_frame_info
*frame
)
3932 if (SMALL_OPERAND (frame
->total_size
))
3933 return frame
->total_size
;
3935 HOST_WIDE_INT min_first_step
=
3936 RISCV_STACK_ALIGN (frame
->total_size
- frame
->fp_sp_offset
);
3937 HOST_WIDE_INT max_first_step
= IMM_REACH
/ 2 - PREFERRED_STACK_BOUNDARY
/ 8;
3938 HOST_WIDE_INT min_second_step
= frame
->total_size
- max_first_step
;
3939 gcc_assert (min_first_step
<= max_first_step
);
3941 /* As an optimization, use the least-significant bits of the total frame
3942 size, so that the second adjustment step is just LUI + ADD. */
3943 if (!SMALL_OPERAND (min_second_step
)
3944 && frame
->total_size
% IMM_REACH
< IMM_REACH
/ 2
3945 && frame
->total_size
% IMM_REACH
>= min_first_step
)
3946 return frame
->total_size
% IMM_REACH
;
3950 /* If we need two subtracts, and one is small enough to allow compressed
3951 loads and stores, then put that one first. */
3952 if (IN_RANGE (min_second_step
, 0,
3953 (TARGET_64BIT
? SDSP_REACH
: SWSP_REACH
)))
3954 return MAX (min_second_step
, min_first_step
);
3956 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
3957 with the minimum first step, so that we can get compressed loads and
3959 else if (!SMALL_OPERAND (min_second_step
))
3960 return min_first_step
;
3963 return max_first_step
;
3967 riscv_adjust_libcall_cfi_prologue ()
3969 rtx dwarf
= NULL_RTX
;
3970 rtx adjust_sp_rtx
, reg
, mem
, insn
;
3971 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3974 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3975 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3977 /* The save order is ra, s0, s1, s2 to s11. */
3978 if (regno
== RETURN_ADDR_REGNUM
)
3979 offset
= saved_size
- UNITS_PER_WORD
;
3980 else if (regno
== S0_REGNUM
)
3981 offset
= saved_size
- UNITS_PER_WORD
* 2;
3982 else if (regno
== S1_REGNUM
)
3983 offset
= saved_size
- UNITS_PER_WORD
* 3;
3985 offset
= saved_size
- ((regno
- S2_REGNUM
+ 4) * UNITS_PER_WORD
);
3987 reg
= gen_rtx_REG (SImode
, regno
);
3988 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3992 insn
= gen_rtx_SET (mem
, reg
);
3993 dwarf
= alloc_reg_note (REG_CFA_OFFSET
, insn
, dwarf
);
3996 /* Debug info for adjust sp. */
3997 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3998 stack_pointer_rtx
, GEN_INT (-saved_size
));
3999 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
4005 riscv_emit_stack_tie (void)
4007 if (Pmode
== SImode
)
4008 emit_insn (gen_stack_tiesi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
4010 emit_insn (gen_stack_tiedi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
4013 /* Expand the "prologue" pattern. */
4016 riscv_expand_prologue (void)
4018 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
4019 HOST_WIDE_INT size
= frame
->total_size
;
4020 unsigned mask
= frame
->mask
;
4023 if (flag_stack_usage_info
)
4024 current_function_static_stack_size
= size
;
4026 if (cfun
->machine
->naked_p
)
4029 /* When optimizing for size, call a subroutine to save the registers. */
4030 if (riscv_use_save_libcall (frame
))
4032 rtx dwarf
= NULL_RTX
;
4033 dwarf
= riscv_adjust_libcall_cfi_prologue ();
4035 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4036 size
-= frame
->save_libcall_adjustment
;
4037 insn
= emit_insn (gen_gpr_save (GEN_INT (mask
)));
4039 RTX_FRAME_RELATED_P (insn
) = 1;
4040 REG_NOTES (insn
) = dwarf
;
4043 /* Save the registers. */
4044 if ((frame
->mask
| frame
->fmask
) != 0)
4046 HOST_WIDE_INT step1
= MIN (size
, riscv_first_stack_step (frame
));
4048 insn
= gen_add3_insn (stack_pointer_rtx
,
4051 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4053 riscv_for_each_saved_reg (size
, riscv_save_reg
, false, false);
4056 frame
->mask
= mask
; /* Undo the above fib. */
4058 /* Set up the frame pointer, if we're using one. */
4059 if (frame_pointer_needed
)
4061 insn
= gen_add3_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
,
4062 GEN_INT (frame
->hard_frame_pointer_offset
- size
));
4063 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4065 riscv_emit_stack_tie ();
4068 /* Allocate the rest of the frame. */
4071 if (SMALL_OPERAND (-size
))
4073 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4075 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
4079 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), GEN_INT (-size
));
4080 emit_insn (gen_add3_insn (stack_pointer_rtx
,
4082 RISCV_PROLOGUE_TEMP (Pmode
)));
4084 /* Describe the effect of the previous instructions. */
4085 insn
= plus_constant (Pmode
, stack_pointer_rtx
, -size
);
4086 insn
= gen_rtx_SET (stack_pointer_rtx
, insn
);
4087 riscv_set_frame_expr (insn
);
4093 riscv_adjust_libcall_cfi_epilogue ()
4095 rtx dwarf
= NULL_RTX
;
4096 rtx adjust_sp_rtx
, reg
;
4097 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
4099 /* Debug info for adjust sp. */
4100 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
4101 stack_pointer_rtx
, GEN_INT (saved_size
));
4102 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
4105 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4106 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
4108 reg
= gen_rtx_REG (SImode
, regno
);
4109 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
4115 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
4116 style says which. */
4119 riscv_expand_epilogue (int style
)
4121 /* Split the frame into two. STEP1 is the amount of stack we should
4122 deallocate before restoring the registers. STEP2 is the amount we
4123 should deallocate afterwards.
4125 Start off by assuming that no registers need to be restored. */
4126 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
4127 unsigned mask
= frame
->mask
;
4128 HOST_WIDE_INT step1
= frame
->total_size
;
4129 HOST_WIDE_INT step2
= 0;
4130 bool use_restore_libcall
= ((style
== NORMAL_RETURN
)
4131 && riscv_use_save_libcall (frame
));
4132 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4135 /* We need to add memory barrier to prevent read from deallocated stack. */
4136 bool need_barrier_p
= (get_frame_size ()
4137 + cfun
->machine
->frame
.arg_pointer_offset
) != 0;
4139 if (cfun
->machine
->naked_p
)
4141 gcc_assert (style
== NORMAL_RETURN
);
4143 emit_jump_insn (gen_return ());
4148 if ((style
== NORMAL_RETURN
) && riscv_can_use_return_insn ())
4150 emit_jump_insn (gen_return ());
4154 /* Reset the epilogue cfa info before starting to emit the epilogue. */
4155 epilogue_cfa_sp_offset
= 0;
4157 /* Move past any dynamic stack allocations. */
4158 if (cfun
->calls_alloca
)
4160 /* Emit a barrier to prevent loads from a deallocated stack. */
4161 riscv_emit_stack_tie ();
4162 need_barrier_p
= false;
4164 rtx adjust
= GEN_INT (-frame
->hard_frame_pointer_offset
);
4165 if (!SMALL_OPERAND (INTVAL (adjust
)))
4167 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4168 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4172 gen_add3_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
,
4175 rtx dwarf
= NULL_RTX
;
4176 rtx cfa_adjust_value
= gen_rtx_PLUS (
4177 Pmode
, hard_frame_pointer_rtx
,
4178 GEN_INT (-frame
->hard_frame_pointer_offset
));
4179 rtx cfa_adjust_rtx
= gen_rtx_SET (stack_pointer_rtx
, cfa_adjust_value
);
4180 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, cfa_adjust_rtx
, dwarf
);
4181 RTX_FRAME_RELATED_P (insn
) = 1;
4183 REG_NOTES (insn
) = dwarf
;
4186 /* If we need to restore registers, deallocate as much stack as
4187 possible in the second step without going out of range. */
4188 if ((frame
->mask
| frame
->fmask
) != 0)
4190 step2
= riscv_first_stack_step (frame
);
4194 /* Set TARGET to BASE + STEP1. */
4197 /* Emit a barrier to prevent loads from a deallocated stack. */
4198 riscv_emit_stack_tie ();
4199 need_barrier_p
= false;
4201 /* Get an rtx for STEP1 that we can add to BASE. */
4202 rtx adjust
= GEN_INT (step1
);
4203 if (!SMALL_OPERAND (step1
))
4205 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
4206 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
4210 gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
, adjust
));
4212 rtx dwarf
= NULL_RTX
;
4213 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4216 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4217 RTX_FRAME_RELATED_P (insn
) = 1;
4219 REG_NOTES (insn
) = dwarf
;
4221 else if (frame_pointer_needed
)
4223 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
4225 epilogue_cfa_sp_offset
= step2
;
4228 if (use_restore_libcall
)
4229 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
4231 /* Restore the registers. */
4232 riscv_for_each_saved_reg (frame
->total_size
- step2
, riscv_restore_reg
,
4233 true, style
== EXCEPTION_RETURN
);
4235 if (use_restore_libcall
)
4237 frame
->mask
= mask
; /* Undo the above fib. */
4238 gcc_assert (step2
>= frame
->save_libcall_adjustment
);
4239 step2
-= frame
->save_libcall_adjustment
;
4243 riscv_emit_stack_tie ();
4245 /* Deallocate the final bit of the frame. */
4248 insn
= emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4251 rtx dwarf
= NULL_RTX
;
4252 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4254 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
4255 RTX_FRAME_RELATED_P (insn
) = 1;
4257 REG_NOTES (insn
) = dwarf
;
4260 if (use_restore_libcall
)
4262 rtx dwarf
= riscv_adjust_libcall_cfi_epilogue ();
4263 insn
= emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask
))));
4264 RTX_FRAME_RELATED_P (insn
) = 1;
4265 REG_NOTES (insn
) = dwarf
;
4267 emit_jump_insn (gen_gpr_restore_return (ra
));
4271 /* Add in the __builtin_eh_return stack adjustment. */
4272 if ((style
== EXCEPTION_RETURN
) && crtl
->calls_eh_return
)
4273 emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
4274 EH_RETURN_STACKADJ_RTX
));
4276 /* Return from interrupt. */
4277 if (cfun
->machine
->interrupt_handler_p
)
4279 enum riscv_privilege_levels mode
= cfun
->machine
->interrupt_mode
;
4281 gcc_assert (mode
!= UNKNOWN_MODE
);
4283 if (mode
== MACHINE_MODE
)
4284 emit_jump_insn (gen_riscv_mret ());
4285 else if (mode
== SUPERVISOR_MODE
)
4286 emit_jump_insn (gen_riscv_sret ());
4288 emit_jump_insn (gen_riscv_uret ());
4290 else if (style
!= SIBCALL_RETURN
)
4291 emit_jump_insn (gen_simple_return_internal (ra
));
4294 /* Implement EPILOGUE_USES. */
4297 riscv_epilogue_uses (unsigned int regno
)
4299 if (regno
== RETURN_ADDR_REGNUM
)
4302 if (epilogue_completed
&& cfun
->machine
->interrupt_handler_p
)
4304 /* An interrupt function restores temp regs, so we must indicate that
4305 they are live at function end. */
4306 if (df_regs_ever_live_p (regno
)
4307 || (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
)))
4314 /* Return nonzero if this function is known to have a null epilogue.
4315 This allows the optimizer to omit jumps to jumps if no stack
4319 riscv_can_use_return_insn (void)
4321 return (reload_completed
&& cfun
->machine
->frame
.total_size
== 0
4322 && ! cfun
->machine
->interrupt_handler_p
);
4325 /* Given that there exists at least one variable that is set (produced)
4326 by OUT_INSN and read (consumed) by IN_INSN, return true iff
4327 IN_INSN represents one or more memory store operations and none of
4328 the variables set by OUT_INSN is used by IN_INSN as the address of a
4329 store operation. If either IN_INSN or OUT_INSN does not represent
4330 a "single" RTL SET expression (as loosely defined by the
4331 implementation of the single_set function) or a PARALLEL with only
4332 SETs, CLOBBERs, and USEs inside, this function returns false.
4334 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
4335 conditions that result in assertion failures in the generic
4336 store_data_bypass_p function and returns FALSE in such cases.
4338 This is required to make -msave-restore work with the sifive-7
4339 pipeline description. */
4342 riscv_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
4344 rtx out_set
, in_set
;
4345 rtx out_pat
, in_pat
;
4346 rtx out_exp
, in_exp
;
4349 in_set
= single_set (in_insn
);
4352 if (MEM_P (SET_DEST (in_set
)))
4354 out_set
= single_set (out_insn
);
4357 out_pat
= PATTERN (out_insn
);
4358 if (GET_CODE (out_pat
) == PARALLEL
)
4360 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
4362 out_exp
= XVECEXP (out_pat
, 0, i
);
4363 if ((GET_CODE (out_exp
) == CLOBBER
)
4364 || (GET_CODE (out_exp
) == USE
))
4366 else if (GET_CODE (out_exp
) != SET
)
4375 in_pat
= PATTERN (in_insn
);
4376 if (GET_CODE (in_pat
) != PARALLEL
)
4379 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
4381 in_exp
= XVECEXP (in_pat
, 0, i
);
4382 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
4384 else if (GET_CODE (in_exp
) != SET
)
4387 if (MEM_P (SET_DEST (in_exp
)))
4389 out_set
= single_set (out_insn
);
4392 out_pat
= PATTERN (out_insn
);
4393 if (GET_CODE (out_pat
) != PARALLEL
)
4395 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
4397 out_exp
= XVECEXP (out_pat
, 0, j
);
4398 if ((GET_CODE (out_exp
) == CLOBBER
)
4399 || (GET_CODE (out_exp
) == USE
))
4401 else if (GET_CODE (out_exp
) != SET
)
4409 return store_data_bypass_p (out_insn
, in_insn
);
4412 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4414 When floating-point registers are wider than integer ones, moves between
4415 them must go through memory. */
4418 riscv_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
4421 return (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4422 && (class1
== FP_REGS
) != (class2
== FP_REGS
));
4425 /* Implement TARGET_REGISTER_MOVE_COST. */
4428 riscv_register_move_cost (machine_mode mode
,
4429 reg_class_t from
, reg_class_t to
)
4431 return riscv_secondary_memory_needed (mode
, from
, to
) ? 8 : 2;
4434 /* Implement TARGET_HARD_REGNO_NREGS. */
4437 riscv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
4439 if (FP_REG_P (regno
))
4440 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_REG
- 1) / UNITS_PER_FP_REG
;
4442 /* All other registers are word-sized. */
4443 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4446 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4449 riscv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4451 unsigned int nregs
= riscv_hard_regno_nregs (regno
, mode
);
4453 if (GP_REG_P (regno
))
4455 if (!GP_REG_P (regno
+ nregs
- 1))
4458 else if (FP_REG_P (regno
))
4460 if (!FP_REG_P (regno
+ nregs
- 1))
4463 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4464 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4467 /* Only use callee-saved registers if a potential callee is guaranteed
4468 to spill the requisite width. */
4469 if (GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_REG
4470 || (!call_used_or_fixed_reg_p (regno
)
4471 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_ARG
))
4477 /* Require same callee-savedness for all registers. */
4478 for (unsigned i
= 1; i
< nregs
; i
++)
4479 if (call_used_or_fixed_reg_p (regno
)
4480 != call_used_or_fixed_reg_p (regno
+ i
))
4486 /* Implement TARGET_MODES_TIEABLE_P.
4488 Don't allow floating-point modes to be tied, since type punning of
4489 single-precision and double-precision is implementation defined. */
4492 riscv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4494 return (mode1
== mode2
4495 || !(GET_MODE_CLASS (mode1
) == MODE_FLOAT
4496 && GET_MODE_CLASS (mode2
) == MODE_FLOAT
));
4499 /* Implement CLASS_MAX_NREGS. */
4501 static unsigned char
4502 riscv_class_max_nregs (reg_class_t rclass
, machine_mode mode
)
4504 if (reg_class_subset_p (FP_REGS
, rclass
))
4505 return riscv_hard_regno_nregs (FP_REG_FIRST
, mode
);
4507 if (reg_class_subset_p (GR_REGS
, rclass
))
4508 return riscv_hard_regno_nregs (GP_REG_FIRST
, mode
);
4513 /* Implement TARGET_MEMORY_MOVE_COST. */
4516 riscv_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
4518 return (tune_info
->memory_cost
4519 + memory_move_secondary_cost (mode
, rclass
, in
));
4522 /* Return the number of instructions that can be issued per cycle. */
4525 riscv_issue_rate (void)
4527 return tune_info
->issue_rate
;
4530 /* Auxiliary function to emit RISC-V ELF attribute. */
4532 riscv_emit_attribute ()
4534 fprintf (asm_out_file
, "\t.attribute arch, \"%s\"\n",
4535 riscv_arch_str ().c_str ());
4537 fprintf (asm_out_file
, "\t.attribute unaligned_access, %d\n",
4538 TARGET_STRICT_ALIGN
? 0 : 1);
4540 fprintf (asm_out_file
, "\t.attribute stack_align, %d\n",
4541 riscv_stack_boundary
/ 8);
4544 /* Implement TARGET_ASM_FILE_START. */
4547 riscv_file_start (void)
4549 default_file_start ();
4551 /* Instruct GAS to generate position-[in]dependent code. */
4552 fprintf (asm_out_file
, "\t.option %spic\n", (flag_pic
? "" : "no"));
4554 /* If the user specifies "-mno-relax" on the command line then disable linker
4555 relaxation in the assembler. */
4557 fprintf (asm_out_file
, "\t.option norelax\n");
4559 if (riscv_emit_attribute_p
)
4560 riscv_emit_attribute ();
4563 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4564 in order to avoid duplicating too much logic from elsewhere. */
4567 riscv_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
4568 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4571 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
4572 rtx this_rtx
, temp1
, temp2
, fnaddr
;
4575 /* Pretend to be a post-reload pass while generating rtl. */
4576 reload_completed
= 1;
4578 /* Mark the end of the (empty) prologue. */
4579 emit_note (NOTE_INSN_PROLOGUE_END
);
4581 /* Determine if we can use a sibcall to call FUNCTION directly. */
4582 fnaddr
= gen_rtx_MEM (FUNCTION_MODE
, XEXP (DECL_RTL (function
), 0));
4584 /* We need two temporary registers in some cases. */
4585 temp1
= gen_rtx_REG (Pmode
, RISCV_PROLOGUE_TEMP_REGNUM
);
4586 temp2
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
4588 /* Find out which register contains the "this" pointer. */
4589 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
4590 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
4592 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
4594 /* Add DELTA to THIS_RTX. */
4597 rtx offset
= GEN_INT (delta
);
4598 if (!SMALL_OPERAND (delta
))
4600 riscv_emit_move (temp1
, offset
);
4603 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
4606 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4607 if (vcall_offset
!= 0)
4611 /* Set TEMP1 to *THIS_RTX. */
4612 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
4614 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4615 addr
= riscv_add_offset (temp2
, temp1
, vcall_offset
);
4617 /* Load the offset and add it to THIS_RTX. */
4618 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
4619 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
4622 /* Jump to the target function. */
4623 insn
= emit_call_insn (gen_sibcall (fnaddr
, const0_rtx
, NULL
, const0_rtx
));
4624 SIBLING_CALL_P (insn
) = 1;
4626 /* Run just enough of rest_of_compilation. This sequence was
4627 "borrowed" from alpha.c. */
4628 insn
= get_insns ();
4629 split_all_insns_noflow ();
4630 shorten_branches (insn
);
4631 assemble_start_function (thunk_fndecl
, fnname
);
4632 final_start_function (insn
, file
, 1);
4633 final (insn
, file
, 1);
4634 final_end_function ();
4635 assemble_end_function (thunk_fndecl
, fnname
);
4637 /* Clean up the vars set above. Note that final_end_function resets
4638 the global pointer for us. */
4639 reload_completed
= 0;
4642 /* Allocate a chunk of memory for per-function machine-dependent data. */
4644 static struct machine_function
*
4645 riscv_init_machine_status (void)
4647 return ggc_cleared_alloc
<machine_function
> ();
4650 /* Implement TARGET_OPTION_OVERRIDE. */
4653 riscv_option_override (void)
4655 const struct riscv_cpu_info
*cpu
;
4657 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4658 SUBTARGET_OVERRIDE_OPTIONS
;
4661 flag_pcc_struct_return
= 0;
4666 /* The presence of the M extension implies that division instructions
4667 are present, so include them unless explicitly disabled. */
4668 if (TARGET_MUL
&& (target_flags_explicit
& MASK_DIV
) == 0)
4669 target_flags
|= MASK_DIV
;
4670 else if (!TARGET_MUL
&& TARGET_DIV
)
4671 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
4673 /* Likewise floating-point division and square root. */
4674 if (TARGET_HARD_FLOAT
&& (target_flags_explicit
& MASK_FDIV
) == 0)
4675 target_flags
|= MASK_FDIV
;
4677 /* Handle -mtune. */
4678 cpu
= riscv_parse_cpu (riscv_tune_string
? riscv_tune_string
:
4679 RISCV_TUNE_STRING_DEFAULT
);
4680 riscv_microarchitecture
= cpu
->microarchitecture
;
4681 tune_info
= optimize_size
? &optimize_size_tune_info
: cpu
->tune_info
;
4683 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
4684 for size. For architectures that trap and emulate unaligned accesses,
4685 the performance cost is too great, even for -Os. Similarly, if
4686 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
4687 riscv_slow_unaligned_access_p
= (cpu
->tune_info
->slow_unaligned_access
4688 || TARGET_STRICT_ALIGN
);
4689 if ((target_flags_explicit
& MASK_STRICT_ALIGN
) == 0
4690 && cpu
->tune_info
->slow_unaligned_access
)
4691 target_flags
|= MASK_STRICT_ALIGN
;
4693 /* If the user hasn't specified a branch cost, use the processor's
4695 if (riscv_branch_cost
== 0)
4696 riscv_branch_cost
= tune_info
->branch_cost
;
4698 /* Function to allocate machine-dependent function status. */
4699 init_machine_status
= &riscv_init_machine_status
;
4702 riscv_cmodel
= CM_PIC
;
4704 /* We get better code with explicit relocs for CM_MEDLOW, but
4705 worse code for the others (for now). Pick the best default. */
4706 if ((target_flags_explicit
& MASK_EXPLICIT_RELOCS
) == 0)
4707 if (riscv_cmodel
== CM_MEDLOW
)
4708 target_flags
|= MASK_EXPLICIT_RELOCS
;
4710 /* Require that the ISA supports the requested floating-point ABI. */
4711 if (UNITS_PER_FP_ARG
> (TARGET_HARD_FLOAT
? UNITS_PER_FP_REG
: 0))
4712 error ("requested ABI requires %<-march%> to subsume the %qc extension",
4713 UNITS_PER_FP_ARG
> 8 ? 'Q' : (UNITS_PER_FP_ARG
> 4 ? 'D' : 'F'));
4715 if (TARGET_RVE
&& riscv_abi
!= ABI_ILP32E
)
4716 error ("rv32e requires ilp32e ABI");
4718 /* We do not yet support ILP32 on RV64. */
4719 if (BITS_PER_WORD
!= POINTER_SIZE
)
4720 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE
);
4722 /* Validate -mpreferred-stack-boundary= value. */
4723 riscv_stack_boundary
= ABI_STACK_BOUNDARY
;
4724 if (riscv_preferred_stack_boundary_arg
)
4726 int min
= ctz_hwi (STACK_BOUNDARY
/ 8);
4729 if (!IN_RANGE (riscv_preferred_stack_boundary_arg
, min
, max
))
4730 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d",
4731 riscv_preferred_stack_boundary_arg
, min
, max
);
4733 riscv_stack_boundary
= 8 << riscv_preferred_stack_boundary_arg
;
4736 if (riscv_emit_attribute_p
< 0)
4737 #ifdef HAVE_AS_RISCV_ATTRIBUTE
4738 riscv_emit_attribute_p
= TARGET_RISCV_ATTRIBUTE
;
4740 riscv_emit_attribute_p
= 0;
4742 if (riscv_emit_attribute_p
)
4743 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"
4744 " [%<-mriscv-attribute%>]");
4749 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4752 riscv_conditional_register_usage (void)
4754 /* We have only x0~x15 on RV32E. */
4757 for (int r
= 16; r
<= 31; r
++)
4761 if (riscv_abi
== ABI_ILP32E
)
4763 for (int r
= 16; r
<= 31; r
++)
4764 call_used_regs
[r
] = 1;
4767 if (!TARGET_HARD_FLOAT
)
4769 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4770 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4773 /* In the soft-float ABI, there are no callee-saved FP registers. */
4774 if (UNITS_PER_FP_ARG
== 0)
4776 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4777 call_used_regs
[regno
] = 1;
4781 /* Return a register priority for hard reg REGNO. */
4784 riscv_register_priority (int regno
)
4786 /* Favor compressed registers to improve the odds of RVC instruction
4788 if (riscv_compressed_reg_p (regno
))
4794 /* Implement TARGET_TRAMPOLINE_INIT. */
4797 riscv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4799 rtx addr
, end_addr
, mem
;
4800 uint32_t trampoline
[4];
4802 HOST_WIDE_INT static_chain_offset
, target_function_offset
;
4804 /* Work out the offsets of the pointers from the start of the
4806 gcc_assert (ARRAY_SIZE (trampoline
) * 4 == TRAMPOLINE_CODE_SIZE
);
4808 /* Get pointers to the beginning and end of the code block. */
4809 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
4810 end_addr
= riscv_force_binary (Pmode
, PLUS
, addr
,
4811 GEN_INT (TRAMPOLINE_CODE_SIZE
));
4814 if (Pmode
== SImode
)
4816 chain_value
= force_reg (Pmode
, chain_value
);
4818 rtx target_function
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
4819 /* lui t2, hi(chain)
4821 addi t2, t2, lo(chain)
4824 unsigned HOST_WIDE_INT lui_hi_chain_code
, lui_hi_func_code
;
4825 unsigned HOST_WIDE_INT lo_chain_code
, lo_func_code
;
4827 rtx uimm_mask
= force_reg (SImode
, gen_int_mode (-IMM_REACH
, SImode
));
4830 rtx imm12_mask
= gen_reg_rtx (SImode
);
4831 emit_insn (gen_one_cmplsi2 (imm12_mask
, uimm_mask
));
4833 rtx fixup_value
= force_reg (SImode
, gen_int_mode (IMM_REACH
/2, SImode
));
4835 /* Gen lui t2, hi(chain). */
4836 rtx hi_chain
= riscv_force_binary (SImode
, PLUS
, chain_value
,
4838 hi_chain
= riscv_force_binary (SImode
, AND
, hi_chain
,
4840 lui_hi_chain_code
= OPCODE_LUI
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4841 rtx lui_hi_chain
= riscv_force_binary (SImode
, IOR
, hi_chain
,
4842 gen_int_mode (lui_hi_chain_code
, SImode
));
4844 mem
= adjust_address (m_tramp
, SImode
, 0);
4845 riscv_emit_move (mem
, lui_hi_chain
);
4847 /* Gen lui t1, hi(func). */
4848 rtx hi_func
= riscv_force_binary (SImode
, PLUS
, target_function
,
4850 hi_func
= riscv_force_binary (SImode
, AND
, hi_func
,
4852 lui_hi_func_code
= OPCODE_LUI
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
);
4853 rtx lui_hi_func
= riscv_force_binary (SImode
, IOR
, hi_func
,
4854 gen_int_mode (lui_hi_func_code
, SImode
));
4856 mem
= adjust_address (m_tramp
, SImode
, 1 * GET_MODE_SIZE (SImode
));
4857 riscv_emit_move (mem
, lui_hi_func
);
4859 /* Gen addi t2, t2, lo(chain). */
4860 rtx lo_chain
= riscv_force_binary (SImode
, AND
, chain_value
,
4862 lo_chain
= riscv_force_binary (SImode
, ASHIFT
, lo_chain
, GEN_INT (20));
4864 lo_chain_code
= OPCODE_ADDI
4865 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4866 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
);
4868 rtx addi_lo_chain
= riscv_force_binary (SImode
, IOR
, lo_chain
,
4869 force_reg (SImode
, GEN_INT (lo_chain_code
)));
4871 mem
= adjust_address (m_tramp
, SImode
, 2 * GET_MODE_SIZE (SImode
));
4872 riscv_emit_move (mem
, addi_lo_chain
);
4874 /* Gen jr r1, lo(func). */
4875 rtx lo_func
= riscv_force_binary (SImode
, AND
, target_function
,
4877 lo_func
= riscv_force_binary (SImode
, ASHIFT
, lo_func
, GEN_INT (20));
4879 lo_func_code
= OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4881 rtx jr_lo_func
= riscv_force_binary (SImode
, IOR
, lo_func
,
4882 force_reg (SImode
, GEN_INT (lo_func_code
)));
4884 mem
= adjust_address (m_tramp
, SImode
, 3 * GET_MODE_SIZE (SImode
));
4885 riscv_emit_move (mem
, jr_lo_func
);
4889 static_chain_offset
= TRAMPOLINE_CODE_SIZE
;
4890 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
4893 l[wd] t1, target_function_offset(t2)
4894 l[wd] t2, static_chain_offset(t2)
4897 trampoline
[0] = OPCODE_AUIPC
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4898 trampoline
[1] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4899 | (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
)
4900 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4901 | (target_function_offset
<< SHIFT_IMM
);
4902 trampoline
[2] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4903 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4904 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4905 | (static_chain_offset
<< SHIFT_IMM
);
4906 trampoline
[3] = OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4908 /* Copy the trampoline code. */
4909 for (i
= 0; i
< ARRAY_SIZE (trampoline
); i
++)
4911 mem
= adjust_address (m_tramp
, SImode
, i
* GET_MODE_SIZE (SImode
));
4912 riscv_emit_move (mem
, gen_int_mode (trampoline
[i
], SImode
));
4915 /* Set up the static chain pointer field. */
4916 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
4917 riscv_emit_move (mem
, chain_value
);
4919 /* Set up the target function field. */
4920 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
4921 riscv_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
4924 /* Flush the code part of the trampoline. */
4925 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
4926 emit_insn (gen_clear_cache (addr
, end_addr
));
4929 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
4932 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
4933 tree exp ATTRIBUTE_UNUSED
)
4935 /* Don't use sibcalls when use save-restore routine. */
4936 if (TARGET_SAVE_RESTORE
)
4939 /* Don't use sibcall for naked functions. */
4940 if (cfun
->machine
->naked_p
)
4943 /* Don't use sibcall for interrupt functions. */
4944 if (cfun
->machine
->interrupt_handler_p
)
4950 /* Get the interrupt type, return UNKNOWN_MODE if it's not
4951 interrupt function. */
4952 static enum riscv_privilege_levels
4953 riscv_get_interrupt_type (tree decl
)
4955 gcc_assert (decl
!= NULL_TREE
);
4957 if ((TREE_CODE(decl
) != FUNCTION_DECL
)
4958 || (!riscv_interrupt_type_p (TREE_TYPE (decl
))))
4959 return UNKNOWN_MODE
;
4962 = TREE_VALUE (lookup_attribute ("interrupt",
4963 TYPE_ATTRIBUTES (TREE_TYPE (decl
))));
4965 if (attr_args
&& TREE_CODE (TREE_VALUE (attr_args
)) != VOID_TYPE
)
4967 const char *string
= TREE_STRING_POINTER (TREE_VALUE (attr_args
));
4969 if (!strcmp (string
, "user"))
4971 else if (!strcmp (string
, "supervisor"))
4972 return SUPERVISOR_MODE
;
4973 else /* Must be "machine". */
4974 return MACHINE_MODE
;
4977 /* Interrupt attributes are machine mode by default. */
4978 return MACHINE_MODE
;
4981 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
4982 /* Sanity cheching for above function attributes. */
4984 riscv_set_current_function (tree decl
)
4986 if (decl
== NULL_TREE
4987 || current_function_decl
== NULL_TREE
4988 || current_function_decl
== error_mark_node
4990 || cfun
->machine
->attributes_checked_p
)
4993 cfun
->machine
->naked_p
= riscv_naked_function_p (decl
);
4994 cfun
->machine
->interrupt_handler_p
4995 = riscv_interrupt_type_p (TREE_TYPE (decl
));
4997 if (cfun
->machine
->naked_p
&& cfun
->machine
->interrupt_handler_p
)
4998 error ("function attributes %qs and %qs are mutually exclusive",
4999 "interrupt", "naked");
5001 if (cfun
->machine
->interrupt_handler_p
)
5003 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
5004 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
5006 if (TREE_CODE (ret
) != VOID_TYPE
)
5007 error ("%qs function cannot return a value", "interrupt");
5009 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
5010 error ("%qs function cannot have arguments", "interrupt");
5012 cfun
->machine
->interrupt_mode
= riscv_get_interrupt_type (decl
);
5014 gcc_assert (cfun
->machine
->interrupt_mode
!= UNKNOWN_MODE
);
5017 /* Don't print the above diagnostics more than once. */
5018 cfun
->machine
->attributes_checked_p
= 1;
5021 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
5023 riscv_merge_decl_attributes (tree olddecl
, tree newdecl
)
5025 tree combined_attrs
;
5027 enum riscv_privilege_levels old_interrupt_type
5028 = riscv_get_interrupt_type (olddecl
);
5029 enum riscv_privilege_levels new_interrupt_type
5030 = riscv_get_interrupt_type (newdecl
);
5032 /* Check old and new has same interrupt type. */
5033 if ((old_interrupt_type
!= UNKNOWN_MODE
)
5034 && (new_interrupt_type
!= UNKNOWN_MODE
)
5035 && (old_interrupt_type
!= new_interrupt_type
))
5036 error ("%qs function cannot have different interrupt type", "interrupt");
5038 /* Create combined attributes. */
5039 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
5040 DECL_ATTRIBUTES (newdecl
));
5042 return combined_attrs
;
5045 /* Implement TARGET_CANNOT_COPY_INSN_P. */
5048 riscv_cannot_copy_insn_p (rtx_insn
*insn
)
5050 return recog_memoized (insn
) >= 0 && get_attr_cannot_copy (insn
);
5053 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
5056 riscv_slow_unaligned_access (machine_mode
, unsigned int)
5058 return riscv_slow_unaligned_access_p
;
5061 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
5064 riscv_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t rclass
)
5066 return !reg_classes_intersect_p (FP_REGS
, rclass
);
5070 /* Implement TARGET_CONSTANT_ALIGNMENT. */
5072 static HOST_WIDE_INT
5073 riscv_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
5075 if ((TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
5076 && (riscv_align_data_type
== riscv_align_data_type_xlen
))
5077 return MAX (align
, BITS_PER_WORD
);
5081 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
5083 /* This function is equivalent to default_promote_function_mode_always_promote
5084 except that it returns a promoted mode even if type is NULL_TREE. This is
5085 needed by libcalls which have no type (only a mode) such as fixed conversion
5086 routines that take a signed or unsigned char/short/int argument and convert
5087 it to a fixed type. */
5090 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
5092 int *punsignedp ATTRIBUTE_UNUSED
,
5093 const_tree fntype ATTRIBUTE_UNUSED
,
5094 int for_return ATTRIBUTE_UNUSED
)
5098 if (type
!= NULL_TREE
)
5099 return promote_mode (type
, mode
, punsignedp
);
5101 unsignedp
= *punsignedp
;
5102 PROMOTE_MODE (mode
, unsignedp
, type
);
5103 *punsignedp
= unsignedp
;
5107 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
5112 /* Do nothing unless we have -msave-restore */
5113 if (TARGET_SAVE_RESTORE
)
5114 riscv_remove_unneeded_save_restore_calls ();
5117 /* Return nonzero if register FROM_REGNO can be renamed to register
5121 riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED
,
5124 /* Interrupt functions can only use registers that have already been
5125 saved by the prologue, even if they would normally be
5127 return !cfun
->machine
->interrupt_handler_p
|| df_regs_ever_live_p (to_regno
);
5130 /* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */
5133 riscv_new_address_profitable_p (rtx memref
, rtx_insn
*insn
, rtx new_addr
)
5135 /* Prefer old address if it is less expensive. */
5136 addr_space_t as
= MEM_ADDR_SPACE (memref
);
5137 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
5138 int old_cost
= address_cost (XEXP (memref
, 0), GET_MODE (memref
), as
, speed
);
5139 int new_cost
= address_cost (new_addr
, GET_MODE (memref
), as
, speed
);
5140 return new_cost
<= old_cost
;
5143 /* Initialize the GCC target structure. */
5144 #undef TARGET_ASM_ALIGNED_HI_OP
5145 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
5146 #undef TARGET_ASM_ALIGNED_SI_OP
5147 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
5148 #undef TARGET_ASM_ALIGNED_DI_OP
5149 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
5151 #undef TARGET_OPTION_OVERRIDE
5152 #define TARGET_OPTION_OVERRIDE riscv_option_override
5154 #undef TARGET_LEGITIMIZE_ADDRESS
5155 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
5157 #undef TARGET_SCHED_ISSUE_RATE
5158 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
5160 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5161 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
5163 #undef TARGET_SET_CURRENT_FUNCTION
5164 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
5166 #undef TARGET_REGISTER_MOVE_COST
5167 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
5168 #undef TARGET_MEMORY_MOVE_COST
5169 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
5170 #undef TARGET_RTX_COSTS
5171 #define TARGET_RTX_COSTS riscv_rtx_costs
5172 #undef TARGET_ADDRESS_COST
5173 #define TARGET_ADDRESS_COST riscv_address_cost
5175 #undef TARGET_ASM_FILE_START
5176 #define TARGET_ASM_FILE_START riscv_file_start
5177 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5178 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5180 #undef TARGET_EXPAND_BUILTIN_VA_START
5181 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
5183 #undef TARGET_PROMOTE_FUNCTION_MODE
5184 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
5186 #undef TARGET_RETURN_IN_MEMORY
5187 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
5189 #undef TARGET_ASM_OUTPUT_MI_THUNK
5190 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
5191 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5192 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5194 #undef TARGET_PRINT_OPERAND
5195 #define TARGET_PRINT_OPERAND riscv_print_operand
5196 #undef TARGET_PRINT_OPERAND_ADDRESS
5197 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
5199 #undef TARGET_SETUP_INCOMING_VARARGS
5200 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
5201 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
5202 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
5203 #undef TARGET_STRICT_ARGUMENT_NAMING
5204 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
5205 #undef TARGET_MUST_PASS_IN_STACK
5206 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
5207 #undef TARGET_PASS_BY_REFERENCE
5208 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
5209 #undef TARGET_ARG_PARTIAL_BYTES
5210 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
5211 #undef TARGET_FUNCTION_ARG
5212 #define TARGET_FUNCTION_ARG riscv_function_arg
5213 #undef TARGET_FUNCTION_ARG_ADVANCE
5214 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
5215 #undef TARGET_FUNCTION_ARG_BOUNDARY
5216 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
5218 /* The generic ELF target does not always have TLS support. */
5220 #undef TARGET_HAVE_TLS
5221 #define TARGET_HAVE_TLS true
5224 #undef TARGET_CANNOT_FORCE_CONST_MEM
5225 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
5227 #undef TARGET_LEGITIMATE_CONSTANT_P
5228 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
5230 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5231 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
5233 #undef TARGET_LEGITIMATE_ADDRESS_P
5234 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
5236 #undef TARGET_CAN_ELIMINATE
5237 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
5239 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5240 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
5242 #undef TARGET_CLASS_MAX_NREGS
5243 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
5245 #undef TARGET_TRAMPOLINE_INIT
5246 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
5248 #undef TARGET_IN_SMALL_DATA_P
5249 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
5251 #undef TARGET_HAVE_SRODATA_SECTION
5252 #define TARGET_HAVE_SRODATA_SECTION true
5254 #undef TARGET_ASM_SELECT_SECTION
5255 #define TARGET_ASM_SELECT_SECTION riscv_select_section
5257 #undef TARGET_ASM_SELECT_RTX_SECTION
5258 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
5260 #undef TARGET_MIN_ANCHOR_OFFSET
5261 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
5263 #undef TARGET_MAX_ANCHOR_OFFSET
5264 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
5266 #undef TARGET_REGISTER_PRIORITY
5267 #define TARGET_REGISTER_PRIORITY riscv_register_priority
5269 #undef TARGET_CANNOT_COPY_INSN_P
5270 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
5272 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
5273 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
5275 #undef TARGET_INIT_BUILTINS
5276 #define TARGET_INIT_BUILTINS riscv_init_builtins
5278 #undef TARGET_BUILTIN_DECL
5279 #define TARGET_BUILTIN_DECL riscv_builtin_decl
5281 #undef TARGET_EXPAND_BUILTIN
5282 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
5284 #undef TARGET_HARD_REGNO_NREGS
5285 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
5286 #undef TARGET_HARD_REGNO_MODE_OK
5287 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
5289 #undef TARGET_MODES_TIEABLE_P
5290 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
5292 #undef TARGET_SLOW_UNALIGNED_ACCESS
5293 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
5295 #undef TARGET_SECONDARY_MEMORY_NEEDED
5296 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
5298 #undef TARGET_CAN_CHANGE_MODE_CLASS
5299 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
5301 #undef TARGET_CONSTANT_ALIGNMENT
5302 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
5304 #undef TARGET_MERGE_DECL_ATTRIBUTES
5305 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
5307 #undef TARGET_ATTRIBUTE_TABLE
5308 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
5310 #undef TARGET_WARN_FUNC_RETURN
5311 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
5313 /* The low bit is ignored by jump instructions so is safe to use. */
5314 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
5315 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
5317 #undef TARGET_MACHINE_DEPENDENT_REORG
5318 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg
5320 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
5321 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
5323 struct gcc_target targetm
= TARGET_INITIALIZER
;
5325 #include "gt-riscv.h"