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RISC-V: Support load/store in mov<mode> pattern for RVV modes.
[thirdparty/gcc.git] / gcc / config / riscv / riscv.h
1 /* Definition of RISC-V target for GNU compiler.
2 Copyright (C) 2011-2022 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_RISCV_H
23 #define GCC_RISCV_H
24
25 #include "config/riscv/riscv-opts.h"
26
27 /* Target CPU builtins. */
28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
29
30 #ifdef TARGET_BIG_ENDIAN_DEFAULT
31 #define DEFAULT_ENDIAN_SPEC "b"
32 #else
33 #define DEFAULT_ENDIAN_SPEC "l"
34 #endif
35
36 /* Default target_flags if no switches are specified */
37
38 #ifndef TARGET_DEFAULT
39 #define TARGET_DEFAULT 0
40 #endif
41
42 #ifndef RISCV_TUNE_STRING_DEFAULT
43 #define RISCV_TUNE_STRING_DEFAULT "rocket"
44 #endif
45
46 extern const char *riscv_expand_arch (int argc, const char **argv);
47 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
48 extern const char *riscv_default_mtune (int argc, const char **argv);
49 extern const char *riscv_multi_lib_check (int argc, const char **argv);
50
51 # define EXTRA_SPEC_FUNCTIONS \
52 { "riscv_expand_arch", riscv_expand_arch }, \
53 { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \
54 { "riscv_default_mtune", riscv_default_mtune }, \
55 { "riscv_multi_lib_check", riscv_multi_lib_check },
56
57 /* Support for a compile-time default CPU, et cetera. The rules are:
58 --with-arch is ignored if -march or -mcpu is specified.
59 --with-abi is ignored if -mabi is specified.
60 --with-tune is ignored if -mtune or -mcpu is specified.
61 --with-isa-spec is ignored if -misa-spec is specified.
62
63 But using default -march/-mtune value if -mcpu don't have valid option. */
64 #define OPTION_DEFAULT_SPECS \
65 {"tune", "%{!mtune=*:" \
66 " %{!mcpu=*:-mtune=%(VALUE)}" \
67 " %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" }, \
68 {"arch", "%{!march=*:" \
69 " %{!mcpu=*:-march=%(VALUE)}" \
70 " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \
71 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
72 {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
73
74 #ifdef IN_LIBGCC2
75 #undef TARGET_64BIT
76 /* Make this compile time constant for libgcc2 */
77 #define TARGET_64BIT (__riscv_xlen == 64)
78 #endif /* IN_LIBGCC2 */
79
80 #ifdef HAVE_AS_MISA_SPEC
81 #define ASM_MISA_SPEC "%{misa-spec=*}"
82 #else
83 #define ASM_MISA_SPEC ""
84 #endif
85
86 /* Reference:
87 https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing */
88 #define STRINGIZING(s) __STRINGIZING(s)
89 #define __STRINGIZING(s) #s
90
91 #define MULTILIB_DEFAULTS \
92 {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \
93 "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) }
94
95 #undef ASM_SPEC
96 #define ASM_SPEC "\
97 %(subtarget_asm_debugging_spec) \
98 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
99 %{march=*} \
100 %{mabi=*} \
101 %{mno-relax} \
102 %{mbig-endian} \
103 %{mlittle-endian} \
104 %(subtarget_asm_spec)" \
105 ASM_MISA_SPEC
106
107 #undef DRIVER_SELF_SPECS
108 #define DRIVER_SELF_SPECS \
109 "%{march=*:%:riscv_expand_arch(%*)} " \
110 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
111
112 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
113
114 #define LOCAL_LABEL_PREFIX "."
115 #define USER_LABEL_PREFIX ""
116
117 /* Offsets recorded in opcodes are a multiple of this alignment factor.
118 The default for this in 64-bit mode is 8, which causes problems with
119 SFmode register saves. */
120 #define DWARF_CIE_DATA_ALIGNMENT -4
121
122 /* The mapping from gcc register number to DWARF 2 CFA column number. */
123 #define DWARF_FRAME_REGNUM(REGNO) \
124 (VL_REG_P (REGNO) ? RISCV_DWARF_VL \
125 : VTYPE_REG_P (REGNO) \
126 ? RISCV_DWARF_VTYPE \
127 : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) \
128 ? REGNO \
129 : INVALID_REGNUM))
130
131 /* The DWARF 2 CFA column which tracks the return address. */
132 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
133 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
134
135 /* Describe how we implement __builtin_eh_return. */
136 #define EH_RETURN_DATA_REGNO(N) \
137 ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
138
139 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
140
141 /* Target machine storage layout */
142
143 #define BITS_BIG_ENDIAN 0
144 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
145 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
146
147 #define MAX_BITS_PER_WORD 64
148
149 /* Width of a word, in units (bytes). */
150 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
151 #ifndef IN_LIBGCC2
152 #define MIN_UNITS_PER_WORD 4
153 #endif
154
155 /* Allows SImode op in builtin overflow pattern, see internal-fn.cc. */
156 #undef TARGET_MIN_ARITHMETIC_PRECISION
157 #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision
158
159 /* The `Q' extension is not yet supported. */
160 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
161 /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */
162 #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
163
164 /* The largest type that can be passed in floating-point registers. */
165 #define UNITS_PER_FP_ARG \
166 ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \
167 || riscv_abi == ABI_LP64) \
168 ? 0 \
169 : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
170
171 /* Set the sizes of the core types. */
172 #define SHORT_TYPE_SIZE 16
173 #define INT_TYPE_SIZE 32
174 #define LONG_LONG_TYPE_SIZE 64
175 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
176 #define LONG_TYPE_SIZE POINTER_SIZE
177
178 #define FLOAT_TYPE_SIZE 32
179 #define DOUBLE_TYPE_SIZE 64
180 #define LONG_DOUBLE_TYPE_SIZE 128
181
182 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
183 #define PARM_BOUNDARY BITS_PER_WORD
184
185 /* Allocation boundary (in *bits*) for the code of a function. */
186 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
187
188 /* The smallest supported stack boundary the calling convention supports. */
189 #define STACK_BOUNDARY \
190 (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
191
192 /* The ABI stack alignment. */
193 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
194
195 /* There is no point aligning anything to a rounder boundary than this. */
196 #define BIGGEST_ALIGNMENT 128
197
198 /* The user-level ISA permits unaligned accesses, but they are not required
199 of the privileged architecture. */
200 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
201
202 /* Define this if you wish to imitate the way many other C compilers
203 handle alignment of bitfields and the structures that contain
204 them.
205
206 The behavior is that the type written for a bit-field (`int',
207 `short', or other integer type) imposes an alignment for the
208 entire structure, as if the structure really did contain an
209 ordinary field of that type. In addition, the bit-field is placed
210 within the structure so that it would fit within such a field,
211 not crossing a boundary for it.
212
213 Thus, on most machines, a bit-field whose type is written as `int'
214 would not cross a four-byte boundary, and would force four-byte
215 alignment for the whole structure. (The alignment used may not
216 be four bytes; it is controlled by the other alignment
217 parameters.)
218
219 If the macro is defined, its definition should be a C expression;
220 a nonzero value for the expression enables this behavior. */
221
222 #define PCC_BITFIELD_TYPE_MATTERS 1
223
224 /* An integer expression for the size in bits of the largest integer machine
225 mode that should actually be used. We allow pairs of registers. */
226 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
227
228 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */
229 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \
230 (((COND) && ((ALIGN) < BITS_PER_WORD) \
231 && (TREE_CODE (TYPE) == ARRAY_TYPE \
232 || TREE_CODE (TYPE) == UNION_TYPE \
233 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
234
235 /* If defined, a C expression to compute the alignment for a static
236 variable. TYPE is the data type, and ALIGN is the alignment that
237 the object would ordinarily have. The value of this macro is used
238 instead of that alignment to align the object.
239
240 If this macro is not defined, then ALIGN is used.
241
242 One use of this macro is to increase alignment of medium-size
243 data to make it all fit in fewer cache lines. Another is to
244 cause character arrays to be word-aligned so that `strcpy' calls
245 that copy constants to character arrays can be done inline. */
246
247 #define DATA_ALIGNMENT(TYPE, ALIGN) \
248 RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \
249 TYPE, ALIGN)
250
251 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
252 character arrays to be word-aligned so that `strcpy' calls that copy
253 constants to character arrays can be done inline, and 'strcmp' can be
254 optimised to use word loads. */
255 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
256 RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
257
258 /* Define if operations between registers always perform the operation
259 on the full register even if a narrower mode is specified. */
260 #define WORD_REGISTER_OPERATIONS 1
261
262 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
263 moves. All other references are zero extended. */
264 #define LOAD_EXTEND_OP(MODE) \
265 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
266
267 /* Define this macro if it is advisable to hold scalars in registers
268 in a wider mode than that declared by the program. In such cases,
269 the value is constrained to be within the bounds of the declared
270 type, but kept valid in the wider mode. The signedness of the
271 extension may differ from that of the type. */
272
273 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
274 if (GET_MODE_CLASS (MODE) == MODE_INT \
275 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
276 { \
277 if ((MODE) == SImode) \
278 (UNSIGNEDP) = 0; \
279 (MODE) = word_mode; \
280 }
281
282 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
283 Extensions of pointers to word_mode must be signed. */
284 #define POINTERS_EXTEND_UNSIGNED false
285
286 /* Define if loading short immediate values into registers sign extends. */
287 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
288
289 /* Standard register usage. */
290
291 /* Number of hardware registers. We have:
292
293 - 32 integer registers
294 - 32 floating point registers
295 - 2 fake registers:
296 - ARG_POINTER_REGNUM
297 - FRAME_POINTER_REGNUM
298 - 1 vl register
299 - 1 vtype register
300 - 30 unused registers for future expansion
301 - 32 vector registers */
302
303 #define FIRST_PSEUDO_REGISTER 128
304
305 /* x0, sp, gp, and tp are fixed. */
306
307 #define FIXED_REGISTERS \
308 { /* General registers. */ \
309 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
310 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
311 /* Floating-point registers. */ \
312 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
313 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
314 /* Others. */ \
315 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
316 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
317 /* Vector registers. */ \
318 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
319 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
320 }
321
322 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
323 The call RTLs themselves clobber ra. */
324
325 #define CALL_USED_REGISTERS \
326 { /* General registers. */ \
327 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
328 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
329 /* Floating-point registers. */ \
330 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
331 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
332 /* Others. */ \
333 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
334 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
335 /* Vector registers. */ \
336 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
337 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
338 }
339
340 /* Select a register mode required for caller save of hard regno REGNO.
341 Contrary to what is documented, the default is not the smallest suitable
342 mode but the largest suitable mode for the given (REGNO, NREGS) pair and
343 it quickly creates paradoxical subregs that can be problematic. */
344 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
345 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
346
347 /* Internal macros to classify an ISA register's type. */
348
349 #define GP_REG_FIRST 0
350 #define GP_REG_LAST (TARGET_RVE ? 15 : 31)
351 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
352
353 #define FP_REG_FIRST 32
354 #define FP_REG_LAST 63
355 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
356
357 #define V_REG_FIRST 96
358 #define V_REG_LAST 127
359 #define V_REG_NUM (V_REG_LAST - V_REG_FIRST + 1)
360
361 /* The DWARF 2 CFA column which tracks the return address from a
362 signal handler context. This means that to maintain backwards
363 compatibility, no hard register can be assigned this column if it
364 would need to be handled by the DWARF unwinder. */
365 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
366
367 #define GP_REG_P(REGNO) \
368 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
369 #define FP_REG_P(REGNO) \
370 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
371 #define V_REG_P(REGNO) \
372 ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
373 #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
374 #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
375
376 /* True when REGNO is in SIBCALL_REGS set. */
377 #define SIBCALL_REG_P(REGNO) \
378 TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
379
380 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
381
382 /* Use s0 as the frame pointer if it is so requested. */
383 #define HARD_FRAME_POINTER_REGNUM 8
384 #define STACK_POINTER_REGNUM 2
385 #define THREAD_POINTER_REGNUM 4
386
387 /* These two registers don't really exist: they get eliminated to either
388 the stack or hard frame pointer. */
389 #define ARG_POINTER_REGNUM 64
390 #define FRAME_POINTER_REGNUM 65
391
392 /* Define Dwarf for RVV. */
393 #define RISCV_DWARF_VL (4096 + 0xc20)
394 #define RISCV_DWARF_VTYPE (4096 + 0xc21)
395
396 /* Register in which static-chain is passed to a function. */
397 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
398
399 /* Registers used as temporaries in prologue/epilogue code.
400
401 The prologue registers mustn't conflict with any
402 incoming arguments, the static chain pointer, or the frame pointer.
403 The epilogue temporary mustn't conflict with the return registers,
404 the frame pointer, the EH stack adjustment, or the EH data registers. */
405
406 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
407 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
408
409 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
410 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
411 gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
412
413 #define MCOUNT_NAME "_mcount"
414
415 #define NO_PROFILE_COUNTERS 1
416
417 /* Emit rtl for profiling. Output assembler code to FILE
418 to call "_mcount" for profiling a function entry. */
419 #define PROFILE_HOOK(LABEL) \
420 { \
421 rtx fun, ra; \
422 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \
423 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
424 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \
425 }
426
427 /* All the work done in PROFILE_HOOK, but still required. */
428 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
429
430 /* Define this macro if it is as good or better to call a constant
431 function address than to call an address kept in a register. */
432 #define NO_FUNCTION_CSE 1
433
434 /* Define the classes of registers for register constraints in the
435 machine description. Also define ranges of constants.
436
437 One of the classes must always be named ALL_REGS and include all hard regs.
438 If there is more than one class, another class must be named NO_REGS
439 and contain no registers.
440
441 The name GENERAL_REGS must be the name of a class (or an alias for
442 another name such as ALL_REGS). This is the class of registers
443 that is allowed by "g" or "r" in a register constraint.
444 Also, registers outside this class are allocated only when
445 instructions express preferences for them.
446
447 The classes must be numbered in nondecreasing order; that is,
448 a larger-numbered class must never be contained completely
449 in a smaller-numbered class.
450
451 For any two classes, it is very desirable that there be another
452 class that represents their union. */
453
454 enum reg_class
455 {
456 NO_REGS, /* no registers in set */
457 SIBCALL_REGS, /* registers used by indirect sibcalls */
458 JALR_REGS, /* registers used by indirect calls */
459 GR_REGS, /* integer registers */
460 FP_REGS, /* floating-point registers */
461 FRAME_REGS, /* arg pointer and frame pointer */
462 VL_REGS, /* vl register */
463 VTYPE_REGS, /* vtype register */
464 VM_REGS, /* v0.t registers */
465 VD_REGS, /* vector registers except v0.t */
466 V_REGS, /* vector registers */
467 ALL_REGS, /* all registers */
468 LIM_REG_CLASSES /* max value + 1 */
469 };
470
471 #define N_REG_CLASSES (int) LIM_REG_CLASSES
472
473 #define GENERAL_REGS GR_REGS
474
475 /* An initializer containing the names of the register classes as C
476 string constants. These names are used in writing some of the
477 debugging dumps. */
478
479 #define REG_CLASS_NAMES \
480 { \
481 "NO_REGS", \
482 "SIBCALL_REGS", \
483 "JALR_REGS", \
484 "GR_REGS", \
485 "FP_REGS", \
486 "FRAME_REGS", \
487 "VL_REGS", \
488 "VTYPE_REGS", \
489 "VM_REGS", \
490 "VD_REGS", \
491 "V_REGS", \
492 "ALL_REGS" \
493 }
494
495 /* An initializer containing the contents of the register classes,
496 as integers which are bit masks. The Nth integer specifies the
497 contents of class N. The way the integer MASK is interpreted is
498 that register R is in the class if `MASK & (1 << R)' is 1.
499
500 When the machine has more than 32 registers, an integer does not
501 suffice. Then the integers are replaced by sub-initializers,
502 braced groupings containing several integers. Each
503 sub-initializer must be suitable as an initializer for the type
504 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
505
506 #define REG_CLASS_CONTENTS \
507 { \
508 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
509 { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
510 { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 }, /* JALR_REGS */ \
511 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
512 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \
513 { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \
514 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* VL_REGS */ \
515 { 0x00000000, 0x00000000, 0x00000008, 0x00000000 }, /* VTYPE_REGS */ \
516 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \
517 { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \
518 { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \
519 { 0xffffffff, 0xffffffff, 0x0000000f, 0xffffffff } /* ALL_REGS */ \
520 }
521
522 /* A C expression whose value is a register class containing hard
523 register REGNO. In general there is more that one such class;
524 choose a class which is "minimal", meaning that no smaller class
525 also contains the register. */
526
527 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
528
529 /* A macro whose definition is the name of the class to which a
530 valid base register must belong. A base register is one used in
531 an address which is the register value plus a displacement. */
532
533 #define BASE_REG_CLASS GR_REGS
534
535 /* A macro whose definition is the name of the class to which a
536 valid index register must belong. An index register is one used
537 in an address where its value is either multiplied by a scale
538 factor or added to another register (as well as added to a
539 displacement). */
540
541 #define INDEX_REG_CLASS NO_REGS
542
543 /* We generally want to put call-clobbered registers ahead of
544 call-saved ones. (IRA expects this.) */
545
546 #define REG_ALLOC_ORDER \
547 { \
548 /* Call-clobbered GPRs. */ \
549 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \
550 /* Call-saved GPRs. */ \
551 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
552 /* GPRs that can never be exposed to the register allocator. */ \
553 0, 2, 3, 4, \
554 /* Call-clobbered FPRs. */ \
555 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \
556 60, 61, 62, 63, \
557 /* Call-saved FPRs. */ \
558 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
559 /* V24 ~ V31. */ \
560 120, 121, 122, 123, 124, 125, 126, 127, \
561 /* V8 ~ V23. */ \
562 104, 105, 106, 107, 108, 109, 110, 111, \
563 112, 113, 114, 115, 116, 117, 118, 119, \
564 /* V0 ~ V7. */ \
565 96, 97, 98, 99, 100, 101, 102, 103, \
566 /* None of the remaining classes have defined call-saved \
567 registers. */ \
568 64, 65, 66, 67 \
569 }
570
571 /* True if VALUE is a signed 12-bit number. */
572
573 #define SMALL_OPERAND(VALUE) \
574 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
575
576 #define POLY_SMALL_OPERAND_P(POLY_VALUE) \
577 (POLY_VALUE.is_constant () ? \
578 SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
579
580 /* True if VALUE can be loaded into a register using LUI. */
581
582 #define LUI_OPERAND(VALUE) \
583 (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \
584 || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
585
586 /* If this is a single bit mask, then we can load it with bseti. Special
587 handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
588 #define SINGLE_BIT_MASK_OPERAND(VALUE) \
589 (pow2p_hwi (TARGET_64BIT \
590 ? (VALUE) \
591 : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1))))
592
593 /* Stack layout; function entry, exit and calling. */
594
595 #define STACK_GROWS_DOWNWARD 1
596
597 #define FRAME_GROWS_DOWNWARD 1
598
599 #define RETURN_ADDR_RTX riscv_return_addr
600
601 #define ELIMINABLE_REGS \
602 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
603 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
604 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
605 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
606
607 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
608 (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
609
610 /* Allocate stack space for arguments at the beginning of each function. */
611 #define ACCUMULATE_OUTGOING_ARGS 1
612
613 /* The argument pointer always points to the first argument. */
614 #define FIRST_PARM_OFFSET(FNDECL) 0
615
616 #define REG_PARM_STACK_SPACE(FNDECL) 0
617
618 /* Define this if it is the responsibility of the caller to
619 allocate the area reserved for arguments passed in registers.
620 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
621 of this macro is to determine whether the space is included in
622 `crtl->outgoing_args_size'. */
623 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
624
625 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
626
627 /* Symbolic macros for the registers used to return integer and floating
628 point values. */
629
630 #define GP_RETURN GP_ARG_FIRST
631 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
632
633 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
634
635 /* Symbolic macros for the first/last argument registers. */
636
637 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
638 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
639 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
640 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
641 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
642
643 #define CALLEE_SAVED_REG_NUMBER(REGNO) \
644 ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \
645 (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
646
647 #define LIBCALL_VALUE(MODE) \
648 riscv_function_value (NULL_TREE, NULL_TREE, MODE)
649
650 #define FUNCTION_VALUE(VALTYPE, FUNC) \
651 riscv_function_value (VALTYPE, FUNC, VOIDmode)
652
653 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
654
655 /* 1 if N is a possible register number for function argument passing.
656 We have no FP argument registers when soft-float. */
657
658 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */
659 #define FUNCTION_ARG_REGNO_P(N) \
660 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \
661 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
662
663 typedef struct {
664 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
665 unsigned int num_gprs;
666
667 /* Number of floating-point registers used so far, likewise. */
668 unsigned int num_fprs;
669 } CUMULATIVE_ARGS;
670
671 /* Initialize a variable CUM of type CUMULATIVE_ARGS
672 for a call to a function whose data type is FNTYPE.
673 For a library call, FNTYPE is 0. */
674
675 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
676 memset (&(CUM), 0, sizeof (CUM))
677
678 #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO)
679
680 /* Align based on stack boundary, which might have been set by the user. */
681 #define RISCV_STACK_ALIGN(LOC) \
682 (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
683
684 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
685 the stack pointer does not matter. The value is tested only in
686 functions that have frame pointers.
687 No definition is equivalent to always zero. */
688
689 #define EXIT_IGNORE_STACK 1
690
691
692 /* Trampolines are a block of code followed by two pointers. */
693
694 #define TRAMPOLINE_CODE_SIZE 16
695 #define TRAMPOLINE_SIZE \
696 ((Pmode == SImode) \
697 ? TRAMPOLINE_CODE_SIZE \
698 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
699 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
700
701 /* Addressing modes, and classification of registers for them. */
702
703 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
704 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
705 riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
706
707 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
708 and check its validity for a certain class.
709 We have two alternate definitions for each of them.
710 The usual definition accepts all pseudo regs; the other rejects them all.
711 The symbol REG_OK_STRICT causes the latter definition to be used.
712
713 Most source files want to accept pseudo regs in the hope that
714 they will get allocated to the class that the insn wants them to be in.
715 Some source files that are used after register allocation
716 need to be strict. */
717
718 #ifndef REG_OK_STRICT
719 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
720 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
721 #else
722 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
723 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
724 #endif
725
726 #define REG_OK_FOR_INDEX_P(X) 0
727
728 /* Maximum number of registers that can appear in a valid memory address. */
729
730 #define MAX_REGS_PER_ADDRESS 1
731
732 #define CONSTANT_ADDRESS_P(X) \
733 (CONSTANT_P (X) && memory_address_p (SImode, X))
734
735 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
736 'the start of the function that this code is output in'. */
737
738 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
739 do { \
740 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
741 asm_fprintf ((FILE), "%U%s", \
742 XSTR (XEXP (DECL_RTL (current_function_decl), \
743 0), 0)); \
744 else \
745 asm_fprintf ((FILE), "%U%s", (NAME)); \
746 } while (0)
747
748 #define JUMP_TABLES_IN_TEXT_SECTION 0
749 #define CASE_VECTOR_MODE SImode
750 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
751
752 #define LOCAL_SYM_P(sym) \
753 ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \
754 || ((GET_CODE (sym) == CONST) \
755 && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \
756 && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))
757
758 /* The load-address macro is used for PC-relative addressing of symbols
759 that bind locally. Don't use it for symbols that should be addressed
760 via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing
761 currently results in more opportunities for linker relaxation. */
762 #define USE_LOAD_ADDRESS_MACRO(sym) \
763 (!TARGET_EXPLICIT_RELOCS && \
764 ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY))
765
766 /* Define this as 1 if `char' should by default be signed; else as 0. */
767 #define DEFAULT_SIGNED_CHAR 0
768
769 #define MOVE_MAX UNITS_PER_WORD
770 #define MAX_MOVE_MAX 8
771
772 /* The SPARC port says:
773 Nonzero if access to memory by bytes is slow and undesirable.
774 For RISC chips, it means that access to memory by bytes is no
775 better than access by words when possible, so grab a whole word
776 and maybe make use of that. */
777 #define SLOW_BYTE_ACCESS 1
778
779 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
780 in the md file instead. */
781 #define SHIFT_COUNT_TRUNCATED 0
782
783 /* Specify the machine mode that pointers have.
784 After generation of rtl, the compiler makes no further distinction
785 between pointers and any other objects of this machine mode. */
786
787 #define Pmode word_mode
788
789 /* Give call MEMs SImode since it is the "most permissive" mode
790 for both 32-bit and 64-bit targets. */
791
792 #define FUNCTION_MODE SImode
793
794 /* A C expression for the cost of a branch instruction. A value of 2
795 seems to minimize code size. */
796
797 #define BRANCH_COST(speed_p, predictable_p) \
798 ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
799
800 /* True if the target optimizes short forward branches around integer
801 arithmetic instructions into predicated operations, e.g., for
802 conditional-move operations. The macro assumes that all branch
803 instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
804 support this feature. The macro further assumes that any integer
805 arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
806 SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
807 counterparts, including C.MV and C.LI) can be in the branch shadow. */
808
809 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
810
811 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
812
813 /* Control the assembler format that we output. */
814
815 /* Output to assembler file text saying following lines
816 may contain character constants, extra white space, comments, etc. */
817
818 #ifndef ASM_APP_ON
819 #define ASM_APP_ON " #APP\n"
820 #endif
821
822 /* Output to assembler file text saying following lines
823 no longer contain unusual constructs. */
824
825 #ifndef ASM_APP_OFF
826 #define ASM_APP_OFF " #NO_APP\n"
827 #endif
828
829 #define REGISTER_NAMES \
830 { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \
831 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \
832 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \
833 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \
834 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \
835 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \
836 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \
837 "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \
838 "arg", "frame", "vl", "vtype", "N/A", "N/A", "N/A", "N/A", \
839 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
840 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
841 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
842 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
843 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
844 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
845 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",}
846
847 #define ADDITIONAL_REGISTER_NAMES \
848 { \
849 { "x0", 0 + GP_REG_FIRST }, \
850 { "x1", 1 + GP_REG_FIRST }, \
851 { "x2", 2 + GP_REG_FIRST }, \
852 { "x3", 3 + GP_REG_FIRST }, \
853 { "x4", 4 + GP_REG_FIRST }, \
854 { "x5", 5 + GP_REG_FIRST }, \
855 { "x6", 6 + GP_REG_FIRST }, \
856 { "x7", 7 + GP_REG_FIRST }, \
857 { "x8", 8 + GP_REG_FIRST }, \
858 { "x9", 9 + GP_REG_FIRST }, \
859 { "x10", 10 + GP_REG_FIRST }, \
860 { "x11", 11 + GP_REG_FIRST }, \
861 { "x12", 12 + GP_REG_FIRST }, \
862 { "x13", 13 + GP_REG_FIRST }, \
863 { "x14", 14 + GP_REG_FIRST }, \
864 { "x15", 15 + GP_REG_FIRST }, \
865 { "x16", 16 + GP_REG_FIRST }, \
866 { "x17", 17 + GP_REG_FIRST }, \
867 { "x18", 18 + GP_REG_FIRST }, \
868 { "x19", 19 + GP_REG_FIRST }, \
869 { "x20", 20 + GP_REG_FIRST }, \
870 { "x21", 21 + GP_REG_FIRST }, \
871 { "x22", 22 + GP_REG_FIRST }, \
872 { "x23", 23 + GP_REG_FIRST }, \
873 { "x24", 24 + GP_REG_FIRST }, \
874 { "x25", 25 + GP_REG_FIRST }, \
875 { "x26", 26 + GP_REG_FIRST }, \
876 { "x27", 27 + GP_REG_FIRST }, \
877 { "x28", 28 + GP_REG_FIRST }, \
878 { "x29", 29 + GP_REG_FIRST }, \
879 { "x30", 30 + GP_REG_FIRST }, \
880 { "x31", 31 + GP_REG_FIRST }, \
881 { "f0", 0 + FP_REG_FIRST }, \
882 { "f1", 1 + FP_REG_FIRST }, \
883 { "f2", 2 + FP_REG_FIRST }, \
884 { "f3", 3 + FP_REG_FIRST }, \
885 { "f4", 4 + FP_REG_FIRST }, \
886 { "f5", 5 + FP_REG_FIRST }, \
887 { "f6", 6 + FP_REG_FIRST }, \
888 { "f7", 7 + FP_REG_FIRST }, \
889 { "f8", 8 + FP_REG_FIRST }, \
890 { "f9", 9 + FP_REG_FIRST }, \
891 { "f10", 10 + FP_REG_FIRST }, \
892 { "f11", 11 + FP_REG_FIRST }, \
893 { "f12", 12 + FP_REG_FIRST }, \
894 { "f13", 13 + FP_REG_FIRST }, \
895 { "f14", 14 + FP_REG_FIRST }, \
896 { "f15", 15 + FP_REG_FIRST }, \
897 { "f16", 16 + FP_REG_FIRST }, \
898 { "f17", 17 + FP_REG_FIRST }, \
899 { "f18", 18 + FP_REG_FIRST }, \
900 { "f19", 19 + FP_REG_FIRST }, \
901 { "f20", 20 + FP_REG_FIRST }, \
902 { "f21", 21 + FP_REG_FIRST }, \
903 { "f22", 22 + FP_REG_FIRST }, \
904 { "f23", 23 + FP_REG_FIRST }, \
905 { "f24", 24 + FP_REG_FIRST }, \
906 { "f25", 25 + FP_REG_FIRST }, \
907 { "f26", 26 + FP_REG_FIRST }, \
908 { "f27", 27 + FP_REG_FIRST }, \
909 { "f28", 28 + FP_REG_FIRST }, \
910 { "f29", 29 + FP_REG_FIRST }, \
911 { "f30", 30 + FP_REG_FIRST }, \
912 { "f31", 31 + FP_REG_FIRST }, \
913 }
914
915 /* Globalizing directive for a label. */
916 #define GLOBAL_ASM_OP "\t.globl\t"
917
918 /* This is how to store into the string LABEL
919 the symbol_ref name of an internal numbered label where
920 PREFIX is the class of label and NUM is the number within the class.
921 This is suitable for output with `assemble_name'. */
922
923 #undef ASM_GENERATE_INTERNAL_LABEL
924 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
925 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
926
927 /* This is how to output an element of a case-vector that is absolute. */
928
929 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
930 fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
931
932 /* This is how to output an element of a PIC case-vector. */
933
934 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
935 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
936 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
937
938 /* This is how to output an assembler line
939 that says to advance the location counter
940 to a multiple of 2**LOG bytes. */
941
942 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
943 fprintf (STREAM, "\t.align\t%d\n", (LOG))
944
945 /* Define the strings to put out for each section in the object file. */
946 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
947 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
948 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata"
949 #define BSS_SECTION_ASM_OP "\t.bss"
950 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits"
951 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits"
952
953 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
954 do \
955 { \
956 fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
957 reg_names[STACK_POINTER_REGNUM], \
958 reg_names[STACK_POINTER_REGNUM], \
959 TARGET_64BIT ? "sd" : "sw", \
960 reg_names[REGNO], \
961 reg_names[STACK_POINTER_REGNUM]); \
962 } \
963 while (0)
964
965 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
966 do \
967 { \
968 fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \
969 TARGET_64BIT ? "ld" : "lw", \
970 reg_names[REGNO], \
971 reg_names[STACK_POINTER_REGNUM], \
972 reg_names[STACK_POINTER_REGNUM], \
973 reg_names[STACK_POINTER_REGNUM]); \
974 } \
975 while (0)
976
977 #define ASM_COMMENT_START "#"
978
979 #undef SIZE_TYPE
980 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
981
982 #undef PTRDIFF_TYPE
983 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
984
985 /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */
986
987 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
988
989 /* The maximum number of bytes that can be copied by a straight-line
990 cpymemsi implementation. */
991
992 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
993
994 /* If a memory-to-memory move would take MOVE_RATIO or more simple
995 move-instruction pairs, we will do a cpymem or libcall instead.
996 Do not use move_by_pieces at all when strict alignment is not
997 in effect but the target has slow unaligned accesses; in this
998 case, cpymem or libcall is more efficient. */
999
1000 #define MOVE_RATIO(speed) \
1001 (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \
1002 (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \
1003 CLEAR_RATIO (speed) / 2)
1004
1005 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
1006 of the length of a memset call, but use the default otherwise. */
1007
1008 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
1009
1010 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
1011 optimizing for size adjust the ratio to account for the overhead of
1012 loading the constant and replicating it across the word. */
1013
1014 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
1015
1016 #ifndef USED_FOR_TARGET
1017 extern const enum reg_class riscv_regno_to_class[];
1018 extern bool riscv_slow_unaligned_access_p;
1019 extern unsigned riscv_stack_boundary;
1020 extern unsigned riscv_bytes_per_vector_chunk;
1021 extern poly_uint16 riscv_vector_chunks;
1022 /* The number of bits and bytes in a RVV vector. */
1023 #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8))
1024 #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
1025 #endif
1026
1027 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1028 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
1029
1030 #define XLEN_SPEC \
1031 "%{march=rv32*:32}" \
1032 "%{march=rv64*:64}" \
1033
1034 #define ABI_SPEC \
1035 "%{mabi=ilp32:ilp32}" \
1036 "%{mabi=ilp32e:ilp32e}" \
1037 "%{mabi=ilp32f:ilp32f}" \
1038 "%{mabi=ilp32d:ilp32d}" \
1039 "%{mabi=lp64:lp64}" \
1040 "%{mabi=lp64f:lp64f}" \
1041 "%{mabi=lp64d:lp64d}" \
1042
1043 /* ISA constants needed for code generation. */
1044 #define OPCODE_LW 0x2003
1045 #define OPCODE_LD 0x3003
1046 #define OPCODE_AUIPC 0x17
1047 #define OPCODE_JALR 0x67
1048 #define OPCODE_LUI 0x37
1049 #define OPCODE_ADDI 0x13
1050 #define SHIFT_RD 7
1051 #define SHIFT_RS1 15
1052 #define SHIFT_IMM 20
1053 #define IMM_BITS 12
1054 #define C_S_BITS 5
1055 #define C_SxSP_BITS 6
1056
1057 #define IMM_REACH (1LL << IMM_BITS)
1058 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
1059 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
1060
1061 #define SWSP_REACH (4LL << C_SxSP_BITS)
1062 #define SDSP_REACH (8LL << C_SxSP_BITS)
1063
1064 /* This is the maximum value that can be represented in a compressed load/store
1065 offset (an unsigned 5-bit value scaled by 4). */
1066 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
1067
1068 /* Called from RISCV_REORG, this is defined in riscv-sr.cc. */
1069
1070 extern void riscv_remove_unneeded_save_restore_calls (void);
1071
1072 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
1073
1074 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1075 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1076 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1077 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1078
1079 #define TARGET_SUPPORTS_WIDE_INT 1
1080
1081 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
1082
1083 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
1084
1085 #endif /* ! GCC_RISCV_H */