gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2023 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include <stdbool.h>
  26 #include "config/riscv/riscv-opts.h"
  27
  28 /* Target CPU builtins.  */
  29 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  30
  31 #ifdef TARGET_BIG_ENDIAN_DEFAULT
  32 #define DEFAULT_ENDIAN_SPEC    "b"
  33 #else
  34 #define DEFAULT_ENDIAN_SPEC    "l"
  35 #endif
  36
  37 /* Default target_flags if no switches are specified  */
  38
  39 #ifndef TARGET_DEFAULT
  40 #define TARGET_DEFAULT 0
  41 #endif
  42
  43 #ifndef RISCV_TUNE_STRING_DEFAULT
  44 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  45 #endif
  46
  47 extern const char *riscv_expand_arch (int argc, const char **argv);
  48 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
  49 extern const char *riscv_default_mtune (int argc, const char **argv);
  50 extern const char *riscv_multi_lib_check (int argc, const char **argv);
  51
  52 # define EXTRA_SPEC_FUNCTIONS                                           \
  53   { "riscv_expand_arch", riscv_expand_arch },                           \
  54   { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu },         \
  55   { "riscv_default_mtune", riscv_default_mtune },                       \
  56   { "riscv_multi_lib_check", riscv_multi_lib_check },
  57
  58 /* Support for a compile-time default CPU, et cetera.  The rules are:
  59    --with-arch is ignored if -march or -mcpu is specified.
  60    --with-abi is ignored if -mabi is specified.
  61    --with-tune is ignored if -mtune or -mcpu is specified.
  62    --with-isa-spec is ignored if -misa-spec is specified.
  63
  64    But using default -march/-mtune value if -mcpu don't have valid option.  */
  65 #define OPTION_DEFAULT_SPECS \
  66   {"tune", "%{!mtune=*:"                                                \
  67            "  %{!mcpu=*:-mtune=%(VALUE)}"                               \
  68            "  %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" },  \
  69   {"arch", "%{!march=*:"                                                \
  70            "  %{!mcpu=*:-march=%(VALUE)}"                               \
  71            "  %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" },  \
  72   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  73   {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
  74
  75 #ifdef IN_LIBGCC2
  76 #undef TARGET_64BIT
  77 /* Make this compile time constant for libgcc2 */
  78 #define TARGET_64BIT           (__riscv_xlen == 64)
  79 #endif /* IN_LIBGCC2 */
  80
  81 #ifdef HAVE_AS_MISA_SPEC
  82 #define ASM_MISA_SPEC "%{misa-spec=*}"
  83 #else
  84 #define ASM_MISA_SPEC ""
  85 #endif
  86
  87 /* Reference:
  88      https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing  */
  89 #define STRINGIZING(s) __STRINGIZING(s)
  90 #define __STRINGIZING(s) #s
  91
  92 #define MULTILIB_DEFAULTS \
  93   {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \
  94    "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) }
  95
  96 #undef ASM_SPEC
  97 #define ASM_SPEC "\
  98 %(subtarget_asm_debugging_spec) \
  99 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
 100 %{march=*} \
 101 %{mabi=*} \
 102 %{mno-relax} \
 103 %{mbig-endian} \
 104 %{mlittle-endian} \
 105 %(subtarget_asm_spec)" \
 106 ASM_MISA_SPEC
 107
 108 #undef DRIVER_SELF_SPECS
 109 #define DRIVER_SELF_SPECS                                       \
 110 "%{march=*:%:riscv_expand_arch(%*)} "                           \
 111 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
 112
 113 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
 114
 115 #define LOCAL_LABEL_PREFIX      "."
 116 #define USER_LABEL_PREFIX       ""
 117
 118 /* Offsets recorded in opcodes are a multiple of this alignment factor.
 119    The default for this in 64-bit mode is 8, which causes problems with
 120    SFmode register saves.  */
 121 #define DWARF_CIE_DATA_ALIGNMENT -4
 122
 123 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 124 #define DWARF_FRAME_REGNUM(REGNO)                                              \
 125   (FRM_REG_P (REGNO)    ? RISCV_DWARF_FRM                                      \
 126    : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM                                     \
 127    : VL_REG_P (REGNO)   ? RISCV_DWARF_VL                                       \
 128    : VTYPE_REG_P (REGNO)                                                       \
 129      ? RISCV_DWARF_VTYPE                                                       \
 130      : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO)                \
 131           ? REGNO                                                              \
 132           : INVALID_REGNUM))
 133
 134 /* The DWARF 2 CFA column which tracks the return address.  */
 135 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
 136 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
 137
 138 /* Describe how we implement __builtin_eh_return.  */
 139 #define EH_RETURN_DATA_REGNO(N) \
 140   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 141
 142 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
 143
 144 /* Target machine storage layout */
 145
 146 #define BITS_BIG_ENDIAN 0
 147 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 148 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
 149
 150 #define MAX_BITS_PER_WORD 64
 151
 152 /* Width of a word, in units (bytes).  */
 153 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 154 #define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD)
 155 #ifndef IN_LIBGCC2
 156 #define MIN_UNITS_PER_WORD 4
 157 #endif
 158
 159 /* Allows SImode op in builtin overflow pattern, see internal-fn.cc.  */
 160 #undef TARGET_MIN_ARITHMETIC_PRECISION
 161 #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision
 162
 163 /* The `Q' extension is not yet supported.  */
 164 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 165 /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */
 166 #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
 167
 168 /* The largest type that can be passed in floating-point registers.  */
 169 #define UNITS_PER_FP_ARG                                                \
 170   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 171     || riscv_abi == ABI_LP64)                                           \
 172    ? 0                                                                  \
 173    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 174
 175 /* Set the sizes of the core types.  */
 176 #define SHORT_TYPE_SIZE 16
 177 #define INT_TYPE_SIZE 32
 178 #define LONG_LONG_TYPE_SIZE 64
 179 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 180 #define LONG_TYPE_SIZE POINTER_SIZE
 181
 182 #define FLOAT_TYPE_SIZE 32
 183 #define DOUBLE_TYPE_SIZE 64
 184 #define LONG_DOUBLE_TYPE_SIZE 128
 185
 186 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 187 #define PARM_BOUNDARY BITS_PER_WORD
 188
 189 /* Allocation boundary (in *bits*) for the code of a function.  */
 190 #define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
 191
 192 /* The smallest supported stack boundary the calling convention supports.  */
 193 #define STACK_BOUNDARY \
 194   (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
 195
 196 /* The ABI stack alignment.  */
 197 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
 198
 199 /* There is no point aligning anything to a rounder boundary than this.  */
 200 #define BIGGEST_ALIGNMENT 128
 201
 202 /* The user-level ISA permits unaligned accesses, but they are not required
 203    of the privileged architecture.  */
 204 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 205
 206 /* Define this if you wish to imitate the way many other C compilers
 207    handle alignment of bitfields and the structures that contain
 208    them.
 209
 210    The behavior is that the type written for a bit-field (`int',
 211    `short', or other integer type) imposes an alignment for the
 212    entire structure, as if the structure really did contain an
 213    ordinary field of that type.  In addition, the bit-field is placed
 214    within the structure so that it would fit within such a field,
 215    not crossing a boundary for it.
 216
 217    Thus, on most machines, a bit-field whose type is written as `int'
 218    would not cross a four-byte boundary, and would force four-byte
 219    alignment for the whole structure.  (The alignment used may not
 220    be four bytes; it is controlled by the other alignment
 221    parameters.)
 222
 223    If the macro is defined, its definition should be a C expression;
 224    a nonzero value for the expression enables this behavior.  */
 225
 226 #define PCC_BITFIELD_TYPE_MATTERS 1
 227
 228 /* An integer expression for the size in bits of the largest integer machine
 229    mode that should actually be used.  We allow pairs of registers.  */
 230 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 231
 232 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
 233 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)                       \
 234   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 235     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 236         || TREE_CODE (TYPE) == UNION_TYPE                               \
 237         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 238
 239 /* If defined, a C expression to compute the alignment for a static
 240    variable.  TYPE is the data type, and ALIGN is the alignment that
 241    the object would ordinarily have.  The value of this macro is used
 242    instead of that alignment to align the object.
 243
 244    If this macro is not defined, then ALIGN is used.
 245
 246    One use of this macro is to increase alignment of medium-size
 247    data to make it all fit in fewer cache lines.  Another is to
 248    cause character arrays to be word-aligned so that `strcpy' calls
 249    that copy constants to character arrays can be done inline.  */
 250
 251 #define DATA_ALIGNMENT(TYPE, ALIGN)                                             \
 252   RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,  \
 253                           TYPE, ALIGN)
 254
 255 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 256    character arrays to be word-aligned so that `strcpy' calls that copy
 257    constants to character arrays can be done inline, and 'strcmp' can be
 258    optimised to use word loads. */
 259 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 260   RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
 261
 262 /* Define if operations between registers always perform the operation
 263    on the full register even if a narrower mode is specified.  */
 264 #define WORD_REGISTER_OPERATIONS 1
 265
 266 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 267    moves.  All other references are zero extended.  */
 268 #define LOAD_EXTEND_OP(MODE) \
 269   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 270
 271 /* Define this macro if it is advisable to hold scalars in registers
 272    in a wider mode than that declared by the program.  In such cases,
 273    the value is constrained to be within the bounds of the declared
 274    type, but kept valid in the wider mode.  The signedness of the
 275    extension may differ from that of the type.  */
 276
 277 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 278   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 279       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 280     {                                           \
 281       if ((MODE) == SImode)                     \
 282         (UNSIGNEDP) = 0;                        \
 283       (MODE) = word_mode;                       \
 284     }
 285
 286 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 287    Extensions of pointers to word_mode must be signed.  */
 288 #define POINTERS_EXTEND_UNSIGNED false
 289
 290 /* Define if loading short immediate values into registers sign extends.  */
 291 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 292
 293 /* Standard register usage.  */
 294
 295 /* Number of hardware registers.  We have:
 296
 297    - 32 integer registers
 298    - 32 floating point registers
 299    - 2 fake registers:
 300         - ARG_POINTER_REGNUM
 301         - FRAME_POINTER_REGNUM
 302    - 1 vl register
 303    - 1 vtype register
 304    - 30 unused registers for future expansion
 305    - 32 vector registers  */
 306
 307 #define FIRST_PSEUDO_REGISTER 128
 308
 309 /* x0, sp, gp, and tp are fixed.  */
 310
 311 #define FIXED_REGISTERS                                                 \
 312 { /* General registers.  */                                             \
 313   1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 314   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 315   /* Floating-point registers.  */                                      \
 316   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 317   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 318   /* Others.  */                                                        \
 319   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 320   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 321   /* Vector registers.  */                                              \
 322   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 323   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0                        \
 324 }
 325
 326 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 327    The call RTLs themselves clobber ra.  */
 328
 329 #define CALL_USED_REGISTERS                                             \
 330 { /* General registers.  */                                             \
 331   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 332   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 333   /* Floating-point registers.  */                                      \
 334   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 335   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 336   /* Others.  */                                                        \
 337   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 338   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 339   /* Vector registers.  */                                              \
 340   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 341   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1                        \
 342 }
 343
 344 /* Select a register mode required for caller save of hard regno REGNO.
 345    Contrary to what is documented, the default is not the smallest suitable
 346    mode but the largest suitable mode for the given (REGNO, NREGS) pair and
 347    it quickly creates paradoxical subregs that can be problematic.  */
 348 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 349   ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
 350
 351 /* Internal macros to classify an ISA register's type.  */
 352
 353 #define GP_REG_FIRST 0
 354 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 355 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 356
 357 #define FP_REG_FIRST 32
 358 #define FP_REG_LAST  63
 359 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 360
 361 #define V_REG_FIRST 96
 362 #define V_REG_LAST  127
 363 #define V_REG_NUM   (V_REG_LAST - V_REG_FIRST + 1)
 364
 365 /* The DWARF 2 CFA column which tracks the return address from a
 366    signal handler context.  This means that to maintain backwards
 367    compatibility, no hard register can be assigned this column if it
 368    would need to be handled by the DWARF unwinder.  */
 369 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 370
 371 #define GP_REG_P(REGNO) \
 372   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 373 #define FP_REG_P(REGNO)  \
 374   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 375 #define V_REG_P(REGNO)  \
 376   ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
 377 #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
 378 #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
 379 #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM)
 380 #define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM)
 381
 382 /* True when REGNO is in SIBCALL_REGS set.  */
 383 #define SIBCALL_REG_P(REGNO)    \
 384   TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
 385
 386 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 387
 388 /* Use s0 as the frame pointer if it is so requested.  */
 389 #define HARD_FRAME_POINTER_REGNUM 8
 390 #define STACK_POINTER_REGNUM 2
 391 #define THREAD_POINTER_REGNUM 4
 392
 393 /* These two registers don't really exist: they get eliminated to either
 394    the stack or hard frame pointer.  */
 395 #define ARG_POINTER_REGNUM 64
 396 #define FRAME_POINTER_REGNUM 65
 397
 398 /* Define Dwarf for RVV.  */
 399 #define RISCV_DWARF_FRM (4096 + 0x003)
 400 #define RISCV_DWARF_VXRM (4096 + 0x00a)
 401 #define RISCV_DWARF_VL (4096 + 0xc20)
 402 #define RISCV_DWARF_VTYPE (4096 + 0xc21)
 403 #define RISCV_DWARF_VLENB (4096 + 0xc22)
 404
 405 /* Register in which static-chain is passed to a function.  */
 406 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 407
 408 /* Registers used as temporaries in prologue/epilogue code.
 409
 410    The prologue registers mustn't conflict with any
 411    incoming arguments, the static chain pointer, or the frame pointer.
 412    The epilogue temporary mustn't conflict with the return registers,
 413    the frame pointer, the EH stack adjustment, or the EH data registers. */
 414
 415 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
 416 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 417 #define RISCV_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST + 1)
 418 #define RISCV_PROLOGUE_TEMP2(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP2_REGNUM)
 419
 420 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 421 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
 422   gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
 423
 424 #define RETURN_ADDR_MASK (1 << RETURN_ADDR_REGNUM)
 425 #define S0_MASK (1 << S0_REGNUM)
 426 #define S1_MASK (1 << S1_REGNUM)
 427 #define S2_MASK (1 << S2_REGNUM)
 428 #define S3_MASK (1 << S3_REGNUM)
 429 #define S4_MASK (1 << S4_REGNUM)
 430 #define S5_MASK (1 << S5_REGNUM)
 431 #define S6_MASK (1 << S6_REGNUM)
 432 #define S7_MASK (1 << S7_REGNUM)
 433 #define S8_MASK (1 << S8_REGNUM)
 434 #define S9_MASK (1 << S9_REGNUM)
 435 #define S10_MASK (1 << S10_REGNUM)
 436 #define S11_MASK (1 << S11_REGNUM)
 437
 438 #define MULTI_PUSH_GPR_MASK                                                    \
 439   (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK          \
 440    | S5_MASK | S6_MASK | S7_MASK | S8_MASK | S9_MASK | S10_MASK | S11_MASK)
 441 #define ZCMP_MAX_SPIMM 3
 442 #define ZCMP_SP_INC_STEP 16
 443 #define ZCMP_INVALID_S0S10_SREGS_COUNTS 11
 444 #define ZCMP_S0S11_SREGS_COUNTS 12
 445 #define ZCMP_MAX_GRP_SLOTS 13
 446
 447 #define MCOUNT_NAME "_mcount"
 448
 449 #define NO_PROFILE_COUNTERS 1
 450
 451 /* Emit rtl for profiling.  Output assembler code to FILE
 452    to call "_mcount" for profiling a function entry.  */
 453 #define PROFILE_HOOK(LABEL)                                             \
 454   {                                                                     \
 455     rtx fun, ra;                                                        \
 456     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 457     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 458     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 459   }
 460
 461 /* All the work done in PROFILE_HOOK, but still required.  */
 462 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 463
 464 /* Define this macro if it is as good or better to call a constant
 465    function address than to call an address kept in a register.  */
 466 #define NO_FUNCTION_CSE 1
 467
 468 /* Define the classes of registers for register constraints in the
 469    machine description.  Also define ranges of constants.
 470
 471    One of the classes must always be named ALL_REGS and include all hard regs.
 472    If there is more than one class, another class must be named NO_REGS
 473    and contain no registers.
 474
 475    The name GENERAL_REGS must be the name of a class (or an alias for
 476    another name such as ALL_REGS).  This is the class of registers
 477    that is allowed by "g" or "r" in a register constraint.
 478    Also, registers outside this class are allocated only when
 479    instructions express preferences for them.
 480
 481    The classes must be numbered in nondecreasing order; that is,
 482    a larger-numbered class must never be contained completely
 483    in a smaller-numbered class.
 484
 485    For any two classes, it is very desirable that there be another
 486    class that represents their union.  */
 487
 488 enum reg_class
 489 {
 490   NO_REGS,                      /* no registers in set */
 491   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 492   JALR_REGS,                    /* registers used by indirect calls */
 493   GR_REGS,                      /* integer registers */
 494   FP_REGS,                      /* floating-point registers */
 495   FRAME_REGS,                   /* arg pointer and frame pointer */
 496   VM_REGS,                      /* v0.t registers */
 497   VD_REGS,                      /* vector registers except v0.t */
 498   V_REGS,                       /* vector registers */
 499   ALL_REGS,                     /* all registers */
 500   LIM_REG_CLASSES               /* max value + 1 */
 501 };
 502
 503 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 504
 505 #define GENERAL_REGS GR_REGS
 506
 507 /* An initializer containing the names of the register classes as C
 508    string constants.  These names are used in writing some of the
 509    debugging dumps.  */
 510
 511 #define REG_CLASS_NAMES                                                 \
 512 {                                                                       \
 513   "NO_REGS",                                                            \
 514   "SIBCALL_REGS",                                                       \
 515   "JALR_REGS",                                                          \
 516   "GR_REGS",                                                            \
 517   "FP_REGS",                                                            \
 518   "FRAME_REGS",                                                         \
 519   "VM_REGS",                                                            \
 520   "VD_REGS",                                                            \
 521   "V_REGS",                                                             \
 522   "ALL_REGS"                                                            \
 523 }
 524
 525 /* An initializer containing the contents of the register classes,
 526    as integers which are bit masks.  The Nth integer specifies the
 527    contents of class N.  The way the integer MASK is interpreted is
 528    that register R is in the class if `MASK & (1 << R)' is 1.
 529
 530    When the machine has more than 32 registers, an integer does not
 531    suffice.  Then the integers are replaced by sub-initializers,
 532    braced groupings containing several integers.  Each
 533    sub-initializer must be suitable as an initializer for the type
 534    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 535
 536 #define REG_CLASS_CONTENTS                                              \
 537 {                                                                       \
 538   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* NO_REGS */           \
 539   { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 },   /* SIBCALL_REGS */      \
 540   { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 },   /* JALR_REGS */         \
 541   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 },   /* GR_REGS */           \
 542   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 },   /* FP_REGS */           \
 543   { 0x00000000, 0x00000000, 0x00000003, 0x00000000 },   /* FRAME_REGS */        \
 544   { 0x00000000, 0x00000000, 0x00000000, 0x00000001 },   /* V0_REGS */           \
 545   { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe },   /* VNoV0_REGS */        \
 546   { 0x00000000, 0x00000000, 0x00000000, 0xffffffff },   /* V_REGS */            \
 547   { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff }    /* ALL_REGS */          \
 548 }
 549
 550 /* A C expression whose value is a register class containing hard
 551    register REGNO.  In general there is more that one such class;
 552    choose a class which is "minimal", meaning that no smaller class
 553    also contains the register.  */
 554
 555 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 556
 557 /* A macro whose definition is the name of the class to which a
 558    valid base register must belong.  A base register is one used in
 559    an address which is the register value plus a displacement.  */
 560
 561 #define BASE_REG_CLASS GR_REGS
 562
 563 /* A macro whose definition is the name of the class to which a
 564    valid index register must belong.  An index register is one used
 565    in an address where its value is either multiplied by a scale
 566    factor or added to another register (as well as added to a
 567    displacement).  */
 568
 569 #define INDEX_REG_CLASS riscv_index_reg_class()
 570
 571 /* We generally want to put call-clobbered registers ahead of
 572    call-saved ones.  (IRA expects this.)  */
 573
 574 #define REG_ALLOC_ORDER                                                 \
 575 { \
 576   /* Call-clobbered GPRs.  */                                           \
 577   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 578   /* Call-saved GPRs.  */                                               \
 579   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 580   /* GPRs that can never be exposed to the register allocator.  */      \
 581   0, 2, 3, 4,                                                           \
 582   /* Call-clobbered FPRs.  */                                           \
 583   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 584   60, 61, 62, 63,                                                       \
 585   /* Call-saved FPRs.  */                                               \
 586   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 587   /* v1 ~ v31 vector registers.  */                                     \
 588   97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,    \
 589   111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123,      \
 590   124, 125, 126, 127,                                                   \
 591   /* The vector mask register.  */                                      \
 592   96,                                                                   \
 593   /* None of the remaining classes have defined call-saved              \
 594      registers.  */                                                     \
 595   64, 65, 66, 67                                                        \
 596 }
 597
 598 /* True if VALUE is a signed 12-bit number.  */
 599
 600 #define SMALL_OPERAND(VALUE) \
 601   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 602
 603 #define POLY_SMALL_OPERAND_P(POLY_VALUE)                \
 604   (POLY_VALUE.is_constant () ?                          \
 605      SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
 606
 607 /* True if VALUE can be loaded into a register using LUI.  */
 608
 609 #define LUI_OPERAND(VALUE)                                              \
 610   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 611    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 612
 613 /* If this is a single bit mask, then we can load it with bseti.  Special
 614    handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
 615 #define SINGLE_BIT_MASK_OPERAND(VALUE)                                  \
 616   (pow2p_hwi (TARGET_64BIT                                              \
 617                 ? (VALUE)                                               \
 618                 : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1))))
 619
 620 /* True if VALUE can be represented as an immediate with 1 extra bit
 621    set: we check that it is not a SMALL_OPERAND (as this would be true
 622    for all small operands) unmodified and turns into a small operand
 623    once we clear the top bit. */
 624 #define UIMM_EXTRA_BIT_OPERAND(VALUE)                                   \
 625   (!SMALL_OPERAND (VALUE)                                               \
 626    && SMALL_OPERAND (VALUE & ~(HOST_WIDE_INT_1U << floor_log2 (VALUE))))
 627
 628 /* Stack layout; function entry, exit and calling.  */
 629
 630 #define STACK_GROWS_DOWNWARD 1
 631
 632 #define FRAME_GROWS_DOWNWARD 1
 633
 634 #define RETURN_ADDR_RTX riscv_return_addr
 635
 636 #define ELIMINABLE_REGS                                                 \
 637 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 638  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 639  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 640  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 641
 642 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 643   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 644
 645 /* Allocate stack space for arguments at the beginning of each function.  */
 646 #define ACCUMULATE_OUTGOING_ARGS 1
 647
 648 /* The argument pointer always points to the first argument.  */
 649 #define FIRST_PARM_OFFSET(FNDECL) 0
 650
 651 #define REG_PARM_STACK_SPACE(FNDECL) 0
 652
 653 /* Define this if it is the responsibility of the caller to
 654    allocate the area reserved for arguments passed in registers.
 655    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 656    of this macro is to determine whether the space is included in
 657    `crtl->outgoing_args_size'.  */
 658 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 659
 660 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 661
 662 /* Symbolic macros for the registers used to return integer and floating
 663    point values.  */
 664
 665 #define GP_RETURN GP_ARG_FIRST
 666 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 667
 668 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
 669
 670 #define MAX_ARGS_IN_VECTOR_REGISTERS (16)
 671 #define MAX_ARGS_IN_MASK_REGISTERS (1)
 672
 673 /* Symbolic macros for the first/last argument registers.  */
 674
 675 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 676 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 677 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 678 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 679 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 680 #define V_ARG_FIRST (V_REG_FIRST + 8)
 681 #define V_ARG_LAST (V_ARG_FIRST + MAX_ARGS_IN_VECTOR_REGISTERS - 1)
 682
 683 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 684   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 685    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 686
 687 #define CALLEE_SAVED_FREG_NUMBER(REGNO) CALLEE_SAVED_REG_NUMBER (REGNO - 32)
 688
 689 #define LIBCALL_VALUE(MODE) \
 690   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 691
 692 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 693   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 694
 695 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 696
 697 /* 1 if N is a possible register number for function argument passing.
 698    We have no FP argument registers when soft-float.  */
 699
 700 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 701 #define FUNCTION_ARG_REGNO_P(N)                                         \
 702   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 703    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 704
 705 /* Define the standard RISC-V calling convention and variants.  */
 706
 707 enum riscv_cc
 708 {
 709   RISCV_CC_BASE = 0, /* Base standard RISC-V ABI.  */
 710   RISCV_CC_V, /* For functions that pass or return values in V registers.  */
 711   RISCV_CC_UNKNOWN
 712 };
 713
 714 typedef struct {
 715   /* The calling convention that current function used.  */
 716   enum riscv_cc variant_cc;
 717
 718   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 719   unsigned int num_gprs;
 720
 721   /* Number of floating-point registers used so far, likewise.  */
 722   unsigned int num_fprs;
 723
 724   int rvv_psabi_warning;
 725
 726   /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS.  */
 727   unsigned int num_mrs;
 728
 729   /* The used state of args in vector registers, true for used by prev arg,
 730      initial to false.  */
 731   bool used_vrs[MAX_ARGS_IN_VECTOR_REGISTERS];
 732 } CUMULATIVE_ARGS;
 733
 734 /* Return riscv calling convention of call_insn.  */
 735 extern enum riscv_cc get_riscv_cc (const rtx use);
 736
 737 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 738    for a call to a function whose data type is FNTYPE.
 739    For a library call, FNTYPE is 0.  */
 740
 741 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 742   riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
 743                         (N_NAMED_ARGS) != -1)
 744
 745 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 746
 747 /* Align based on stack boundary, which might have been set by the user.  */
 748 #define RISCV_STACK_ALIGN(LOC) \
 749   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 750
 751 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 752    the stack pointer does not matter.  The value is tested only in
 753    functions that have frame pointers.
 754    No definition is equivalent to always zero.  */
 755
 756 #define EXIT_IGNORE_STACK 1
 757
 758
 759 /* Trampolines are a block of code followed by two pointers.  */
 760
 761 #define TRAMPOLINE_CODE_SIZE 16
 762 #define TRAMPOLINE_SIZE         \
 763   ((Pmode == SImode)            \
 764    ? TRAMPOLINE_CODE_SIZE       \
 765    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 766 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 767
 768 /* Addressing modes, and classification of registers for them.  */
 769
 770 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 771   riscv_regno_ok_for_index_p (REGNO)
 772
 773 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 774   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 775
 776 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 777    and check its validity for a certain class.
 778    We have two alternate definitions for each of them.
 779    The usual definition accepts all pseudo regs; the other rejects them all.
 780    The symbol REG_OK_STRICT causes the latter definition to be used.
 781
 782    Most source files want to accept pseudo regs in the hope that
 783    they will get allocated to the class that the insn wants them to be in.
 784    Some source files that are used after register allocation
 785    need to be strict.  */
 786
 787 #ifndef REG_OK_STRICT
 788 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 789   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 790 #else
 791 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 792   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 793 #endif
 794
 795 #define REG_OK_FOR_INDEX_P(X) 0
 796
 797 /* Maximum number of registers that can appear in a valid memory address.  */
 798
 799 #define MAX_REGS_PER_ADDRESS 1
 800
 801 #define CONSTANT_ADDRESS_P(X) \
 802   (CONSTANT_P (X) && memory_address_p (SImode, X))
 803
 804 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 805    'the start of the function that this code is output in'.  */
 806
 807 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 808   do {                                                                  \
 809     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 810       asm_fprintf ((FILE), "%U%s",                                      \
 811                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 812                                0), 0));                                 \
 813     else                                                                \
 814       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 815   } while (0)
 816
 817 #define JUMP_TABLES_IN_TEXT_SECTION 0
 818 #define CASE_VECTOR_MODE SImode
 819 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 820
 821 #define LOCAL_SYM_P(sym)                                                \
 822      ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))                  \
 823          || ((GET_CODE (sym) == CONST)                                  \
 824              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 825              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))
 826
 827 /* The load-address macro is used for PC-relative addressing of symbols
 828    that bind locally.  Don't use it for symbols that should be addressed
 829    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 830    currently results in more opportunities for linker relaxation.  */
 831 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 832   (!TARGET_EXPLICIT_RELOCS &&                                           \
 833    ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY))
 834
 835 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 836 #define DEFAULT_SIGNED_CHAR 0
 837
 838 #define MOVE_MAX UNITS_PER_WORD
 839 #define MAX_MOVE_MAX 8
 840
 841 /* The SPARC port says:
 842    Nonzero if access to memory by bytes is slow and undesirable.
 843    For RISC chips, it means that access to memory by bytes is no
 844    better than access by words when possible, so grab a whole word
 845    and maybe make use of that.  */
 846 #define SLOW_BYTE_ACCESS 1
 847
 848 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 849    in the md file instead.  */
 850 #define SHIFT_COUNT_TRUNCATED 0
 851
 852 /* Specify the machine mode that pointers have.
 853    After generation of rtl, the compiler makes no further distinction
 854    between pointers and any other objects of this machine mode.  */
 855
 856 #define Pmode word_mode
 857
 858 /* Specify the machine mode that registers have.  */
 859
 860 #define Xmode (TARGET_64BIT ? DImode : SImode)
 861
 862 /* Give call MEMs SImode since it is the "most permissive" mode
 863    for both 32-bit and 64-bit targets.  */
 864
 865 #define FUNCTION_MODE SImode
 866
 867 /* A C expression for the cost of a branch instruction.  A value of 2
 868    seems to minimize code size.  */
 869
 870 #define BRANCH_COST(speed_p, predictable_p) \
 871   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 872
 873 /* True if the target optimizes short forward branches around integer
 874    arithmetic instructions into predicated operations, e.g., for
 875    conditional-move operations.  The macro assumes that all branch
 876    instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
 877    support this feature.  The macro further assumes that any integer
 878    arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
 879    SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
 880    counterparts, including C.MV and C.LI) can be in the branch shadow.  */
 881
 882 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
 883
 884 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 885
 886 /* Control the assembler format that we output.  */
 887
 888 /* Output to assembler file text saying following lines
 889    may contain character constants, extra white space, comments, etc.  */
 890
 891 #ifndef ASM_APP_ON
 892 #define ASM_APP_ON " #APP\n"
 893 #endif
 894
 895 /* Output to assembler file text saying following lines
 896    no longer contain unusual constructs.  */
 897
 898 #ifndef ASM_APP_OFF
 899 #define ASM_APP_OFF " #NO_APP\n"
 900 #endif
 901
 902 #define REGISTER_NAMES                                          \
 903 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 904   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 905   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 906   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 907   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 908   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 909   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 910   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 911   "arg", "frame", "vl", "vtype", "vxrm", "frm", "N/A", "N/A",   \
 912   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 913   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 914   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 915   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",        \
 916   "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",       \
 917   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",       \
 918   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",}
 919
 920 #define ADDITIONAL_REGISTER_NAMES                                       \
 921 {                                                                       \
 922   { "x0",        0 + GP_REG_FIRST },                                    \
 923   { "x1",        1 + GP_REG_FIRST },                                    \
 924   { "x2",        2 + GP_REG_FIRST },                                    \
 925   { "x3",        3 + GP_REG_FIRST },                                    \
 926   { "x4",        4 + GP_REG_FIRST },                                    \
 927   { "x5",        5 + GP_REG_FIRST },                                    \
 928   { "x6",        6 + GP_REG_FIRST },                                    \
 929   { "x7",        7 + GP_REG_FIRST },                                    \
 930   { "x8",        8 + GP_REG_FIRST },                                    \
 931   { "x9",        9 + GP_REG_FIRST },                                    \
 932   { "x10",      10 + GP_REG_FIRST },                                    \
 933   { "x11",      11 + GP_REG_FIRST },                                    \
 934   { "x12",      12 + GP_REG_FIRST },                                    \
 935   { "x13",      13 + GP_REG_FIRST },                                    \
 936   { "x14",      14 + GP_REG_FIRST },                                    \
 937   { "x15",      15 + GP_REG_FIRST },                                    \
 938   { "x16",      16 + GP_REG_FIRST },                                    \
 939   { "x17",      17 + GP_REG_FIRST },                                    \
 940   { "x18",      18 + GP_REG_FIRST },                                    \
 941   { "x19",      19 + GP_REG_FIRST },                                    \
 942   { "x20",      20 + GP_REG_FIRST },                                    \
 943   { "x21",      21 + GP_REG_FIRST },                                    \
 944   { "x22",      22 + GP_REG_FIRST },                                    \
 945   { "x23",      23 + GP_REG_FIRST },                                    \
 946   { "x24",      24 + GP_REG_FIRST },                                    \
 947   { "x25",      25 + GP_REG_FIRST },                                    \
 948   { "x26",      26 + GP_REG_FIRST },                                    \
 949   { "x27",      27 + GP_REG_FIRST },                                    \
 950   { "x28",      28 + GP_REG_FIRST },                                    \
 951   { "x29",      29 + GP_REG_FIRST },                                    \
 952   { "x30",      30 + GP_REG_FIRST },                                    \
 953   { "x31",      31 + GP_REG_FIRST },                                    \
 954   { "f0",        0 + FP_REG_FIRST },                                    \
 955   { "f1",        1 + FP_REG_FIRST },                                    \
 956   { "f2",        2 + FP_REG_FIRST },                                    \
 957   { "f3",        3 + FP_REG_FIRST },                                    \
 958   { "f4",        4 + FP_REG_FIRST },                                    \
 959   { "f5",        5 + FP_REG_FIRST },                                    \
 960   { "f6",        6 + FP_REG_FIRST },                                    \
 961   { "f7",        7 + FP_REG_FIRST },                                    \
 962   { "f8",        8 + FP_REG_FIRST },                                    \
 963   { "f9",        9 + FP_REG_FIRST },                                    \
 964   { "f10",      10 + FP_REG_FIRST },                                    \
 965   { "f11",      11 + FP_REG_FIRST },                                    \
 966   { "f12",      12 + FP_REG_FIRST },                                    \
 967   { "f13",      13 + FP_REG_FIRST },                                    \
 968   { "f14",      14 + FP_REG_FIRST },                                    \
 969   { "f15",      15 + FP_REG_FIRST },                                    \
 970   { "f16",      16 + FP_REG_FIRST },                                    \
 971   { "f17",      17 + FP_REG_FIRST },                                    \
 972   { "f18",      18 + FP_REG_FIRST },                                    \
 973   { "f19",      19 + FP_REG_FIRST },                                    \
 974   { "f20",      20 + FP_REG_FIRST },                                    \
 975   { "f21",      21 + FP_REG_FIRST },                                    \
 976   { "f22",      22 + FP_REG_FIRST },                                    \
 977   { "f23",      23 + FP_REG_FIRST },                                    \
 978   { "f24",      24 + FP_REG_FIRST },                                    \
 979   { "f25",      25 + FP_REG_FIRST },                                    \
 980   { "f26",      26 + FP_REG_FIRST },                                    \
 981   { "f27",      27 + FP_REG_FIRST },                                    \
 982   { "f28",      28 + FP_REG_FIRST },                                    \
 983   { "f29",      29 + FP_REG_FIRST },                                    \
 984   { "f30",      30 + FP_REG_FIRST },                                    \
 985   { "f31",      31 + FP_REG_FIRST },                                    \
 986 }
 987
 988 /* Globalizing directive for a label.  */
 989 #define GLOBAL_ASM_OP "\t.globl\t"
 990
 991 /* This is how to store into the string LABEL
 992    the symbol_ref name of an internal numbered label where
 993    PREFIX is the class of label and NUM is the number within the class.
 994    This is suitable for output with `assemble_name'.  */
 995
 996 #undef ASM_GENERATE_INTERNAL_LABEL
 997 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 998   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 999
1000 /* This is how to output an element of a case-vector that is absolute.  */
1001
1002 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
1003   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
1004
1005 /* This is how to output an element of a PIC case-vector. */
1006
1007 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
1008   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
1009            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
1010
1011 /* This is how to output an assembler line
1012    that says to advance the location counter
1013    to a multiple of 2**LOG bytes.  */
1014
1015 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
1016   fprintf (STREAM, "\t.align\t%d\n", (LOG))
1017
1018 /* Define the strings to put out for each section in the object file.  */
1019 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
1020 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
1021 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
1022 #define BSS_SECTION_ASM_OP      "\t.bss"
1023 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
1024 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
1025
1026 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
1027 do                                                                      \
1028   {                                                                     \
1029     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
1030              reg_names[STACK_POINTER_REGNUM],                           \
1031              reg_names[STACK_POINTER_REGNUM],                           \
1032              TARGET_64BIT ? "sd" : "sw",                                \
1033              reg_names[REGNO],                                          \
1034              reg_names[STACK_POINTER_REGNUM]);                          \
1035   }                                                                     \
1036 while (0)
1037
1038 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
1039 do                                                                      \
1040   {                                                                     \
1041     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
1042              TARGET_64BIT ? "ld" : "lw",                                \
1043              reg_names[REGNO],                                          \
1044              reg_names[STACK_POINTER_REGNUM],                           \
1045              reg_names[STACK_POINTER_REGNUM],                           \
1046              reg_names[STACK_POINTER_REGNUM]);                          \
1047   }                                                                     \
1048 while (0)
1049
1050 #define ASM_COMMENT_START "#"
1051
1052 /* Add output .variant_cc directive for specific function definition.  */
1053 #undef ASM_DECLARE_FUNCTION_NAME
1054 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)                             \
1055   riscv_declare_function_name (STR, NAME, DECL)
1056
1057 /* Add output .variant_cc directive for specific alias definition.  */
1058 #undef ASM_OUTPUT_DEF_FROM_DECLS
1059 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET)                           \
1060   riscv_asm_output_alias (STR, DECL, TARGET)
1061
1062 /* Add output .variant_cc directive for specific extern function.  */
1063 #undef ASM_OUTPUT_EXTERNAL
1064 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME)                                   \
1065   riscv_asm_output_external (STR, DECL, NAME)
1066
1067 #undef SIZE_TYPE
1068 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
1069
1070 #undef PTRDIFF_TYPE
1071 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
1072
1073 /* The maximum number of bytes copied by one iteration of a cpymemsi loop.  */
1074
1075 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
1076
1077 /* The maximum number of bytes that can be copied by a straight-line
1078    cpymemsi implementation.  */
1079
1080 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
1081
1082 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1083    move-instruction pairs, we will do a cpymem or libcall instead.
1084    Do not use move_by_pieces at all when strict alignment is not
1085    in effect but the target has slow unaligned accesses; in this
1086    case, cpymem or libcall is more efficient.  */
1087
1088 #define MOVE_RATIO(speed)                                               \
1089   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
1090    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
1091    CLEAR_RATIO (speed) / 2)
1092
1093 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
1094    of the length of a memset call, but use the default otherwise.  */
1095
1096 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
1097
1098 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
1099    optimizing for size adjust the ratio to account for the overhead of
1100    loading the constant and replicating it across the word.  */
1101
1102 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
1103
1104 #ifndef USED_FOR_TARGET
1105 extern const enum reg_class riscv_regno_to_class[];
1106 extern bool riscv_slow_unaligned_access_p;
1107 extern bool riscv_user_wants_strict_align;
1108 extern unsigned riscv_stack_boundary;
1109 extern unsigned riscv_bytes_per_vector_chunk;
1110 extern poly_uint16 riscv_vector_chunks;
1111 extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int);
1112 extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int);
1113 extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
1114 extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
1115 /* The number of bits and bytes in a RVV vector.  */
1116 #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8))
1117 #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
1118 #endif
1119
1120 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1121   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
1122
1123 #define XLEN_SPEC \
1124   "%{march=rv32*:32}" \
1125   "%{march=rv64*:64}" \
1126
1127 #define ABI_SPEC \
1128   "%{mabi=ilp32:ilp32}" \
1129   "%{mabi=ilp32e:ilp32e}" \
1130   "%{mabi=ilp32f:ilp32f}" \
1131   "%{mabi=ilp32d:ilp32d}" \
1132   "%{mabi=lp64:lp64}" \
1133   "%{mabi=lp64f:lp64f}" \
1134   "%{mabi=lp64d:lp64d}" \
1135
1136 /* ISA constants needed for code generation.  */
1137 #define OPCODE_LW    0x2003
1138 #define OPCODE_LD    0x3003
1139 #define OPCODE_AUIPC 0x17
1140 #define OPCODE_JALR  0x67
1141 #define OPCODE_LUI   0x37
1142 #define OPCODE_ADDI  0x13
1143 #define SHIFT_RD  7
1144 #define SHIFT_RS1 15
1145 #define SHIFT_IMM 20
1146 #define IMM_BITS 12
1147 #define C_S_BITS 5
1148 #define C_SxSP_BITS 6
1149
1150 #define IMM_REACH (1LL << IMM_BITS)
1151 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
1152 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
1153
1154 #define SWSP_REACH (4LL << C_SxSP_BITS)
1155 #define SDSP_REACH (8LL << C_SxSP_BITS)
1156
1157 /* This is the maximum value that can be represented in a compressed load/store
1158    offset (an unsigned 5-bit value scaled by 4).  */
1159 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
1160
1161 /* Called from RISCV_REORG, this is defined in riscv-sr.cc.  */
1162
1163 extern void riscv_remove_unneeded_save_restore_calls (void);
1164
1165 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
1166
1167 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1168   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1169 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1170   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1171
1172 #define TARGET_SUPPORTS_WIDE_INT 1
1173
1174 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
1175
1176 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
1177
1178 #define RISCV_DWARF_VLENB (4096 + 0xc22)
1179
1180 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */)
1181
1182 #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
1183   ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO)
1184
1185 /* Like s390, riscv also defined this macro for the vector comparision.  Then
1186    the simplify-rtx relational_result will canonicalize the result to the
1187    CONST1_RTX for the simplification.  */
1188 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE))
1189
1190 /* Mode switching (Lazy code motion) for RVV rounding mode instructions.  */
1191 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
1192 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
1193
1194
1195 /* The size difference between different RVV modes can be up to 64 times.
1196    e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
1197 #define MAX_POLY_VARIANT 64
1198
1199 #endif /* ! GCC_RISCV_H */