gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2020 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Target CPU versions for D.  */
  31 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions
  32
  33 /* Default target_flags if no switches are specified  */
  34
  35 #ifndef TARGET_DEFAULT
  36 #define TARGET_DEFAULT 0
  37 #endif
  38
  39 #ifndef RISCV_TUNE_STRING_DEFAULT
  40 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  41 #endif
  42
  43 extern const char *riscv_expand_arch (int argc, const char **argv);
  44 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
  45 extern const char *riscv_default_mtune (int argc, const char **argv);
  46
  47 # define EXTRA_SPEC_FUNCTIONS                                           \
  48   { "riscv_expand_arch", riscv_expand_arch },                           \
  49   { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu },         \
  50   { "riscv_default_mtune", riscv_default_mtune },
  51
  52 /* Support for a compile-time default CPU, et cetera.  The rules are:
  53    --with-arch is ignored if -march or -mcpu is specified.
  54    --with-abi is ignored if -mabi is specified.
  55    --with-tune is ignored if -mtune or -mcpu is specified.
  56
  57    But using default -march/-mtune value if -mcpu don't have valid option.  */
  58 #define OPTION_DEFAULT_SPECS \
  59   {"tune", "%{!mtune=*:"                                                \
  60            "  %{!mcpu=*:-mtune=%(VALUE)}"                               \
  61            "  %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" },  \
  62   {"arch", "%{!march=*:"                                                \
  63            "  %{!mcpu=*:-march=%(VALUE)}"                               \
  64            "  %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" },  \
  65   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  66
  67 #ifdef IN_LIBGCC2
  68 #undef TARGET_64BIT
  69 /* Make this compile time constant for libgcc2 */
  70 #define TARGET_64BIT           (__riscv_xlen == 64)
  71 #endif /* IN_LIBGCC2 */
  72
  73 #undef ASM_SPEC
  74 #define ASM_SPEC "\
  75 %(subtarget_asm_debugging_spec) \
  76 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  77 %{march=*} \
  78 %{mabi=*} \
  79 %(subtarget_asm_spec)"
  80
  81 #undef DRIVER_SELF_SPECS
  82 #define DRIVER_SELF_SPECS                                       \
  83 "%{march=*:%:riscv_expand_arch(%*)} "                           \
  84 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
  85
  86 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
  87
  88 #define LOCAL_LABEL_PREFIX      "."
  89 #define USER_LABEL_PREFIX       ""
  90
  91 /* Offsets recorded in opcodes are a multiple of this alignment factor.
  92    The default for this in 64-bit mode is 8, which causes problems with
  93    SFmode register saves.  */
  94 #define DWARF_CIE_DATA_ALIGNMENT -4
  95
  96 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
  97 #define DWARF_FRAME_REGNUM(REGNO) \
  98   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
  99
 100 /* The DWARF 2 CFA column which tracks the return address.  */
 101 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
 102 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
 103
 104 /* Describe how we implement __builtin_eh_return.  */
 105 #define EH_RETURN_DATA_REGNO(N) \
 106   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 107
 108 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
 109
 110 /* Target machine storage layout */
 111
 112 #define BITS_BIG_ENDIAN 0
 113 #define BYTES_BIG_ENDIAN 0
 114 #define WORDS_BIG_ENDIAN 0
 115
 116 #define MAX_BITS_PER_WORD 64
 117
 118 /* Width of a word, in units (bytes).  */
 119 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 120 #ifndef IN_LIBGCC2
 121 #define MIN_UNITS_PER_WORD 4
 122 #endif
 123
 124 /* The `Q' extension is not yet supported.  */
 125 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 126
 127 /* The largest type that can be passed in floating-point registers.  */
 128 #define UNITS_PER_FP_ARG                                                \
 129   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 130     || riscv_abi == ABI_LP64)                                           \
 131    ? 0                                                                  \
 132    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 133
 134 /* Set the sizes of the core types.  */
 135 #define SHORT_TYPE_SIZE 16
 136 #define INT_TYPE_SIZE 32
 137 #define LONG_LONG_TYPE_SIZE 64
 138 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 139 #define LONG_TYPE_SIZE POINTER_SIZE
 140
 141 #define FLOAT_TYPE_SIZE 32
 142 #define DOUBLE_TYPE_SIZE 64
 143 #define LONG_DOUBLE_TYPE_SIZE 128
 144
 145 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 146 #define PARM_BOUNDARY BITS_PER_WORD
 147
 148 /* Allocation boundary (in *bits*) for the code of a function.  */
 149 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 150
 151 /* The smallest supported stack boundary the calling convention supports.  */
 152 #define STACK_BOUNDARY \
 153   (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
 154
 155 /* The ABI stack alignment.  */
 156 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
 157
 158 /* There is no point aligning anything to a rounder boundary than this.  */
 159 #define BIGGEST_ALIGNMENT 128
 160
 161 /* The user-level ISA permits unaligned accesses, but they are not required
 162    of the privileged architecture.  */
 163 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 164
 165 /* Define this if you wish to imitate the way many other C compilers
 166    handle alignment of bitfields and the structures that contain
 167    them.
 168
 169    The behavior is that the type written for a bit-field (`int',
 170    `short', or other integer type) imposes an alignment for the
 171    entire structure, as if the structure really did contain an
 172    ordinary field of that type.  In addition, the bit-field is placed
 173    within the structure so that it would fit within such a field,
 174    not crossing a boundary for it.
 175
 176    Thus, on most machines, a bit-field whose type is written as `int'
 177    would not cross a four-byte boundary, and would force four-byte
 178    alignment for the whole structure.  (The alignment used may not
 179    be four bytes; it is controlled by the other alignment
 180    parameters.)
 181
 182    If the macro is defined, its definition should be a C expression;
 183    a nonzero value for the expression enables this behavior.  */
 184
 185 #define PCC_BITFIELD_TYPE_MATTERS 1
 186
 187 /* An integer expression for the size in bits of the largest integer machine
 188    mode that should actually be used.  We allow pairs of registers.  */
 189 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 190
 191 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
 192 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)                       \
 193   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 194     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 195         || TREE_CODE (TYPE) == UNION_TYPE                               \
 196         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 197
 198 /* If defined, a C expression to compute the alignment for a static
 199    variable.  TYPE is the data type, and ALIGN is the alignment that
 200    the object would ordinarily have.  The value of this macro is used
 201    instead of that alignment to align the object.
 202
 203    If this macro is not defined, then ALIGN is used.
 204
 205    One use of this macro is to increase alignment of medium-size
 206    data to make it all fit in fewer cache lines.  Another is to
 207    cause character arrays to be word-aligned so that `strcpy' calls
 208    that copy constants to character arrays can be done inline.  */
 209
 210 #define DATA_ALIGNMENT(TYPE, ALIGN)                                             \
 211   RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,  \
 212                           TYPE, ALIGN)
 213
 214 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 215    character arrays to be word-aligned so that `strcpy' calls that copy
 216    constants to character arrays can be done inline, and 'strcmp' can be
 217    optimised to use word loads. */
 218 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 219   RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
 220
 221 /* Define if operations between registers always perform the operation
 222    on the full register even if a narrower mode is specified.  */
 223 #define WORD_REGISTER_OPERATIONS 1
 224
 225 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 226    moves.  All other references are zero extended.  */
 227 #define LOAD_EXTEND_OP(MODE) \
 228   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 229
 230 /* Define this macro if it is advisable to hold scalars in registers
 231    in a wider mode than that declared by the program.  In such cases,
 232    the value is constrained to be within the bounds of the declared
 233    type, but kept valid in the wider mode.  The signedness of the
 234    extension may differ from that of the type.  */
 235
 236 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 237   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 238       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 239     {                                           \
 240       if ((MODE) == SImode)                     \
 241         (UNSIGNEDP) = 0;                        \
 242       (MODE) = word_mode;                       \
 243     }
 244
 245 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 246    Extensions of pointers to word_mode must be signed.  */
 247 #define POINTERS_EXTEND_UNSIGNED false
 248
 249 /* Define if loading short immediate values into registers sign extends.  */
 250 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 251
 252 /* Standard register usage.  */
 253
 254 /* Number of hardware registers.  We have:
 255
 256    - 32 integer registers
 257    - 32 floating point registers
 258    - 2 fake registers:
 259         - ARG_POINTER_REGNUM
 260         - FRAME_POINTER_REGNUM */
 261
 262 #define FIRST_PSEUDO_REGISTER 66
 263
 264 /* x0, sp, gp, and tp are fixed.  */
 265
 266 #define FIXED_REGISTERS                                                 \
 267 { /* General registers.  */                                             \
 268   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 269   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 270   /* Floating-point registers.  */                                      \
 271   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 272   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 273   /* Others.  */                                                        \
 274   1, 1                                                                  \
 275 }
 276
 277 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 278    The call RTLs themselves clobber ra.  */
 279
 280 #define CALL_USED_REGISTERS                                             \
 281 { /* General registers.  */                                             \
 282   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 283   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 284   /* Floating-point registers.  */                                      \
 285   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 286   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 287   /* Others.  */                                                        \
 288   1, 1                                                                  \
 289 }
 290
 291 /* Select a register mode required for caller save of hard regno REGNO.
 292    Contrary to what is documented, the default is not the smallest suitable
 293    mode but the largest suitable mode for the given (REGNO, NREGS) pair and
 294    it quickly creates paradoxical subregs that can be problematic.  */
 295 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 296   ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
 297
 298 /* Internal macros to classify an ISA register's type.  */
 299
 300 #define GP_REG_FIRST 0
 301 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 302 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 303
 304 #define FP_REG_FIRST 32
 305 #define FP_REG_LAST  63
 306 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 307
 308 /* The DWARF 2 CFA column which tracks the return address from a
 309    signal handler context.  This means that to maintain backwards
 310    compatibility, no hard register can be assigned this column if it
 311    would need to be handled by the DWARF unwinder.  */
 312 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 313
 314 #define GP_REG_P(REGNO) \
 315   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 316 #define FP_REG_P(REGNO)  \
 317   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 318
 319 /* True when REGNO is in SIBCALL_REGS set.  */
 320 #define SIBCALL_REG_P(REGNO)    \
 321   TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
 322
 323 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 324
 325 /* Use s0 as the frame pointer if it is so requested.  */
 326 #define HARD_FRAME_POINTER_REGNUM 8
 327 #define STACK_POINTER_REGNUM 2
 328 #define THREAD_POINTER_REGNUM 4
 329
 330 /* These two registers don't really exist: they get eliminated to either
 331    the stack or hard frame pointer.  */
 332 #define ARG_POINTER_REGNUM 64
 333 #define FRAME_POINTER_REGNUM 65
 334
 335 /* Register in which static-chain is passed to a function.  */
 336 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 337
 338 /* Registers used as temporaries in prologue/epilogue code.
 339
 340    The prologue registers mustn't conflict with any
 341    incoming arguments, the static chain pointer, or the frame pointer.
 342    The epilogue temporary mustn't conflict with the return registers,
 343    the frame pointer, the EH stack adjustment, or the EH data registers. */
 344
 345 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
 346 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 347
 348 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 349 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
 350   gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
 351
 352 #define MCOUNT_NAME "_mcount"
 353
 354 #define NO_PROFILE_COUNTERS 1
 355
 356 /* Emit rtl for profiling.  Output assembler code to FILE
 357    to call "_mcount" for profiling a function entry.  */
 358 #define PROFILE_HOOK(LABEL)                                             \
 359   {                                                                     \
 360     rtx fun, ra;                                                        \
 361     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 362     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 363     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 364   }
 365
 366 /* All the work done in PROFILE_HOOK, but still required.  */
 367 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 368
 369 /* Define this macro if it is as good or better to call a constant
 370    function address than to call an address kept in a register.  */
 371 #define NO_FUNCTION_CSE 1
 372
 373 /* Define the classes of registers for register constraints in the
 374    machine description.  Also define ranges of constants.
 375
 376    One of the classes must always be named ALL_REGS and include all hard regs.
 377    If there is more than one class, another class must be named NO_REGS
 378    and contain no registers.
 379
 380    The name GENERAL_REGS must be the name of a class (or an alias for
 381    another name such as ALL_REGS).  This is the class of registers
 382    that is allowed by "g" or "r" in a register constraint.
 383    Also, registers outside this class are allocated only when
 384    instructions express preferences for them.
 385
 386    The classes must be numbered in nondecreasing order; that is,
 387    a larger-numbered class must never be contained completely
 388    in a smaller-numbered class.
 389
 390    For any two classes, it is very desirable that there be another
 391    class that represents their union.  */
 392
 393 enum reg_class
 394 {
 395   NO_REGS,                      /* no registers in set */
 396   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 397   JALR_REGS,                    /* registers used by indirect calls */
 398   GR_REGS,                      /* integer registers */
 399   FP_REGS,                      /* floating-point registers */
 400   FRAME_REGS,                   /* arg pointer and frame pointer */
 401   ALL_REGS,                     /* all registers */
 402   LIM_REG_CLASSES               /* max value + 1 */
 403 };
 404
 405 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 406
 407 #define GENERAL_REGS GR_REGS
 408
 409 /* An initializer containing the names of the register classes as C
 410    string constants.  These names are used in writing some of the
 411    debugging dumps.  */
 412
 413 #define REG_CLASS_NAMES                                                 \
 414 {                                                                       \
 415   "NO_REGS",                                                            \
 416   "SIBCALL_REGS",                                                       \
 417   "JALR_REGS",                                                          \
 418   "GR_REGS",                                                            \
 419   "FP_REGS",                                                            \
 420   "FRAME_REGS",                                                         \
 421   "ALL_REGS"                                                            \
 422 }
 423
 424 /* An initializer containing the contents of the register classes,
 425    as integers which are bit masks.  The Nth integer specifies the
 426    contents of class N.  The way the integer MASK is interpreted is
 427    that register R is in the class if `MASK & (1 << R)' is 1.
 428
 429    When the machine has more than 32 registers, an integer does not
 430    suffice.  Then the integers are replaced by sub-initializers,
 431    braced groupings containing several integers.  Each
 432    sub-initializer must be suitable as an initializer for the type
 433    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 434
 435 #define REG_CLASS_CONTENTS                                              \
 436 {                                                                       \
 437   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 438   { 0xf003fcc0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 439   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 440   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 441   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 442   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 443   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 444 }
 445
 446 /* A C expression whose value is a register class containing hard
 447    register REGNO.  In general there is more that one such class;
 448    choose a class which is "minimal", meaning that no smaller class
 449    also contains the register.  */
 450
 451 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 452
 453 /* A macro whose definition is the name of the class to which a
 454    valid base register must belong.  A base register is one used in
 455    an address which is the register value plus a displacement.  */
 456
 457 #define BASE_REG_CLASS GR_REGS
 458
 459 /* A macro whose definition is the name of the class to which a
 460    valid index register must belong.  An index register is one used
 461    in an address where its value is either multiplied by a scale
 462    factor or added to another register (as well as added to a
 463    displacement).  */
 464
 465 #define INDEX_REG_CLASS NO_REGS
 466
 467 /* We generally want to put call-clobbered registers ahead of
 468    call-saved ones.  (IRA expects this.)  */
 469
 470 #define REG_ALLOC_ORDER                                                 \
 471 { \
 472   /* Call-clobbered GPRs.  */                                           \
 473   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 474   /* Call-saved GPRs.  */                                               \
 475   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 476   /* GPRs that can never be exposed to the register allocator.  */      \
 477   0, 2, 3, 4,                                                           \
 478   /* Call-clobbered FPRs.  */                                           \
 479   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 480   60, 61, 62, 63,                                                       \
 481   /* Call-saved FPRs.  */                                               \
 482   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 483   /* None of the remaining classes have defined call-saved              \
 484      registers.  */                                                     \
 485   64, 65                                                                \
 486 }
 487
 488 /* True if VALUE is a signed 12-bit number.  */
 489
 490 #define SMALL_OPERAND(VALUE) \
 491   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 492
 493 /* True if VALUE can be loaded into a register using LUI.  */
 494
 495 #define LUI_OPERAND(VALUE)                                              \
 496   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 497    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 498
 499 /* Stack layout; function entry, exit and calling.  */
 500
 501 #define STACK_GROWS_DOWNWARD 1
 502
 503 #define FRAME_GROWS_DOWNWARD 1
 504
 505 #define RETURN_ADDR_RTX riscv_return_addr
 506
 507 #define ELIMINABLE_REGS                                                 \
 508 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 509  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 510  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 511  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 512
 513 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 514   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 515
 516 /* Allocate stack space for arguments at the beginning of each function.  */
 517 #define ACCUMULATE_OUTGOING_ARGS 1
 518
 519 /* The argument pointer always points to the first argument.  */
 520 #define FIRST_PARM_OFFSET(FNDECL) 0
 521
 522 #define REG_PARM_STACK_SPACE(FNDECL) 0
 523
 524 /* Define this if it is the responsibility of the caller to
 525    allocate the area reserved for arguments passed in registers.
 526    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 527    of this macro is to determine whether the space is included in
 528    `crtl->outgoing_args_size'.  */
 529 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 530
 531 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 532
 533 /* Symbolic macros for the registers used to return integer and floating
 534    point values.  */
 535
 536 #define GP_RETURN GP_ARG_FIRST
 537 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 538
 539 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
 540
 541 /* Symbolic macros for the first/last argument registers.  */
 542
 543 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 544 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 545 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 546 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 547 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 548
 549 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 550   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 551    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 552
 553 #define LIBCALL_VALUE(MODE) \
 554   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 555
 556 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 557   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 558
 559 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 560
 561 /* 1 if N is a possible register number for function argument passing.
 562    We have no FP argument registers when soft-float.  */
 563
 564 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 565 #define FUNCTION_ARG_REGNO_P(N)                                         \
 566   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 567    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 568
 569 typedef struct {
 570   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 571   unsigned int num_gprs;
 572
 573   /* Number of floating-point registers used so far, likewise.  */
 574   unsigned int num_fprs;
 575 } CUMULATIVE_ARGS;
 576
 577 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 578    for a call to a function whose data type is FNTYPE.
 579    For a library call, FNTYPE is 0.  */
 580
 581 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 582   memset (&(CUM), 0, sizeof (CUM))
 583
 584 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 585
 586 /* Align based on stack boundary, which might have been set by the user.  */
 587 #define RISCV_STACK_ALIGN(LOC) \
 588   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 589
 590 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 591    the stack pointer does not matter.  The value is tested only in
 592    functions that have frame pointers.
 593    No definition is equivalent to always zero.  */
 594
 595 #define EXIT_IGNORE_STACK 1
 596
 597
 598 /* Trampolines are a block of code followed by two pointers.  */
 599
 600 #define TRAMPOLINE_CODE_SIZE 16
 601 #define TRAMPOLINE_SIZE         \
 602   ((Pmode == SImode)            \
 603    ? TRAMPOLINE_CODE_SIZE       \
 604    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 605 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 606
 607 /* Addressing modes, and classification of registers for them.  */
 608
 609 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 610 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 611   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 612
 613 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 614    and check its validity for a certain class.
 615    We have two alternate definitions for each of them.
 616    The usual definition accepts all pseudo regs; the other rejects them all.
 617    The symbol REG_OK_STRICT causes the latter definition to be used.
 618
 619    Most source files want to accept pseudo regs in the hope that
 620    they will get allocated to the class that the insn wants them to be in.
 621    Some source files that are used after register allocation
 622    need to be strict.  */
 623
 624 #ifndef REG_OK_STRICT
 625 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 626   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 627 #else
 628 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 629   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 630 #endif
 631
 632 #define REG_OK_FOR_INDEX_P(X) 0
 633
 634 /* Maximum number of registers that can appear in a valid memory address.  */
 635
 636 #define MAX_REGS_PER_ADDRESS 1
 637
 638 #define CONSTANT_ADDRESS_P(X) \
 639   (CONSTANT_P (X) && memory_address_p (SImode, X))
 640
 641 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 642    'the start of the function that this code is output in'.  */
 643
 644 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 645   do {                                                                  \
 646     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 647       asm_fprintf ((FILE), "%U%s",                                      \
 648                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 649                                0), 0));                                 \
 650     else                                                                \
 651       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 652   } while (0)
 653
 654 #define JUMP_TABLES_IN_TEXT_SECTION 0
 655 #define CASE_VECTOR_MODE SImode
 656 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 657
 658 /* The load-address macro is used for PC-relative addressing of symbols
 659    that bind locally.  Don't use it for symbols that should be addressed
 660    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 661    currently results in more opportunities for linker relaxation.  */
 662 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 663   (!TARGET_EXPLICIT_RELOCS &&                                           \
 664    ((flag_pic                                                           \
 665      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 666          || ((GET_CODE (sym) == CONST)                                  \
 667              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 668              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 669      || riscv_cmodel == CM_MEDANY))
 670
 671 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 672 #define DEFAULT_SIGNED_CHAR 0
 673
 674 #define MOVE_MAX UNITS_PER_WORD
 675 #define MAX_MOVE_MAX 8
 676
 677 /* The SPARC port says:
 678    Nonzero if access to memory by bytes is slow and undesirable.
 679    For RISC chips, it means that access to memory by bytes is no
 680    better than access by words when possible, so grab a whole word
 681    and maybe make use of that.  */
 682 #define SLOW_BYTE_ACCESS 1
 683
 684 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 685    in the md file instead.  */
 686 #define SHIFT_COUNT_TRUNCATED 0
 687
 688 /* Specify the machine mode that pointers have.
 689    After generation of rtl, the compiler makes no further distinction
 690    between pointers and any other objects of this machine mode.  */
 691
 692 #define Pmode word_mode
 693
 694 /* Give call MEMs SImode since it is the "most permissive" mode
 695    for both 32-bit and 64-bit targets.  */
 696
 697 #define FUNCTION_MODE SImode
 698
 699 /* A C expression for the cost of a branch instruction.  A value of 2
 700    seems to minimize code size.  */
 701
 702 #define BRANCH_COST(speed_p, predictable_p) \
 703   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 704
 705 /* True if the target optimizes short forward branches around integer
 706    arithmetic instructions into predicated operations, e.g., for
 707    conditional-move operations.  The macro assumes that all branch
 708    instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
 709    support this feature.  The macro further assumes that any integer
 710    arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
 711    SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
 712    counterparts, including C.MV and C.LI) can be in the branch shadow.  */
 713
 714 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
 715
 716 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 717
 718 /* Control the assembler format that we output.  */
 719
 720 /* Output to assembler file text saying following lines
 721    may contain character constants, extra white space, comments, etc.  */
 722
 723 #ifndef ASM_APP_ON
 724 #define ASM_APP_ON " #APP\n"
 725 #endif
 726
 727 /* Output to assembler file text saying following lines
 728    no longer contain unusual constructs.  */
 729
 730 #ifndef ASM_APP_OFF
 731 #define ASM_APP_OFF " #NO_APP\n"
 732 #endif
 733
 734 #define REGISTER_NAMES                                          \
 735 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 736   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 737   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 738   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 739   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 740   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 741   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 742   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 743   "arg", "frame", }
 744
 745 #define ADDITIONAL_REGISTER_NAMES                                       \
 746 {                                                                       \
 747   { "x0",        0 + GP_REG_FIRST },                                    \
 748   { "x1",        1 + GP_REG_FIRST },                                    \
 749   { "x2",        2 + GP_REG_FIRST },                                    \
 750   { "x3",        3 + GP_REG_FIRST },                                    \
 751   { "x4",        4 + GP_REG_FIRST },                                    \
 752   { "x5",        5 + GP_REG_FIRST },                                    \
 753   { "x6",        6 + GP_REG_FIRST },                                    \
 754   { "x7",        7 + GP_REG_FIRST },                                    \
 755   { "x8",        8 + GP_REG_FIRST },                                    \
 756   { "x9",        9 + GP_REG_FIRST },                                    \
 757   { "x10",      10 + GP_REG_FIRST },                                    \
 758   { "x11",      11 + GP_REG_FIRST },                                    \
 759   { "x12",      12 + GP_REG_FIRST },                                    \
 760   { "x13",      13 + GP_REG_FIRST },                                    \
 761   { "x14",      14 + GP_REG_FIRST },                                    \
 762   { "x15",      15 + GP_REG_FIRST },                                    \
 763   { "x16",      16 + GP_REG_FIRST },                                    \
 764   { "x17",      17 + GP_REG_FIRST },                                    \
 765   { "x18",      18 + GP_REG_FIRST },                                    \
 766   { "x19",      19 + GP_REG_FIRST },                                    \
 767   { "x20",      20 + GP_REG_FIRST },                                    \
 768   { "x21",      21 + GP_REG_FIRST },                                    \
 769   { "x22",      22 + GP_REG_FIRST },                                    \
 770   { "x23",      23 + GP_REG_FIRST },                                    \
 771   { "x24",      24 + GP_REG_FIRST },                                    \
 772   { "x25",      25 + GP_REG_FIRST },                                    \
 773   { "x26",      26 + GP_REG_FIRST },                                    \
 774   { "x27",      27 + GP_REG_FIRST },                                    \
 775   { "x28",      28 + GP_REG_FIRST },                                    \
 776   { "x29",      29 + GP_REG_FIRST },                                    \
 777   { "x30",      30 + GP_REG_FIRST },                                    \
 778   { "x31",      31 + GP_REG_FIRST },                                    \
 779   { "f0",        0 + FP_REG_FIRST },                                    \
 780   { "f1",        1 + FP_REG_FIRST },                                    \
 781   { "f2",        2 + FP_REG_FIRST },                                    \
 782   { "f3",        3 + FP_REG_FIRST },                                    \
 783   { "f4",        4 + FP_REG_FIRST },                                    \
 784   { "f5",        5 + FP_REG_FIRST },                                    \
 785   { "f6",        6 + FP_REG_FIRST },                                    \
 786   { "f7",        7 + FP_REG_FIRST },                                    \
 787   { "f8",        8 + FP_REG_FIRST },                                    \
 788   { "f9",        9 + FP_REG_FIRST },                                    \
 789   { "f10",      10 + FP_REG_FIRST },                                    \
 790   { "f11",      11 + FP_REG_FIRST },                                    \
 791   { "f12",      12 + FP_REG_FIRST },                                    \
 792   { "f13",      13 + FP_REG_FIRST },                                    \
 793   { "f14",      14 + FP_REG_FIRST },                                    \
 794   { "f15",      15 + FP_REG_FIRST },                                    \
 795   { "f16",      16 + FP_REG_FIRST },                                    \
 796   { "f17",      17 + FP_REG_FIRST },                                    \
 797   { "f18",      18 + FP_REG_FIRST },                                    \
 798   { "f19",      19 + FP_REG_FIRST },                                    \
 799   { "f20",      20 + FP_REG_FIRST },                                    \
 800   { "f21",      21 + FP_REG_FIRST },                                    \
 801   { "f22",      22 + FP_REG_FIRST },                                    \
 802   { "f23",      23 + FP_REG_FIRST },                                    \
 803   { "f24",      24 + FP_REG_FIRST },                                    \
 804   { "f25",      25 + FP_REG_FIRST },                                    \
 805   { "f26",      26 + FP_REG_FIRST },                                    \
 806   { "f27",      27 + FP_REG_FIRST },                                    \
 807   { "f28",      28 + FP_REG_FIRST },                                    \
 808   { "f29",      29 + FP_REG_FIRST },                                    \
 809   { "f30",      30 + FP_REG_FIRST },                                    \
 810   { "f31",      31 + FP_REG_FIRST },                                    \
 811 }
 812
 813 /* Globalizing directive for a label.  */
 814 #define GLOBAL_ASM_OP "\t.globl\t"
 815
 816 /* This is how to store into the string LABEL
 817    the symbol_ref name of an internal numbered label where
 818    PREFIX is the class of label and NUM is the number within the class.
 819    This is suitable for output with `assemble_name'.  */
 820
 821 #undef ASM_GENERATE_INTERNAL_LABEL
 822 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 823   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 824
 825 /* This is how to output an element of a case-vector that is absolute.  */
 826
 827 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 828   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 829
 830 /* This is how to output an element of a PIC case-vector. */
 831
 832 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 833   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 834            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 835
 836 /* This is how to output an assembler line
 837    that says to advance the location counter
 838    to a multiple of 2**LOG bytes.  */
 839
 840 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 841   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 842
 843 /* Define the strings to put out for each section in the object file.  */
 844 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 845 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 846 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 847 #define BSS_SECTION_ASM_OP      "\t.bss"
 848 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 849 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 850
 851 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 852 do                                                                      \
 853   {                                                                     \
 854     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 855              reg_names[STACK_POINTER_REGNUM],                           \
 856              reg_names[STACK_POINTER_REGNUM],                           \
 857              TARGET_64BIT ? "sd" : "sw",                                \
 858              reg_names[REGNO],                                          \
 859              reg_names[STACK_POINTER_REGNUM]);                          \
 860   }                                                                     \
 861 while (0)
 862
 863 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 864 do                                                                      \
 865   {                                                                     \
 866     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 867              TARGET_64BIT ? "ld" : "lw",                                \
 868              reg_names[REGNO],                                          \
 869              reg_names[STACK_POINTER_REGNUM],                           \
 870              reg_names[STACK_POINTER_REGNUM],                           \
 871              reg_names[STACK_POINTER_REGNUM]);                          \
 872   }                                                                     \
 873 while (0)
 874
 875 #define ASM_COMMENT_START "#"
 876
 877 #undef SIZE_TYPE
 878 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 879
 880 #undef PTRDIFF_TYPE
 881 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 882
 883 /* The maximum number of bytes copied by one iteration of a cpymemsi loop.  */
 884
 885 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
 886
 887 /* The maximum number of bytes that can be copied by a straight-line
 888    cpymemsi implementation.  */
 889
 890 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
 891
 892 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 893    move-instruction pairs, we will do a cpymem or libcall instead.
 894    Do not use move_by_pieces at all when strict alignment is not
 895    in effect but the target has slow unaligned accesses; in this
 896    case, cpymem or libcall is more efficient.  */
 897
 898 #define MOVE_RATIO(speed)                                               \
 899   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
 900    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
 901    CLEAR_RATIO (speed) / 2)
 902
 903 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 904    of the length of a memset call, but use the default otherwise.  */
 905
 906 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 907
 908 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 909    optimizing for size adjust the ratio to account for the overhead of
 910    loading the constant and replicating it across the word.  */
 911
 912 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 913
 914 #ifndef USED_FOR_TARGET
 915 extern const enum reg_class riscv_regno_to_class[];
 916 extern bool riscv_slow_unaligned_access_p;
 917 extern unsigned riscv_stack_boundary;
 918 #endif
 919
 920 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 921   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 922
 923 #define XLEN_SPEC \
 924   "%{march=rv32*:32}" \
 925   "%{march=rv64*:64}" \
 926
 927 #define ABI_SPEC \
 928   "%{mabi=ilp32:ilp32}" \
 929   "%{mabi=ilp32e:ilp32e}" \
 930   "%{mabi=ilp32f:ilp32f}" \
 931   "%{mabi=ilp32d:ilp32d}" \
 932   "%{mabi=lp64:lp64}" \
 933   "%{mabi=lp64f:lp64f}" \
 934   "%{mabi=lp64d:lp64d}" \
 935
 936 /* ISA constants needed for code generation.  */
 937 #define OPCODE_LW    0x2003
 938 #define OPCODE_LD    0x3003
 939 #define OPCODE_AUIPC 0x17
 940 #define OPCODE_JALR  0x67
 941 #define OPCODE_LUI   0x37
 942 #define OPCODE_ADDI  0x13
 943 #define SHIFT_RD  7
 944 #define SHIFT_RS1 15
 945 #define SHIFT_IMM 20
 946 #define IMM_BITS 12
 947 #define C_S_BITS 5
 948 #define C_SxSP_BITS 6
 949
 950 #define IMM_REACH (1LL << IMM_BITS)
 951 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 952 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 953
 954 #define SWSP_REACH (4LL << C_SxSP_BITS)
 955 #define SDSP_REACH (8LL << C_SxSP_BITS)
 956
 957 /* This is the maximum value that can be represented in a compressed load/store
 958    offset (an unsigned 5-bit value scaled by 4).  */
 959 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
 960
 961 /* Called from RISCV_REORG, this is defined in riscv-sr.c.  */
 962
 963 extern void riscv_remove_unneeded_save_restore_calls (void);
 964
 965 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
 966
 967 #endif /* ! GCC_RISCV_H */