gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2023 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include <stdbool.h>
  26 #include "config/riscv/riscv-opts.h"
  27
  28 #define SWITCHABLE_TARGET 1
  29
  30 /* Target CPU builtins.  */
  31 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  32
  33 #ifdef TARGET_BIG_ENDIAN_DEFAULT
  34 #define DEFAULT_ENDIAN_SPEC    "b"
  35 #else
  36 #define DEFAULT_ENDIAN_SPEC    "l"
  37 #endif
  38
  39 /* Default target_flags if no switches are specified  */
  40
  41 #ifndef TARGET_DEFAULT
  42 #define TARGET_DEFAULT 0
  43 #endif
  44
  45 #ifndef RISCV_TUNE_STRING_DEFAULT
  46 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  47 #endif
  48
  49 extern const char *riscv_expand_arch (int argc, const char **argv);
  50 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
  51 extern const char *riscv_default_mtune (int argc, const char **argv);
  52 extern const char *riscv_multi_lib_check (int argc, const char **argv);
  53
  54 # define EXTRA_SPEC_FUNCTIONS                                           \
  55   { "riscv_expand_arch", riscv_expand_arch },                           \
  56   { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu },         \
  57   { "riscv_default_mtune", riscv_default_mtune },                       \
  58   { "riscv_multi_lib_check", riscv_multi_lib_check },
  59
  60 /* Support for a compile-time default CPU, et cetera.  The rules are:
  61    --with-arch is ignored if -march or -mcpu is specified.
  62    --with-abi is ignored if -mabi is specified.
  63    --with-tune is ignored if -mtune or -mcpu is specified.
  64    --with-isa-spec is ignored if -misa-spec is specified.
  65
  66    But using default -march/-mtune value if -mcpu don't have valid option.  */
  67 #define OPTION_DEFAULT_SPECS \
  68   {"tune", "%{!mtune=*:"                                                \
  69            "  %{!mcpu=*:-mtune=%(VALUE)}"                               \
  70            "  %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" },  \
  71   {"arch", "%{!march=*:"                                                \
  72            "  %{!mcpu=*:-march=%(VALUE)}"                               \
  73            "  %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" },  \
  74   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  75   {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
  76
  77 #ifdef IN_LIBGCC2
  78 #undef TARGET_64BIT
  79 /* Make this compile time constant for libgcc2 */
  80 #define TARGET_64BIT           (__riscv_xlen == 64)
  81 #endif /* IN_LIBGCC2 */
  82
  83 #ifdef HAVE_AS_MISA_SPEC
  84 #define ASM_MISA_SPEC "%{misa-spec=*}"
  85 #else
  86 #define ASM_MISA_SPEC ""
  87 #endif
  88
  89 /* Reference:
  90      https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing  */
  91 #define STRINGIZING(s) __STRINGIZING(s)
  92 #define __STRINGIZING(s) #s
  93
  94 #define MULTILIB_DEFAULTS \
  95   {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \
  96    "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) }
  97
  98 #undef ASM_SPEC
  99 #define ASM_SPEC "\
 100 %(subtarget_asm_debugging_spec) \
 101 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
 102 %{march=*} \
 103 %{mabi=*} \
 104 %{mno-relax} \
 105 %{mbig-endian} \
 106 %{mlittle-endian} \
 107 %(subtarget_asm_spec)" \
 108 ASM_MISA_SPEC
 109
 110 #undef DRIVER_SELF_SPECS
 111 #define DRIVER_SELF_SPECS                                       \
 112 "%{march=*:%:riscv_expand_arch(%*)} "                           \
 113 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
 114
 115 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
 116
 117 #define LOCAL_LABEL_PREFIX      "."
 118 #define USER_LABEL_PREFIX       ""
 119
 120 /* Offsets recorded in opcodes are a multiple of this alignment factor.
 121    The default for this in 64-bit mode is 8, which causes problems with
 122    SFmode register saves.  */
 123 #define DWARF_CIE_DATA_ALIGNMENT -4
 124
 125 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 126 #define DWARF_FRAME_REGNUM(REGNO)                                              \
 127   (FRM_REG_P (REGNO)    ? RISCV_DWARF_FRM                                      \
 128    : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM                                     \
 129    : VL_REG_P (REGNO)   ? RISCV_DWARF_VL                                       \
 130    : VTYPE_REG_P (REGNO)                                                       \
 131      ? RISCV_DWARF_VTYPE                                                       \
 132      : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO)                \
 133           ? REGNO                                                              \
 134           : INVALID_REGNUM))
 135
 136 /* The DWARF 2 CFA column which tracks the return address.  */
 137 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
 138 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
 139
 140 /* Describe how we implement __builtin_eh_return.  */
 141 #define EH_RETURN_DATA_REGNO(N) \
 142   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 143
 144 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
 145
 146 /* Target machine storage layout */
 147
 148 #define BITS_BIG_ENDIAN 0
 149 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 150 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
 151
 152 #define MAX_BITS_PER_WORD 64
 153
 154 /* Width of a word, in units (bytes).  */
 155 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 156 #define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD)
 157 #ifndef IN_LIBGCC2
 158 #define MIN_UNITS_PER_WORD 4
 159 #endif
 160
 161 /* Allows SImode op in builtin overflow pattern, see internal-fn.cc.  */
 162 #undef TARGET_MIN_ARITHMETIC_PRECISION
 163 #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision
 164
 165 /* The `Q' extension is not yet supported.  */
 166 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 167 /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */
 168 #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
 169
 170 /* The largest type that can be passed in floating-point registers.  */
 171 #define UNITS_PER_FP_ARG                                                \
 172   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 173     || riscv_abi == ABI_LP64)                                           \
 174    ? 0                                                                  \
 175    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 176
 177 /* Set the sizes of the core types.  */
 178 #define SHORT_TYPE_SIZE 16
 179 #define INT_TYPE_SIZE 32
 180 #define LONG_LONG_TYPE_SIZE 64
 181 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 182 #define LONG_TYPE_SIZE POINTER_SIZE
 183
 184 #define FLOAT_TYPE_SIZE 32
 185 #define DOUBLE_TYPE_SIZE 64
 186 #define LONG_DOUBLE_TYPE_SIZE 128
 187
 188 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 189 #define PARM_BOUNDARY BITS_PER_WORD
 190
 191 /* Allocation boundary (in *bits*) for the code of a function.  */
 192 #define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
 193
 194 /* The smallest supported stack boundary the calling convention supports.  */
 195 #define STACK_BOUNDARY \
 196   (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
 197
 198 /* The ABI stack alignment.  */
 199 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
 200
 201 /* There is no point aligning anything to a rounder boundary than this.  */
 202 #define BIGGEST_ALIGNMENT 128
 203
 204 /* The user-level ISA permits unaligned accesses, but they are not required
 205    of the privileged architecture.  */
 206 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 207
 208 /* Define this if you wish to imitate the way many other C compilers
 209    handle alignment of bitfields and the structures that contain
 210    them.
 211
 212    The behavior is that the type written for a bit-field (`int',
 213    `short', or other integer type) imposes an alignment for the
 214    entire structure, as if the structure really did contain an
 215    ordinary field of that type.  In addition, the bit-field is placed
 216    within the structure so that it would fit within such a field,
 217    not crossing a boundary for it.
 218
 219    Thus, on most machines, a bit-field whose type is written as `int'
 220    would not cross a four-byte boundary, and would force four-byte
 221    alignment for the whole structure.  (The alignment used may not
 222    be four bytes; it is controlled by the other alignment
 223    parameters.)
 224
 225    If the macro is defined, its definition should be a C expression;
 226    a nonzero value for the expression enables this behavior.  */
 227
 228 #define PCC_BITFIELD_TYPE_MATTERS 1
 229
 230 /* An integer expression for the size in bits of the largest integer machine
 231    mode that should actually be used.  We allow pairs of registers.  */
 232 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 233
 234 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
 235 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)                       \
 236   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 237     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 238         || TREE_CODE (TYPE) == UNION_TYPE                               \
 239         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 240
 241 /* If defined, a C expression to compute the alignment for a static
 242    variable.  TYPE is the data type, and ALIGN is the alignment that
 243    the object would ordinarily have.  The value of this macro is used
 244    instead of that alignment to align the object.
 245
 246    If this macro is not defined, then ALIGN is used.
 247
 248    One use of this macro is to increase alignment of medium-size
 249    data to make it all fit in fewer cache lines.  Another is to
 250    cause character arrays to be word-aligned so that `strcpy' calls
 251    that copy constants to character arrays can be done inline.  */
 252
 253 #define DATA_ALIGNMENT(TYPE, ALIGN)                                             \
 254   RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,  \
 255                           TYPE, ALIGN)
 256
 257 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 258    character arrays to be word-aligned so that `strcpy' calls that copy
 259    constants to character arrays can be done inline, and 'strcmp' can be
 260    optimised to use word loads. */
 261 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 262   RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
 263
 264 /* Define if operations between registers always perform the operation
 265    on the full register even if a narrower mode is specified.  */
 266 #define WORD_REGISTER_OPERATIONS 1
 267
 268 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 269    moves.  All other references are zero extended.  */
 270 #define LOAD_EXTEND_OP(MODE) \
 271   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 272
 273 /* Define this macro if it is advisable to hold scalars in registers
 274    in a wider mode than that declared by the program.  In such cases,
 275    the value is constrained to be within the bounds of the declared
 276    type, but kept valid in the wider mode.  The signedness of the
 277    extension may differ from that of the type.  */
 278
 279 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 280   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 281       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 282     {                                           \
 283       if ((MODE) == SImode)                     \
 284         (UNSIGNEDP) = 0;                        \
 285       (MODE) = word_mode;                       \
 286     }
 287
 288 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 289    Extensions of pointers to word_mode must be signed.  */
 290 #define POINTERS_EXTEND_UNSIGNED false
 291
 292 /* Define if loading short immediate values into registers sign extends.  */
 293 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 294
 295 /* Standard register usage.  */
 296
 297 /* Number of hardware registers.  We have:
 298
 299    - 32 integer registers
 300    - 32 floating point registers
 301    - 2 fake registers:
 302         - ARG_POINTER_REGNUM
 303         - FRAME_POINTER_REGNUM
 304    - 1 vl register
 305    - 1 vtype register
 306    - 30 unused registers for future expansion
 307    - 32 vector registers  */
 308
 309 #define FIRST_PSEUDO_REGISTER 128
 310
 311 /* x0, sp, gp, and tp are fixed.  */
 312
 313 #define FIXED_REGISTERS                                                 \
 314 { /* General registers.  */                                             \
 315   1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 316   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 317   /* Floating-point registers.  */                                      \
 318   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 319   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 320   /* Others.  */                                                        \
 321   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 322   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 323   /* Vector registers.  */                                              \
 324   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 325   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0                        \
 326 }
 327
 328 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 329    The call RTLs themselves clobber ra.  */
 330
 331 #define CALL_USED_REGISTERS                                             \
 332 { /* General registers.  */                                             \
 333   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 334   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 335   /* Floating-point registers.  */                                      \
 336   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 337   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 338   /* Others.  */                                                        \
 339   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 340   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 341   /* Vector registers.  */                                              \
 342   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 343   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1                        \
 344 }
 345
 346 /* Select a register mode required for caller save of hard regno REGNO.
 347    Contrary to what is documented, the default is not the smallest suitable
 348    mode but the largest suitable mode for the given (REGNO, NREGS) pair and
 349    it quickly creates paradoxical subregs that can be problematic.  */
 350 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 351   ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
 352
 353 /* Internal macros to classify an ISA register's type.  */
 354
 355 #define GP_REG_FIRST 0
 356 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 357 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 358
 359 #define FP_REG_FIRST 32
 360 #define FP_REG_LAST  63
 361 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 362
 363 #define V_REG_FIRST 96
 364 #define V_REG_LAST  127
 365 #define V_REG_NUM   (V_REG_LAST - V_REG_FIRST + 1)
 366
 367 /* The DWARF 2 CFA column which tracks the return address from a
 368    signal handler context.  This means that to maintain backwards
 369    compatibility, no hard register can be assigned this column if it
 370    would need to be handled by the DWARF unwinder.  */
 371 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 372
 373 #define GP_REG_P(REGNO) \
 374   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 375 #define FP_REG_P(REGNO)  \
 376   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 377 #define HARDFP_REG_P(REGNO)  \
 378   ((REGNO) >= FP_REG_FIRST && (REGNO) <= FP_REG_LAST)
 379 #define V_REG_P(REGNO)  \
 380   ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
 381 #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
 382 #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
 383 #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM)
 384 #define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM)
 385
 386 /* True when REGNO is in SIBCALL_REGS set.  */
 387 #define SIBCALL_REG_P(REGNO)    \
 388   TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
 389
 390 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 391
 392 /* Use s0 as the frame pointer if it is so requested.  */
 393 #define HARD_FRAME_POINTER_REGNUM 8
 394 #define STACK_POINTER_REGNUM 2
 395 #define THREAD_POINTER_REGNUM 4
 396
 397 /* These two registers don't really exist: they get eliminated to either
 398    the stack or hard frame pointer.  */
 399 #define ARG_POINTER_REGNUM 64
 400 #define FRAME_POINTER_REGNUM 65
 401
 402 /* Define Dwarf for RVV.  */
 403 #define RISCV_DWARF_FRM (4096 + 0x003)
 404 #define RISCV_DWARF_VXRM (4096 + 0x00a)
 405 #define RISCV_DWARF_VL (4096 + 0xc20)
 406 #define RISCV_DWARF_VTYPE (4096 + 0xc21)
 407 #define RISCV_DWARF_VLENB (4096 + 0xc22)
 408
 409 /* Register in which static-chain is passed to a function.  */
 410 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 411
 412 /* Registers used as temporaries in prologue/epilogue code.
 413
 414    The prologue registers mustn't conflict with any
 415    incoming arguments, the static chain pointer, or the frame pointer.
 416    The epilogue temporary mustn't conflict with the return registers,
 417    the frame pointer, the EH stack adjustment, or the EH data registers. */
 418
 419 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
 420 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 421 #define RISCV_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST + 1)
 422 #define RISCV_PROLOGUE_TEMP2(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP2_REGNUM)
 423
 424 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 425 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
 426   gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
 427
 428 #define RETURN_ADDR_MASK (1 << RETURN_ADDR_REGNUM)
 429 #define S0_MASK (1 << S0_REGNUM)
 430 #define S1_MASK (1 << S1_REGNUM)
 431 #define S2_MASK (1 << S2_REGNUM)
 432 #define S3_MASK (1 << S3_REGNUM)
 433 #define S4_MASK (1 << S4_REGNUM)
 434 #define S5_MASK (1 << S5_REGNUM)
 435 #define S6_MASK (1 << S6_REGNUM)
 436 #define S7_MASK (1 << S7_REGNUM)
 437 #define S8_MASK (1 << S8_REGNUM)
 438 #define S9_MASK (1 << S9_REGNUM)
 439 #define S10_MASK (1 << S10_REGNUM)
 440 #define S11_MASK (1 << S11_REGNUM)
 441
 442 #define MULTI_PUSH_GPR_MASK                                                    \
 443   (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK          \
 444    | S5_MASK | S6_MASK | S7_MASK | S8_MASK | S9_MASK | S10_MASK | S11_MASK)
 445 #define ZCMP_MAX_SPIMM 3
 446 #define ZCMP_SP_INC_STEP 16
 447 #define ZCMP_INVALID_S0S10_SREGS_COUNTS 11
 448 #define ZCMP_S0S11_SREGS_COUNTS 12
 449 #define ZCMP_MAX_GRP_SLOTS 13
 450
 451 #define MCOUNT_NAME "_mcount"
 452
 453 #define NO_PROFILE_COUNTERS 1
 454
 455 /* Emit rtl for profiling.  Output assembler code to FILE
 456    to call "_mcount" for profiling a function entry.  */
 457 #define PROFILE_HOOK(LABEL)                                             \
 458   {                                                                     \
 459     rtx fun, ra;                                                        \
 460     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 461     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 462     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 463   }
 464
 465 /* All the work done in PROFILE_HOOK, but still required.  */
 466 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 467
 468 /* Define this macro if it is as good or better to call a constant
 469    function address than to call an address kept in a register.  */
 470 #define NO_FUNCTION_CSE 1
 471
 472 /* Define the classes of registers for register constraints in the
 473    machine description.  Also define ranges of constants.
 474
 475    One of the classes must always be named ALL_REGS and include all hard regs.
 476    If there is more than one class, another class must be named NO_REGS
 477    and contain no registers.
 478
 479    The name GENERAL_REGS must be the name of a class (or an alias for
 480    another name such as ALL_REGS).  This is the class of registers
 481    that is allowed by "g" or "r" in a register constraint.
 482    Also, registers outside this class are allocated only when
 483    instructions express preferences for them.
 484
 485    The classes must be numbered in nondecreasing order; that is,
 486    a larger-numbered class must never be contained completely
 487    in a smaller-numbered class.
 488
 489    For any two classes, it is very desirable that there be another
 490    class that represents their union.  */
 491
 492 enum reg_class
 493 {
 494   NO_REGS,                      /* no registers in set */
 495   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 496   JALR_REGS,                    /* registers used by indirect calls */
 497   GR_REGS,                      /* integer registers */
 498   FP_REGS,                      /* floating-point registers */
 499   FRAME_REGS,                   /* arg pointer and frame pointer */
 500   VM_REGS,                      /* v0.t registers */
 501   VD_REGS,                      /* vector registers except v0.t */
 502   V_REGS,                       /* vector registers */
 503   ALL_REGS,                     /* all registers */
 504   LIM_REG_CLASSES               /* max value + 1 */
 505 };
 506
 507 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 508
 509 #define GENERAL_REGS GR_REGS
 510
 511 /* An initializer containing the names of the register classes as C
 512    string constants.  These names are used in writing some of the
 513    debugging dumps.  */
 514
 515 #define REG_CLASS_NAMES                                                 \
 516 {                                                                       \
 517   "NO_REGS",                                                            \
 518   "SIBCALL_REGS",                                                       \
 519   "JALR_REGS",                                                          \
 520   "GR_REGS",                                                            \
 521   "FP_REGS",                                                            \
 522   "FRAME_REGS",                                                         \
 523   "VM_REGS",                                                            \
 524   "VD_REGS",                                                            \
 525   "V_REGS",                                                             \
 526   "ALL_REGS"                                                            \
 527 }
 528
 529 /* An initializer containing the contents of the register classes,
 530    as integers which are bit masks.  The Nth integer specifies the
 531    contents of class N.  The way the integer MASK is interpreted is
 532    that register R is in the class if `MASK & (1 << R)' is 1.
 533
 534    When the machine has more than 32 registers, an integer does not
 535    suffice.  Then the integers are replaced by sub-initializers,
 536    braced groupings containing several integers.  Each
 537    sub-initializer must be suitable as an initializer for the type
 538    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 539
 540 #define REG_CLASS_CONTENTS                                              \
 541 {                                                                       \
 542   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* NO_REGS */           \
 543   { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 },   /* SIBCALL_REGS */      \
 544   { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 },   /* JALR_REGS */         \
 545   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 },   /* GR_REGS */           \
 546   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 },   /* FP_REGS */           \
 547   { 0x00000000, 0x00000000, 0x00000003, 0x00000000 },   /* FRAME_REGS */        \
 548   { 0x00000000, 0x00000000, 0x00000000, 0x00000001 },   /* V0_REGS */           \
 549   { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe },   /* VNoV0_REGS */        \
 550   { 0x00000000, 0x00000000, 0x00000000, 0xffffffff },   /* V_REGS */            \
 551   { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff }    /* ALL_REGS */          \
 552 }
 553
 554 /* A C expression whose value is a register class containing hard
 555    register REGNO.  In general there is more that one such class;
 556    choose a class which is "minimal", meaning that no smaller class
 557    also contains the register.  */
 558
 559 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 560
 561 /* A macro whose definition is the name of the class to which a
 562    valid base register must belong.  A base register is one used in
 563    an address which is the register value plus a displacement.  */
 564
 565 #define BASE_REG_CLASS GR_REGS
 566
 567 /* A macro whose definition is the name of the class to which a
 568    valid index register must belong.  An index register is one used
 569    in an address where its value is either multiplied by a scale
 570    factor or added to another register (as well as added to a
 571    displacement).  */
 572
 573 #define INDEX_REG_CLASS riscv_index_reg_class()
 574
 575 /* We generally want to put call-clobbered registers ahead of
 576    call-saved ones.  (IRA expects this.)  */
 577
 578 #define REG_ALLOC_ORDER                                                 \
 579 { \
 580   /* Call-clobbered GPRs.  */                                           \
 581   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 582   /* Call-saved GPRs.  */                                               \
 583   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 584   /* GPRs that can never be exposed to the register allocator.  */      \
 585   0, 2, 3, 4,                                                           \
 586   /* Call-clobbered FPRs.  */                                           \
 587   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 588   60, 61, 62, 63,                                                       \
 589   /* Call-saved FPRs.  */                                               \
 590   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 591   /* v1 ~ v31 vector registers.  */                                     \
 592   97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,    \
 593   111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123,      \
 594   124, 125, 126, 127,                                                   \
 595   /* The vector mask register.  */                                      \
 596   96,                                                                   \
 597   /* None of the remaining classes have defined call-saved              \
 598      registers.  */                                                     \
 599   64, 65, 66, 67                                                        \
 600 }
 601
 602 /* True if VALUE is a signed 12-bit number.  */
 603
 604 #define SMALL_OPERAND(VALUE) \
 605   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 606
 607 #define POLY_SMALL_OPERAND_P(POLY_VALUE)                \
 608   (POLY_VALUE.is_constant () ?                          \
 609      SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
 610
 611 /* True if VALUE can be loaded into a register using LUI.  */
 612
 613 #define LUI_OPERAND(VALUE)                                              \
 614   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 615    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 616
 617 /* If this is a single bit mask, then we can load it with bseti.  Special
 618    handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
 619 #define SINGLE_BIT_MASK_OPERAND(VALUE)                                  \
 620   (pow2p_hwi (TARGET_64BIT                                              \
 621                 ? (VALUE)                                               \
 622                 : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1))))
 623
 624 /* True if VALUE can be represented as an immediate with 1 extra bit
 625    set: we check that it is not a SMALL_OPERAND (as this would be true
 626    for all small operands) unmodified and turns into a small operand
 627    once we clear the top bit. */
 628 #define UIMM_EXTRA_BIT_OPERAND(VALUE)                                   \
 629   (!SMALL_OPERAND (VALUE)                                               \
 630    && SMALL_OPERAND (VALUE & ~(HOST_WIDE_INT_1U << floor_log2 (VALUE))))
 631
 632 /* Stack layout; function entry, exit and calling.  */
 633
 634 #define STACK_GROWS_DOWNWARD 1
 635
 636 #define FRAME_GROWS_DOWNWARD 1
 637
 638 #define RETURN_ADDR_RTX riscv_return_addr
 639
 640 #define ELIMINABLE_REGS                                                 \
 641 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 642  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 643  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 644  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 645
 646 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 647   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 648
 649 /* Allocate stack space for arguments at the beginning of each function.  */
 650 #define ACCUMULATE_OUTGOING_ARGS 1
 651
 652 /* The argument pointer always points to the first argument.  */
 653 #define FIRST_PARM_OFFSET(FNDECL) 0
 654
 655 #define REG_PARM_STACK_SPACE(FNDECL) 0
 656
 657 /* Define this if it is the responsibility of the caller to
 658    allocate the area reserved for arguments passed in registers.
 659    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 660    of this macro is to determine whether the space is included in
 661    `crtl->outgoing_args_size'.  */
 662 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 663
 664 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 665
 666 /* Symbolic macros for the registers used to return integer and floating
 667    point values.  */
 668
 669 #define GP_RETURN GP_ARG_FIRST
 670 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 671
 672 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
 673
 674 #define MAX_ARGS_IN_VECTOR_REGISTERS (16)
 675 #define MAX_ARGS_IN_MASK_REGISTERS (1)
 676
 677 /* Symbolic macros for the first/last argument registers.  */
 678
 679 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 680 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 681 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 682 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 683 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 684 #define V_ARG_FIRST (V_REG_FIRST + 8)
 685 #define V_ARG_LAST (V_ARG_FIRST + MAX_ARGS_IN_VECTOR_REGISTERS - 1)
 686
 687 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 688   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 689    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 690
 691 #define CALLEE_SAVED_FREG_NUMBER(REGNO) CALLEE_SAVED_REG_NUMBER (REGNO - 32)
 692
 693 #define LIBCALL_VALUE(MODE) \
 694   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 695
 696 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 697   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 698
 699 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 700
 701 /* 1 if N is a possible register number for function argument passing.
 702    We have no FP argument registers when soft-float.  */
 703
 704 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 705 #define FUNCTION_ARG_REGNO_P(N)                                         \
 706   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 707    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 708
 709 /* Define the standard RISC-V calling convention and variants.  */
 710
 711 enum riscv_cc
 712 {
 713   RISCV_CC_BASE = 0, /* Base standard RISC-V ABI.  */
 714   RISCV_CC_V, /* For functions that pass or return values in V registers.  */
 715   RISCV_CC_UNKNOWN
 716 };
 717
 718 typedef struct {
 719   /* The calling convention that current function used.  */
 720   enum riscv_cc variant_cc;
 721
 722   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 723   unsigned int num_gprs;
 724
 725   /* Number of floating-point registers used so far, likewise.  */
 726   unsigned int num_fprs;
 727
 728   int rvv_psabi_warning;
 729
 730   /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS.  */
 731   unsigned int num_mrs;
 732
 733   /* The used state of args in vector registers, true for used by prev arg,
 734      initial to false.  */
 735   bool used_vrs[MAX_ARGS_IN_VECTOR_REGISTERS];
 736 } CUMULATIVE_ARGS;
 737
 738 /* Return riscv calling convention of call_insn.  */
 739 extern enum riscv_cc get_riscv_cc (const rtx use);
 740
 741 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 742    for a call to a function whose data type is FNTYPE.
 743    For a library call, FNTYPE is 0.  */
 744
 745 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 746   riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
 747                         (N_NAMED_ARGS) != -1)
 748
 749 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 750
 751 /* Align based on stack boundary, which might have been set by the user.  */
 752 #define RISCV_STACK_ALIGN(LOC) \
 753   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 754
 755 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 756    the stack pointer does not matter.  The value is tested only in
 757    functions that have frame pointers.
 758    No definition is equivalent to always zero.  */
 759
 760 #define EXIT_IGNORE_STACK 1
 761
 762
 763 /* Trampolines are a block of code followed by two pointers.  */
 764
 765 #define TRAMPOLINE_CODE_SIZE 16
 766 #define TRAMPOLINE_SIZE         \
 767   ((Pmode == SImode)            \
 768    ? TRAMPOLINE_CODE_SIZE       \
 769    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 770 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 771
 772 /* Addressing modes, and classification of registers for them.  */
 773
 774 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 775   riscv_regno_ok_for_index_p (REGNO)
 776
 777 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 778   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 779
 780 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 781    and check its validity for a certain class.
 782    We have two alternate definitions for each of them.
 783    The usual definition accepts all pseudo regs; the other rejects them all.
 784    The symbol REG_OK_STRICT causes the latter definition to be used.
 785
 786    Most source files want to accept pseudo regs in the hope that
 787    they will get allocated to the class that the insn wants them to be in.
 788    Some source files that are used after register allocation
 789    need to be strict.  */
 790
 791 #ifndef REG_OK_STRICT
 792 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 793   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 794 #else
 795 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 796   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 797 #endif
 798
 799 #define REG_OK_FOR_INDEX_P(X) 0
 800
 801 /* Maximum number of registers that can appear in a valid memory address.  */
 802
 803 #define MAX_REGS_PER_ADDRESS 1
 804
 805 #define CONSTANT_ADDRESS_P(X) \
 806   (CONSTANT_P (X) && memory_address_p (SImode, X))
 807
 808 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 809    'the start of the function that this code is output in'.  */
 810
 811 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 812   do {                                                                  \
 813     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 814       asm_fprintf ((FILE), "%U%s",                                      \
 815                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 816                                0), 0));                                 \
 817     else                                                                \
 818       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 819   } while (0)
 820
 821 #define JUMP_TABLES_IN_TEXT_SECTION 0
 822 #define CASE_VECTOR_MODE SImode
 823 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 824
 825 #define LOCAL_SYM_P(sym)                                                \
 826      ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))                  \
 827          || ((GET_CODE (sym) == CONST)                                  \
 828              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 829              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))
 830
 831 /* The load-address macro is used for PC-relative addressing of symbols
 832    that bind locally.  Don't use it for symbols that should be addressed
 833    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 834    currently results in more opportunities for linker relaxation.  */
 835 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 836   (!TARGET_EXPLICIT_RELOCS &&                                           \
 837    ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY))
 838
 839 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 840 #define DEFAULT_SIGNED_CHAR 0
 841
 842 #define MOVE_MAX UNITS_PER_WORD
 843 #define MAX_MOVE_MAX 8
 844
 845 /* The SPARC port says:
 846    Nonzero if access to memory by bytes is slow and undesirable.
 847    For RISC chips, it means that access to memory by bytes is no
 848    better than access by words when possible, so grab a whole word
 849    and maybe make use of that.  */
 850 #define SLOW_BYTE_ACCESS 1
 851
 852 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 853    in the md file instead.  */
 854 #define SHIFT_COUNT_TRUNCATED 0
 855
 856 /* Specify the machine mode that pointers have.
 857    After generation of rtl, the compiler makes no further distinction
 858    between pointers and any other objects of this machine mode.  */
 859
 860 #define Pmode word_mode
 861
 862 /* Specify the machine mode that registers have.  */
 863
 864 #define Xmode (TARGET_64BIT ? DImode : SImode)
 865
 866 /* Give call MEMs SImode since it is the "most permissive" mode
 867    for both 32-bit and 64-bit targets.  */
 868
 869 #define FUNCTION_MODE SImode
 870
 871 /* A C expression for the cost of a branch instruction.  A value of 2
 872    seems to minimize code size.  */
 873
 874 #define BRANCH_COST(speed_p, predictable_p) \
 875   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 876
 877 /* True if the target optimizes short forward branches around integer
 878    arithmetic instructions into predicated operations, e.g., for
 879    conditional-move operations.  The macro assumes that all branch
 880    instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
 881    support this feature.  The macro further assumes that any integer
 882    arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
 883    SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
 884    counterparts, including C.MV and C.LI) can be in the branch shadow.  */
 885
 886 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
 887
 888 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 889
 890 /* Control the assembler format that we output.  */
 891
 892 /* Output to assembler file text saying following lines
 893    may contain character constants, extra white space, comments, etc.  */
 894
 895 #ifndef ASM_APP_ON
 896 #define ASM_APP_ON " #APP\n"
 897 #endif
 898
 899 /* Output to assembler file text saying following lines
 900    no longer contain unusual constructs.  */
 901
 902 #ifndef ASM_APP_OFF
 903 #define ASM_APP_OFF " #NO_APP\n"
 904 #endif
 905
 906 #define REGISTER_NAMES                                          \
 907 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 908   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 909   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 910   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 911   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 912   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 913   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 914   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 915   "arg", "frame", "vl", "vtype", "vxrm", "frm", "N/A", "N/A",   \
 916   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 917   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 918   "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",       \
 919   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",        \
 920   "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",       \
 921   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",       \
 922   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",}
 923
 924 #define ADDITIONAL_REGISTER_NAMES                                       \
 925 {                                                                       \
 926   { "x0",        0 + GP_REG_FIRST },                                    \
 927   { "x1",        1 + GP_REG_FIRST },                                    \
 928   { "x2",        2 + GP_REG_FIRST },                                    \
 929   { "x3",        3 + GP_REG_FIRST },                                    \
 930   { "x4",        4 + GP_REG_FIRST },                                    \
 931   { "x5",        5 + GP_REG_FIRST },                                    \
 932   { "x6",        6 + GP_REG_FIRST },                                    \
 933   { "x7",        7 + GP_REG_FIRST },                                    \
 934   { "x8",        8 + GP_REG_FIRST },                                    \
 935   { "x9",        9 + GP_REG_FIRST },                                    \
 936   { "x10",      10 + GP_REG_FIRST },                                    \
 937   { "x11",      11 + GP_REG_FIRST },                                    \
 938   { "x12",      12 + GP_REG_FIRST },                                    \
 939   { "x13",      13 + GP_REG_FIRST },                                    \
 940   { "x14",      14 + GP_REG_FIRST },                                    \
 941   { "x15",      15 + GP_REG_FIRST },                                    \
 942   { "x16",      16 + GP_REG_FIRST },                                    \
 943   { "x17",      17 + GP_REG_FIRST },                                    \
 944   { "x18",      18 + GP_REG_FIRST },                                    \
 945   { "x19",      19 + GP_REG_FIRST },                                    \
 946   { "x20",      20 + GP_REG_FIRST },                                    \
 947   { "x21",      21 + GP_REG_FIRST },                                    \
 948   { "x22",      22 + GP_REG_FIRST },                                    \
 949   { "x23",      23 + GP_REG_FIRST },                                    \
 950   { "x24",      24 + GP_REG_FIRST },                                    \
 951   { "x25",      25 + GP_REG_FIRST },                                    \
 952   { "x26",      26 + GP_REG_FIRST },                                    \
 953   { "x27",      27 + GP_REG_FIRST },                                    \
 954   { "x28",      28 + GP_REG_FIRST },                                    \
 955   { "x29",      29 + GP_REG_FIRST },                                    \
 956   { "x30",      30 + GP_REG_FIRST },                                    \
 957   { "x31",      31 + GP_REG_FIRST },                                    \
 958   { "f0",        0 + FP_REG_FIRST },                                    \
 959   { "f1",        1 + FP_REG_FIRST },                                    \
 960   { "f2",        2 + FP_REG_FIRST },                                    \
 961   { "f3",        3 + FP_REG_FIRST },                                    \
 962   { "f4",        4 + FP_REG_FIRST },                                    \
 963   { "f5",        5 + FP_REG_FIRST },                                    \
 964   { "f6",        6 + FP_REG_FIRST },                                    \
 965   { "f7",        7 + FP_REG_FIRST },                                    \
 966   { "f8",        8 + FP_REG_FIRST },                                    \
 967   { "f9",        9 + FP_REG_FIRST },                                    \
 968   { "f10",      10 + FP_REG_FIRST },                                    \
 969   { "f11",      11 + FP_REG_FIRST },                                    \
 970   { "f12",      12 + FP_REG_FIRST },                                    \
 971   { "f13",      13 + FP_REG_FIRST },                                    \
 972   { "f14",      14 + FP_REG_FIRST },                                    \
 973   { "f15",      15 + FP_REG_FIRST },                                    \
 974   { "f16",      16 + FP_REG_FIRST },                                    \
 975   { "f17",      17 + FP_REG_FIRST },                                    \
 976   { "f18",      18 + FP_REG_FIRST },                                    \
 977   { "f19",      19 + FP_REG_FIRST },                                    \
 978   { "f20",      20 + FP_REG_FIRST },                                    \
 979   { "f21",      21 + FP_REG_FIRST },                                    \
 980   { "f22",      22 + FP_REG_FIRST },                                    \
 981   { "f23",      23 + FP_REG_FIRST },                                    \
 982   { "f24",      24 + FP_REG_FIRST },                                    \
 983   { "f25",      25 + FP_REG_FIRST },                                    \
 984   { "f26",      26 + FP_REG_FIRST },                                    \
 985   { "f27",      27 + FP_REG_FIRST },                                    \
 986   { "f28",      28 + FP_REG_FIRST },                                    \
 987   { "f29",      29 + FP_REG_FIRST },                                    \
 988   { "f30",      30 + FP_REG_FIRST },                                    \
 989   { "f31",      31 + FP_REG_FIRST },                                    \
 990 }
 991
 992 /* Globalizing directive for a label.  */
 993 #define GLOBAL_ASM_OP "\t.globl\t"
 994
 995 /* This is how to store into the string LABEL
 996    the symbol_ref name of an internal numbered label where
 997    PREFIX is the class of label and NUM is the number within the class.
 998    This is suitable for output with `assemble_name'.  */
 999
1000 #undef ASM_GENERATE_INTERNAL_LABEL
1001 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
1002   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
1003
1004 /* This is how to output an element of a case-vector that is absolute.  */
1005
1006 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
1007   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
1008
1009 /* This is how to output an element of a PIC case-vector. */
1010
1011 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
1012   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
1013            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
1014
1015 /* This is how to output an assembler line
1016    that says to advance the location counter
1017    to a multiple of 2**LOG bytes.  */
1018
1019 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
1020   fprintf (STREAM, "\t.align\t%d\n", (LOG))
1021
1022 /* Define the strings to put out for each section in the object file.  */
1023 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
1024 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
1025 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
1026 #define BSS_SECTION_ASM_OP      "\t.bss"
1027 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
1028 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
1029
1030 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
1031 do                                                                      \
1032   {                                                                     \
1033     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
1034              reg_names[STACK_POINTER_REGNUM],                           \
1035              reg_names[STACK_POINTER_REGNUM],                           \
1036              TARGET_64BIT ? "sd" : "sw",                                \
1037              reg_names[REGNO],                                          \
1038              reg_names[STACK_POINTER_REGNUM]);                          \
1039   }                                                                     \
1040 while (0)
1041
1042 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
1043 do                                                                      \
1044   {                                                                     \
1045     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
1046              TARGET_64BIT ? "ld" : "lw",                                \
1047              reg_names[REGNO],                                          \
1048              reg_names[STACK_POINTER_REGNUM],                           \
1049              reg_names[STACK_POINTER_REGNUM],                           \
1050              reg_names[STACK_POINTER_REGNUM]);                          \
1051   }                                                                     \
1052 while (0)
1053
1054 #define ASM_COMMENT_START "#"
1055
1056 /* Add output .variant_cc directive for specific function definition.  */
1057 #undef ASM_DECLARE_FUNCTION_NAME
1058 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)                             \
1059   riscv_declare_function_name (STR, NAME, DECL)
1060
1061 #undef ASM_DECLARE_FUNCTION_SIZE
1062 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)                           \
1063   riscv_declare_function_size (FILE, FNAME, DECL)
1064
1065 /* Add output .variant_cc directive for specific alias definition.  */
1066 #undef ASM_OUTPUT_DEF_FROM_DECLS
1067 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET)                           \
1068   riscv_asm_output_alias (STR, DECL, TARGET)
1069
1070 /* Add output .variant_cc directive for specific extern function.  */
1071 #undef ASM_OUTPUT_EXTERNAL
1072 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME)                                   \
1073   riscv_asm_output_external (STR, DECL, NAME)
1074
1075 #undef SIZE_TYPE
1076 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
1077
1078 #undef PTRDIFF_TYPE
1079 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
1080
1081 /* The maximum number of bytes copied by one iteration of a cpymemsi loop.  */
1082
1083 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
1084
1085 /* The maximum number of bytes that can be copied by a straight-line
1086    cpymemsi implementation.  */
1087
1088 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
1089
1090 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1091    move-instruction pairs, we will do a cpymem or libcall instead.
1092    Do not use move_by_pieces at all when strict alignment is not
1093    in effect but the target has slow unaligned accesses; in this
1094    case, cpymem or libcall is more efficient.  */
1095
1096 #define MOVE_RATIO(speed)                                               \
1097   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
1098    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
1099    CLEAR_RATIO (speed) / 2)
1100
1101 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
1102    of the length of a memset call, but use the default otherwise.  */
1103
1104 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
1105
1106 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
1107    optimizing for size adjust the ratio to account for the overhead of
1108    loading the constant and replicating it across the word.  */
1109
1110 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
1111
1112 #ifndef USED_FOR_TARGET
1113 extern const enum reg_class riscv_regno_to_class[];
1114 extern bool riscv_slow_unaligned_access_p;
1115 extern bool riscv_user_wants_strict_align;
1116 extern unsigned riscv_stack_boundary;
1117 extern unsigned riscv_bytes_per_vector_chunk;
1118 extern poly_uint16 riscv_vector_chunks;
1119 extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int);
1120 extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int);
1121 extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
1122 extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
1123 /* The number of bits and bytes in a RVV vector.  */
1124 #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8))
1125 #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
1126 #endif
1127
1128 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1129   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
1130
1131 #define XLEN_SPEC \
1132   "%{march=rv32*:32}" \
1133   "%{march=rv64*:64}" \
1134
1135 #define ABI_SPEC \
1136   "%{mabi=ilp32:ilp32}" \
1137   "%{mabi=ilp32e:ilp32e}" \
1138   "%{mabi=ilp32f:ilp32f}" \
1139   "%{mabi=ilp32d:ilp32d}" \
1140   "%{mabi=lp64:lp64}" \
1141   "%{mabi=lp64f:lp64f}" \
1142   "%{mabi=lp64d:lp64d}" \
1143
1144 /* ISA constants needed for code generation.  */
1145 #define OPCODE_LW    0x2003
1146 #define OPCODE_LD    0x3003
1147 #define OPCODE_AUIPC 0x17
1148 #define OPCODE_JALR  0x67
1149 #define OPCODE_LUI   0x37
1150 #define OPCODE_ADDI  0x13
1151 #define SHIFT_RD  7
1152 #define SHIFT_RS1 15
1153 #define SHIFT_IMM 20
1154 #define IMM_BITS 12
1155 #define C_S_BITS 5
1156 #define C_SxSP_BITS 6
1157
1158 #define IMM_REACH (1LL << IMM_BITS)
1159 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
1160 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
1161
1162 #define SWSP_REACH (4LL << C_SxSP_BITS)
1163 #define SDSP_REACH (8LL << C_SxSP_BITS)
1164
1165 /* This is the maximum value that can be represented in a compressed load/store
1166    offset (an unsigned 5-bit value scaled by 4).  */
1167 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
1168
1169 /* Called from RISCV_REORG, this is defined in riscv-sr.cc.  */
1170
1171 extern void riscv_remove_unneeded_save_restore_calls (void);
1172
1173 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
1174
1175 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1176   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1177 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1178   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1179
1180 #define TARGET_SUPPORTS_WIDE_INT 1
1181
1182 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
1183
1184 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
1185
1186 #define RISCV_DWARF_VLENB (4096 + 0xc22)
1187
1188 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */)
1189
1190 #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
1191   ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO)
1192
1193 /* Like s390, riscv also defined this macro for the vector comparision.  Then
1194    the simplify-rtx relational_result will canonicalize the result to the
1195    CONST1_RTX for the simplification.  */
1196 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE))
1197
1198 /* Mode switching (Lazy code motion) for RVV rounding mode instructions.  */
1199 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
1200 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
1201
1202 /* The size difference between different RVV modes can be up to 64 times.
1203    e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
1204 #define MAX_POLY_VARIANT 64
1205
1206 #define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX
1207 #define HAVE_PRE_MODIFY_DISP  TARGET_XTHEADMEMIDX
1208
1209 #endif /* ! GCC_RISCV_H */