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riscv: Define Xmode macro
[thirdparty/gcc.git] / gcc / config / riscv / riscv.h
1 /* Definition of RISC-V target for GNU compiler.
2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_RISCV_H
23 #define GCC_RISCV_H
24
25 #include "config/riscv/riscv-opts.h"
26
27 /* Target CPU builtins. */
28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
29
30 #ifdef TARGET_BIG_ENDIAN_DEFAULT
31 #define DEFAULT_ENDIAN_SPEC "b"
32 #else
33 #define DEFAULT_ENDIAN_SPEC "l"
34 #endif
35
36 /* Default target_flags if no switches are specified */
37
38 #ifndef TARGET_DEFAULT
39 #define TARGET_DEFAULT 0
40 #endif
41
42 #ifndef RISCV_TUNE_STRING_DEFAULT
43 #define RISCV_TUNE_STRING_DEFAULT "rocket"
44 #endif
45
46 extern const char *riscv_expand_arch (int argc, const char **argv);
47 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
48 extern const char *riscv_default_mtune (int argc, const char **argv);
49 extern const char *riscv_multi_lib_check (int argc, const char **argv);
50
51 # define EXTRA_SPEC_FUNCTIONS \
52 { "riscv_expand_arch", riscv_expand_arch }, \
53 { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \
54 { "riscv_default_mtune", riscv_default_mtune }, \
55 { "riscv_multi_lib_check", riscv_multi_lib_check },
56
57 /* Support for a compile-time default CPU, et cetera. The rules are:
58 --with-arch is ignored if -march or -mcpu is specified.
59 --with-abi is ignored if -mabi is specified.
60 --with-tune is ignored if -mtune or -mcpu is specified.
61 --with-isa-spec is ignored if -misa-spec is specified.
62
63 But using default -march/-mtune value if -mcpu don't have valid option. */
64 #define OPTION_DEFAULT_SPECS \
65 {"tune", "%{!mtune=*:" \
66 " %{!mcpu=*:-mtune=%(VALUE)}" \
67 " %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" }, \
68 {"arch", "%{!march=*:" \
69 " %{!mcpu=*:-march=%(VALUE)}" \
70 " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \
71 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
72 {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
73
74 #ifdef IN_LIBGCC2
75 #undef TARGET_64BIT
76 /* Make this compile time constant for libgcc2 */
77 #define TARGET_64BIT (__riscv_xlen == 64)
78 #endif /* IN_LIBGCC2 */
79
80 #ifdef HAVE_AS_MISA_SPEC
81 #define ASM_MISA_SPEC "%{misa-spec=*}"
82 #else
83 #define ASM_MISA_SPEC ""
84 #endif
85
86 /* Reference:
87 https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing */
88 #define STRINGIZING(s) __STRINGIZING(s)
89 #define __STRINGIZING(s) #s
90
91 #define MULTILIB_DEFAULTS \
92 {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \
93 "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) }
94
95 #undef ASM_SPEC
96 #define ASM_SPEC "\
97 %(subtarget_asm_debugging_spec) \
98 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
99 %{march=*} \
100 %{mabi=*} \
101 %{mno-relax} \
102 %{mbig-endian} \
103 %{mlittle-endian} \
104 %(subtarget_asm_spec)" \
105 ASM_MISA_SPEC
106
107 #undef DRIVER_SELF_SPECS
108 #define DRIVER_SELF_SPECS \
109 "%{march=*:%:riscv_expand_arch(%*)} " \
110 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
111
112 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
113
114 #define LOCAL_LABEL_PREFIX "."
115 #define USER_LABEL_PREFIX ""
116
117 /* Offsets recorded in opcodes are a multiple of this alignment factor.
118 The default for this in 64-bit mode is 8, which causes problems with
119 SFmode register saves. */
120 #define DWARF_CIE_DATA_ALIGNMENT -4
121
122 /* The mapping from gcc register number to DWARF 2 CFA column number. */
123 #define DWARF_FRAME_REGNUM(REGNO) \
124 (FRM_REG_P (REGNO) ? RISCV_DWARF_FRM \
125 : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM \
126 : VL_REG_P (REGNO) ? RISCV_DWARF_VL \
127 : VTYPE_REG_P (REGNO) \
128 ? RISCV_DWARF_VTYPE \
129 : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) \
130 ? REGNO \
131 : INVALID_REGNUM))
132
133 /* The DWARF 2 CFA column which tracks the return address. */
134 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
135 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
136
137 /* Describe how we implement __builtin_eh_return. */
138 #define EH_RETURN_DATA_REGNO(N) \
139 ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
140
141 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
142
143 /* Target machine storage layout */
144
145 #define BITS_BIG_ENDIAN 0
146 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
147 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
148
149 #define MAX_BITS_PER_WORD 64
150
151 /* Width of a word, in units (bytes). */
152 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
153 #define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD)
154 #ifndef IN_LIBGCC2
155 #define MIN_UNITS_PER_WORD 4
156 #endif
157
158 /* Allows SImode op in builtin overflow pattern, see internal-fn.cc. */
159 #undef TARGET_MIN_ARITHMETIC_PRECISION
160 #define TARGET_MIN_ARITHMETIC_PRECISION riscv_min_arithmetic_precision
161
162 /* The `Q' extension is not yet supported. */
163 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
164 /* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */
165 #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
166
167 /* The largest type that can be passed in floating-point registers. */
168 #define UNITS_PER_FP_ARG \
169 ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \
170 || riscv_abi == ABI_LP64) \
171 ? 0 \
172 : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
173
174 /* Set the sizes of the core types. */
175 #define SHORT_TYPE_SIZE 16
176 #define INT_TYPE_SIZE 32
177 #define LONG_LONG_TYPE_SIZE 64
178 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
179 #define LONG_TYPE_SIZE POINTER_SIZE
180
181 #define FLOAT_TYPE_SIZE 32
182 #define DOUBLE_TYPE_SIZE 64
183 #define LONG_DOUBLE_TYPE_SIZE 128
184
185 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
186 #define PARM_BOUNDARY BITS_PER_WORD
187
188 /* Allocation boundary (in *bits*) for the code of a function. */
189 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
190
191 /* The smallest supported stack boundary the calling convention supports. */
192 #define STACK_BOUNDARY \
193 (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
194
195 /* The ABI stack alignment. */
196 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
197
198 /* There is no point aligning anything to a rounder boundary than this. */
199 #define BIGGEST_ALIGNMENT 128
200
201 /* The user-level ISA permits unaligned accesses, but they are not required
202 of the privileged architecture. */
203 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
204
205 /* Define this if you wish to imitate the way many other C compilers
206 handle alignment of bitfields and the structures that contain
207 them.
208
209 The behavior is that the type written for a bit-field (`int',
210 `short', or other integer type) imposes an alignment for the
211 entire structure, as if the structure really did contain an
212 ordinary field of that type. In addition, the bit-field is placed
213 within the structure so that it would fit within such a field,
214 not crossing a boundary for it.
215
216 Thus, on most machines, a bit-field whose type is written as `int'
217 would not cross a four-byte boundary, and would force four-byte
218 alignment for the whole structure. (The alignment used may not
219 be four bytes; it is controlled by the other alignment
220 parameters.)
221
222 If the macro is defined, its definition should be a C expression;
223 a nonzero value for the expression enables this behavior. */
224
225 #define PCC_BITFIELD_TYPE_MATTERS 1
226
227 /* An integer expression for the size in bits of the largest integer machine
228 mode that should actually be used. We allow pairs of registers. */
229 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
230
231 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */
232 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \
233 (((COND) && ((ALIGN) < BITS_PER_WORD) \
234 && (TREE_CODE (TYPE) == ARRAY_TYPE \
235 || TREE_CODE (TYPE) == UNION_TYPE \
236 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
237
238 /* If defined, a C expression to compute the alignment for a static
239 variable. TYPE is the data type, and ALIGN is the alignment that
240 the object would ordinarily have. The value of this macro is used
241 instead of that alignment to align the object.
242
243 If this macro is not defined, then ALIGN is used.
244
245 One use of this macro is to increase alignment of medium-size
246 data to make it all fit in fewer cache lines. Another is to
247 cause character arrays to be word-aligned so that `strcpy' calls
248 that copy constants to character arrays can be done inline. */
249
250 #define DATA_ALIGNMENT(TYPE, ALIGN) \
251 RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \
252 TYPE, ALIGN)
253
254 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
255 character arrays to be word-aligned so that `strcpy' calls that copy
256 constants to character arrays can be done inline, and 'strcmp' can be
257 optimised to use word loads. */
258 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
259 RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
260
261 /* Define if operations between registers always perform the operation
262 on the full register even if a narrower mode is specified. */
263 #define WORD_REGISTER_OPERATIONS 1
264
265 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
266 moves. All other references are zero extended. */
267 #define LOAD_EXTEND_OP(MODE) \
268 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
269
270 /* Define this macro if it is advisable to hold scalars in registers
271 in a wider mode than that declared by the program. In such cases,
272 the value is constrained to be within the bounds of the declared
273 type, but kept valid in the wider mode. The signedness of the
274 extension may differ from that of the type. */
275
276 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
277 if (GET_MODE_CLASS (MODE) == MODE_INT \
278 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
279 { \
280 if ((MODE) == SImode) \
281 (UNSIGNEDP) = 0; \
282 (MODE) = word_mode; \
283 }
284
285 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
286 Extensions of pointers to word_mode must be signed. */
287 #define POINTERS_EXTEND_UNSIGNED false
288
289 /* Define if loading short immediate values into registers sign extends. */
290 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
291
292 /* Standard register usage. */
293
294 /* Number of hardware registers. We have:
295
296 - 32 integer registers
297 - 32 floating point registers
298 - 2 fake registers:
299 - ARG_POINTER_REGNUM
300 - FRAME_POINTER_REGNUM
301 - 1 vl register
302 - 1 vtype register
303 - 30 unused registers for future expansion
304 - 32 vector registers */
305
306 #define FIRST_PSEUDO_REGISTER 128
307
308 /* x0, sp, gp, and tp are fixed. */
309
310 #define FIXED_REGISTERS \
311 { /* General registers. */ \
312 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
313 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
314 /* Floating-point registers. */ \
315 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
316 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
317 /* Others. */ \
318 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
319 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
320 /* Vector registers. */ \
321 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
322 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
323 }
324
325 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
326 The call RTLs themselves clobber ra. */
327
328 #define CALL_USED_REGISTERS \
329 { /* General registers. */ \
330 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
331 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
332 /* Floating-point registers. */ \
333 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
334 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
335 /* Others. */ \
336 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
337 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
338 /* Vector registers. */ \
339 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
340 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
341 }
342
343 /* Select a register mode required for caller save of hard regno REGNO.
344 Contrary to what is documented, the default is not the smallest suitable
345 mode but the largest suitable mode for the given (REGNO, NREGS) pair and
346 it quickly creates paradoxical subregs that can be problematic. */
347 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
348 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
349
350 /* Internal macros to classify an ISA register's type. */
351
352 #define GP_REG_FIRST 0
353 #define GP_REG_LAST (TARGET_RVE ? 15 : 31)
354 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
355
356 #define FP_REG_FIRST 32
357 #define FP_REG_LAST 63
358 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
359
360 #define V_REG_FIRST 96
361 #define V_REG_LAST 127
362 #define V_REG_NUM (V_REG_LAST - V_REG_FIRST + 1)
363
364 /* The DWARF 2 CFA column which tracks the return address from a
365 signal handler context. This means that to maintain backwards
366 compatibility, no hard register can be assigned this column if it
367 would need to be handled by the DWARF unwinder. */
368 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
369
370 #define GP_REG_P(REGNO) \
371 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
372 #define FP_REG_P(REGNO) \
373 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
374 #define V_REG_P(REGNO) \
375 ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
376 #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
377 #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
378 #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM)
379 #define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM)
380
381 /* True when REGNO is in SIBCALL_REGS set. */
382 #define SIBCALL_REG_P(REGNO) \
383 TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
384
385 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
386
387 /* Use s0 as the frame pointer if it is so requested. */
388 #define HARD_FRAME_POINTER_REGNUM 8
389 #define STACK_POINTER_REGNUM 2
390 #define THREAD_POINTER_REGNUM 4
391
392 /* These two registers don't really exist: they get eliminated to either
393 the stack or hard frame pointer. */
394 #define ARG_POINTER_REGNUM 64
395 #define FRAME_POINTER_REGNUM 65
396
397 /* Define Dwarf for RVV. */
398 #define RISCV_DWARF_FRM (4096 + 0x003)
399 #define RISCV_DWARF_VXRM (4096 + 0x00a)
400 #define RISCV_DWARF_VL (4096 + 0xc20)
401 #define RISCV_DWARF_VTYPE (4096 + 0xc21)
402 #define RISCV_DWARF_VLENB (4096 + 0xc22)
403
404 /* Register in which static-chain is passed to a function. */
405 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
406
407 /* Registers used as temporaries in prologue/epilogue code.
408
409 The prologue registers mustn't conflict with any
410 incoming arguments, the static chain pointer, or the frame pointer.
411 The epilogue temporary mustn't conflict with the return registers,
412 the frame pointer, the EH stack adjustment, or the EH data registers. */
413
414 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
415 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
416 #define RISCV_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST + 1)
417 #define RISCV_PROLOGUE_TEMP2(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP2_REGNUM)
418
419 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
420 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
421 gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
422
423 #define MCOUNT_NAME "_mcount"
424
425 #define NO_PROFILE_COUNTERS 1
426
427 /* Emit rtl for profiling. Output assembler code to FILE
428 to call "_mcount" for profiling a function entry. */
429 #define PROFILE_HOOK(LABEL) \
430 { \
431 rtx fun, ra; \
432 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \
433 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
434 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \
435 }
436
437 /* All the work done in PROFILE_HOOK, but still required. */
438 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
439
440 /* Define this macro if it is as good or better to call a constant
441 function address than to call an address kept in a register. */
442 #define NO_FUNCTION_CSE 1
443
444 /* Define the classes of registers for register constraints in the
445 machine description. Also define ranges of constants.
446
447 One of the classes must always be named ALL_REGS and include all hard regs.
448 If there is more than one class, another class must be named NO_REGS
449 and contain no registers.
450
451 The name GENERAL_REGS must be the name of a class (or an alias for
452 another name such as ALL_REGS). This is the class of registers
453 that is allowed by "g" or "r" in a register constraint.
454 Also, registers outside this class are allocated only when
455 instructions express preferences for them.
456
457 The classes must be numbered in nondecreasing order; that is,
458 a larger-numbered class must never be contained completely
459 in a smaller-numbered class.
460
461 For any two classes, it is very desirable that there be another
462 class that represents their union. */
463
464 enum reg_class
465 {
466 NO_REGS, /* no registers in set */
467 SIBCALL_REGS, /* registers used by indirect sibcalls */
468 JALR_REGS, /* registers used by indirect calls */
469 GR_REGS, /* integer registers */
470 FP_REGS, /* floating-point registers */
471 FRAME_REGS, /* arg pointer and frame pointer */
472 VM_REGS, /* v0.t registers */
473 VD_REGS, /* vector registers except v0.t */
474 V_REGS, /* vector registers */
475 ALL_REGS, /* all registers */
476 LIM_REG_CLASSES /* max value + 1 */
477 };
478
479 #define N_REG_CLASSES (int) LIM_REG_CLASSES
480
481 #define GENERAL_REGS GR_REGS
482
483 /* An initializer containing the names of the register classes as C
484 string constants. These names are used in writing some of the
485 debugging dumps. */
486
487 #define REG_CLASS_NAMES \
488 { \
489 "NO_REGS", \
490 "SIBCALL_REGS", \
491 "JALR_REGS", \
492 "GR_REGS", \
493 "FP_REGS", \
494 "FRAME_REGS", \
495 "VM_REGS", \
496 "VD_REGS", \
497 "V_REGS", \
498 "ALL_REGS" \
499 }
500
501 /* An initializer containing the contents of the register classes,
502 as integers which are bit masks. The Nth integer specifies the
503 contents of class N. The way the integer MASK is interpreted is
504 that register R is in the class if `MASK & (1 << R)' is 1.
505
506 When the machine has more than 32 registers, an integer does not
507 suffice. Then the integers are replaced by sub-initializers,
508 braced groupings containing several integers. Each
509 sub-initializer must be suitable as an initializer for the type
510 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
511
512 #define REG_CLASS_CONTENTS \
513 { \
514 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
515 { 0xf003fcc0, 0x00000000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
516 { 0xffffffc0, 0x00000000, 0x00000000, 0x00000000 }, /* JALR_REGS */ \
517 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
518 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \
519 { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \
520 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \
521 { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \
522 { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \
523 { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff } /* ALL_REGS */ \
524 }
525
526 /* A C expression whose value is a register class containing hard
527 register REGNO. In general there is more that one such class;
528 choose a class which is "minimal", meaning that no smaller class
529 also contains the register. */
530
531 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
532
533 /* A macro whose definition is the name of the class to which a
534 valid base register must belong. A base register is one used in
535 an address which is the register value plus a displacement. */
536
537 #define BASE_REG_CLASS GR_REGS
538
539 /* A macro whose definition is the name of the class to which a
540 valid index register must belong. An index register is one used
541 in an address where its value is either multiplied by a scale
542 factor or added to another register (as well as added to a
543 displacement). */
544
545 #define INDEX_REG_CLASS NO_REGS
546
547 /* We generally want to put call-clobbered registers ahead of
548 call-saved ones. (IRA expects this.) */
549
550 #define REG_ALLOC_ORDER \
551 { \
552 /* Call-clobbered GPRs. */ \
553 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \
554 /* Call-saved GPRs. */ \
555 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
556 /* GPRs that can never be exposed to the register allocator. */ \
557 0, 2, 3, 4, \
558 /* Call-clobbered FPRs. */ \
559 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \
560 60, 61, 62, 63, \
561 /* Call-saved FPRs. */ \
562 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
563 /* v1 ~ v31 vector registers. */ \
564 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, \
565 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \
566 124, 125, 126, 127, \
567 /* The vector mask register. */ \
568 96, \
569 /* None of the remaining classes have defined call-saved \
570 registers. */ \
571 64, 65, 66, 67 \
572 }
573
574 /* True if VALUE is a signed 12-bit number. */
575
576 #define SMALL_OPERAND(VALUE) \
577 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
578
579 #define POLY_SMALL_OPERAND_P(POLY_VALUE) \
580 (POLY_VALUE.is_constant () ? \
581 SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
582
583 /* True if VALUE can be loaded into a register using LUI. */
584
585 #define LUI_OPERAND(VALUE) \
586 (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \
587 || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
588
589 /* If this is a single bit mask, then we can load it with bseti. Special
590 handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
591 #define SINGLE_BIT_MASK_OPERAND(VALUE) \
592 (pow2p_hwi (TARGET_64BIT \
593 ? (VALUE) \
594 : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1))))
595
596 /* True if VALUE can be represented as an immediate with 1 extra bit
597 set: we check that it is not a SMALL_OPERAND (as this would be true
598 for all small operands) unmodified and turns into a small operand
599 once we clear the top bit. */
600 #define UIMM_EXTRA_BIT_OPERAND(VALUE) \
601 (!SMALL_OPERAND (VALUE) \
602 && SMALL_OPERAND (VALUE & ~(HOST_WIDE_INT_1U << floor_log2 (VALUE))))
603
604 /* Stack layout; function entry, exit and calling. */
605
606 #define STACK_GROWS_DOWNWARD 1
607
608 #define FRAME_GROWS_DOWNWARD 1
609
610 #define RETURN_ADDR_RTX riscv_return_addr
611
612 #define ELIMINABLE_REGS \
613 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
614 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
615 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
616 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
617
618 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
619 (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
620
621 /* Allocate stack space for arguments at the beginning of each function. */
622 #define ACCUMULATE_OUTGOING_ARGS 1
623
624 /* The argument pointer always points to the first argument. */
625 #define FIRST_PARM_OFFSET(FNDECL) 0
626
627 #define REG_PARM_STACK_SPACE(FNDECL) 0
628
629 /* Define this if it is the responsibility of the caller to
630 allocate the area reserved for arguments passed in registers.
631 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
632 of this macro is to determine whether the space is included in
633 `crtl->outgoing_args_size'. */
634 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
635
636 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
637
638 /* Symbolic macros for the registers used to return integer and floating
639 point values. */
640
641 #define GP_RETURN GP_ARG_FIRST
642 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
643
644 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
645
646 /* Symbolic macros for the first/last argument registers. */
647
648 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
649 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
650 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
651 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
652 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
653
654 #define CALLEE_SAVED_REG_NUMBER(REGNO) \
655 ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \
656 (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
657
658 #define LIBCALL_VALUE(MODE) \
659 riscv_function_value (NULL_TREE, NULL_TREE, MODE)
660
661 #define FUNCTION_VALUE(VALTYPE, FUNC) \
662 riscv_function_value (VALTYPE, FUNC, VOIDmode)
663
664 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
665
666 /* 1 if N is a possible register number for function argument passing.
667 We have no FP argument registers when soft-float. */
668
669 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */
670 #define FUNCTION_ARG_REGNO_P(N) \
671 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \
672 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
673
674 typedef struct {
675 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
676 unsigned int num_gprs;
677
678 /* Number of floating-point registers used so far, likewise. */
679 unsigned int num_fprs;
680
681 int rvv_psabi_warning;
682 } CUMULATIVE_ARGS;
683
684 /* Initialize a variable CUM of type CUMULATIVE_ARGS
685 for a call to a function whose data type is FNTYPE.
686 For a library call, FNTYPE is 0. */
687
688 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
689 riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \
690 (N_NAMED_ARGS) != -1)
691
692 #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO)
693
694 /* Align based on stack boundary, which might have been set by the user. */
695 #define RISCV_STACK_ALIGN(LOC) \
696 (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
697
698 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
699 the stack pointer does not matter. The value is tested only in
700 functions that have frame pointers.
701 No definition is equivalent to always zero. */
702
703 #define EXIT_IGNORE_STACK 1
704
705
706 /* Trampolines are a block of code followed by two pointers. */
707
708 #define TRAMPOLINE_CODE_SIZE 16
709 #define TRAMPOLINE_SIZE \
710 ((Pmode == SImode) \
711 ? TRAMPOLINE_CODE_SIZE \
712 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
713 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
714
715 /* Addressing modes, and classification of registers for them. */
716
717 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
718 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
719 riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
720
721 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
722 and check its validity for a certain class.
723 We have two alternate definitions for each of them.
724 The usual definition accepts all pseudo regs; the other rejects them all.
725 The symbol REG_OK_STRICT causes the latter definition to be used.
726
727 Most source files want to accept pseudo regs in the hope that
728 they will get allocated to the class that the insn wants them to be in.
729 Some source files that are used after register allocation
730 need to be strict. */
731
732 #ifndef REG_OK_STRICT
733 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
734 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
735 #else
736 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
737 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
738 #endif
739
740 #define REG_OK_FOR_INDEX_P(X) 0
741
742 /* Maximum number of registers that can appear in a valid memory address. */
743
744 #define MAX_REGS_PER_ADDRESS 1
745
746 #define CONSTANT_ADDRESS_P(X) \
747 (CONSTANT_P (X) && memory_address_p (SImode, X))
748
749 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
750 'the start of the function that this code is output in'. */
751
752 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
753 do { \
754 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
755 asm_fprintf ((FILE), "%U%s", \
756 XSTR (XEXP (DECL_RTL (current_function_decl), \
757 0), 0)); \
758 else \
759 asm_fprintf ((FILE), "%U%s", (NAME)); \
760 } while (0)
761
762 #define JUMP_TABLES_IN_TEXT_SECTION 0
763 #define CASE_VECTOR_MODE SImode
764 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
765
766 #define LOCAL_SYM_P(sym) \
767 ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \
768 || ((GET_CODE (sym) == CONST) \
769 && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \
770 && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))
771
772 /* The load-address macro is used for PC-relative addressing of symbols
773 that bind locally. Don't use it for symbols that should be addressed
774 via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing
775 currently results in more opportunities for linker relaxation. */
776 #define USE_LOAD_ADDRESS_MACRO(sym) \
777 (!TARGET_EXPLICIT_RELOCS && \
778 ((flag_pic && LOCAL_SYM_P (sym)) || riscv_cmodel == CM_MEDANY))
779
780 /* Define this as 1 if `char' should by default be signed; else as 0. */
781 #define DEFAULT_SIGNED_CHAR 0
782
783 #define MOVE_MAX UNITS_PER_WORD
784 #define MAX_MOVE_MAX 8
785
786 /* The SPARC port says:
787 Nonzero if access to memory by bytes is slow and undesirable.
788 For RISC chips, it means that access to memory by bytes is no
789 better than access by words when possible, so grab a whole word
790 and maybe make use of that. */
791 #define SLOW_BYTE_ACCESS 1
792
793 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
794 in the md file instead. */
795 #define SHIFT_COUNT_TRUNCATED 0
796
797 /* Specify the machine mode that pointers have.
798 After generation of rtl, the compiler makes no further distinction
799 between pointers and any other objects of this machine mode. */
800
801 #define Pmode word_mode
802
803 /* Specify the machine mode that registers have. */
804
805 #define Xmode (TARGET_64BIT ? DImode : SImode)
806
807 /* Give call MEMs SImode since it is the "most permissive" mode
808 for both 32-bit and 64-bit targets. */
809
810 #define FUNCTION_MODE SImode
811
812 /* A C expression for the cost of a branch instruction. A value of 2
813 seems to minimize code size. */
814
815 #define BRANCH_COST(speed_p, predictable_p) \
816 ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
817
818 /* True if the target optimizes short forward branches around integer
819 arithmetic instructions into predicated operations, e.g., for
820 conditional-move operations. The macro assumes that all branch
821 instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
822 support this feature. The macro further assumes that any integer
823 arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
824 SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
825 counterparts, including C.MV and C.LI) can be in the branch shadow. */
826
827 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
828
829 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
830
831 /* Control the assembler format that we output. */
832
833 /* Output to assembler file text saying following lines
834 may contain character constants, extra white space, comments, etc. */
835
836 #ifndef ASM_APP_ON
837 #define ASM_APP_ON " #APP\n"
838 #endif
839
840 /* Output to assembler file text saying following lines
841 no longer contain unusual constructs. */
842
843 #ifndef ASM_APP_OFF
844 #define ASM_APP_OFF " #NO_APP\n"
845 #endif
846
847 #define REGISTER_NAMES \
848 { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \
849 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \
850 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \
851 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \
852 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \
853 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \
854 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \
855 "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \
856 "arg", "frame", "vl", "vtype", "vxrm", "frm", "N/A", "N/A", \
857 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
858 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
859 "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", \
860 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
861 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
862 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
863 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",}
864
865 #define ADDITIONAL_REGISTER_NAMES \
866 { \
867 { "x0", 0 + GP_REG_FIRST }, \
868 { "x1", 1 + GP_REG_FIRST }, \
869 { "x2", 2 + GP_REG_FIRST }, \
870 { "x3", 3 + GP_REG_FIRST }, \
871 { "x4", 4 + GP_REG_FIRST }, \
872 { "x5", 5 + GP_REG_FIRST }, \
873 { "x6", 6 + GP_REG_FIRST }, \
874 { "x7", 7 + GP_REG_FIRST }, \
875 { "x8", 8 + GP_REG_FIRST }, \
876 { "x9", 9 + GP_REG_FIRST }, \
877 { "x10", 10 + GP_REG_FIRST }, \
878 { "x11", 11 + GP_REG_FIRST }, \
879 { "x12", 12 + GP_REG_FIRST }, \
880 { "x13", 13 + GP_REG_FIRST }, \
881 { "x14", 14 + GP_REG_FIRST }, \
882 { "x15", 15 + GP_REG_FIRST }, \
883 { "x16", 16 + GP_REG_FIRST }, \
884 { "x17", 17 + GP_REG_FIRST }, \
885 { "x18", 18 + GP_REG_FIRST }, \
886 { "x19", 19 + GP_REG_FIRST }, \
887 { "x20", 20 + GP_REG_FIRST }, \
888 { "x21", 21 + GP_REG_FIRST }, \
889 { "x22", 22 + GP_REG_FIRST }, \
890 { "x23", 23 + GP_REG_FIRST }, \
891 { "x24", 24 + GP_REG_FIRST }, \
892 { "x25", 25 + GP_REG_FIRST }, \
893 { "x26", 26 + GP_REG_FIRST }, \
894 { "x27", 27 + GP_REG_FIRST }, \
895 { "x28", 28 + GP_REG_FIRST }, \
896 { "x29", 29 + GP_REG_FIRST }, \
897 { "x30", 30 + GP_REG_FIRST }, \
898 { "x31", 31 + GP_REG_FIRST }, \
899 { "f0", 0 + FP_REG_FIRST }, \
900 { "f1", 1 + FP_REG_FIRST }, \
901 { "f2", 2 + FP_REG_FIRST }, \
902 { "f3", 3 + FP_REG_FIRST }, \
903 { "f4", 4 + FP_REG_FIRST }, \
904 { "f5", 5 + FP_REG_FIRST }, \
905 { "f6", 6 + FP_REG_FIRST }, \
906 { "f7", 7 + FP_REG_FIRST }, \
907 { "f8", 8 + FP_REG_FIRST }, \
908 { "f9", 9 + FP_REG_FIRST }, \
909 { "f10", 10 + FP_REG_FIRST }, \
910 { "f11", 11 + FP_REG_FIRST }, \
911 { "f12", 12 + FP_REG_FIRST }, \
912 { "f13", 13 + FP_REG_FIRST }, \
913 { "f14", 14 + FP_REG_FIRST }, \
914 { "f15", 15 + FP_REG_FIRST }, \
915 { "f16", 16 + FP_REG_FIRST }, \
916 { "f17", 17 + FP_REG_FIRST }, \
917 { "f18", 18 + FP_REG_FIRST }, \
918 { "f19", 19 + FP_REG_FIRST }, \
919 { "f20", 20 + FP_REG_FIRST }, \
920 { "f21", 21 + FP_REG_FIRST }, \
921 { "f22", 22 + FP_REG_FIRST }, \
922 { "f23", 23 + FP_REG_FIRST }, \
923 { "f24", 24 + FP_REG_FIRST }, \
924 { "f25", 25 + FP_REG_FIRST }, \
925 { "f26", 26 + FP_REG_FIRST }, \
926 { "f27", 27 + FP_REG_FIRST }, \
927 { "f28", 28 + FP_REG_FIRST }, \
928 { "f29", 29 + FP_REG_FIRST }, \
929 { "f30", 30 + FP_REG_FIRST }, \
930 { "f31", 31 + FP_REG_FIRST }, \
931 }
932
933 /* Globalizing directive for a label. */
934 #define GLOBAL_ASM_OP "\t.globl\t"
935
936 /* This is how to store into the string LABEL
937 the symbol_ref name of an internal numbered label where
938 PREFIX is the class of label and NUM is the number within the class.
939 This is suitable for output with `assemble_name'. */
940
941 #undef ASM_GENERATE_INTERNAL_LABEL
942 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
943 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
944
945 /* This is how to output an element of a case-vector that is absolute. */
946
947 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
948 fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
949
950 /* This is how to output an element of a PIC case-vector. */
951
952 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
953 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
954 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
955
956 /* This is how to output an assembler line
957 that says to advance the location counter
958 to a multiple of 2**LOG bytes. */
959
960 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
961 fprintf (STREAM, "\t.align\t%d\n", (LOG))
962
963 /* Define the strings to put out for each section in the object file. */
964 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
965 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
966 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata"
967 #define BSS_SECTION_ASM_OP "\t.bss"
968 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits"
969 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits"
970
971 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
972 do \
973 { \
974 fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
975 reg_names[STACK_POINTER_REGNUM], \
976 reg_names[STACK_POINTER_REGNUM], \
977 TARGET_64BIT ? "sd" : "sw", \
978 reg_names[REGNO], \
979 reg_names[STACK_POINTER_REGNUM]); \
980 } \
981 while (0)
982
983 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
984 do \
985 { \
986 fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \
987 TARGET_64BIT ? "ld" : "lw", \
988 reg_names[REGNO], \
989 reg_names[STACK_POINTER_REGNUM], \
990 reg_names[STACK_POINTER_REGNUM], \
991 reg_names[STACK_POINTER_REGNUM]); \
992 } \
993 while (0)
994
995 #define ASM_COMMENT_START "#"
996
997 #undef SIZE_TYPE
998 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
999
1000 #undef PTRDIFF_TYPE
1001 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
1002
1003 /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */
1004
1005 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
1006
1007 /* The maximum number of bytes that can be copied by a straight-line
1008 cpymemsi implementation. */
1009
1010 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
1011
1012 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1013 move-instruction pairs, we will do a cpymem or libcall instead.
1014 Do not use move_by_pieces at all when strict alignment is not
1015 in effect but the target has slow unaligned accesses; in this
1016 case, cpymem or libcall is more efficient. */
1017
1018 #define MOVE_RATIO(speed) \
1019 (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \
1020 (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \
1021 CLEAR_RATIO (speed) / 2)
1022
1023 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
1024 of the length of a memset call, but use the default otherwise. */
1025
1026 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
1027
1028 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
1029 optimizing for size adjust the ratio to account for the overhead of
1030 loading the constant and replicating it across the word. */
1031
1032 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
1033
1034 #ifndef USED_FOR_TARGET
1035 extern const enum reg_class riscv_regno_to_class[];
1036 extern bool riscv_slow_unaligned_access_p;
1037 extern unsigned riscv_stack_boundary;
1038 extern unsigned riscv_bytes_per_vector_chunk;
1039 extern poly_uint16 riscv_vector_chunks;
1040 extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int);
1041 extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
1042 extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
1043 /* The number of bits and bytes in a RVV vector. */
1044 #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8))
1045 #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
1046 #endif
1047
1048 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1049 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
1050
1051 #define XLEN_SPEC \
1052 "%{march=rv32*:32}" \
1053 "%{march=rv64*:64}" \
1054
1055 #define ABI_SPEC \
1056 "%{mabi=ilp32:ilp32}" \
1057 "%{mabi=ilp32e:ilp32e}" \
1058 "%{mabi=ilp32f:ilp32f}" \
1059 "%{mabi=ilp32d:ilp32d}" \
1060 "%{mabi=lp64:lp64}" \
1061 "%{mabi=lp64f:lp64f}" \
1062 "%{mabi=lp64d:lp64d}" \
1063
1064 /* ISA constants needed for code generation. */
1065 #define OPCODE_LW 0x2003
1066 #define OPCODE_LD 0x3003
1067 #define OPCODE_AUIPC 0x17
1068 #define OPCODE_JALR 0x67
1069 #define OPCODE_LUI 0x37
1070 #define OPCODE_ADDI 0x13
1071 #define SHIFT_RD 7
1072 #define SHIFT_RS1 15
1073 #define SHIFT_IMM 20
1074 #define IMM_BITS 12
1075 #define C_S_BITS 5
1076 #define C_SxSP_BITS 6
1077
1078 #define IMM_REACH (1LL << IMM_BITS)
1079 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
1080 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
1081
1082 #define SWSP_REACH (4LL << C_SxSP_BITS)
1083 #define SDSP_REACH (8LL << C_SxSP_BITS)
1084
1085 /* This is the maximum value that can be represented in a compressed load/store
1086 offset (an unsigned 5-bit value scaled by 4). */
1087 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
1088
1089 /* Called from RISCV_REORG, this is defined in riscv-sr.cc. */
1090
1091 extern void riscv_remove_unneeded_save_restore_calls (void);
1092
1093 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
1094
1095 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1096 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1097 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1098 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1099
1100 #define TARGET_SUPPORTS_WIDE_INT 1
1101
1102 #define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
1103
1104 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
1105
1106 #define RISCV_DWARF_VLENB (4096 + 0xc22)
1107
1108 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */)
1109
1110 #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
1111 ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO)
1112
1113 /* Like s390, riscv also defined this macro for the vector comparision. Then
1114 the simplify-rtx relational_result will canonicalize the result to the
1115 CONST1_RTX for the simplification. */
1116 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE))
1117
1118 /* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
1119 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
1120 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
1121
1122 #endif /* ! GCC_RISCV_H */
Mirror of https://gcc.gnu.org/git/gcc.git