gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2021 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Target CPU versions for D.  */
  31 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions
  32
  33 /* Default target_flags if no switches are specified  */
  34
  35 #ifndef TARGET_DEFAULT
  36 #define TARGET_DEFAULT 0
  37 #endif
  38
  39 #ifndef RISCV_TUNE_STRING_DEFAULT
  40 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  41 #endif
  42
  43 extern const char *riscv_expand_arch (int argc, const char **argv);
  44 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv);
  45 extern const char *riscv_default_mtune (int argc, const char **argv);
  46
  47 # define EXTRA_SPEC_FUNCTIONS                                           \
  48   { "riscv_expand_arch", riscv_expand_arch },                           \
  49   { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu },         \
  50   { "riscv_default_mtune", riscv_default_mtune },
  51
  52 /* Support for a compile-time default CPU, et cetera.  The rules are:
  53    --with-arch is ignored if -march or -mcpu is specified.
  54    --with-abi is ignored if -mabi is specified.
  55    --with-tune is ignored if -mtune or -mcpu is specified.
  56
  57    But using default -march/-mtune value if -mcpu don't have valid option.  */
  58 #define OPTION_DEFAULT_SPECS \
  59   {"tune", "%{!mtune=*:"                                                \
  60            "  %{!mcpu=*:-mtune=%(VALUE)}"                               \
  61            "  %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" },  \
  62   {"arch", "%{!march=*:"                                                \
  63            "  %{!mcpu=*:-march=%(VALUE)}"                               \
  64            "  %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" },  \
  65   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  66
  67 #ifdef IN_LIBGCC2
  68 #undef TARGET_64BIT
  69 /* Make this compile time constant for libgcc2 */
  70 #define TARGET_64BIT           (__riscv_xlen == 64)
  71 #endif /* IN_LIBGCC2 */
  72
  73 #ifdef HAVE_AS_MISA_SPEC
  74 #define ASM_MISA_SPEC "%{misa-spec=*}"
  75 #else
  76 #define ASM_MISA_SPEC ""
  77 #endif
  78
  79 /* Reference:
  80      https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing  */
  81 #define STRINGIZING(s) __STRINGIZING(s)
  82 #define __STRINGIZING(s) #s
  83
  84 #define MULTILIB_DEFAULTS \
  85   {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \
  86    "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) }
  87
  88 #undef ASM_SPEC
  89 #define ASM_SPEC "\
  90 %(subtarget_asm_debugging_spec) \
  91 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  92 %{march=*} \
  93 %{mabi=*} \
  94 %{mbig-endian} \
  95 %{mlittle-endian} \
  96 %(subtarget_asm_spec)" \
  97 ASM_MISA_SPEC
  98
  99 #undef DRIVER_SELF_SPECS
 100 #define DRIVER_SELF_SPECS                                       \
 101 "%{march=*:%:riscv_expand_arch(%*)} "                           \
 102 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
 103
 104 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
 105
 106 #define LOCAL_LABEL_PREFIX      "."
 107 #define USER_LABEL_PREFIX       ""
 108
 109 /* Offsets recorded in opcodes are a multiple of this alignment factor.
 110    The default for this in 64-bit mode is 8, which causes problems with
 111    SFmode register saves.  */
 112 #define DWARF_CIE_DATA_ALIGNMENT -4
 113
 114 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 115 #define DWARF_FRAME_REGNUM(REGNO) \
 116   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
 117
 118 /* The DWARF 2 CFA column which tracks the return address.  */
 119 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
 120 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
 121
 122 /* Describe how we implement __builtin_eh_return.  */
 123 #define EH_RETURN_DATA_REGNO(N) \
 124   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 125
 126 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
 127
 128 /* Target machine storage layout */
 129
 130 #define BITS_BIG_ENDIAN 0
 131 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 132 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
 133
 134 #define MAX_BITS_PER_WORD 64
 135
 136 /* Width of a word, in units (bytes).  */
 137 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 138 #ifndef IN_LIBGCC2
 139 #define MIN_UNITS_PER_WORD 4
 140 #endif
 141
 142 /* The `Q' extension is not yet supported.  */
 143 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 144
 145 /* The largest type that can be passed in floating-point registers.  */
 146 #define UNITS_PER_FP_ARG                                                \
 147   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 148     || riscv_abi == ABI_LP64)                                           \
 149    ? 0                                                                  \
 150    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 151
 152 /* Set the sizes of the core types.  */
 153 #define SHORT_TYPE_SIZE 16
 154 #define INT_TYPE_SIZE 32
 155 #define LONG_LONG_TYPE_SIZE 64
 156 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 157 #define LONG_TYPE_SIZE POINTER_SIZE
 158
 159 #define FLOAT_TYPE_SIZE 32
 160 #define DOUBLE_TYPE_SIZE 64
 161 #define LONG_DOUBLE_TYPE_SIZE 128
 162
 163 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 164 #define PARM_BOUNDARY BITS_PER_WORD
 165
 166 /* Allocation boundary (in *bits*) for the code of a function.  */
 167 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 168
 169 /* The smallest supported stack boundary the calling convention supports.  */
 170 #define STACK_BOUNDARY \
 171   (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
 172
 173 /* The ABI stack alignment.  */
 174 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
 175
 176 /* There is no point aligning anything to a rounder boundary than this.  */
 177 #define BIGGEST_ALIGNMENT 128
 178
 179 /* The user-level ISA permits unaligned accesses, but they are not required
 180    of the privileged architecture.  */
 181 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 182
 183 /* Define this if you wish to imitate the way many other C compilers
 184    handle alignment of bitfields and the structures that contain
 185    them.
 186
 187    The behavior is that the type written for a bit-field (`int',
 188    `short', or other integer type) imposes an alignment for the
 189    entire structure, as if the structure really did contain an
 190    ordinary field of that type.  In addition, the bit-field is placed
 191    within the structure so that it would fit within such a field,
 192    not crossing a boundary for it.
 193
 194    Thus, on most machines, a bit-field whose type is written as `int'
 195    would not cross a four-byte boundary, and would force four-byte
 196    alignment for the whole structure.  (The alignment used may not
 197    be four bytes; it is controlled by the other alignment
 198    parameters.)
 199
 200    If the macro is defined, its definition should be a C expression;
 201    a nonzero value for the expression enables this behavior.  */
 202
 203 #define PCC_BITFIELD_TYPE_MATTERS 1
 204
 205 /* An integer expression for the size in bits of the largest integer machine
 206    mode that should actually be used.  We allow pairs of registers.  */
 207 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 208
 209 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
 210 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)                       \
 211   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 212     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 213         || TREE_CODE (TYPE) == UNION_TYPE                               \
 214         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 215
 216 /* If defined, a C expression to compute the alignment for a static
 217    variable.  TYPE is the data type, and ALIGN is the alignment that
 218    the object would ordinarily have.  The value of this macro is used
 219    instead of that alignment to align the object.
 220
 221    If this macro is not defined, then ALIGN is used.
 222
 223    One use of this macro is to increase alignment of medium-size
 224    data to make it all fit in fewer cache lines.  Another is to
 225    cause character arrays to be word-aligned so that `strcpy' calls
 226    that copy constants to character arrays can be done inline.  */
 227
 228 #define DATA_ALIGNMENT(TYPE, ALIGN)                                             \
 229   RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,  \
 230                           TYPE, ALIGN)
 231
 232 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 233    character arrays to be word-aligned so that `strcpy' calls that copy
 234    constants to character arrays can be done inline, and 'strcmp' can be
 235    optimised to use word loads. */
 236 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 237   RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
 238
 239 /* Define if operations between registers always perform the operation
 240    on the full register even if a narrower mode is specified.  */
 241 #define WORD_REGISTER_OPERATIONS 1
 242
 243 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 244    moves.  All other references are zero extended.  */
 245 #define LOAD_EXTEND_OP(MODE) \
 246   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 247
 248 /* Define this macro if it is advisable to hold scalars in registers
 249    in a wider mode than that declared by the program.  In such cases,
 250    the value is constrained to be within the bounds of the declared
 251    type, but kept valid in the wider mode.  The signedness of the
 252    extension may differ from that of the type.  */
 253
 254 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 255   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 256       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 257     {                                           \
 258       if ((MODE) == SImode)                     \
 259         (UNSIGNEDP) = 0;                        \
 260       (MODE) = word_mode;                       \
 261     }
 262
 263 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 264    Extensions of pointers to word_mode must be signed.  */
 265 #define POINTERS_EXTEND_UNSIGNED false
 266
 267 /* Define if loading short immediate values into registers sign extends.  */
 268 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 269
 270 /* Standard register usage.  */
 271
 272 /* Number of hardware registers.  We have:
 273
 274    - 32 integer registers
 275    - 32 floating point registers
 276    - 2 fake registers:
 277         - ARG_POINTER_REGNUM
 278         - FRAME_POINTER_REGNUM */
 279
 280 #define FIRST_PSEUDO_REGISTER 66
 281
 282 /* x0, sp, gp, and tp are fixed.  */
 283
 284 #define FIXED_REGISTERS                                                 \
 285 { /* General registers.  */                                             \
 286   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 287   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 288   /* Floating-point registers.  */                                      \
 289   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 290   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 291   /* Others.  */                                                        \
 292   1, 1                                                                  \
 293 }
 294
 295 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 296    The call RTLs themselves clobber ra.  */
 297
 298 #define CALL_USED_REGISTERS                                             \
 299 { /* General registers.  */                                             \
 300   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 301   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 302   /* Floating-point registers.  */                                      \
 303   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 304   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 305   /* Others.  */                                                        \
 306   1, 1                                                                  \
 307 }
 308
 309 /* Select a register mode required for caller save of hard regno REGNO.
 310    Contrary to what is documented, the default is not the smallest suitable
 311    mode but the largest suitable mode for the given (REGNO, NREGS) pair and
 312    it quickly creates paradoxical subregs that can be problematic.  */
 313 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 314   ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
 315
 316 /* Internal macros to classify an ISA register's type.  */
 317
 318 #define GP_REG_FIRST 0
 319 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 320 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 321
 322 #define FP_REG_FIRST 32
 323 #define FP_REG_LAST  63
 324 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 325
 326 /* The DWARF 2 CFA column which tracks the return address from a
 327    signal handler context.  This means that to maintain backwards
 328    compatibility, no hard register can be assigned this column if it
 329    would need to be handled by the DWARF unwinder.  */
 330 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 331
 332 #define GP_REG_P(REGNO) \
 333   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 334 #define FP_REG_P(REGNO)  \
 335   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 336
 337 /* True when REGNO is in SIBCALL_REGS set.  */
 338 #define SIBCALL_REG_P(REGNO)    \
 339   TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
 340
 341 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 342
 343 /* Use s0 as the frame pointer if it is so requested.  */
 344 #define HARD_FRAME_POINTER_REGNUM 8
 345 #define STACK_POINTER_REGNUM 2
 346 #define THREAD_POINTER_REGNUM 4
 347
 348 /* These two registers don't really exist: they get eliminated to either
 349    the stack or hard frame pointer.  */
 350 #define ARG_POINTER_REGNUM 64
 351 #define FRAME_POINTER_REGNUM 65
 352
 353 /* Register in which static-chain is passed to a function.  */
 354 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 355
 356 /* Registers used as temporaries in prologue/epilogue code.
 357
 358    The prologue registers mustn't conflict with any
 359    incoming arguments, the static chain pointer, or the frame pointer.
 360    The epilogue temporary mustn't conflict with the return registers,
 361    the frame pointer, the EH stack adjustment, or the EH data registers. */
 362
 363 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
 364 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 365
 366 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 367 #define RISCV_CALL_ADDRESS_TEMP(MODE) \
 368   gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
 369
 370 #define MCOUNT_NAME "_mcount"
 371
 372 #define NO_PROFILE_COUNTERS 1
 373
 374 /* Emit rtl for profiling.  Output assembler code to FILE
 375    to call "_mcount" for profiling a function entry.  */
 376 #define PROFILE_HOOK(LABEL)                                             \
 377   {                                                                     \
 378     rtx fun, ra;                                                        \
 379     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 380     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 381     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 382   }
 383
 384 /* All the work done in PROFILE_HOOK, but still required.  */
 385 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 386
 387 /* Define this macro if it is as good or better to call a constant
 388    function address than to call an address kept in a register.  */
 389 #define NO_FUNCTION_CSE 1
 390
 391 /* Define the classes of registers for register constraints in the
 392    machine description.  Also define ranges of constants.
 393
 394    One of the classes must always be named ALL_REGS and include all hard regs.
 395    If there is more than one class, another class must be named NO_REGS
 396    and contain no registers.
 397
 398    The name GENERAL_REGS must be the name of a class (or an alias for
 399    another name such as ALL_REGS).  This is the class of registers
 400    that is allowed by "g" or "r" in a register constraint.
 401    Also, registers outside this class are allocated only when
 402    instructions express preferences for them.
 403
 404    The classes must be numbered in nondecreasing order; that is,
 405    a larger-numbered class must never be contained completely
 406    in a smaller-numbered class.
 407
 408    For any two classes, it is very desirable that there be another
 409    class that represents their union.  */
 410
 411 enum reg_class
 412 {
 413   NO_REGS,                      /* no registers in set */
 414   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 415   JALR_REGS,                    /* registers used by indirect calls */
 416   GR_REGS,                      /* integer registers */
 417   FP_REGS,                      /* floating-point registers */
 418   FRAME_REGS,                   /* arg pointer and frame pointer */
 419   ALL_REGS,                     /* all registers */
 420   LIM_REG_CLASSES               /* max value + 1 */
 421 };
 422
 423 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 424
 425 #define GENERAL_REGS GR_REGS
 426
 427 /* An initializer containing the names of the register classes as C
 428    string constants.  These names are used in writing some of the
 429    debugging dumps.  */
 430
 431 #define REG_CLASS_NAMES                                                 \
 432 {                                                                       \
 433   "NO_REGS",                                                            \
 434   "SIBCALL_REGS",                                                       \
 435   "JALR_REGS",                                                          \
 436   "GR_REGS",                                                            \
 437   "FP_REGS",                                                            \
 438   "FRAME_REGS",                                                         \
 439   "ALL_REGS"                                                            \
 440 }
 441
 442 /* An initializer containing the contents of the register classes,
 443    as integers which are bit masks.  The Nth integer specifies the
 444    contents of class N.  The way the integer MASK is interpreted is
 445    that register R is in the class if `MASK & (1 << R)' is 1.
 446
 447    When the machine has more than 32 registers, an integer does not
 448    suffice.  Then the integers are replaced by sub-initializers,
 449    braced groupings containing several integers.  Each
 450    sub-initializer must be suitable as an initializer for the type
 451    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 452
 453 #define REG_CLASS_CONTENTS                                              \
 454 {                                                                       \
 455   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 456   { 0xf003fcc0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 457   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 458   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 459   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 460   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 461   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 462 }
 463
 464 /* A C expression whose value is a register class containing hard
 465    register REGNO.  In general there is more that one such class;
 466    choose a class which is "minimal", meaning that no smaller class
 467    also contains the register.  */
 468
 469 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 470
 471 /* A macro whose definition is the name of the class to which a
 472    valid base register must belong.  A base register is one used in
 473    an address which is the register value plus a displacement.  */
 474
 475 #define BASE_REG_CLASS GR_REGS
 476
 477 /* A macro whose definition is the name of the class to which a
 478    valid index register must belong.  An index register is one used
 479    in an address where its value is either multiplied by a scale
 480    factor or added to another register (as well as added to a
 481    displacement).  */
 482
 483 #define INDEX_REG_CLASS NO_REGS
 484
 485 /* We generally want to put call-clobbered registers ahead of
 486    call-saved ones.  (IRA expects this.)  */
 487
 488 #define REG_ALLOC_ORDER                                                 \
 489 { \
 490   /* Call-clobbered GPRs.  */                                           \
 491   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 492   /* Call-saved GPRs.  */                                               \
 493   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 494   /* GPRs that can never be exposed to the register allocator.  */      \
 495   0, 2, 3, 4,                                                           \
 496   /* Call-clobbered FPRs.  */                                           \
 497   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 498   60, 61, 62, 63,                                                       \
 499   /* Call-saved FPRs.  */                                               \
 500   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 501   /* None of the remaining classes have defined call-saved              \
 502      registers.  */                                                     \
 503   64, 65                                                                \
 504 }
 505
 506 /* True if VALUE is a signed 12-bit number.  */
 507
 508 #define SMALL_OPERAND(VALUE) \
 509   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 510
 511 /* True if VALUE can be loaded into a register using LUI.  */
 512
 513 #define LUI_OPERAND(VALUE)                                              \
 514   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 515    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 516
 517 /* Stack layout; function entry, exit and calling.  */
 518
 519 #define STACK_GROWS_DOWNWARD 1
 520
 521 #define FRAME_GROWS_DOWNWARD 1
 522
 523 #define RETURN_ADDR_RTX riscv_return_addr
 524
 525 #define ELIMINABLE_REGS                                                 \
 526 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 527  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 528  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 529  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 530
 531 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 532   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 533
 534 /* Allocate stack space for arguments at the beginning of each function.  */
 535 #define ACCUMULATE_OUTGOING_ARGS 1
 536
 537 /* The argument pointer always points to the first argument.  */
 538 #define FIRST_PARM_OFFSET(FNDECL) 0
 539
 540 #define REG_PARM_STACK_SPACE(FNDECL) 0
 541
 542 /* Define this if it is the responsibility of the caller to
 543    allocate the area reserved for arguments passed in registers.
 544    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 545    of this macro is to determine whether the space is included in
 546    `crtl->outgoing_args_size'.  */
 547 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 548
 549 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 550
 551 /* Symbolic macros for the registers used to return integer and floating
 552    point values.  */
 553
 554 #define GP_RETURN GP_ARG_FIRST
 555 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 556
 557 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
 558
 559 /* Symbolic macros for the first/last argument registers.  */
 560
 561 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 562 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 563 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 564 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 565 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 566
 567 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 568   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 569    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 570
 571 #define LIBCALL_VALUE(MODE) \
 572   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 573
 574 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 575   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 576
 577 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 578
 579 /* 1 if N is a possible register number for function argument passing.
 580    We have no FP argument registers when soft-float.  */
 581
 582 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 583 #define FUNCTION_ARG_REGNO_P(N)                                         \
 584   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 585    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 586
 587 typedef struct {
 588   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 589   unsigned int num_gprs;
 590
 591   /* Number of floating-point registers used so far, likewise.  */
 592   unsigned int num_fprs;
 593 } CUMULATIVE_ARGS;
 594
 595 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 596    for a call to a function whose data type is FNTYPE.
 597    For a library call, FNTYPE is 0.  */
 598
 599 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 600   memset (&(CUM), 0, sizeof (CUM))
 601
 602 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 603
 604 /* Align based on stack boundary, which might have been set by the user.  */
 605 #define RISCV_STACK_ALIGN(LOC) \
 606   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 607
 608 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 609    the stack pointer does not matter.  The value is tested only in
 610    functions that have frame pointers.
 611    No definition is equivalent to always zero.  */
 612
 613 #define EXIT_IGNORE_STACK 1
 614
 615
 616 /* Trampolines are a block of code followed by two pointers.  */
 617
 618 #define TRAMPOLINE_CODE_SIZE 16
 619 #define TRAMPOLINE_SIZE         \
 620   ((Pmode == SImode)            \
 621    ? TRAMPOLINE_CODE_SIZE       \
 622    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 623 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 624
 625 /* Addressing modes, and classification of registers for them.  */
 626
 627 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 628 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 629   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 630
 631 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 632    and check its validity for a certain class.
 633    We have two alternate definitions for each of them.
 634    The usual definition accepts all pseudo regs; the other rejects them all.
 635    The symbol REG_OK_STRICT causes the latter definition to be used.
 636
 637    Most source files want to accept pseudo regs in the hope that
 638    they will get allocated to the class that the insn wants them to be in.
 639    Some source files that are used after register allocation
 640    need to be strict.  */
 641
 642 #ifndef REG_OK_STRICT
 643 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 644   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 645 #else
 646 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 647   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 648 #endif
 649
 650 #define REG_OK_FOR_INDEX_P(X) 0
 651
 652 /* Maximum number of registers that can appear in a valid memory address.  */
 653
 654 #define MAX_REGS_PER_ADDRESS 1
 655
 656 #define CONSTANT_ADDRESS_P(X) \
 657   (CONSTANT_P (X) && memory_address_p (SImode, X))
 658
 659 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 660    'the start of the function that this code is output in'.  */
 661
 662 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 663   do {                                                                  \
 664     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 665       asm_fprintf ((FILE), "%U%s",                                      \
 666                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 667                                0), 0));                                 \
 668     else                                                                \
 669       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 670   } while (0)
 671
 672 #define JUMP_TABLES_IN_TEXT_SECTION 0
 673 #define CASE_VECTOR_MODE SImode
 674 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 675
 676 /* The load-address macro is used for PC-relative addressing of symbols
 677    that bind locally.  Don't use it for symbols that should be addressed
 678    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 679    currently results in more opportunities for linker relaxation.  */
 680 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 681   (!TARGET_EXPLICIT_RELOCS &&                                           \
 682    ((flag_pic                                                           \
 683      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 684          || ((GET_CODE (sym) == CONST)                                  \
 685              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 686              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 687      || riscv_cmodel == CM_MEDANY))
 688
 689 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 690 #define DEFAULT_SIGNED_CHAR 0
 691
 692 #define MOVE_MAX UNITS_PER_WORD
 693 #define MAX_MOVE_MAX 8
 694
 695 /* The SPARC port says:
 696    Nonzero if access to memory by bytes is slow and undesirable.
 697    For RISC chips, it means that access to memory by bytes is no
 698    better than access by words when possible, so grab a whole word
 699    and maybe make use of that.  */
 700 #define SLOW_BYTE_ACCESS 1
 701
 702 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 703    in the md file instead.  */
 704 #define SHIFT_COUNT_TRUNCATED 0
 705
 706 /* Specify the machine mode that pointers have.
 707    After generation of rtl, the compiler makes no further distinction
 708    between pointers and any other objects of this machine mode.  */
 709
 710 #define Pmode word_mode
 711
 712 /* Give call MEMs SImode since it is the "most permissive" mode
 713    for both 32-bit and 64-bit targets.  */
 714
 715 #define FUNCTION_MODE SImode
 716
 717 /* A C expression for the cost of a branch instruction.  A value of 2
 718    seems to minimize code size.  */
 719
 720 #define BRANCH_COST(speed_p, predictable_p) \
 721   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 722
 723 /* True if the target optimizes short forward branches around integer
 724    arithmetic instructions into predicated operations, e.g., for
 725    conditional-move operations.  The macro assumes that all branch
 726    instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
 727    support this feature.  The macro further assumes that any integer
 728    arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
 729    SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
 730    counterparts, including C.MV and C.LI) can be in the branch shadow.  */
 731
 732 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
 733
 734 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 735
 736 /* Control the assembler format that we output.  */
 737
 738 /* Output to assembler file text saying following lines
 739    may contain character constants, extra white space, comments, etc.  */
 740
 741 #ifndef ASM_APP_ON
 742 #define ASM_APP_ON " #APP\n"
 743 #endif
 744
 745 /* Output to assembler file text saying following lines
 746    no longer contain unusual constructs.  */
 747
 748 #ifndef ASM_APP_OFF
 749 #define ASM_APP_OFF " #NO_APP\n"
 750 #endif
 751
 752 #define REGISTER_NAMES                                          \
 753 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 754   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 755   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 756   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 757   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 758   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 759   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 760   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 761   "arg", "frame", }
 762
 763 #define ADDITIONAL_REGISTER_NAMES                                       \
 764 {                                                                       \
 765   { "x0",        0 + GP_REG_FIRST },                                    \
 766   { "x1",        1 + GP_REG_FIRST },                                    \
 767   { "x2",        2 + GP_REG_FIRST },                                    \
 768   { "x3",        3 + GP_REG_FIRST },                                    \
 769   { "x4",        4 + GP_REG_FIRST },                                    \
 770   { "x5",        5 + GP_REG_FIRST },                                    \
 771   { "x6",        6 + GP_REG_FIRST },                                    \
 772   { "x7",        7 + GP_REG_FIRST },                                    \
 773   { "x8",        8 + GP_REG_FIRST },                                    \
 774   { "x9",        9 + GP_REG_FIRST },                                    \
 775   { "x10",      10 + GP_REG_FIRST },                                    \
 776   { "x11",      11 + GP_REG_FIRST },                                    \
 777   { "x12",      12 + GP_REG_FIRST },                                    \
 778   { "x13",      13 + GP_REG_FIRST },                                    \
 779   { "x14",      14 + GP_REG_FIRST },                                    \
 780   { "x15",      15 + GP_REG_FIRST },                                    \
 781   { "x16",      16 + GP_REG_FIRST },                                    \
 782   { "x17",      17 + GP_REG_FIRST },                                    \
 783   { "x18",      18 + GP_REG_FIRST },                                    \
 784   { "x19",      19 + GP_REG_FIRST },                                    \
 785   { "x20",      20 + GP_REG_FIRST },                                    \
 786   { "x21",      21 + GP_REG_FIRST },                                    \
 787   { "x22",      22 + GP_REG_FIRST },                                    \
 788   { "x23",      23 + GP_REG_FIRST },                                    \
 789   { "x24",      24 + GP_REG_FIRST },                                    \
 790   { "x25",      25 + GP_REG_FIRST },                                    \
 791   { "x26",      26 + GP_REG_FIRST },                                    \
 792   { "x27",      27 + GP_REG_FIRST },                                    \
 793   { "x28",      28 + GP_REG_FIRST },                                    \
 794   { "x29",      29 + GP_REG_FIRST },                                    \
 795   { "x30",      30 + GP_REG_FIRST },                                    \
 796   { "x31",      31 + GP_REG_FIRST },                                    \
 797   { "f0",        0 + FP_REG_FIRST },                                    \
 798   { "f1",        1 + FP_REG_FIRST },                                    \
 799   { "f2",        2 + FP_REG_FIRST },                                    \
 800   { "f3",        3 + FP_REG_FIRST },                                    \
 801   { "f4",        4 + FP_REG_FIRST },                                    \
 802   { "f5",        5 + FP_REG_FIRST },                                    \
 803   { "f6",        6 + FP_REG_FIRST },                                    \
 804   { "f7",        7 + FP_REG_FIRST },                                    \
 805   { "f8",        8 + FP_REG_FIRST },                                    \
 806   { "f9",        9 + FP_REG_FIRST },                                    \
 807   { "f10",      10 + FP_REG_FIRST },                                    \
 808   { "f11",      11 + FP_REG_FIRST },                                    \
 809   { "f12",      12 + FP_REG_FIRST },                                    \
 810   { "f13",      13 + FP_REG_FIRST },                                    \
 811   { "f14",      14 + FP_REG_FIRST },                                    \
 812   { "f15",      15 + FP_REG_FIRST },                                    \
 813   { "f16",      16 + FP_REG_FIRST },                                    \
 814   { "f17",      17 + FP_REG_FIRST },                                    \
 815   { "f18",      18 + FP_REG_FIRST },                                    \
 816   { "f19",      19 + FP_REG_FIRST },                                    \
 817   { "f20",      20 + FP_REG_FIRST },                                    \
 818   { "f21",      21 + FP_REG_FIRST },                                    \
 819   { "f22",      22 + FP_REG_FIRST },                                    \
 820   { "f23",      23 + FP_REG_FIRST },                                    \
 821   { "f24",      24 + FP_REG_FIRST },                                    \
 822   { "f25",      25 + FP_REG_FIRST },                                    \
 823   { "f26",      26 + FP_REG_FIRST },                                    \
 824   { "f27",      27 + FP_REG_FIRST },                                    \
 825   { "f28",      28 + FP_REG_FIRST },                                    \
 826   { "f29",      29 + FP_REG_FIRST },                                    \
 827   { "f30",      30 + FP_REG_FIRST },                                    \
 828   { "f31",      31 + FP_REG_FIRST },                                    \
 829 }
 830
 831 /* Globalizing directive for a label.  */
 832 #define GLOBAL_ASM_OP "\t.globl\t"
 833
 834 /* This is how to store into the string LABEL
 835    the symbol_ref name of an internal numbered label where
 836    PREFIX is the class of label and NUM is the number within the class.
 837    This is suitable for output with `assemble_name'.  */
 838
 839 #undef ASM_GENERATE_INTERNAL_LABEL
 840 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 841   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 842
 843 /* This is how to output an element of a case-vector that is absolute.  */
 844
 845 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 846   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 847
 848 /* This is how to output an element of a PIC case-vector. */
 849
 850 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 851   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 852            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 853
 854 /* This is how to output an assembler line
 855    that says to advance the location counter
 856    to a multiple of 2**LOG bytes.  */
 857
 858 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 859   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 860
 861 /* Define the strings to put out for each section in the object file.  */
 862 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 863 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 864 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 865 #define BSS_SECTION_ASM_OP      "\t.bss"
 866 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 867 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 868
 869 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 870 do                                                                      \
 871   {                                                                     \
 872     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 873              reg_names[STACK_POINTER_REGNUM],                           \
 874              reg_names[STACK_POINTER_REGNUM],                           \
 875              TARGET_64BIT ? "sd" : "sw",                                \
 876              reg_names[REGNO],                                          \
 877              reg_names[STACK_POINTER_REGNUM]);                          \
 878   }                                                                     \
 879 while (0)
 880
 881 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 882 do                                                                      \
 883   {                                                                     \
 884     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 885              TARGET_64BIT ? "ld" : "lw",                                \
 886              reg_names[REGNO],                                          \
 887              reg_names[STACK_POINTER_REGNUM],                           \
 888              reg_names[STACK_POINTER_REGNUM],                           \
 889              reg_names[STACK_POINTER_REGNUM]);                          \
 890   }                                                                     \
 891 while (0)
 892
 893 #define ASM_COMMENT_START "#"
 894
 895 #undef SIZE_TYPE
 896 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 897
 898 #undef PTRDIFF_TYPE
 899 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 900
 901 /* The maximum number of bytes copied by one iteration of a cpymemsi loop.  */
 902
 903 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
 904
 905 /* The maximum number of bytes that can be copied by a straight-line
 906    cpymemsi implementation.  */
 907
 908 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
 909
 910 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 911    move-instruction pairs, we will do a cpymem or libcall instead.
 912    Do not use move_by_pieces at all when strict alignment is not
 913    in effect but the target has slow unaligned accesses; in this
 914    case, cpymem or libcall is more efficient.  */
 915
 916 #define MOVE_RATIO(speed)                                               \
 917   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
 918    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
 919    CLEAR_RATIO (speed) / 2)
 920
 921 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 922    of the length of a memset call, but use the default otherwise.  */
 923
 924 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 925
 926 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 927    optimizing for size adjust the ratio to account for the overhead of
 928    loading the constant and replicating it across the word.  */
 929
 930 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 931
 932 #ifndef USED_FOR_TARGET
 933 extern const enum reg_class riscv_regno_to_class[];
 934 extern bool riscv_slow_unaligned_access_p;
 935 extern unsigned riscv_stack_boundary;
 936 #endif
 937
 938 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 939   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 940
 941 #define XLEN_SPEC \
 942   "%{march=rv32*:32}" \
 943   "%{march=rv64*:64}" \
 944
 945 #define ABI_SPEC \
 946   "%{mabi=ilp32:ilp32}" \
 947   "%{mabi=ilp32e:ilp32e}" \
 948   "%{mabi=ilp32f:ilp32f}" \
 949   "%{mabi=ilp32d:ilp32d}" \
 950   "%{mabi=lp64:lp64}" \
 951   "%{mabi=lp64f:lp64f}" \
 952   "%{mabi=lp64d:lp64d}" \
 953
 954 /* ISA constants needed for code generation.  */
 955 #define OPCODE_LW    0x2003
 956 #define OPCODE_LD    0x3003
 957 #define OPCODE_AUIPC 0x17
 958 #define OPCODE_JALR  0x67
 959 #define OPCODE_LUI   0x37
 960 #define OPCODE_ADDI  0x13
 961 #define SHIFT_RD  7
 962 #define SHIFT_RS1 15
 963 #define SHIFT_IMM 20
 964 #define IMM_BITS 12
 965 #define C_S_BITS 5
 966 #define C_SxSP_BITS 6
 967
 968 #define IMM_REACH (1LL << IMM_BITS)
 969 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 970 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 971
 972 #define SWSP_REACH (4LL << C_SxSP_BITS)
 973 #define SDSP_REACH (8LL << C_SxSP_BITS)
 974
 975 /* This is the maximum value that can be represented in a compressed load/store
 976    offset (an unsigned 5-bit value scaled by 4).  */
 977 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3)
 978
 979 /* Called from RISCV_REORG, this is defined in riscv-sr.c.  */
 980
 981 extern void riscv_remove_unneeded_save_restore_calls (void);
 982
 983 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
 984
 985 #endif /* ! GCC_RISCV_H */