gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2020 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Target CPU versions for D.  */
  31 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions
  32
  33 /* Default target_flags if no switches are specified  */
  34
  35 #ifndef TARGET_DEFAULT
  36 #define TARGET_DEFAULT 0
  37 #endif
  38
  39 #ifndef RISCV_TUNE_STRING_DEFAULT
  40 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  41 #endif
  42
  43 extern const char *riscv_expand_arch (int argc, const char **argv);
  44
  45 # define EXTRA_SPEC_FUNCTIONS                                           \
  46   { "riscv_expand_arch", riscv_expand_arch },
  47
  48 /* Support for a compile-time default CPU, et cetera.  The rules are:
  49    --with-arch is ignored if -march is specified.
  50    --with-abi is ignored if -mabi is specified.
  51    --with-tune is ignored if -mtune is specified.  */
  52 #define OPTION_DEFAULT_SPECS \
  53   {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  54   {"arch", "%{!march=*:-march=%(VALUE)}" }, \
  55   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  56
  57 #ifdef IN_LIBGCC2
  58 #undef TARGET_64BIT
  59 /* Make this compile time constant for libgcc2 */
  60 #define TARGET_64BIT           (__riscv_xlen == 64)
  61 #endif /* IN_LIBGCC2 */
  62
  63 #undef ASM_SPEC
  64 #define ASM_SPEC "\
  65 %(subtarget_asm_debugging_spec) \
  66 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  67 %{march=*:-march=%:riscv_expand_arch(%*)} \
  68 %{mabi=*} \
  69 %(subtarget_asm_spec)"
  70
  71 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
  72
  73 #define LOCAL_LABEL_PREFIX      "."
  74 #define USER_LABEL_PREFIX       ""
  75
  76 /* Offsets recorded in opcodes are a multiple of this alignment factor.
  77    The default for this in 64-bit mode is 8, which causes problems with
  78    SFmode register saves.  */
  79 #define DWARF_CIE_DATA_ALIGNMENT -4
  80
  81 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
  82 #define DWARF_FRAME_REGNUM(REGNO) \
  83   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
  84
  85 /* The DWARF 2 CFA column which tracks the return address.  */
  86 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
  87 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
  88
  89 /* Describe how we implement __builtin_eh_return.  */
  90 #define EH_RETURN_DATA_REGNO(N) \
  91   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
  92
  93 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
  94
  95 /* Target machine storage layout */
  96
  97 #define BITS_BIG_ENDIAN 0
  98 #define BYTES_BIG_ENDIAN 0
  99 #define WORDS_BIG_ENDIAN 0
 100
 101 #define MAX_BITS_PER_WORD 64
 102
 103 /* Width of a word, in units (bytes).  */
 104 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 105 #ifndef IN_LIBGCC2
 106 #define MIN_UNITS_PER_WORD 4
 107 #endif
 108
 109 /* The `Q' extension is not yet supported.  */
 110 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 111
 112 /* The largest type that can be passed in floating-point registers.  */
 113 #define UNITS_PER_FP_ARG                                                \
 114   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 115     || riscv_abi == ABI_LP64)                                           \
 116    ? 0                                                                  \
 117    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 118
 119 /* Set the sizes of the core types.  */
 120 #define SHORT_TYPE_SIZE 16
 121 #define INT_TYPE_SIZE 32
 122 #define LONG_LONG_TYPE_SIZE 64
 123 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 124 #define LONG_TYPE_SIZE POINTER_SIZE
 125
 126 #define FLOAT_TYPE_SIZE 32
 127 #define DOUBLE_TYPE_SIZE 64
 128 #define LONG_DOUBLE_TYPE_SIZE 128
 129
 130 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 131 #define PARM_BOUNDARY BITS_PER_WORD
 132
 133 /* Allocation boundary (in *bits*) for the code of a function.  */
 134 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 135
 136 /* The smallest supported stack boundary the calling convention supports.  */
 137 #define STACK_BOUNDARY \
 138   (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
 139
 140 /* The ABI stack alignment.  */
 141 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
 142
 143 /* There is no point aligning anything to a rounder boundary than this.  */
 144 #define BIGGEST_ALIGNMENT 128
 145
 146 /* The user-level ISA permits unaligned accesses, but they are not required
 147    of the privileged architecture.  */
 148 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 149
 150 /* Define this if you wish to imitate the way many other C compilers
 151    handle alignment of bitfields and the structures that contain
 152    them.
 153
 154    The behavior is that the type written for a bit-field (`int',
 155    `short', or other integer type) imposes an alignment for the
 156    entire structure, as if the structure really did contain an
 157    ordinary field of that type.  In addition, the bit-field is placed
 158    within the structure so that it would fit within such a field,
 159    not crossing a boundary for it.
 160
 161    Thus, on most machines, a bit-field whose type is written as `int'
 162    would not cross a four-byte boundary, and would force four-byte
 163    alignment for the whole structure.  (The alignment used may not
 164    be four bytes; it is controlled by the other alignment
 165    parameters.)
 166
 167    If the macro is defined, its definition should be a C expression;
 168    a nonzero value for the expression enables this behavior.  */
 169
 170 #define PCC_BITFIELD_TYPE_MATTERS 1
 171
 172 /* An integer expression for the size in bits of the largest integer machine
 173    mode that should actually be used.  We allow pairs of registers.  */
 174 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 175
 176 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
 177 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)                       \
 178   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 179     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 180         || TREE_CODE (TYPE) == UNION_TYPE                               \
 181         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 182
 183 /* If defined, a C expression to compute the alignment for a static
 184    variable.  TYPE is the data type, and ALIGN is the alignment that
 185    the object would ordinarily have.  The value of this macro is used
 186    instead of that alignment to align the object.
 187
 188    If this macro is not defined, then ALIGN is used.
 189
 190    One use of this macro is to increase alignment of medium-size
 191    data to make it all fit in fewer cache lines.  Another is to
 192    cause character arrays to be word-aligned so that `strcpy' calls
 193    that copy constants to character arrays can be done inline.  */
 194
 195 #define DATA_ALIGNMENT(TYPE, ALIGN)                                             \
 196   RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,  \
 197                           TYPE, ALIGN)
 198
 199 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 200    character arrays to be word-aligned so that `strcpy' calls that copy
 201    constants to character arrays can be done inline, and 'strcmp' can be
 202    optimised to use word loads. */
 203 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 204   RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
 205
 206 /* Define if operations between registers always perform the operation
 207    on the full register even if a narrower mode is specified.  */
 208 #define WORD_REGISTER_OPERATIONS 1
 209
 210 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 211    moves.  All other references are zero extended.  */
 212 #define LOAD_EXTEND_OP(MODE) \
 213   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 214
 215 /* Define this macro if it is advisable to hold scalars in registers
 216    in a wider mode than that declared by the program.  In such cases,
 217    the value is constrained to be within the bounds of the declared
 218    type, but kept valid in the wider mode.  The signedness of the
 219    extension may differ from that of the type.  */
 220
 221 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 222   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 223       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 224     {                                           \
 225       if ((MODE) == SImode)                     \
 226         (UNSIGNEDP) = 0;                        \
 227       (MODE) = word_mode;                       \
 228     }
 229
 230 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 231    Extensions of pointers to word_mode must be signed.  */
 232 #define POINTERS_EXTEND_UNSIGNED false
 233
 234 /* Define if loading short immediate values into registers sign extends.  */
 235 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 236
 237 /* Standard register usage.  */
 238
 239 /* Number of hardware registers.  We have:
 240
 241    - 32 integer registers
 242    - 32 floating point registers
 243    - 2 fake registers:
 244         - ARG_POINTER_REGNUM
 245         - FRAME_POINTER_REGNUM */
 246
 247 #define FIRST_PSEUDO_REGISTER 66
 248
 249 /* x0, sp, gp, and tp are fixed.  */
 250
 251 #define FIXED_REGISTERS                                                 \
 252 { /* General registers.  */                                             \
 253   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 254   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 255   /* Floating-point registers.  */                                      \
 256   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 257   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 258   /* Others.  */                                                        \
 259   1, 1                                                                  \
 260 }
 261
 262 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 263    The call RTLs themselves clobber ra.  */
 264
 265 #define CALL_USED_REGISTERS                                             \
 266 { /* General registers.  */                                             \
 267   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 268   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 269   /* Floating-point registers.  */                                      \
 270   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 271   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 272   /* Others.  */                                                        \
 273   1, 1                                                                  \
 274 }
 275
 276 /* Select a register mode required for caller save of hard regno REGNO.
 277    Contrary to what is documented, the default is not the smallest suitable
 278    mode but the largest suitable mode for the given (REGNO, NREGS) pair and
 279    it quickly creates paradoxical subregs that can be problematic.  */
 280 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 281   ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
 282
 283 /* Internal macros to classify an ISA register's type.  */
 284
 285 #define GP_REG_FIRST 0
 286 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 287 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 288
 289 #define FP_REG_FIRST 32
 290 #define FP_REG_LAST  63
 291 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 292
 293 /* The DWARF 2 CFA column which tracks the return address from a
 294    signal handler context.  This means that to maintain backwards
 295    compatibility, no hard register can be assigned this column if it
 296    would need to be handled by the DWARF unwinder.  */
 297 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 298
 299 #define GP_REG_P(REGNO) \
 300   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 301 #define FP_REG_P(REGNO)  \
 302   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 303
 304 /* True when REGNO is in SIBCALL_REGS set.  */
 305 #define SIBCALL_REG_P(REGNO)    \
 306   TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO)
 307
 308 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 309
 310 /* Use s0 as the frame pointer if it is so requested.  */
 311 #define HARD_FRAME_POINTER_REGNUM 8
 312 #define STACK_POINTER_REGNUM 2
 313 #define THREAD_POINTER_REGNUM 4
 314
 315 /* These two registers don't really exist: they get eliminated to either
 316    the stack or hard frame pointer.  */
 317 #define ARG_POINTER_REGNUM 64
 318 #define FRAME_POINTER_REGNUM 65
 319
 320 /* Register in which static-chain is passed to a function.  */
 321 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 322
 323 /* Registers used as temporaries in prologue/epilogue code.
 324
 325    The prologue registers mustn't conflict with any
 326    incoming arguments, the static chain pointer, or the frame pointer.
 327    The epilogue temporary mustn't conflict with the return registers,
 328    the frame pointer, the EH stack adjustment, or the EH data registers. */
 329
 330 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 331 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 332
 333 #define MCOUNT_NAME "_mcount"
 334
 335 #define NO_PROFILE_COUNTERS 1
 336
 337 /* Emit rtl for profiling.  Output assembler code to FILE
 338    to call "_mcount" for profiling a function entry.  */
 339 #define PROFILE_HOOK(LABEL)                                             \
 340   {                                                                     \
 341     rtx fun, ra;                                                        \
 342     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 343     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 344     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 345   }
 346
 347 /* All the work done in PROFILE_HOOK, but still required.  */
 348 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 349
 350 /* Define this macro if it is as good or better to call a constant
 351    function address than to call an address kept in a register.  */
 352 #define NO_FUNCTION_CSE 1
 353
 354 /* Define the classes of registers for register constraints in the
 355    machine description.  Also define ranges of constants.
 356
 357    One of the classes must always be named ALL_REGS and include all hard regs.
 358    If there is more than one class, another class must be named NO_REGS
 359    and contain no registers.
 360
 361    The name GENERAL_REGS must be the name of a class (or an alias for
 362    another name such as ALL_REGS).  This is the class of registers
 363    that is allowed by "g" or "r" in a register constraint.
 364    Also, registers outside this class are allocated only when
 365    instructions express preferences for them.
 366
 367    The classes must be numbered in nondecreasing order; that is,
 368    a larger-numbered class must never be contained completely
 369    in a smaller-numbered class.
 370
 371    For any two classes, it is very desirable that there be another
 372    class that represents their union.  */
 373
 374 enum reg_class
 375 {
 376   NO_REGS,                      /* no registers in set */
 377   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 378   JALR_REGS,                    /* registers used by indirect calls */
 379   GR_REGS,                      /* integer registers */
 380   FP_REGS,                      /* floating-point registers */
 381   FRAME_REGS,                   /* arg pointer and frame pointer */
 382   ALL_REGS,                     /* all registers */
 383   LIM_REG_CLASSES               /* max value + 1 */
 384 };
 385
 386 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 387
 388 #define GENERAL_REGS GR_REGS
 389
 390 /* An initializer containing the names of the register classes as C
 391    string constants.  These names are used in writing some of the
 392    debugging dumps.  */
 393
 394 #define REG_CLASS_NAMES                                                 \
 395 {                                                                       \
 396   "NO_REGS",                                                            \
 397   "SIBCALL_REGS",                                                       \
 398   "JALR_REGS",                                                          \
 399   "GR_REGS",                                                            \
 400   "FP_REGS",                                                            \
 401   "FRAME_REGS",                                                         \
 402   "ALL_REGS"                                                            \
 403 }
 404
 405 /* An initializer containing the contents of the register classes,
 406    as integers which are bit masks.  The Nth integer specifies the
 407    contents of class N.  The way the integer MASK is interpreted is
 408    that register R is in the class if `MASK & (1 << R)' is 1.
 409
 410    When the machine has more than 32 registers, an integer does not
 411    suffice.  Then the integers are replaced by sub-initializers,
 412    braced groupings containing several integers.  Each
 413    sub-initializer must be suitable as an initializer for the type
 414    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 415
 416 #define REG_CLASS_CONTENTS                                              \
 417 {                                                                       \
 418   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 419   { 0xf003fcc0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 420   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 421   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 422   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 423   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 424   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 425 }
 426
 427 /* A C expression whose value is a register class containing hard
 428    register REGNO.  In general there is more that one such class;
 429    choose a class which is "minimal", meaning that no smaller class
 430    also contains the register.  */
 431
 432 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 433
 434 /* A macro whose definition is the name of the class to which a
 435    valid base register must belong.  A base register is one used in
 436    an address which is the register value plus a displacement.  */
 437
 438 #define BASE_REG_CLASS GR_REGS
 439
 440 /* A macro whose definition is the name of the class to which a
 441    valid index register must belong.  An index register is one used
 442    in an address where its value is either multiplied by a scale
 443    factor or added to another register (as well as added to a
 444    displacement).  */
 445
 446 #define INDEX_REG_CLASS NO_REGS
 447
 448 /* We generally want to put call-clobbered registers ahead of
 449    call-saved ones.  (IRA expects this.)  */
 450
 451 #define REG_ALLOC_ORDER                                                 \
 452 { \
 453   /* Call-clobbered GPRs.  */                                           \
 454   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 455   /* Call-saved GPRs.  */                                               \
 456   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 457   /* GPRs that can never be exposed to the register allocator.  */      \
 458   0, 2, 3, 4,                                                           \
 459   /* Call-clobbered FPRs.  */                                           \
 460   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 461   60, 61, 62, 63,                                                       \
 462   /* Call-saved FPRs.  */                                               \
 463   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 464   /* None of the remaining classes have defined call-saved              \
 465      registers.  */                                                     \
 466   64, 65                                                                \
 467 }
 468
 469 /* True if VALUE is a signed 12-bit number.  */
 470
 471 #define SMALL_OPERAND(VALUE) \
 472   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 473
 474 /* True if VALUE can be loaded into a register using LUI.  */
 475
 476 #define LUI_OPERAND(VALUE)                                              \
 477   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 478    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 479
 480 /* Stack layout; function entry, exit and calling.  */
 481
 482 #define STACK_GROWS_DOWNWARD 1
 483
 484 #define FRAME_GROWS_DOWNWARD 1
 485
 486 #define RETURN_ADDR_RTX riscv_return_addr
 487
 488 #define ELIMINABLE_REGS                                                 \
 489 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 490  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 491  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 492  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 493
 494 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 495   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 496
 497 /* Allocate stack space for arguments at the beginning of each function.  */
 498 #define ACCUMULATE_OUTGOING_ARGS 1
 499
 500 /* The argument pointer always points to the first argument.  */
 501 #define FIRST_PARM_OFFSET(FNDECL) 0
 502
 503 #define REG_PARM_STACK_SPACE(FNDECL) 0
 504
 505 /* Define this if it is the responsibility of the caller to
 506    allocate the area reserved for arguments passed in registers.
 507    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 508    of this macro is to determine whether the space is included in
 509    `crtl->outgoing_args_size'.  */
 510 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 511
 512 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 513
 514 /* Symbolic macros for the registers used to return integer and floating
 515    point values.  */
 516
 517 #define GP_RETURN GP_ARG_FIRST
 518 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 519
 520 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
 521
 522 /* Symbolic macros for the first/last argument registers.  */
 523
 524 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 525 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 526 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 527 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 528 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 529
 530 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 531   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 532    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 533
 534 #define LIBCALL_VALUE(MODE) \
 535   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 536
 537 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 538   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 539
 540 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 541
 542 /* 1 if N is a possible register number for function argument passing.
 543    We have no FP argument registers when soft-float.  */
 544
 545 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 546 #define FUNCTION_ARG_REGNO_P(N)                                         \
 547   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 548    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 549
 550 typedef struct {
 551   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 552   unsigned int num_gprs;
 553
 554   /* Number of floating-point registers used so far, likewise.  */
 555   unsigned int num_fprs;
 556 } CUMULATIVE_ARGS;
 557
 558 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 559    for a call to a function whose data type is FNTYPE.
 560    For a library call, FNTYPE is 0.  */
 561
 562 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 563   memset (&(CUM), 0, sizeof (CUM))
 564
 565 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 566
 567 /* Align based on stack boundary, which might have been set by the user.  */
 568 #define RISCV_STACK_ALIGN(LOC) \
 569   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 570
 571 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 572    the stack pointer does not matter.  The value is tested only in
 573    functions that have frame pointers.
 574    No definition is equivalent to always zero.  */
 575
 576 #define EXIT_IGNORE_STACK 1
 577
 578
 579 /* Trampolines are a block of code followed by two pointers.  */
 580
 581 #define TRAMPOLINE_CODE_SIZE 16
 582 #define TRAMPOLINE_SIZE         \
 583   ((Pmode == SImode)            \
 584    ? TRAMPOLINE_CODE_SIZE       \
 585    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 586 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 587
 588 /* Addressing modes, and classification of registers for them.  */
 589
 590 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 591 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 592   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 593
 594 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 595    and check its validity for a certain class.
 596    We have two alternate definitions for each of them.
 597    The usual definition accepts all pseudo regs; the other rejects them all.
 598    The symbol REG_OK_STRICT causes the latter definition to be used.
 599
 600    Most source files want to accept pseudo regs in the hope that
 601    they will get allocated to the class that the insn wants them to be in.
 602    Some source files that are used after register allocation
 603    need to be strict.  */
 604
 605 #ifndef REG_OK_STRICT
 606 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 607   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 608 #else
 609 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 610   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 611 #endif
 612
 613 #define REG_OK_FOR_INDEX_P(X) 0
 614
 615 /* Maximum number of registers that can appear in a valid memory address.  */
 616
 617 #define MAX_REGS_PER_ADDRESS 1
 618
 619 #define CONSTANT_ADDRESS_P(X) \
 620   (CONSTANT_P (X) && memory_address_p (SImode, X))
 621
 622 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 623    'the start of the function that this code is output in'.  */
 624
 625 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 626   do {                                                                  \
 627     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 628       asm_fprintf ((FILE), "%U%s",                                      \
 629                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 630                                0), 0));                                 \
 631     else                                                                \
 632       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 633   } while (0)
 634
 635 #define JUMP_TABLES_IN_TEXT_SECTION 0
 636 #define CASE_VECTOR_MODE SImode
 637 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 638
 639 /* The load-address macro is used for PC-relative addressing of symbols
 640    that bind locally.  Don't use it for symbols that should be addressed
 641    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 642    currently results in more opportunities for linker relaxation.  */
 643 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 644   (!TARGET_EXPLICIT_RELOCS &&                                           \
 645    ((flag_pic                                                           \
 646      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 647          || ((GET_CODE (sym) == CONST)                                  \
 648              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 649              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 650      || riscv_cmodel == CM_MEDANY))
 651
 652 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 653 #define DEFAULT_SIGNED_CHAR 0
 654
 655 #define MOVE_MAX UNITS_PER_WORD
 656 #define MAX_MOVE_MAX 8
 657
 658 /* The SPARC port says:
 659    Nonzero if access to memory by bytes is slow and undesirable.
 660    For RISC chips, it means that access to memory by bytes is no
 661    better than access by words when possible, so grab a whole word
 662    and maybe make use of that.  */
 663 #define SLOW_BYTE_ACCESS 1
 664
 665 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 666    in the md file instead.  */
 667 #define SHIFT_COUNT_TRUNCATED 0
 668
 669 /* Specify the machine mode that pointers have.
 670    After generation of rtl, the compiler makes no further distinction
 671    between pointers and any other objects of this machine mode.  */
 672
 673 #define Pmode word_mode
 674
 675 /* Give call MEMs SImode since it is the "most permissive" mode
 676    for both 32-bit and 64-bit targets.  */
 677
 678 #define FUNCTION_MODE SImode
 679
 680 /* A C expression for the cost of a branch instruction.  A value of 2
 681    seems to minimize code size.  */
 682
 683 #define BRANCH_COST(speed_p, predictable_p) \
 684   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 685
 686 /* True if the target optimizes short forward branches around integer
 687    arithmetic instructions into predicated operations, e.g., for
 688    conditional-move operations.  The macro assumes that all branch
 689    instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
 690    support this feature.  The macro further assumes that any integer
 691    arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
 692    SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
 693    counterparts, including C.MV and C.LI) can be in the branch shadow.  */
 694
 695 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
 696
 697 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 698
 699 /* Control the assembler format that we output.  */
 700
 701 /* Output to assembler file text saying following lines
 702    may contain character constants, extra white space, comments, etc.  */
 703
 704 #ifndef ASM_APP_ON
 705 #define ASM_APP_ON " #APP\n"
 706 #endif
 707
 708 /* Output to assembler file text saying following lines
 709    no longer contain unusual constructs.  */
 710
 711 #ifndef ASM_APP_OFF
 712 #define ASM_APP_OFF " #NO_APP\n"
 713 #endif
 714
 715 #define REGISTER_NAMES                                          \
 716 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 717   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 718   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 719   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 720   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 721   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 722   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 723   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 724   "arg", "frame", }
 725
 726 #define ADDITIONAL_REGISTER_NAMES                                       \
 727 {                                                                       \
 728   { "x0",        0 + GP_REG_FIRST },                                    \
 729   { "x1",        1 + GP_REG_FIRST },                                    \
 730   { "x2",        2 + GP_REG_FIRST },                                    \
 731   { "x3",        3 + GP_REG_FIRST },                                    \
 732   { "x4",        4 + GP_REG_FIRST },                                    \
 733   { "x5",        5 + GP_REG_FIRST },                                    \
 734   { "x6",        6 + GP_REG_FIRST },                                    \
 735   { "x7",        7 + GP_REG_FIRST },                                    \
 736   { "x8",        8 + GP_REG_FIRST },                                    \
 737   { "x9",        9 + GP_REG_FIRST },                                    \
 738   { "x10",      10 + GP_REG_FIRST },                                    \
 739   { "x11",      11 + GP_REG_FIRST },                                    \
 740   { "x12",      12 + GP_REG_FIRST },                                    \
 741   { "x13",      13 + GP_REG_FIRST },                                    \
 742   { "x14",      14 + GP_REG_FIRST },                                    \
 743   { "x15",      15 + GP_REG_FIRST },                                    \
 744   { "x16",      16 + GP_REG_FIRST },                                    \
 745   { "x17",      17 + GP_REG_FIRST },                                    \
 746   { "x18",      18 + GP_REG_FIRST },                                    \
 747   { "x19",      19 + GP_REG_FIRST },                                    \
 748   { "x20",      20 + GP_REG_FIRST },                                    \
 749   { "x21",      21 + GP_REG_FIRST },                                    \
 750   { "x22",      22 + GP_REG_FIRST },                                    \
 751   { "x23",      23 + GP_REG_FIRST },                                    \
 752   { "x24",      24 + GP_REG_FIRST },                                    \
 753   { "x25",      25 + GP_REG_FIRST },                                    \
 754   { "x26",      26 + GP_REG_FIRST },                                    \
 755   { "x27",      27 + GP_REG_FIRST },                                    \
 756   { "x28",      28 + GP_REG_FIRST },                                    \
 757   { "x29",      29 + GP_REG_FIRST },                                    \
 758   { "x30",      30 + GP_REG_FIRST },                                    \
 759   { "x31",      31 + GP_REG_FIRST },                                    \
 760   { "f0",        0 + FP_REG_FIRST },                                    \
 761   { "f1",        1 + FP_REG_FIRST },                                    \
 762   { "f2",        2 + FP_REG_FIRST },                                    \
 763   { "f3",        3 + FP_REG_FIRST },                                    \
 764   { "f4",        4 + FP_REG_FIRST },                                    \
 765   { "f5",        5 + FP_REG_FIRST },                                    \
 766   { "f6",        6 + FP_REG_FIRST },                                    \
 767   { "f7",        7 + FP_REG_FIRST },                                    \
 768   { "f8",        8 + FP_REG_FIRST },                                    \
 769   { "f9",        9 + FP_REG_FIRST },                                    \
 770   { "f10",      10 + FP_REG_FIRST },                                    \
 771   { "f11",      11 + FP_REG_FIRST },                                    \
 772   { "f12",      12 + FP_REG_FIRST },                                    \
 773   { "f13",      13 + FP_REG_FIRST },                                    \
 774   { "f14",      14 + FP_REG_FIRST },                                    \
 775   { "f15",      15 + FP_REG_FIRST },                                    \
 776   { "f16",      16 + FP_REG_FIRST },                                    \
 777   { "f17",      17 + FP_REG_FIRST },                                    \
 778   { "f18",      18 + FP_REG_FIRST },                                    \
 779   { "f19",      19 + FP_REG_FIRST },                                    \
 780   { "f20",      20 + FP_REG_FIRST },                                    \
 781   { "f21",      21 + FP_REG_FIRST },                                    \
 782   { "f22",      22 + FP_REG_FIRST },                                    \
 783   { "f23",      23 + FP_REG_FIRST },                                    \
 784   { "f24",      24 + FP_REG_FIRST },                                    \
 785   { "f25",      25 + FP_REG_FIRST },                                    \
 786   { "f26",      26 + FP_REG_FIRST },                                    \
 787   { "f27",      27 + FP_REG_FIRST },                                    \
 788   { "f28",      28 + FP_REG_FIRST },                                    \
 789   { "f29",      29 + FP_REG_FIRST },                                    \
 790   { "f30",      30 + FP_REG_FIRST },                                    \
 791   { "f31",      31 + FP_REG_FIRST },                                    \
 792 }
 793
 794 /* Globalizing directive for a label.  */
 795 #define GLOBAL_ASM_OP "\t.globl\t"
 796
 797 /* This is how to store into the string LABEL
 798    the symbol_ref name of an internal numbered label where
 799    PREFIX is the class of label and NUM is the number within the class.
 800    This is suitable for output with `assemble_name'.  */
 801
 802 #undef ASM_GENERATE_INTERNAL_LABEL
 803 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 804   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 805
 806 /* This is how to output an element of a case-vector that is absolute.  */
 807
 808 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 809   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 810
 811 /* This is how to output an element of a PIC case-vector. */
 812
 813 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 814   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 815            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 816
 817 /* This is how to output an assembler line
 818    that says to advance the location counter
 819    to a multiple of 2**LOG bytes.  */
 820
 821 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 822   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 823
 824 /* Define the strings to put out for each section in the object file.  */
 825 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 826 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 827 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 828 #define BSS_SECTION_ASM_OP      "\t.bss"
 829 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 830 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 831
 832 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 833 do                                                                      \
 834   {                                                                     \
 835     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 836              reg_names[STACK_POINTER_REGNUM],                           \
 837              reg_names[STACK_POINTER_REGNUM],                           \
 838              TARGET_64BIT ? "sd" : "sw",                                \
 839              reg_names[REGNO],                                          \
 840              reg_names[STACK_POINTER_REGNUM]);                          \
 841   }                                                                     \
 842 while (0)
 843
 844 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 845 do                                                                      \
 846   {                                                                     \
 847     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 848              TARGET_64BIT ? "ld" : "lw",                                \
 849              reg_names[REGNO],                                          \
 850              reg_names[STACK_POINTER_REGNUM],                           \
 851              reg_names[STACK_POINTER_REGNUM],                           \
 852              reg_names[STACK_POINTER_REGNUM]);                          \
 853   }                                                                     \
 854 while (0)
 855
 856 #define ASM_COMMENT_START "#"
 857
 858 #undef SIZE_TYPE
 859 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 860
 861 #undef PTRDIFF_TYPE
 862 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 863
 864 /* The maximum number of bytes copied by one iteration of a cpymemsi loop.  */
 865
 866 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
 867
 868 /* The maximum number of bytes that can be copied by a straight-line
 869    cpymemsi implementation.  */
 870
 871 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
 872
 873 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 874    move-instruction pairs, we will do a cpymem or libcall instead.
 875    Do not use move_by_pieces at all when strict alignment is not
 876    in effect but the target has slow unaligned accesses; in this
 877    case, cpymem or libcall is more efficient.  */
 878
 879 #define MOVE_RATIO(speed)                                               \
 880   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
 881    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
 882    CLEAR_RATIO (speed) / 2)
 883
 884 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 885    of the length of a memset call, but use the default otherwise.  */
 886
 887 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 888
 889 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 890    optimizing for size adjust the ratio to account for the overhead of
 891    loading the constant and replicating it across the word.  */
 892
 893 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 894
 895 #ifndef USED_FOR_TARGET
 896 extern const enum reg_class riscv_regno_to_class[];
 897 extern bool riscv_slow_unaligned_access_p;
 898 extern unsigned riscv_stack_boundary;
 899 #endif
 900
 901 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 902   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 903
 904 #define XLEN_SPEC \
 905   "%{march=rv32*:32}" \
 906   "%{march=rv64*:64}" \
 907
 908 #define ABI_SPEC \
 909   "%{mabi=ilp32:ilp32}" \
 910   "%{mabi=ilp32e:ilp32e}" \
 911   "%{mabi=ilp32f:ilp32f}" \
 912   "%{mabi=ilp32d:ilp32d}" \
 913   "%{mabi=lp64:lp64}" \
 914   "%{mabi=lp64f:lp64f}" \
 915   "%{mabi=lp64d:lp64d}" \
 916
 917 /* ISA constants needed for code generation.  */
 918 #define OPCODE_LW    0x2003
 919 #define OPCODE_LD    0x3003
 920 #define OPCODE_AUIPC 0x17
 921 #define OPCODE_JALR  0x67
 922 #define OPCODE_LUI   0x37
 923 #define OPCODE_ADDI  0x13
 924 #define SHIFT_RD  7
 925 #define SHIFT_RS1 15
 926 #define SHIFT_IMM 20
 927 #define IMM_BITS 12
 928 #define C_S_BITS 5
 929 #define C_SxSP_BITS 6
 930
 931 #define IMM_REACH (1LL << IMM_BITS)
 932 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 933 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 934
 935 #define SWSP_REACH (4LL << C_SxSP_BITS)
 936 #define SDSP_REACH (8LL << C_SxSP_BITS)
 937
 938 /* This is the maximum value that can be represented in a compressed load/store
 939    offset (an unsigned 5-bit value scaled by 4).  */
 940 #define CSW_MAX_OFFSET ((4LL << C_S_BITS) - 1) & ~3
 941
 942 /* Called from RISCV_REORG, this is defined in riscv-sr.c.  */
 943
 944 extern void riscv_remove_unneeded_save_restore_calls (void);
 945
 946 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
 947
 948 #endif /* ! GCC_RISCV_H */