gcc/config/riscv/riscv_vector.h

   1 /* RISC-V 'V' Extension intrinsics include file.
   2    Copyright (C) 2022-2023 Free Software Foundation, Inc.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published
   8    by the Free Software Foundation; either version 3, or (at your
   9    option) any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    Under Section 7 of GPL version 3, you are granted additional
  17    permissions described in the GCC Runtime Library Exception, version
  18    3.1, as published by the Free Software Foundation.
  19
  20    You should have received a copy of the GNU General Public License and
  21    a copy of the GCC Runtime Library Exception along with this program;
  22    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  23    <http://www.gnu.org/licenses/>.  */
  24
  25 #ifndef __RISCV_VECTOR_H
  26 #define __RISCV_VECTOR_H
  27
  28 #include <stdint.h>
  29 #include <stddef.h>
  30
  31 #ifndef __riscv_vector
  32 #error "Vector intrinsics require the vector extension."
  33 #else
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 enum RVV_CSR {
  39   RVV_VSTART = 0,
  40   RVV_VXSAT,
  41   RVV_VXRM,
  42   RVV_VCSR,
  43 };
  44
  45 __extension__ extern __inline unsigned long
  46 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
  47 vread_csr(enum RVV_CSR csr)
  48 {
  49   unsigned long rv = 0;
  50   switch (csr)
  51     {
  52     case RVV_VSTART:
  53       __asm__ __volatile__ ("csrr\t%0,vstart" : "=r"(rv) : : "memory");
  54       break;
  55     case RVV_VXSAT:
  56       __asm__ __volatile__ ("csrr\t%0,vxsat" : "=r"(rv) : : "memory");
  57       break;
  58     case RVV_VXRM:
  59       __asm__ __volatile__ ("csrr\t%0,vxrm" : "=r"(rv) : : "memory");
  60       break;
  61     case RVV_VCSR:
  62       __asm__ __volatile__ ("csrr\t%0,vcsr" : "=r"(rv) : : "memory");
  63       break;
  64     }
  65   return rv;
  66 }
  67
  68 __extension__ extern __inline void
  69 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
  70 vwrite_csr(enum RVV_CSR csr, unsigned long value)
  71 {
  72   switch (csr)
  73     {
  74     case RVV_VSTART:
  75       __asm__ __volatile__ ("csrw\tvstart,%z0" : : "rJ"(value) : "memory");
  76       break;
  77     case RVV_VXSAT:
  78       __asm__ __volatile__ ("csrw\tvxsat,%z0" : : "rJ"(value) : "memory");
  79       break;
  80     case RVV_VXRM:
  81       __asm__ __volatile__ ("csrw\tvxrm,%z0" : : "rJ"(value) : "memory");
  82       break;
  83     case RVV_VCSR:
  84       __asm__ __volatile__ ("csrw\tvcsr,%z0" : : "rJ"(value) : "memory");
  85       break;
  86     }
  87 }
  88
  89 /* NOTE: This implementation of riscv_vector.h is intentionally short.  It does
  90    not define the RVV types and intrinsic functions directly in C and C++
  91    code, but instead uses the following pragma to tell GCC to insert the
  92    necessary type and function definitions itself.  The net effect is the
  93    same, and the file is a complete implementation of riscv_vector.h.  */
  94 #pragma riscv intrinsic "vector"
  95
  96 #ifdef __cplusplus
  97 }
  98 #endif // __cplusplus
  99 #endif // __riscv_vector
 100 #endif // __RISCV_VECTOR_H