1 /* Subroutines used for code generation on Renesas RL78 processors.
2 Copyright (C) 2011-2015 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
29 #include "fold-const.h"
31 #include "stor-layout.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "insn-codes.h"
49 #include "diagnostic-core.h"
56 #include "cfgcleanup.h"
60 #include "langhooks.h"
61 #include "rl78-protos.h"
63 #include "tree-pass.h"
65 #include "tm-constrs.h" /* for satisfies_constraint_*(). */
66 #include "insn-flags.h" /* for gen_*(). */
68 #include "stringpool.h"
70 /* This file should be included last. */
71 #include "target-def.h"
73 static inline bool is_interrupt_func (const_tree decl
);
74 static inline bool is_brk_interrupt_func (const_tree decl
);
75 static void rl78_reorg (void);
76 static const char *rl78_strip_name_encoding (const char *);
77 static const char *rl78_strip_nonasm_name_encoding (const char *);
78 static section
* rl78_select_section (tree
, int, unsigned HOST_WIDE_INT
);
81 /* Debugging statements are tagged with DEBUG0 only so that they can
82 be easily enabled individually, by replacing the '0' with '1' as
87 /* REGISTER_NAMES has the names for individual 8-bit registers, but
88 these have the names we need to use when referring to 16-bit
90 static const char * const word_regnames
[] =
92 "ax", "AX", "bc", "BC", "de", "DE", "hl", "HL",
93 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
94 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
95 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
96 "sp", "ap", "psw", "es", "cs"
99 struct GTY(()) machine_function
101 /* If set, the rest of the fields have been computed. */
103 /* Which register pairs need to be pushed in the prologue. */
104 int need_to_push
[FIRST_PSEUDO_REGISTER
/ 2];
106 /* These fields describe the frame layout... */
108 /* 4 bytes for saved PC */
111 int framesize_locals
;
112 int framesize_outgoing
;
116 /* If set, recog is allowed to match against the "real" patterns. */
118 /* If set, recog is allowed to match against the "virtual" patterns. */
120 /* Set if the current function needs to clean up any trampolines. */
121 int trampolines_used
;
122 /* True if the ES register is used and hence
123 needs to be saved inside interrupt handlers. */
127 /* This is our init_machine_status, as set in
128 rl78_option_override. */
129 static struct machine_function
*
130 rl78_init_machine_status (void)
132 struct machine_function
*m
;
134 m
= ggc_cleared_alloc
<machine_function
> ();
135 m
->virt_insns_ok
= 1;
140 /* This pass converts virtual instructions using virtual registers, to
141 real instructions using real registers. Rather than run it as
142 reorg, we reschedule it before vartrack to help with debugging. */
145 const pass_data pass_data_rl78_devirt
=
149 OPTGROUP_NONE
, /* optinfo_flags */
150 TV_MACH_DEP
, /* tv_id */
151 0, /* properties_required */
152 0, /* properties_provided */
153 0, /* properties_destroyed */
154 0, /* todo_flags_start */
155 0, /* todo_flags_finish */
158 class pass_rl78_devirt
: public rtl_opt_pass
161 pass_rl78_devirt (gcc::context
*ctxt
)
162 : rtl_opt_pass (pass_data_rl78_devirt
, ctxt
)
166 /* opt_pass methods: */
167 virtual unsigned int execute (function
*)
176 make_pass_rl78_devirt (gcc::context
*ctxt
)
178 return new pass_rl78_devirt (ctxt
);
181 /* Redundant move elimination pass. Must be run after the basic block
182 reordering pass for the best effect. */
185 move_elim_pass (void)
187 rtx_insn
*insn
, *ninsn
;
190 for (insn
= get_insns (); insn
; insn
= ninsn
)
194 ninsn
= next_nonnote_nondebug_insn (insn
);
196 if ((set
= single_set (insn
)) == NULL_RTX
)
202 /* If we have two SET insns in a row (without anything
203 between them) and the source of the second one is the
204 destination of the first one, and vice versa, then we
205 can eliminate the second SET. */
207 && rtx_equal_p (SET_DEST (prev
), SET_SRC (set
))
208 && rtx_equal_p (SET_DEST (set
), SET_SRC (prev
))
209 /* ... and none of the operands are volatile. */
210 && ! volatile_refs_p (SET_SRC (prev
))
211 && ! volatile_refs_p (SET_DEST (prev
))
212 && ! volatile_refs_p (SET_SRC (set
))
213 && ! volatile_refs_p (SET_DEST (set
)))
216 fprintf (dump_file
, " Delete insn %d because it is redundant\n",
227 print_rtl_with_bb (dump_file
, get_insns (), 0);
234 const pass_data pass_data_rl78_move_elim
=
237 "move_elim", /* name */
238 OPTGROUP_NONE
, /* optinfo_flags */
239 TV_MACH_DEP
, /* tv_id */
240 0, /* properties_required */
241 0, /* properties_provided */
242 0, /* properties_destroyed */
243 0, /* todo_flags_start */
244 0, /* todo_flags_finish */
247 class pass_rl78_move_elim
: public rtl_opt_pass
250 pass_rl78_move_elim (gcc::context
*ctxt
)
251 : rtl_opt_pass (pass_data_rl78_move_elim
, ctxt
)
255 /* opt_pass methods: */
256 virtual unsigned int execute (function
*) { return move_elim_pass (); }
261 make_pass_rl78_move_elim (gcc::context
*ctxt
)
263 return new pass_rl78_move_elim (ctxt
);
266 #undef TARGET_ASM_FILE_START
267 #define TARGET_ASM_FILE_START rl78_asm_file_start
270 rl78_asm_file_start (void)
276 /* The memory used is 0xffec8 to 0xffedf; real registers are in
277 0xffee0 to 0xffee7. */
278 for (i
= 8; i
< 32; i
++)
279 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", i
, 0xffec0 + i
);
283 for (i
= 0; i
< 8; i
++)
285 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", 8 + i
, 0xffef0 + i
);
286 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", 16 + i
, 0xffee8 + i
);
287 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", 24 + i
, 0xffee0 + i
);
291 opt_pass
*rl78_devirt_pass
= make_pass_rl78_devirt (g
);
292 struct register_pass_info rl78_devirt_info
=
297 PASS_POS_INSERT_BEFORE
300 opt_pass
*rl78_move_elim_pass
= make_pass_rl78_move_elim (g
);
301 struct register_pass_info rl78_move_elim_info
=
306 PASS_POS_INSERT_AFTER
309 register_pass (& rl78_devirt_info
);
310 register_pass (& rl78_move_elim_info
);
314 rl78_output_symbol_ref (FILE * file
, rtx sym
)
316 tree type
= SYMBOL_REF_DECL (sym
);
317 const char *str
= XSTR (sym
, 0);
321 fputs (str
+ 1, file
);
325 str
= rl78_strip_nonasm_name_encoding (str
);
326 if (type
&& TREE_CODE (type
) == FUNCTION_DECL
)
328 fprintf (file
, "%%code(");
329 assemble_name (file
, str
);
333 assemble_name (file
, str
);
337 #undef TARGET_OPTION_OVERRIDE
338 #define TARGET_OPTION_OVERRIDE rl78_option_override
341 rl78_option_override (void)
343 flag_omit_frame_pointer
= 1;
344 flag_no_function_cse
= 1;
345 flag_split_wide_types
= 0;
347 init_machine_status
= rl78_init_machine_status
;
353 for (i
= 24; i
< 32; i
++)
358 && strcmp (lang_hooks
.name
, "GNU C")
359 /* Compiling with -flto results in a language of GNU GIMPLE being used... */
360 && strcmp (lang_hooks
.name
, "GNU GIMPLE"))
361 /* Address spaces are currently only supported by C. */
362 error ("-mes0 can only be used with C");
364 switch (rl78_cpu_type
)
367 rl78_cpu_type
= CPU_G14
;
368 if (rl78_mul_type
== MUL_UNINIT
)
369 rl78_mul_type
= MUL_NONE
;
373 switch (rl78_mul_type
)
375 case MUL_UNINIT
: rl78_mul_type
= MUL_NONE
; break;
376 case MUL_NONE
: break;
377 case MUL_G13
: error ("-mmul=g13 cannot be used with -mcpu=g10"); break;
378 case MUL_G14
: error ("-mmul=g14 cannot be used with -mcpu=g10"); break;
383 switch (rl78_mul_type
)
385 case MUL_UNINIT
: rl78_mul_type
= MUL_G13
; break;
386 case MUL_NONE
: break;
388 /* The S2 core does not have mul/div instructions. */
389 case MUL_G14
: error ("-mmul=g14 cannot be used with -mcpu=g13"); break;
394 switch (rl78_mul_type
)
396 case MUL_UNINIT
: rl78_mul_type
= MUL_G14
; break;
397 case MUL_NONE
: break;
399 /* The G14 core does not have the hardware multiply peripheral used by the
400 G13 core, hence you cannot use G13 multipliy routines on G14 hardware. */
401 case MUL_G13
: error ("-mmul=g13 cannot be used with -mcpu=g14"); break;
407 /* Most registers are 8 bits. Some are 16 bits because, for example,
408 gcc doesn't like dealing with $FP as a register pair (the second
409 half of $fp is also 2 to keep reload happy wrt register pairs, but
410 no register class includes it). This table maps register numbers
412 static const int register_sizes
[] =
414 1, 1, 1, 1, 1, 1, 1, 1,
415 1, 1, 1, 1, 1, 1, 1, 1,
416 1, 1, 1, 1, 1, 1, 2, 2,
417 1, 1, 1, 1, 1, 1, 1, 1,
421 /* Predicates used in the MD patterns. This one is true when virtual
422 insns may be matched, which typically means before (or during) the
425 rl78_virt_insns_ok (void)
428 return cfun
->machine
->virt_insns_ok
;
432 /* Predicates used in the MD patterns. This one is true when real
433 insns may be matched, which typically means after (or during) the
436 rl78_real_insns_ok (void)
439 return cfun
->machine
->real_insns_ok
;
443 /* Implements HARD_REGNO_NREGS. */
445 rl78_hard_regno_nregs (int regno
, machine_mode mode
)
447 int rs
= register_sizes
[regno
];
450 return ((GET_MODE_SIZE (mode
) + rs
- 1) / rs
);
453 /* Implements HARD_REGNO_MODE_OK. */
455 rl78_hard_regno_mode_ok (int regno
, machine_mode mode
)
457 int s
= GET_MODE_SIZE (mode
);
461 /* These are not to be used by gcc. */
462 if (regno
== 23 || regno
== ES_REG
|| regno
== CS_REG
)
464 /* $fp can always be accessed as a 16-bit value. */
465 if (regno
== FP_REG
&& s
== 2)
469 /* Since a reg-reg move is really a reg-mem move, we must
470 enforce alignment. */
471 if (s
> 1 && (regno
% 2))
476 return (mode
== BImode
);
477 /* All other registers must be accessed in their natural sizes. */
478 if (s
== register_sizes
[regno
])
483 /* Simplify_gen_subreg() doesn't handle memory references the way we
484 need it to below, so we use this function for when we must get a
485 valid subreg in a "natural" state. */
487 rl78_subreg (machine_mode mode
, rtx r
, machine_mode omode
, int byte
)
489 if (GET_CODE (r
) == MEM
)
490 return adjust_address (r
, mode
, byte
);
492 return simplify_gen_subreg (mode
, r
, omode
, byte
);
495 /* Used by movsi. Split SImode moves into two HImode moves, using
496 appropriate patterns for the upper and lower halves of symbols. */
498 rl78_expand_movsi (rtx
*operands
)
500 rtx op00
, op02
, op10
, op12
;
502 op00
= rl78_subreg (HImode
, operands
[0], SImode
, 0);
503 op02
= rl78_subreg (HImode
, operands
[0], SImode
, 2);
504 if (GET_CODE (operands
[1]) == CONST
505 || GET_CODE (operands
[1]) == SYMBOL_REF
)
507 op10
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (0));
508 op10
= gen_rtx_CONST (HImode
, op10
);
509 op12
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (16));
510 op12
= gen_rtx_CONST (HImode
, op12
);
514 op10
= rl78_subreg (HImode
, operands
[1], SImode
, 0);
515 op12
= rl78_subreg (HImode
, operands
[1], SImode
, 2);
518 if (rtx_equal_p (operands
[0], operands
[1]))
520 else if (rtx_equal_p (op00
, op12
))
522 emit_move_insn (op02
, op12
);
523 emit_move_insn (op00
, op10
);
527 emit_move_insn (op00
, op10
);
528 emit_move_insn (op02
, op12
);
532 /* Generate code to move an SImode value. */
534 rl78_split_movsi (rtx
*operands
, enum machine_mode omode
)
536 rtx op00
, op02
, op10
, op12
;
538 op00
= rl78_subreg (HImode
, operands
[0], omode
, 0);
539 op02
= rl78_subreg (HImode
, operands
[0], omode
, 2);
541 if (GET_CODE (operands
[1]) == CONST
542 || GET_CODE (operands
[1]) == SYMBOL_REF
)
544 op10
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (0));
545 op10
= gen_rtx_CONST (HImode
, op10
);
546 op12
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (16));
547 op12
= gen_rtx_CONST (HImode
, op12
);
551 op10
= rl78_subreg (HImode
, operands
[1], omode
, 0);
552 op12
= rl78_subreg (HImode
, operands
[1], omode
, 2);
555 if (rtx_equal_p (operands
[0], operands
[1]))
557 else if (rtx_equal_p (op00
, op12
))
573 /* Used by various two-operand expanders which cannot accept all
574 operands in the "far" namespace. Force some such operands into
575 registers so that each pattern has at most one far operand. */
577 rl78_force_nonfar_2 (rtx
*operands
, rtx (*gen
)(rtx
,rtx
))
582 /* FIXME: in the future, be smarter about only doing this if the
583 other operand is also far, assuming the devirtualizer can also
585 if (rl78_far_p (operands
[0]))
587 temp_reg
= operands
[0];
588 operands
[0] = gen_reg_rtx (GET_MODE (operands
[0]));
594 emit_insn (gen (operands
[0], operands
[1]));
596 emit_move_insn (temp_reg
, operands
[0]);
600 /* Likewise, but for three-operand expanders. */
602 rl78_force_nonfar_3 (rtx
*operands
, rtx (*gen
)(rtx
,rtx
,rtx
))
607 /* As an exception, we allow two far operands if they're identical
608 and the third operand is not a MEM. This allows global variables
609 to be incremented, for example. */
610 if (rtx_equal_p (operands
[0], operands
[1])
611 && ! MEM_P (operands
[2]))
614 /* FIXME: Likewise. */
615 if (rl78_far_p (operands
[1]))
617 rtx temp_reg
= gen_reg_rtx (GET_MODE (operands
[1]));
618 emit_move_insn (temp_reg
, operands
[1]);
619 operands
[1] = temp_reg
;
622 if (rl78_far_p (operands
[0]))
624 temp_reg
= operands
[0];
625 operands
[0] = gen_reg_rtx (GET_MODE (operands
[0]));
631 emit_insn (gen (operands
[0], operands
[1], operands
[2]));
633 emit_move_insn (temp_reg
, operands
[0]);
637 #undef TARGET_CAN_ELIMINATE
638 #define TARGET_CAN_ELIMINATE rl78_can_eliminate
641 rl78_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to ATTRIBUTE_UNUSED
)
646 /* Returns true if the given register needs to be saved by the
649 need_to_save (unsigned int regno
)
651 if (is_interrupt_func (cfun
->decl
))
653 /* We don't know what devirt will need */
657 /* We don't need to save registers that have
658 been reserved for interrupt handlers. */
662 /* If the handler is a non-leaf function then it may call
663 non-interrupt aware routines which will happily clobber
664 any call_used registers, so we have to preserve them.
665 We do not have to worry about the frame pointer register
666 though, as that is handled below. */
667 if (!crtl
->is_leaf
&& call_used_regs
[regno
] && regno
< 22)
670 /* Otherwise we only have to save a register, call_used
671 or not, if it is used by this handler. */
672 return df_regs_ever_live_p (regno
);
675 if (regno
== FRAME_POINTER_REGNUM
676 && (frame_pointer_needed
|| df_regs_ever_live_p (regno
)))
678 if (fixed_regs
[regno
])
680 if (crtl
->calls_eh_return
)
682 if (df_regs_ever_live_p (regno
)
683 && !call_used_regs
[regno
])
688 /* We use this to wrap all emitted insns in the prologue. */
692 RTX_FRAME_RELATED_P (x
) = 1;
696 /* Compute all the frame-related fields in our machine_function
699 rl78_compute_frame_info (void)
703 cfun
->machine
->computed
= 1;
704 cfun
->machine
->framesize_regs
= 0;
705 cfun
->machine
->framesize_locals
= get_frame_size ();
706 cfun
->machine
->framesize_outgoing
= crtl
->outgoing_args_size
;
708 for (i
= 0; i
< 16; i
++)
709 if (need_to_save (i
* 2) || need_to_save (i
* 2 + 1))
711 cfun
->machine
->need_to_push
[i
] = 1;
712 cfun
->machine
->framesize_regs
+= 2;
715 cfun
->machine
->need_to_push
[i
] = 0;
717 if ((cfun
->machine
->framesize_locals
+ cfun
->machine
->framesize_outgoing
) & 1)
718 cfun
->machine
->framesize_locals
++;
720 cfun
->machine
->framesize
= (cfun
->machine
->framesize_regs
721 + cfun
->machine
->framesize_locals
722 + cfun
->machine
->framesize_outgoing
);
725 /* Returns true if the provided function has the specified attribute. */
727 has_func_attr (const_tree decl
, const char * func_attr
)
729 if (decl
== NULL_TREE
)
730 decl
= current_function_decl
;
732 return lookup_attribute (func_attr
, DECL_ATTRIBUTES (decl
)) != NULL_TREE
;
735 /* Returns true if the provided function has the "interrupt" attribute. */
737 is_interrupt_func (const_tree decl
)
739 return has_func_attr (decl
, "interrupt") || has_func_attr (decl
, "brk_interrupt");
742 /* Returns true if the provided function has the "brk_interrupt" attribute. */
744 is_brk_interrupt_func (const_tree decl
)
746 return has_func_attr (decl
, "brk_interrupt");
749 /* Check "interrupt" attributes. */
751 rl78_handle_func_attribute (tree
* node
,
754 int flags ATTRIBUTE_UNUSED
,
757 gcc_assert (DECL_P (* node
));
758 gcc_assert (args
== NULL_TREE
);
760 if (TREE_CODE (* node
) != FUNCTION_DECL
)
762 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
764 * no_add_attrs
= true;
767 /* FIXME: We ought to check that the interrupt and exception
768 handler attributes have been applied to void functions. */
772 /* Check "naked" attributes. */
774 rl78_handle_naked_attribute (tree
* node
,
775 tree name ATTRIBUTE_UNUSED
,
777 int flags ATTRIBUTE_UNUSED
,
780 gcc_assert (DECL_P (* node
));
781 gcc_assert (args
== NULL_TREE
);
783 if (TREE_CODE (* node
) != FUNCTION_DECL
)
785 warning (OPT_Wattributes
, "naked attribute only applies to functions");
786 * no_add_attrs
= true;
789 /* Disable warnings about this function - eg reaching the end without
790 seeing a return statement - because the programmer is doing things
791 that gcc does not know about. */
792 TREE_NO_WARNING (* node
) = 1;
797 /* Check "saddr" attributes. */
799 rl78_handle_saddr_attribute (tree
* node
,
801 tree args ATTRIBUTE_UNUSED
,
802 int flags ATTRIBUTE_UNUSED
,
805 gcc_assert (DECL_P (* node
));
807 if (TREE_CODE (* node
) == FUNCTION_DECL
)
809 warning (OPT_Wattributes
, "%qE attribute doesn't apply to functions",
811 * no_add_attrs
= true;
817 #undef TARGET_ATTRIBUTE_TABLE
818 #define TARGET_ATTRIBUTE_TABLE rl78_attribute_table
820 /* Table of RL78-specific attributes. */
821 const struct attribute_spec rl78_attribute_table
[] =
823 /* Name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
824 affects_type_identity. */
825 { "interrupt", 0, 0, true, false, false, rl78_handle_func_attribute
,
827 { "brk_interrupt", 0, 0, true, false, false, rl78_handle_func_attribute
,
829 { "naked", 0, 0, true, false, false, rl78_handle_naked_attribute
,
831 { "saddr", 0, 0, true, false, false, rl78_handle_saddr_attribute
,
833 { NULL
, 0, 0, false, false, false, NULL
, false }
838 /* Break down an address RTX into its component base/index/addend
839 portions and return TRUE if the address is of a valid form, else
842 characterize_address (rtx x
, rtx
*base
, rtx
*index
, rtx
*addend
)
848 if (GET_CODE (x
) == UNSPEC
849 && XINT (x
, 1) == UNS_ES_ADDR
)
850 x
= XVECEXP (x
, 0, 1);
852 if (GET_CODE (x
) == REG
)
858 /* We sometimes get these without the CONST wrapper */
859 if (GET_CODE (x
) == PLUS
860 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
861 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
867 if (GET_CODE (x
) == PLUS
)
872 if (GET_CODE (*base
) == SUBREG
)
874 if (GET_MODE (*base
) == HImode
875 && GET_MODE (XEXP (*base
, 0)) == SImode
876 && GET_CODE (XEXP (*base
, 0)) == REG
)
878 /* This is a throw-away rtx just to tell everyone
879 else what effective register we're using. */
880 *base
= gen_rtx_REG (HImode
, REGNO (XEXP (*base
, 0)));
884 if (GET_CODE (*base
) != REG
885 && GET_CODE (x
) == REG
)
892 if (GET_CODE (*base
) != REG
)
895 if (GET_CODE (x
) == ZERO_EXTEND
896 && GET_CODE (XEXP (x
, 0)) == REG
)
898 *index
= XEXP (x
, 0);
903 switch (GET_CODE (x
))
906 if (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
907 && GET_CODE (XEXP (x
, 0)) == CONST_INT
)
918 switch (GET_CODE (XEXP (x
, 0)))
942 /* Used by the Whb constraint. Match addresses that use HL+B or HL+C
945 rl78_hl_b_c_addr_p (rtx op
)
949 if (GET_CODE (op
) != PLUS
)
953 if (GET_CODE (hl
) == ZERO_EXTEND
)
959 if (GET_CODE (hl
) != REG
)
961 if (GET_CODE (bc
) != ZERO_EXTEND
)
964 if (GET_CODE (bc
) != REG
)
966 if (REGNO (hl
) != HL_REG
)
968 if (REGNO (bc
) != B_REG
&& REGNO (bc
) != C_REG
)
974 #define REG_IS(r, regno) (((r) == (regno)) || ((r) >= FIRST_PSEUDO_REGISTER && !(strict)))
976 /* Return the appropriate mode for a named address address. */
978 #undef TARGET_ADDR_SPACE_ADDRESS_MODE
979 #define TARGET_ADDR_SPACE_ADDRESS_MODE rl78_addr_space_address_mode
981 static enum machine_mode
982 rl78_addr_space_address_mode (addr_space_t addrspace
)
986 case ADDR_SPACE_GENERIC
:
988 case ADDR_SPACE_NEAR
:
997 /* Used in various constraints and predicates to match operands in the
998 "far" address space. */
1005 fprintf (stderr
, "\033[35mrl78_far_p: "); debug_rtx (x
);
1006 fprintf (stderr
, " = %d\033[0m\n", MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
);
1009 /* Not all far addresses are legitimate, because the devirtualizer
1010 can't handle them. */
1011 if (! rl78_as_legitimate_address (GET_MODE (x
), XEXP (x
, 0), false, ADDR_SPACE_FAR
))
1014 return GET_MODE_BITSIZE (rl78_addr_space_address_mode (MEM_ADDR_SPACE (x
))) == 32;
1017 /* Return the appropriate mode for a named address pointer. */
1018 #undef TARGET_ADDR_SPACE_POINTER_MODE
1019 #define TARGET_ADDR_SPACE_POINTER_MODE rl78_addr_space_pointer_mode
1022 rl78_addr_space_pointer_mode (addr_space_t addrspace
)
1026 case ADDR_SPACE_GENERIC
:
1028 case ADDR_SPACE_NEAR
:
1030 case ADDR_SPACE_FAR
:
1037 /* Returns TRUE for valid addresses. */
1038 #undef TARGET_VALID_POINTER_MODE
1039 #define TARGET_VALID_POINTER_MODE rl78_valid_pointer_mode
1042 rl78_valid_pointer_mode (machine_mode m
)
1044 return (m
== HImode
|| m
== SImode
);
1047 #undef TARGET_LEGITIMATE_CONSTANT_P
1048 #define TARGET_LEGITIMATE_CONSTANT_P rl78_is_legitimate_constant
1051 rl78_is_legitimate_constant (machine_mode mode ATTRIBUTE_UNUSED
, rtx x ATTRIBUTE_UNUSED
)
1056 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
1057 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P rl78_as_legitimate_address
1060 rl78_as_legitimate_address (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
,
1061 bool strict ATTRIBUTE_UNUSED
, addr_space_t as ATTRIBUTE_UNUSED
)
1063 rtx base
, index
, addend
;
1064 bool is_far_addr
= false;
1067 as_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (as
));
1069 if (GET_CODE (x
) == UNSPEC
1070 && XINT (x
, 1) == UNS_ES_ADDR
)
1072 x
= XVECEXP (x
, 0, 1);
1076 if (as_bits
== 16 && is_far_addr
)
1079 if (! characterize_address (x
, &base
, &index
, &addend
))
1082 /* We can't extract the high/low portions of a PLUS address
1083 involving a register during devirtualization, so make sure all
1084 such __far addresses do not have addends. This forces GCC to do
1085 the sum separately. */
1086 if (addend
&& base
&& as_bits
== 32 && GET_MODE (base
) == SImode
)
1091 int ir
= REGNO (index
);
1092 int br
= REGNO (base
);
1094 #define OK(test, debug) if (test) { /*fprintf(stderr, "%d: OK %s\n", __LINE__, debug);*/ return true; }
1095 OK (REG_IS (br
, HL_REG
) && REG_IS (ir
, B_REG
), "[hl+b]");
1096 OK (REG_IS (br
, HL_REG
) && REG_IS (ir
, C_REG
), "[hl+c]");
1100 if (strict
&& base
&& GET_CODE (base
) == REG
&& REGNO (base
) >= FIRST_PSEUDO_REGISTER
)
1103 if (! cfun
->machine
->virt_insns_ok
&& base
&& GET_CODE (base
) == REG
1104 && REGNO (base
) >= 8 && REGNO (base
) <= 31)
1110 /* Determine if one named address space is a subset of another. */
1111 #undef TARGET_ADDR_SPACE_SUBSET_P
1112 #define TARGET_ADDR_SPACE_SUBSET_P rl78_addr_space_subset_p
1115 rl78_addr_space_subset_p (addr_space_t subset
, addr_space_t superset
)
1120 subset_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (subset
));
1121 superset_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (superset
));
1123 return (subset_bits
<= superset_bits
);
1126 #undef TARGET_ADDR_SPACE_CONVERT
1127 #define TARGET_ADDR_SPACE_CONVERT rl78_addr_space_convert
1129 /* Convert from one address space to another. */
1131 rl78_addr_space_convert (rtx op
, tree from_type
, tree to_type
)
1133 addr_space_t from_as
= TYPE_ADDR_SPACE (TREE_TYPE (from_type
));
1134 addr_space_t to_as
= TYPE_ADDR_SPACE (TREE_TYPE (to_type
));
1139 to_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (to_as
));
1140 from_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (from_as
));
1142 if (to_bits
< from_bits
)
1145 /* This is unpredictable, as we're truncating off usable address
1148 warning (OPT_Waddress
, "converting far pointer to near pointer");
1149 result
= gen_reg_rtx (HImode
);
1150 if (GET_CODE (op
) == SYMBOL_REF
1151 || (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1152 tmp
= gen_rtx_raw_SUBREG (HImode
, op
, 0);
1154 tmp
= simplify_subreg (HImode
, op
, SImode
, 0);
1155 gcc_assert (tmp
!= NULL_RTX
);
1156 emit_move_insn (result
, tmp
);
1159 else if (to_bits
> from_bits
)
1161 /* This always works. */
1162 result
= gen_reg_rtx (SImode
);
1163 emit_move_insn (rl78_subreg (HImode
, result
, SImode
, 0), op
);
1164 if (TREE_CODE (from_type
) == POINTER_TYPE
1165 && TREE_CODE (TREE_TYPE (from_type
)) == FUNCTION_TYPE
)
1166 emit_move_insn (rl78_subreg (HImode
, result
, SImode
, 2), const0_rtx
);
1168 emit_move_insn (rl78_subreg (HImode
, result
, SImode
, 2), GEN_INT (0x0f));
1176 /* Implements REGNO_MODE_CODE_OK_FOR_BASE_P. */
1178 rl78_regno_mode_code_ok_for_base_p (int regno
, machine_mode mode ATTRIBUTE_UNUSED
,
1179 addr_space_t address_space ATTRIBUTE_UNUSED
,
1180 int outer_code ATTRIBUTE_UNUSED
, int index_code
)
1182 if (regno
<= SP_REG
&& regno
>= 16)
1184 if (index_code
== REG
)
1185 return (regno
== HL_REG
);
1186 if (regno
== C_REG
|| regno
== B_REG
|| regno
== E_REG
|| regno
== L_REG
)
1191 /* Implements MODE_CODE_BASE_REG_CLASS. */
1193 rl78_mode_code_base_reg_class (machine_mode mode ATTRIBUTE_UNUSED
,
1194 addr_space_t address_space ATTRIBUTE_UNUSED
,
1195 int outer_code ATTRIBUTE_UNUSED
,
1196 int index_code ATTRIBUTE_UNUSED
)
1201 /* Typical stack layout should looks like this after the function's prologue:
1206 | | arguments saved | Increasing
1207 | | on the stack | addresses
1208 PARENT arg pointer -> | | /
1209 -------------------------- ---- -------------------
1210 CHILD |ret | return address
1215 frame pointer -> | | /
1223 | | outgoing | Decreasing
1224 | | arguments | addresses
1225 current stack pointer -> | | / |
1226 -------------------------- ---- ------------------ V
1229 /* Implements INITIAL_ELIMINATION_OFFSET. The frame layout is
1230 described in the machine_Function struct definition, above. */
1232 rl78_initial_elimination_offset (int from
, int to
)
1234 int rv
= 0; /* as if arg to arg */
1236 rl78_compute_frame_info ();
1240 case STACK_POINTER_REGNUM
:
1241 rv
+= cfun
->machine
->framesize_outgoing
;
1242 rv
+= cfun
->machine
->framesize_locals
;
1244 case FRAME_POINTER_REGNUM
:
1245 rv
+= cfun
->machine
->framesize_regs
;
1254 case FRAME_POINTER_REGNUM
:
1256 rv
-= cfun
->machine
->framesize_regs
;
1257 case ARG_POINTER_REGNUM
:
1267 rl78_is_naked_func (void)
1269 return (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
);
1272 /* Expand the function prologue (from the prologue pattern). */
1274 rl78_expand_prologue (void)
1277 rtx sp
= gen_rtx_REG (HImode
, STACK_POINTER_REGNUM
);
1278 rtx ax
= gen_rtx_REG (HImode
, AX_REG
);
1281 if (rl78_is_naked_func ())
1284 /* Always re-compute the frame info - the register usage may have changed. */
1285 rl78_compute_frame_info ();
1287 if (flag_stack_usage_info
)
1288 current_function_static_stack_size
= cfun
->machine
->framesize
;
1290 if (is_interrupt_func (cfun
->decl
) && !TARGET_G10
)
1291 for (i
= 0; i
< 4; i
++)
1292 if (cfun
->machine
->need_to_push
[i
])
1294 /* Select Bank 0 if we are using any registers from Bank 0. */
1295 emit_insn (gen_sel_rb (GEN_INT (0)));
1299 for (i
= 0; i
< 16; i
++)
1300 if (cfun
->machine
->need_to_push
[i
])
1308 emit_move_insn (ax
, gen_rtx_REG (HImode
, reg
));
1314 int need_bank
= i
/4;
1316 if (need_bank
!= rb
)
1318 emit_insn (gen_sel_rb (GEN_INT (need_bank
)));
1323 F (emit_insn (gen_push (gen_rtx_REG (HImode
, reg
))));
1327 emit_insn (gen_sel_rb (GEN_INT (0)));
1329 /* Save ES register inside interrupt functions if it is used. */
1330 if (is_interrupt_func (cfun
->decl
) && cfun
->machine
->uses_es
)
1332 emit_insn (gen_movqi_from_es (gen_rtx_REG (QImode
, A_REG
)));
1333 F (emit_insn (gen_push (ax
)));
1336 if (frame_pointer_needed
)
1338 F (emit_move_insn (ax
, sp
));
1339 F (emit_move_insn (gen_rtx_REG (HImode
, FRAME_POINTER_REGNUM
), ax
));
1342 fs
= cfun
->machine
->framesize_locals
+ cfun
->machine
->framesize_outgoing
;
1345 /* If we need to subtract more than 254*3 then it is faster and
1346 smaller to move SP into AX and perform the subtraction there. */
1351 emit_move_insn (ax
, sp
);
1352 emit_insn (gen_subhi3 (ax
, ax
, GEN_INT (fs
)));
1353 insn
= F (emit_move_insn (sp
, ax
));
1354 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
1355 gen_rtx_SET (sp
, gen_rtx_PLUS (HImode
, sp
,
1362 int fs_byte
= (fs
> 254) ? 254 : fs
;
1364 F (emit_insn (gen_subhi3 (sp
, sp
, GEN_INT (fs_byte
))));
1371 /* Expand the function epilogue (from the epilogue pattern). */
1373 rl78_expand_epilogue (void)
1376 rtx sp
= gen_rtx_REG (HImode
, STACK_POINTER_REGNUM
);
1377 rtx ax
= gen_rtx_REG (HImode
, AX_REG
);
1380 if (rl78_is_naked_func ())
1383 if (frame_pointer_needed
)
1385 emit_move_insn (ax
, gen_rtx_REG (HImode
, FRAME_POINTER_REGNUM
));
1386 emit_move_insn (sp
, ax
);
1390 fs
= cfun
->machine
->framesize_locals
+ cfun
->machine
->framesize_outgoing
;
1393 emit_move_insn (ax
, sp
);
1394 emit_insn (gen_addhi3 (ax
, ax
, GEN_INT (fs
)));
1395 emit_move_insn (sp
, ax
);
1401 int fs_byte
= (fs
> 254) ? 254 : fs
;
1403 emit_insn (gen_addhi3 (sp
, sp
, GEN_INT (fs_byte
)));
1409 if (is_interrupt_func (cfun
->decl
) && cfun
->machine
->uses_es
)
1411 emit_insn (gen_pop (gen_rtx_REG (HImode
, AX_REG
)));
1412 emit_insn (gen_movqi_to_es (gen_rtx_REG (QImode
, A_REG
)));
1415 for (i
= 15; i
>= 0; i
--)
1416 if (cfun
->machine
->need_to_push
[i
])
1418 rtx dest
= gen_rtx_REG (HImode
, i
* 2);
1423 emit_insn (gen_pop (dest
));
1426 emit_insn (gen_pop (ax
));
1427 emit_move_insn (dest
, ax
);
1428 /* Generate a USE of the pop'd register so that DCE will not eliminate the move. */
1429 emit_insn (gen_use (dest
));
1434 int need_bank
= i
/ 4;
1436 if (need_bank
!= rb
)
1438 emit_insn (gen_sel_rb (GEN_INT (need_bank
)));
1441 emit_insn (gen_pop (dest
));
1446 emit_insn (gen_sel_rb (GEN_INT (0)));
1448 if (cfun
->machine
->trampolines_used
)
1449 emit_insn (gen_trampoline_uninit ());
1451 if (is_brk_interrupt_func (cfun
->decl
))
1452 emit_jump_insn (gen_brk_interrupt_return ());
1453 else if (is_interrupt_func (cfun
->decl
))
1454 emit_jump_insn (gen_interrupt_return ());
1456 emit_jump_insn (gen_rl78_return ());
1459 /* Likewise, for exception handlers. */
1461 rl78_expand_eh_epilogue (rtx x ATTRIBUTE_UNUSED
)
1463 /* FIXME - replace this with an indirect jump with stack adjust. */
1464 emit_jump_insn (gen_rl78_return ());
1467 #undef TARGET_ASM_FUNCTION_PROLOGUE
1468 #define TARGET_ASM_FUNCTION_PROLOGUE rl78_start_function
1470 /* We don't use this to actually emit the function prologue. We use
1471 this to insert a comment in the asm file describing the
1474 rl78_start_function (FILE *file
, HOST_WIDE_INT hwi_local ATTRIBUTE_UNUSED
)
1478 if (cfun
->machine
->framesize
== 0)
1480 fprintf (file
, "\t; start of function\n");
1482 if (cfun
->machine
->framesize_regs
)
1484 fprintf (file
, "\t; push %d:", cfun
->machine
->framesize_regs
);
1485 for (i
= 0; i
< 16; i
++)
1486 if (cfun
->machine
->need_to_push
[i
])
1487 fprintf (file
, " %s", word_regnames
[i
*2]);
1488 fprintf (file
, "\n");
1491 if (frame_pointer_needed
)
1492 fprintf (file
, "\t; $fp points here (r22)\n");
1494 if (cfun
->machine
->framesize_locals
)
1495 fprintf (file
, "\t; locals: %d byte%s\n", cfun
->machine
->framesize_locals
,
1496 cfun
->machine
->framesize_locals
== 1 ? "" : "s");
1498 if (cfun
->machine
->framesize_outgoing
)
1499 fprintf (file
, "\t; outgoing: %d byte%s\n", cfun
->machine
->framesize_outgoing
,
1500 cfun
->machine
->framesize_outgoing
== 1 ? "" : "s");
1502 if (cfun
->machine
->uses_es
)
1503 fprintf (file
, "\t; uses ES register\n");
1506 /* Return an RTL describing where a function return value of type RET_TYPE
1509 #undef TARGET_FUNCTION_VALUE
1510 #define TARGET_FUNCTION_VALUE rl78_function_value
1513 rl78_function_value (const_tree ret_type
,
1514 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1515 bool outgoing ATTRIBUTE_UNUSED
)
1517 machine_mode mode
= TYPE_MODE (ret_type
);
1519 return gen_rtx_REG (mode
, 8);
1522 #undef TARGET_PROMOTE_FUNCTION_MODE
1523 #define TARGET_PROMOTE_FUNCTION_MODE rl78_promote_function_mode
1526 rl78_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
1528 int *punsignedp ATTRIBUTE_UNUSED
,
1529 const_tree funtype ATTRIBUTE_UNUSED
, int for_return ATTRIBUTE_UNUSED
)
1534 /* Return an RTL expression describing the register holding a function
1535 parameter of mode MODE and type TYPE or NULL_RTX if the parameter should
1536 be passed on the stack. CUM describes the previous parameters to the
1537 function and NAMED is false if the parameter is part of a variable
1538 parameter list, or the last named parameter before the start of a
1539 variable parameter list. */
1541 #undef TARGET_FUNCTION_ARG
1542 #define TARGET_FUNCTION_ARG rl78_function_arg
1545 rl78_function_arg (cumulative_args_t cum_v ATTRIBUTE_UNUSED
,
1546 machine_mode mode ATTRIBUTE_UNUSED
,
1547 const_tree type ATTRIBUTE_UNUSED
,
1548 bool named ATTRIBUTE_UNUSED
)
1553 #undef TARGET_FUNCTION_ARG_ADVANCE
1554 #define TARGET_FUNCTION_ARG_ADVANCE rl78_function_arg_advance
1557 rl78_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
, const_tree type
,
1558 bool named ATTRIBUTE_UNUSED
)
1561 CUMULATIVE_ARGS
* cum
= get_cumulative_args (cum_v
);
1563 rounded_size
= ((mode
== BLKmode
)
1564 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
1565 if (rounded_size
& 1)
1567 (*cum
) += rounded_size
;
1570 #undef TARGET_FUNCTION_ARG_BOUNDARY
1571 #define TARGET_FUNCTION_ARG_BOUNDARY rl78_function_arg_boundary
1574 rl78_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
1575 const_tree type ATTRIBUTE_UNUSED
)
1580 /* Supported modifier letters:
1582 A - address of a MEM
1583 S - SADDR form of a real register
1584 v - real register corresponding to a virtual register
1585 m - minus - negative of CONST_INT value.
1586 C - inverse of a conditional (NE vs EQ for example)
1587 C - complement of an integer
1588 z - collapsed conditional
1589 s - shift count mod 8
1590 S - shift count mod 16
1591 r - reverse shift count (8-(count mod 8))
1594 h - bottom HI of an SI
1596 q - bottom QI of an HI
1598 e - third QI of an SI (i.e. where the ES register gets values from)
1599 E - fourth QI of an SI (i.e. MSB)
1601 p - Add +0 to a zero-indexed HL based address.
1604 /* Implements the bulk of rl78_print_operand, below. We do it this
1605 way because we need to test for a constant at the top level and
1606 insert the '#', but not test for it anywhere else as we recurse
1607 down into the operand. */
1609 rl78_print_operand_1 (FILE * file
, rtx op
, int letter
)
1613 switch (GET_CODE (op
))
1617 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1620 if (rl78_far_p (op
))
1622 fprintf (file
, "es:");
1623 if (GET_CODE (XEXP (op
, 0)) == UNSPEC
)
1624 op
= gen_rtx_MEM (GET_MODE (op
), XVECEXP (XEXP (op
, 0), 0, 1));
1628 op
= adjust_address (op
, HImode
, 2);
1633 op
= adjust_address (op
, HImode
, 0);
1638 op
= adjust_address (op
, QImode
, 1);
1643 op
= adjust_address (op
, QImode
, 0);
1648 op
= adjust_address (op
, QImode
, 2);
1653 op
= adjust_address (op
, QImode
, 3);
1656 if (CONSTANT_P (XEXP (op
, 0)))
1658 if (!rl78_saddr_p (op
))
1659 fprintf (file
, "!");
1660 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1662 else if (GET_CODE (XEXP (op
, 0)) == PLUS
1663 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
)
1665 if (!rl78_saddr_p (op
))
1666 fprintf (file
, "!");
1667 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1669 else if (GET_CODE (XEXP (op
, 0)) == PLUS
1670 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == REG
1671 && REGNO (XEXP (XEXP (op
, 0), 0)) == 2)
1673 rl78_print_operand_1 (file
, XEXP (XEXP (op
, 0), 1), 'u');
1674 fprintf (file
, "[");
1675 rl78_print_operand_1 (file
, XEXP (XEXP (op
, 0), 0), 0);
1676 if (letter
== 'p' && GET_CODE (XEXP (op
, 0)) == REG
)
1677 fprintf (file
, "+0");
1678 fprintf (file
, "]");
1683 fprintf (file
, "[");
1684 rl78_print_operand_1 (file
, op
, letter
);
1685 if (letter
== 'p' && REG_P (op
) && REGNO (op
) == 6)
1686 fprintf (file
, "+0");
1687 fprintf (file
, "]");
1694 fprintf (file
, "%s", reg_names
[REGNO (op
) | 1]);
1695 else if (letter
== 'H')
1696 fprintf (file
, "%s", reg_names
[REGNO (op
) + 2]);
1697 else if (letter
== 'q')
1698 fprintf (file
, "%s", reg_names
[REGNO (op
) & ~1]);
1699 else if (letter
== 'e')
1700 fprintf (file
, "%s", reg_names
[REGNO (op
) + 2]);
1701 else if (letter
== 'E')
1702 fprintf (file
, "%s", reg_names
[REGNO (op
) + 3]);
1703 else if (letter
== 'S')
1704 fprintf (file
, "0x%x", 0xffef8 + REGNO (op
));
1705 else if (GET_MODE (op
) == HImode
1706 && ! (REGNO (op
) & ~0xfe))
1709 fprintf (file
, "%s", word_regnames
[REGNO (op
) % 8]);
1711 fprintf (file
, "%s", word_regnames
[REGNO (op
)]);
1714 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
1719 fprintf (file
, "%ld", INTVAL (op
) >> 8);
1720 else if (letter
== 'H')
1721 fprintf (file
, "%ld", INTVAL (op
) >> 16);
1722 else if (letter
== 'q')
1723 fprintf (file
, "%ld", INTVAL (op
) & 0xff);
1724 else if (letter
== 'h')
1725 fprintf (file
, "%ld", INTVAL (op
) & 0xffff);
1726 else if (letter
== 'e')
1727 fprintf (file
, "%ld", (INTVAL (op
) >> 16) & 0xff);
1728 else if (letter
== 'B')
1730 int ival
= INTVAL (op
);
1733 if (exact_log2 (ival
) >= 0)
1734 fprintf (file
, "%d", exact_log2 (ival
));
1736 fprintf (file
, "%d", exact_log2 (~ival
& 0xff));
1738 else if (letter
== 'E')
1739 fprintf (file
, "%ld", (INTVAL (op
) >> 24) & 0xff);
1740 else if (letter
== 'm')
1741 fprintf (file
, "%ld", - INTVAL (op
));
1742 else if (letter
== 's')
1743 fprintf (file
, "%ld", INTVAL (op
) % 8);
1744 else if (letter
== 'S')
1745 fprintf (file
, "%ld", INTVAL (op
) % 16);
1746 else if (letter
== 'r')
1747 fprintf (file
, "%ld", 8 - (INTVAL (op
) % 8));
1748 else if (letter
== 'C')
1749 fprintf (file
, "%ld", (INTVAL (op
) ^ 0x8000) & 0xffff);
1751 fprintf (file
, "%ld", INTVAL (op
));
1755 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1760 int bits
= INTVAL (XEXP (op
, 1));
1761 int ofs
= INTVAL (XEXP (op
, 2));
1762 if (bits
== 16 && ofs
== 0)
1763 fprintf (file
, "%%lo16(");
1764 else if (bits
== 16 && ofs
== 16)
1765 fprintf (file
, "%%hi16(");
1766 else if (bits
== 8 && ofs
== 16)
1767 fprintf (file
, "%%hi8(");
1770 rl78_print_operand_1 (file
, XEXP (op
, 0), 0);
1771 fprintf (file
, ")");
1776 if (GET_CODE (XEXP (op
, 0)) == REG
)
1777 fprintf (file
, "%s", reg_names
[REGNO (XEXP (op
, 0))]);
1779 print_rtl (file
, op
);
1786 fprintf (file
, "%%hi16(");
1792 fprintf (file
, "%%lo16(");
1798 fprintf (file
, "%%hi8(");
1802 if (letter
== 'q' || letter
== 'Q')
1803 output_operand_lossage ("q/Q modifiers invalid for symbol references");
1805 if (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
1807 if (GET_CODE (XEXP (op
, 1)) == SYMBOL_REF
1808 && SYMBOL_REF_DECL (XEXP (op
, 1))
1809 && TREE_CODE (SYMBOL_REF_DECL (XEXP (op
, 1))) == FUNCTION_DECL
)
1811 fprintf (file
, "%%code(");
1812 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op
, 1), 0)));
1813 fprintf (file
, "+");
1814 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1815 fprintf (file
, ")");
1819 rl78_print_operand_1 (file
, XEXP (op
, 1), letter
);
1820 fprintf (file
, "+");
1821 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1826 if (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1827 && SYMBOL_REF_DECL (XEXP (op
, 0))
1828 && TREE_CODE (SYMBOL_REF_DECL (XEXP (op
, 0))) == FUNCTION_DECL
)
1830 fprintf (file
, "%%code(");
1831 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op
, 0), 0)));
1832 fprintf (file
, "+");
1833 rl78_print_operand_1 (file
, XEXP (op
, 1), letter
);
1834 fprintf (file
, ")");
1838 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1839 fprintf (file
, "+");
1840 rl78_print_operand_1 (file
, XEXP (op
, 1), letter
);
1844 fprintf (file
, ")");
1848 if (GET_MODE (op
) == HImode
1849 && SUBREG_BYTE (op
) == 0)
1851 fprintf (file
, "%%lo16(");
1852 rl78_print_operand_1 (file
, SUBREG_REG (op
), 0);
1853 fprintf (file
, ")");
1855 else if (GET_MODE (op
) == HImode
1856 && SUBREG_BYTE (op
) == 2)
1858 fprintf (file
, "%%hi16(");
1859 rl78_print_operand_1 (file
, SUBREG_REG (op
), 0);
1860 fprintf (file
, ")");
1864 fprintf (file
, "(%s)", GET_RTX_NAME (GET_CODE (op
)));
1872 fprintf (file
, "%%hi16(");
1878 fprintf (file
, "%%lo16(");
1884 fprintf (file
, "%%hi8(");
1888 if (letter
== 'q' || letter
== 'Q')
1889 output_operand_lossage ("q/Q modifiers invalid for symbol references");
1891 if (SYMBOL_REF_DECL (op
) && TREE_CODE (SYMBOL_REF_DECL (op
)) == FUNCTION_DECL
)
1893 fprintf (file
, "%%code(");
1894 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (op
, 0)));
1895 fprintf (file
, ")");
1898 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (op
, 0)));
1900 fprintf (file
, ")");
1905 output_asm_label (op
);
1910 fprintf (file
, "#comparison eliminated");
1912 fprintf (file
, letter
== 'C' ? "nc" : "c");
1916 fprintf (file
, "br");
1918 fprintf (file
, letter
== 'C' ? "h" : "nh");
1922 fprintf (file
, "br");
1924 fprintf (file
, letter
== 'C' ? "c" : "nc");
1928 fprintf (file
, "#comparison eliminated");
1930 fprintf (file
, letter
== 'C' ? "nh" : "h");
1934 fprintf (file
, "br");
1936 fprintf (file
, letter
== 'C' ? "nz" : "z");
1940 fprintf (file
, "#comparison eliminated");
1942 fprintf (file
, letter
== 'C' ? "z" : "nz");
1945 /* Note: these assume appropriate adjustments were made so that
1946 unsigned comparisons, which is all this chip has, will
1950 fprintf (file
, "#comparison eliminated");
1952 fprintf (file
, letter
== 'C' ? "nc" : "c");
1956 fprintf (file
, "br");
1958 fprintf (file
, letter
== 'C' ? "h" : "nh");
1962 fprintf (file
, "br");
1964 fprintf (file
, letter
== 'C' ? "c" : "nc");
1968 fprintf (file
, "#comparison eliminated");
1970 fprintf (file
, letter
== 'C' ? "nh" : "h");
1974 fprintf (file
, "(%s)", GET_RTX_NAME (GET_CODE (op
)));
1979 #undef TARGET_PRINT_OPERAND
1980 #define TARGET_PRINT_OPERAND rl78_print_operand
1983 rl78_print_operand (FILE * file
, rtx op
, int letter
)
1985 if (CONSTANT_P (op
) && letter
!= 'u' && letter
!= 's' && letter
!= 'r' && letter
!= 'S' && letter
!= 'B')
1986 fprintf (file
, "#");
1987 rl78_print_operand_1 (file
, op
, letter
);
1990 #undef TARGET_TRAMPOLINE_INIT
1991 #define TARGET_TRAMPOLINE_INIT rl78_trampoline_init
1993 /* Note that the RL78's addressing makes it very difficult to do
1994 trampolines on the stack. So, libgcc has a small pool of
1995 trampolines from which one is allocated to this task. */
1997 rl78_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
1999 rtx mov_addr
, thunk_addr
;
2000 rtx function
= XEXP (DECL_RTL (fndecl
), 0);
2002 mov_addr
= adjust_address (m_tramp
, HImode
, 0);
2003 thunk_addr
= gen_reg_rtx (HImode
);
2005 function
= force_reg (HImode
, function
);
2006 static_chain
= force_reg (HImode
, static_chain
);
2008 emit_insn (gen_trampoline_init (thunk_addr
, function
, static_chain
));
2009 emit_move_insn (mov_addr
, thunk_addr
);
2011 cfun
->machine
->trampolines_used
= 1;
2014 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
2015 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS rl78_trampoline_adjust_address
2018 rl78_trampoline_adjust_address (rtx m_tramp
)
2020 rtx x
= gen_rtx_MEM (HImode
, m_tramp
);
2024 /* Expander for cbranchqi4 and cbranchhi4. RL78 is missing some of
2025 the "normal" compares, specifically, it only has unsigned compares,
2026 so we must synthesize the missing ones. */
2028 rl78_expand_compare (rtx
*operands
)
2030 if (GET_CODE (operands
[2]) == MEM
)
2031 operands
[2] = copy_to_mode_reg (GET_MODE (operands
[2]), operands
[2]);
2036 /* Define this to 1 if you are debugging the peephole optimizers. */
2037 #define DEBUG_PEEP 0
2039 /* Predicate used to enable the peephole2 patterns in rl78-virt.md.
2040 The default "word" size is a byte so we can effectively use all the
2041 registers, but we want to do 16-bit moves whenever possible. This
2042 function determines when such a move is an option. */
2044 rl78_peep_movhi_p (rtx
*operands
)
2049 /* (set (op0) (op1))
2050 (set (op2) (op3)) */
2052 if (! rl78_virt_insns_ok ())
2056 fprintf (stderr
, "\033[33m");
2057 debug_rtx (operands
[0]);
2058 debug_rtx (operands
[1]);
2059 debug_rtx (operands
[2]);
2060 debug_rtx (operands
[3]);
2061 fprintf (stderr
, "\033[0m");
2064 /* You can move a constant to memory as QImode, but not HImode. */
2065 if (GET_CODE (operands
[0]) == MEM
2066 && GET_CODE (operands
[1]) != REG
)
2069 fprintf (stderr
, "no peep: move constant to memory\n");
2074 if (rtx_equal_p (operands
[0], operands
[3]))
2077 fprintf (stderr
, "no peep: overlapping\n");
2082 for (i
= 0; i
< 2; i
++)
2084 if (GET_CODE (operands
[i
]) != GET_CODE (operands
[i
+2]))
2087 fprintf (stderr
, "no peep: different codes\n");
2091 if (GET_MODE (operands
[i
]) != GET_MODE (operands
[i
+2]))
2094 fprintf (stderr
, "no peep: different modes\n");
2099 switch (GET_CODE (operands
[i
]))
2103 if (REGNO (operands
[i
]) + 1 != REGNO (operands
[i
+2])
2104 || GET_MODE (operands
[i
]) != QImode
)
2107 fprintf (stderr
, "no peep: wrong regnos %d %d %d\n",
2108 REGNO (operands
[i
]), REGNO (operands
[i
+2]),
2113 if (! rl78_hard_regno_mode_ok (REGNO (operands
[i
]), HImode
))
2116 fprintf (stderr
, "no peep: reg %d not HI\n", REGNO (operands
[i
]));
2126 if (GET_MODE (operands
[i
]) != QImode
)
2128 if (MEM_ALIGN (operands
[i
]) < 16)
2130 a
= XEXP (operands
[i
], 0);
2131 if (GET_CODE (a
) == CONST
)
2133 if (GET_CODE (a
) == PLUS
)
2135 if (GET_CODE (a
) == CONST_INT
2139 fprintf (stderr
, "no peep: misaligned mem %d\n", i
);
2140 debug_rtx (operands
[i
]);
2144 m
= adjust_address (operands
[i
], QImode
, 1);
2145 if (! rtx_equal_p (m
, operands
[i
+2]))
2148 fprintf (stderr
, "no peep: wrong mem %d\n", i
);
2150 debug_rtx (operands
[i
+2]);
2158 fprintf (stderr
, "no peep: wrong rtx %d\n", i
);
2164 fprintf (stderr
, "\033[32mpeep!\033[0m\n");
2169 /* Likewise, when a peephole is activated, this function helps compute
2170 the new operands. */
2172 rl78_setup_peep_movhi (rtx
*operands
)
2176 for (i
= 0; i
< 2; i
++)
2178 switch (GET_CODE (operands
[i
]))
2181 operands
[i
+4] = gen_rtx_REG (HImode
, REGNO (operands
[i
]));
2185 operands
[i
+4] = GEN_INT ((INTVAL (operands
[i
]) & 0xff) + ((char) INTVAL (operands
[i
+2])) * 256);
2189 operands
[i
+4] = adjust_address (operands
[i
], HImode
, 0);
2199 How Devirtualization works in the RL78 GCC port
2203 The RL78 is an 8-bit port with some 16-bit operations. It has 32
2204 bytes of register space, in four banks, memory-mapped. One bank is
2205 the "selected" bank and holds the registers used for primary
2206 operations. Since the registers are memory mapped, often you can
2207 still refer to the unselected banks via memory accesses.
2211 The GCC port uses bank 0 as the "selected" registers (A, X, BC, etc)
2212 and refers to the other banks via their memory addresses, although
2213 they're treated as regular registers internally. These "virtual"
2214 registers are R8 through R23 (bank3 is reserved for asm-based
2215 interrupt handlers).
2217 There are four machine description files:
2219 rl78.md - common register-independent patterns and definitions
2220 rl78-expand.md - expanders
2221 rl78-virt.md - patterns that match BEFORE devirtualization
2222 rl78-real.md - patterns that match AFTER devirtualization
2224 At least through register allocation and reload, gcc is told that it
2225 can do pretty much anything - but may only use the virtual registers.
2226 GCC cannot properly create the varying addressing modes that the RL78
2227 supports in an efficient way.
2229 Sometime after reload, the RL78 backend "devirtualizes" the RTL. It
2230 uses the "valloc" attribute in rl78-virt.md for determining the rules
2231 by which it will replace virtual registers with real registers (or
2232 not) and how to make up addressing modes. For example, insns tagged
2233 with "ro1" have a single read-only parameter, which may need to be
2234 moved from memory/constant/vreg to a suitable real register. As part
2235 of devirtualization, a flag is toggled, disabling the rl78-virt.md
2236 patterns and enabling the rl78-real.md patterns. The new patterns'
2237 constraints are used to determine the real registers used. NOTE:
2238 patterns in rl78-virt.md essentially ignore the constrains and rely on
2239 predicates, where the rl78-real.md ones essentially ignore the
2240 predicates and rely on the constraints.
2242 The devirtualization pass is scheduled via the pass manager (despite
2243 being called "rl78_reorg") so it can be scheduled prior to var-track
2244 (the idea is to let gdb know about the new registers). Ideally, it
2245 would be scheduled right after pro/epilogue generation, so the
2246 post-reload optimizers could operate on the real registers, but when I
2247 tried that there were some issues building the target libraries.
2249 During devirtualization, a simple register move optimizer is run. It
2250 would be better to run a full CSE/propogation pass on it though, but
2251 that has not yet been attempted.
2254 #define DEBUG_ALLOC 0
2256 #define OP(x) (*recog_data.operand_loc[x])
2258 /* This array is used to hold knowledge about the contents of the
2259 real registers (A ... H), the memory-based registers (r8 ... r31)
2260 and the first NUM_STACK_LOCS words on the stack. We use this to
2261 avoid generating redundant move instructions.
2263 A value in the range 0 .. 31 indicates register A .. r31.
2264 A value in the range 32 .. 63 indicates stack slot (value - 32).
2265 A value of NOT_KNOWN indicates that the contents of that location
2268 #define NUM_STACK_LOCS 32
2269 #define NOT_KNOWN 127
2271 static unsigned char content_memory
[32 + NUM_STACK_LOCS
];
2273 static unsigned char saved_update_index
= NOT_KNOWN
;
2274 static unsigned char saved_update_value
;
2275 static machine_mode saved_update_mode
;
2279 clear_content_memory (void)
2281 memset (content_memory
, NOT_KNOWN
, sizeof content_memory
);
2283 fprintf (dump_file
, " clear content memory\n");
2284 saved_update_index
= NOT_KNOWN
;
2287 /* Convert LOC into an index into the content_memory array.
2288 If LOC cannot be converted, return NOT_KNOWN. */
2290 static unsigned char
2291 get_content_index (rtx loc
)
2295 if (loc
== NULL_RTX
)
2300 if (REGNO (loc
) < 32)
2305 mode
= GET_MODE (loc
);
2307 if (! rl78_stack_based_mem (loc
, mode
))
2310 loc
= XEXP (loc
, 0);
2313 /* loc = MEM (SP) */
2316 /* loc = MEM (PLUS (SP, INT)). */
2317 loc
= XEXP (loc
, 1);
2319 if (INTVAL (loc
) < NUM_STACK_LOCS
)
2320 return 32 + INTVAL (loc
);
2325 /* Return a string describing content INDEX in mode MODE.
2326 WARNING: Can return a pointer to a static buffer. */
2328 get_content_name (unsigned char index
, machine_mode mode
)
2330 static char buffer
[128];
2332 if (index
== NOT_KNOWN
)
2336 sprintf (buffer
, "stack slot %d", index
- 32);
2337 else if (mode
== HImode
)
2338 sprintf (buffer
, "%s%s",
2339 reg_names
[index
+ 1], reg_names
[index
]);
2341 return reg_names
[index
];
2349 display_content_memory (FILE * file
)
2353 fprintf (file
, " Known memory contents:\n");
2355 for (i
= 0; i
< sizeof content_memory
; i
++)
2356 if (content_memory
[i
] != NOT_KNOWN
)
2358 fprintf (file
, " %s contains a copy of ", get_content_name (i
, QImode
));
2359 fprintf (file
, "%s\n", get_content_name (content_memory
[i
], QImode
));
2365 update_content (unsigned char index
, unsigned char val
, machine_mode mode
)
2369 gcc_assert (index
< sizeof content_memory
);
2371 content_memory
[index
] = val
;
2372 if (val
!= NOT_KNOWN
)
2373 content_memory
[val
] = index
;
2375 /* Make the entry in dump_file *before* VAL is increased below. */
2378 fprintf (dump_file
, " %s now contains ", get_content_name (index
, mode
));
2379 if (val
== NOT_KNOWN
)
2380 fprintf (dump_file
, "Unknown\n");
2382 fprintf (dump_file
, "%s and vice versa\n", get_content_name (val
, mode
));
2387 val
= val
== NOT_KNOWN
? val
: val
+ 1;
2389 content_memory
[index
+ 1] = val
;
2390 if (val
!= NOT_KNOWN
)
2392 content_memory
[val
] = index
+ 1;
2397 /* Any other places that had INDEX recorded as their contents are now invalid. */
2398 for (i
= 0; i
< sizeof content_memory
; i
++)
2401 || (val
!= NOT_KNOWN
&& i
== val
))
2408 if (content_memory
[i
] == index
2409 || (val
!= NOT_KNOWN
&& content_memory
[i
] == val
))
2411 content_memory
[i
] = NOT_KNOWN
;
2414 fprintf (dump_file
, " %s cleared\n", get_content_name (i
, mode
));
2417 content_memory
[++ i
] = NOT_KNOWN
;
2422 /* Record that LOC contains VALUE.
2423 For HImode locations record that LOC+1 contains VALUE+1.
2424 If LOC is not a register or stack slot, do nothing.
2425 If VALUE is not a register or stack slot, clear the recorded content. */
2428 record_content (rtx loc
, rtx value
)
2431 unsigned char index
;
2434 if ((index
= get_content_index (loc
)) == NOT_KNOWN
)
2437 val
= get_content_index (value
);
2439 mode
= GET_MODE (loc
);
2446 /* This should not happen when optimizing. */
2448 fprintf (stderr
, "ASSIGNMENT of location to itself detected! [%s]\n",
2449 get_content_name (val
, mode
));
2456 update_content (index
, val
, mode
);
2459 /* Returns TRUE if LOC already contains a copy of VALUE. */
2462 already_contains (rtx loc
, rtx value
)
2464 unsigned char index
;
2467 if ((index
= get_content_index (loc
)) == NOT_KNOWN
)
2470 if ((val
= get_content_index (value
)) == NOT_KNOWN
)
2473 if (content_memory
[index
] != val
)
2476 if (GET_MODE (loc
) == HImode
)
2477 return content_memory
[index
+ 1] == val
+ 1;
2483 rl78_es_addr (rtx addr
)
2485 if (GET_CODE (addr
) == MEM
)
2486 addr
= XEXP (addr
, 0);
2487 if (GET_CODE (addr
) != UNSPEC
)
2489 if (XINT (addr
, 1) != UNS_ES_ADDR
)
2495 rl78_es_base (rtx addr
)
2497 if (GET_CODE (addr
) == MEM
)
2498 addr
= XEXP (addr
, 0);
2499 addr
= XVECEXP (addr
, 0, 1);
2500 if (GET_CODE (addr
) == CONST
2501 && GET_CODE (XEXP (addr
, 0)) == ZERO_EXTRACT
)
2502 addr
= XEXP (XEXP (addr
, 0), 0);
2503 /* Mode doesn't matter here. */
2504 return gen_rtx_MEM (HImode
, addr
);
2507 /* Rescans an insn to see if it's recognized again. This is done
2508 carefully to ensure that all the constraint information is accurate
2509 for the newly matched insn. */
2511 insn_ok_now (rtx_insn
* insn
)
2513 rtx pattern
= PATTERN (insn
);
2516 INSN_CODE (insn
) = -1;
2518 if (recog (pattern
, insn
, 0) > -1)
2520 extract_insn (insn
);
2521 if (constrain_operands (1, get_preferred_alternatives (insn
)))
2524 fprintf (stderr
, "\033[32m");
2526 fprintf (stderr
, "\033[0m");
2528 if (SET_P (pattern
))
2529 record_content (SET_DEST (pattern
), SET_SRC (pattern
));
2531 /* We need to detect far addresses that haven't been
2532 converted to es/lo16 format. */
2533 for (i
=0; i
<recog_data
.n_operands
; i
++)
2534 if (GET_CODE (OP (i
)) == MEM
2535 && GET_MODE (XEXP (OP (i
), 0)) == SImode
2536 && GET_CODE (XEXP (OP (i
), 0)) != UNSPEC
)
2544 /* We need to re-recog the insn with virtual registers to get
2546 cfun
->machine
->virt_insns_ok
= 1;
2547 if (recog (pattern
, insn
, 0) > -1)
2549 extract_insn (insn
);
2550 if (constrain_operands (0, get_preferred_alternatives (insn
)))
2552 cfun
->machine
->virt_insns_ok
= 0;
2558 fprintf (stderr
, "\033[41;30m Unrecognized *virtual* insn \033[0m\n");
2565 fprintf (stderr
, "\033[31m");
2567 fprintf (stderr
, "\033[0m");
2573 #define WORKED fprintf (stderr, "\033[48;5;22m Worked at line %d \033[0m\n", __LINE__)
2574 #define FAILEDSOFAR fprintf (stderr, "\033[48;5;52m FAILED at line %d \033[0m\n", __LINE__)
2575 #define FAILED fprintf (stderr, "\033[48;5;52m FAILED at line %d \033[0m\n", __LINE__), gcc_unreachable ()
2576 #define MAYBE_OK(insn) if (insn_ok_now (insn)) { WORKED; return; } else { FAILEDSOFAR; }
2577 #define MUST_BE_OK(insn) if (insn_ok_now (insn)) { WORKED; return; } FAILED
2579 #define FAILED gcc_unreachable ()
2580 #define MAYBE_OK(insn) if (insn_ok_now (insn)) return;
2581 #define MUST_BE_OK(insn) if (insn_ok_now (insn)) return; FAILED
2584 /* Registers into which we move the contents of virtual registers. */
2585 #define X gen_rtx_REG (QImode, X_REG)
2586 #define A gen_rtx_REG (QImode, A_REG)
2587 #define C gen_rtx_REG (QImode, C_REG)
2588 #define B gen_rtx_REG (QImode, B_REG)
2589 #define E gen_rtx_REG (QImode, E_REG)
2590 #define D gen_rtx_REG (QImode, D_REG)
2591 #define L gen_rtx_REG (QImode, L_REG)
2592 #define H gen_rtx_REG (QImode, H_REG)
2594 #define AX gen_rtx_REG (HImode, AX_REG)
2595 #define BC gen_rtx_REG (HImode, BC_REG)
2596 #define DE gen_rtx_REG (HImode, DE_REG)
2597 #define HL gen_rtx_REG (HImode, HL_REG)
2599 /* Returns TRUE if R is a virtual register. */
2601 is_virtual_register (rtx r
)
2603 return (GET_CODE (r
) == REG
2608 /* In all these alloc routines, we expect the following: the insn
2609 pattern is unshared, the insn was previously recognized and failed
2610 due to predicates or constraints, and the operand data is in
2613 static int virt_insn_was_frame
;
2615 /* Hook for all insns we emit. Re-mark them as FRAME_RELATED if
2618 EM2 (int line ATTRIBUTE_UNUSED
, rtx r
)
2621 fprintf (stderr
, "\033[36m%d: ", line
);
2623 fprintf (stderr
, "\033[0m");
2625 /*SCHED_GROUP_P (r) = 1;*/
2626 if (virt_insn_was_frame
)
2627 RTX_FRAME_RELATED_P (r
) = 1;
2631 #define EM(x) EM2 (__LINE__, x)
2633 /* Return a suitable RTX for the low half of a __far address. */
2635 rl78_lo16 (rtx addr
)
2639 if (GET_CODE (addr
) == SYMBOL_REF
2640 || GET_CODE (addr
) == CONST
)
2642 r
= gen_rtx_ZERO_EXTRACT (HImode
, addr
, GEN_INT (16), GEN_INT (0));
2643 r
= gen_rtx_CONST (HImode
, r
);
2646 r
= rl78_subreg (HImode
, addr
, SImode
, 0);
2648 r
= gen_es_addr (r
);
2649 cfun
->machine
->uses_es
= true;
2654 /* Return a suitable RTX for the high half's lower byte of a __far address. */
2658 if (GET_CODE (addr
) == SYMBOL_REF
2659 || GET_CODE (addr
) == CONST
)
2661 rtx r
= gen_rtx_ZERO_EXTRACT (QImode
, addr
, GEN_INT (8), GEN_INT (16));
2662 r
= gen_rtx_CONST (QImode
, r
);
2665 return rl78_subreg (QImode
, addr
, SImode
, 2);
2669 add_postponed_content_update (rtx to
, rtx value
)
2671 unsigned char index
;
2673 if ((index
= get_content_index (to
)) == NOT_KNOWN
)
2676 gcc_assert (saved_update_index
== NOT_KNOWN
);
2677 saved_update_index
= index
;
2678 saved_update_value
= get_content_index (value
);
2679 saved_update_mode
= GET_MODE (to
);
2683 process_postponed_content_update (void)
2685 if (saved_update_index
!= NOT_KNOWN
)
2687 update_content (saved_update_index
, saved_update_value
, saved_update_mode
);
2688 saved_update_index
= NOT_KNOWN
;
2692 /* Generate and emit a move of (register) FROM into TO. if WHERE is not NULL
2693 then if BEFORE is true then emit the insn before WHERE, otherwise emit it
2694 after WHERE. If TO already contains FROM then do nothing. Returns TO if
2695 BEFORE is true, FROM otherwise. */
2697 gen_and_emit_move (rtx to
, rtx from
, rtx where
, bool before
)
2699 machine_mode mode
= GET_MODE (to
);
2701 if (optimize
&& before
&& already_contains (to
, from
))
2704 display_content_memory (stderr
);
2708 fprintf (dump_file
, " Omit move of %s into ",
2709 get_content_name (get_content_index (from
), mode
));
2710 fprintf (dump_file
, "%s as it already contains this value\n",
2711 get_content_name (get_content_index (to
), mode
));
2716 rtx move
= mode
== QImode
? gen_movqi (to
, from
) : gen_movhi (to
, from
);
2720 if (where
== NULL_RTX
)
2723 emit_insn_before (move
, where
);
2726 rtx note
= find_reg_note (where
, REG_EH_REGION
, NULL_RTX
);
2728 /* If necessary move REG_EH_REGION notes forward.
2729 cf. compiling gcc.dg/pr44545.c. */
2730 if (note
!= NULL_RTX
)
2732 add_reg_note (move
, REG_EH_REGION
, XEXP (note
, 0));
2733 remove_note (where
, note
);
2736 emit_insn_after (move
, where
);
2740 record_content (to
, from
);
2742 add_postponed_content_update (to
, from
);
2745 return before
? to
: from
;
2748 /* If M is MEM(REG) or MEM(PLUS(REG,INT)) and REG is virtual then
2749 copy it into NEWBASE and return the updated MEM. Otherwise just
2750 return M. Any needed insns are emitted before BEFORE. */
2752 transcode_memory_rtx (rtx m
, rtx newbase
, rtx before
)
2754 rtx base
, index
, addendr
;
2761 if (GET_MODE (XEXP (m
, 0)) == SImode
)
2764 rtx seg
= rl78_hi8 (XEXP (m
, 0));
2768 emit_insn_before (EM (gen_movqi (A
, seg
)), before
);
2769 emit_insn_before (EM (gen_movqi_to_es (A
)), before
);
2772 record_content (A
, NULL_RTX
);
2774 new_m
= gen_rtx_MEM (GET_MODE (m
), rl78_lo16 (XEXP (m
, 0)));
2775 MEM_COPY_ATTRIBUTES (new_m
, m
);
2780 characterize_address (XEXP (m
, 0), & base
, & index
, & addendr
);
2781 gcc_assert (index
== NULL_RTX
);
2783 if (base
== NULL_RTX
)
2786 if (addendr
&& GET_CODE (addendr
) == CONST_INT
)
2787 addend
= INTVAL (addendr
);
2789 gcc_assert (REG_P (base
));
2790 gcc_assert (REG_P (newbase
));
2792 int limit
= 256 - GET_MODE_SIZE (GET_MODE (m
));
2794 if (REGNO (base
) == SP_REG
)
2796 if (addend
>= 0 && addend
<= limit
)
2800 /* BASE should be a virtual register. We copy it to NEWBASE. If
2801 the addend is out of range for DE/HL, we use AX to compute the full
2805 || (addend
> limit
&& REGNO (newbase
) != BC_REG
)
2807 && (GET_CODE (addendr
) != CONST_INT
)
2808 && ((REGNO (newbase
) != BC_REG
))
2814 EM (emit_insn_before (gen_movhi (AX
, base
), before
));
2815 EM (emit_insn_before (gen_addhi3 (AX
, AX
, addendr
), before
));
2816 EM (emit_insn_before (gen_movhi (newbase
, AX
), before
));
2817 record_content (AX
, NULL_RTX
);
2818 record_content (newbase
, NULL_RTX
);
2826 base
= gen_and_emit_move (newbase
, base
, before
, true);
2831 record_content (base
, NULL_RTX
);
2832 base
= gen_rtx_PLUS (HImode
, base
, GEN_INT (addend
));
2836 record_content (base
, NULL_RTX
);
2837 base
= gen_rtx_PLUS (HImode
, base
, addendr
);
2842 m
= change_address (m
, GET_MODE (m
), gen_es_addr (base
));
2843 cfun
->machine
->uses_es
= true;
2846 m
= change_address (m
, GET_MODE (m
), base
);
2850 /* Copy SRC to accumulator (A or AX), placing any generated insns
2851 before BEFORE. Returns accumulator RTX. */
2853 move_to_acc (int opno
, rtx before
)
2855 rtx src
= OP (opno
);
2856 machine_mode mode
= GET_MODE (src
);
2858 if (REG_P (src
) && REGNO (src
) < 2)
2861 if (mode
== VOIDmode
)
2862 mode
= recog_data
.operand_mode
[opno
];
2864 return gen_and_emit_move (mode
== QImode
? A
: AX
, src
, before
, true);
2868 force_into_acc (rtx src
, rtx before
)
2870 machine_mode mode
= GET_MODE (src
);
2873 if (REG_P (src
) && REGNO (src
) < 2)
2876 move
= mode
== QImode
? gen_movqi (A
, src
) : gen_movhi (AX
, src
);
2880 emit_insn_before (move
, before
);
2881 record_content (AX
, NULL_RTX
);
2884 /* Copy accumulator (A or AX) to DEST, placing any generated insns
2885 after AFTER. Returns accumulator RTX. */
2887 move_from_acc (unsigned int opno
, rtx after
)
2889 rtx dest
= OP (opno
);
2890 machine_mode mode
= GET_MODE (dest
);
2892 if (REG_P (dest
) && REGNO (dest
) < 2)
2895 return gen_and_emit_move (dest
, mode
== QImode
? A
: AX
, after
, false);
2898 /* Copy accumulator (A or AX) to REGNO, placing any generated insns
2899 before BEFORE. Returns reg RTX. */
2901 move_acc_to_reg (rtx acc
, int regno
, rtx before
)
2903 machine_mode mode
= GET_MODE (acc
);
2906 reg
= gen_rtx_REG (mode
, regno
);
2908 return gen_and_emit_move (reg
, acc
, before
, true);
2911 /* Copy SRC to X, placing any generated insns before BEFORE.
2914 move_to_x (int opno
, rtx before
)
2916 rtx src
= OP (opno
);
2917 machine_mode mode
= GET_MODE (src
);
2920 if (mode
== VOIDmode
)
2921 mode
= recog_data
.operand_mode
[opno
];
2922 reg
= (mode
== QImode
) ? X
: AX
;
2924 if (mode
== QImode
|| ! is_virtual_register (OP (opno
)))
2926 OP (opno
) = move_to_acc (opno
, before
);
2927 OP (opno
) = move_acc_to_reg (OP (opno
), X_REG
, before
);
2931 return gen_and_emit_move (reg
, src
, before
, true);
2934 /* Copy OP (opno) to H or HL, placing any generated insns before BEFORE.
2935 Returns H/HL RTX. */
2937 move_to_hl (int opno
, rtx before
)
2939 rtx src
= OP (opno
);
2940 machine_mode mode
= GET_MODE (src
);
2943 if (mode
== VOIDmode
)
2944 mode
= recog_data
.operand_mode
[opno
];
2945 reg
= (mode
== QImode
) ? L
: HL
;
2947 if (mode
== QImode
|| ! is_virtual_register (OP (opno
)))
2949 OP (opno
) = move_to_acc (opno
, before
);
2950 OP (opno
) = move_acc_to_reg (OP (opno
), L_REG
, before
);
2954 return gen_and_emit_move (reg
, src
, before
, true);
2957 /* Copy OP (opno) to E or DE, placing any generated insns before BEFORE.
2958 Returns E/DE RTX. */
2960 move_to_de (int opno
, rtx before
)
2962 rtx src
= OP (opno
);
2963 machine_mode mode
= GET_MODE (src
);
2966 if (mode
== VOIDmode
)
2967 mode
= recog_data
.operand_mode
[opno
];
2969 reg
= (mode
== QImode
) ? E
: DE
;
2971 if (mode
== QImode
|| ! is_virtual_register (OP (opno
)))
2973 OP (opno
) = move_to_acc (opno
, before
);
2974 OP (opno
) = move_acc_to_reg (OP (opno
), E_REG
, before
);
2978 gen_and_emit_move (reg
, src
, before
, true);
2984 /* Devirtualize an insn of the form (SET (op) (unop (op))). */
2986 rl78_alloc_physical_registers_op1 (rtx_insn
* insn
)
2988 /* op[0] = func op[1] */
2990 /* We first try using A as the destination, then copying it
2992 if (rtx_equal_p (OP (0), OP (1)))
2995 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
2999 /* If necessary, load the operands into BC and HL.
3000 Check to see if we already have OP (0) in HL
3001 and if so, swap the order.
3003 It is tempting to perform this optimization when OP(0) does
3004 not hold a MEM, but this leads to bigger code in general.
3005 The problem is that if OP(1) holds a MEM then swapping it
3006 into BC means a BC-relative load is used and these are 3
3007 bytes long vs 1 byte for an HL load. */
3009 && already_contains (HL
, XEXP (OP (0), 0)))
3011 OP (0) = transcode_memory_rtx (OP (0), HL
, insn
);
3012 OP (1) = transcode_memory_rtx (OP (1), BC
, insn
);
3016 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3017 OP (1) = transcode_memory_rtx (OP (1), HL
, insn
);
3023 OP (0) = move_from_acc (0, insn
);
3027 /* Try copying the src to acc first, then. This is for, for
3028 example, ZERO_EXTEND or NOT. */
3029 OP (1) = move_to_acc (1, insn
);
3034 /* Returns true if operand OPNUM contains a constraint of type CONSTRAINT.
3035 Assumes that the current insn has already been recognised and hence the
3036 constraint data has been filled in. */
3038 has_constraint (unsigned int opnum
, enum constraint_num constraint
)
3040 const char * p
= recog_data
.constraints
[opnum
];
3042 /* No constraints means anything is accepted. */
3043 if (p
== NULL
|| *p
== 0 || *p
== ',')
3052 len
= CONSTRAINT_LEN (c
, p
);
3053 gcc_assert (len
> 0);
3061 if (lookup_constraint (p
) == constraint
)
3069 /* Devirtualize an insn of the form (SET (op) (binop (op) (op))). */
3071 rl78_alloc_physical_registers_op2 (rtx_insn
* insn
)
3079 if (rtx_equal_p (OP (0), OP (1)))
3084 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3085 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3090 OP (1) = transcode_memory_rtx (OP (1), HL
, insn
);
3091 OP (2) = transcode_memory_rtx (OP (2), DE
, insn
);
3094 else if (rtx_equal_p (OP (0), OP (2)))
3096 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3098 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3102 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3103 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3104 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3109 prev
= prev_nonnote_nondebug_insn (insn
);
3110 if (recog_data
.constraints
[1][0] == '%'
3111 && is_virtual_register (OP (1))
3112 && ! is_virtual_register (OP (2))
3113 && ! CONSTANT_P (OP (2)))
3120 /* Make a note of whether (H)L is being used. It matters
3121 because if OP (2) also needs reloading, then we must take
3122 care not to corrupt HL. */
3123 hl_used
= reg_mentioned_p (L
, OP (0)) || reg_mentioned_p (L
, OP (1));
3125 /* If HL is not currently being used and dest == op1 then there are
3126 some possible optimizations available by reloading one of the
3127 operands into HL, before trying to use the accumulator. */
3130 && rtx_equal_p (OP (0), OP (1)))
3132 /* If op0 is a Ws1 type memory address then switching the base
3133 address register to HL might allow us to perform an in-memory
3134 operation. (eg for the INCW instruction).
3136 FIXME: Adding the move into HL is costly if this optimization is not
3137 going to work, so for now, make sure that we know that the new insn will
3138 match the requirements of the addhi3_real pattern. Really we ought to
3139 generate a candidate sequence, test that, and then install it if the
3140 results are good. */
3141 if (satisfies_constraint_Ws1 (OP (0))
3142 && has_constraint (0, CONSTRAINT_Wh1
)
3143 && (satisfies_constraint_K (OP (2)) || satisfies_constraint_L (OP (2))))
3145 rtx base
, index
, addend
, newbase
;
3147 characterize_address (XEXP (OP (0), 0), & base
, & index
, & addend
);
3148 gcc_assert (index
== NULL_RTX
);
3149 gcc_assert (REG_P (base
) && REGNO (base
) == SP_REG
);
3151 /* Ws1 addressing allows an offset of 0, Wh1 addressing requires a non-zero offset. */
3152 if (addend
!= NULL_RTX
)
3154 newbase
= gen_and_emit_move (HL
, base
, insn
, true);
3155 record_content (newbase
, NULL_RTX
);
3156 newbase
= gen_rtx_PLUS (HImode
, newbase
, addend
);
3158 OP (0) = OP (1) = change_address (OP (0), VOIDmode
, newbase
);
3160 /* We do not want to fail here as this means that
3161 we have inserted useless insns into the stream. */
3165 else if (REG_P (OP (0))
3166 && satisfies_constraint_Ws1 (OP (2))
3167 && has_constraint (2, CONSTRAINT_Wh1
))
3169 rtx base
, index
, addend
, newbase
;
3171 characterize_address (XEXP (OP (2), 0), & base
, & index
, & addend
);
3172 gcc_assert (index
== NULL_RTX
);
3173 gcc_assert (REG_P (base
) && REGNO (base
) == SP_REG
);
3175 /* Ws1 addressing allows an offset of 0, Wh1 addressing requires a non-zero offset. */
3176 if (addend
!= NULL_RTX
)
3178 gen_and_emit_move (HL
, base
, insn
, true);
3180 if (REGNO (OP (0)) != X_REG
)
3182 OP (1) = move_to_acc (1, insn
);
3183 OP (0) = move_from_acc (0, insn
);
3186 record_content (HL
, NULL_RTX
);
3187 newbase
= gen_rtx_PLUS (HImode
, HL
, addend
);
3189 OP (2) = change_address (OP (2), VOIDmode
, newbase
);
3191 /* We do not want to fail here as this means that
3192 we have inserted useless insns into the stream. */
3198 OP (0) = move_from_acc (0, insn
);
3200 tmp_id
= get_max_insn_count ();
3203 if (rtx_equal_p (OP (1), OP (2)))
3204 OP (2) = OP (1) = move_to_acc (1, insn
);
3206 OP (1) = move_to_acc (1, insn
);
3210 /* If we omitted the move of OP1 into the accumulator (because
3211 it was already there from a previous insn), then force the
3212 generation of the move instruction now. We know that we
3213 are about to emit a move into HL (or DE) via AX, and hence
3214 our optimization to remove the load of OP1 is no longer valid. */
3215 if (tmp_id
== get_max_insn_count ())
3216 force_into_acc (saved_op1
, insn
);
3218 /* We have to copy op2 to HL (or DE), but that involves AX, which
3219 already has a live value. Emit it before those insns. */
3222 first
= next_nonnote_nondebug_insn (prev
);
3224 for (first
= insn
; prev_nonnote_nondebug_insn (first
); first
= prev_nonnote_nondebug_insn (first
))
3227 OP (2) = hl_used
? move_to_de (2, first
) : move_to_hl (2, first
);
3232 /* Devirtualize an insn of the form SET (PC) (MEM/REG). */
3234 rl78_alloc_physical_registers_ro1 (rtx_insn
* insn
)
3236 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3240 OP (0) = move_to_acc (0, insn
);
3245 /* Devirtualize a compare insn. */
3247 rl78_alloc_physical_registers_cmp (rtx_insn
* insn
)
3251 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
3254 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3255 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3257 /* HI compares have to have OP (1) in AX, but QI
3258 compares do not, so it is worth checking here. */
3261 /* For an HImode compare, OP (1) must always be in AX.
3262 But if OP (1) is a REG (and not AX), then we can avoid
3263 a reload of OP (1) if we reload OP (2) into AX and invert
3266 && REGNO (OP (1)) != AX_REG
3267 && GET_MODE (OP (1)) == HImode
3270 rtx cmp
= XEXP (SET_SRC (PATTERN (insn
)), 0);
3272 OP (2) = move_to_acc (2, insn
);
3274 switch (GET_CODE (cmp
))
3279 case LTU
: cmp
= gen_rtx_GTU (HImode
, OP (2), OP (1)); break;
3280 case GTU
: cmp
= gen_rtx_LTU (HImode
, OP (2), OP (1)); break;
3281 case LEU
: cmp
= gen_rtx_GEU (HImode
, OP (2), OP (1)); break;
3282 case GEU
: cmp
= gen_rtx_LEU (HImode
, OP (2), OP (1)); break;
3295 if (GET_CODE (cmp
) == EQ
|| GET_CODE (cmp
) == NE
)
3296 PATTERN (insn
) = gen_cbranchhi4_real (cmp
, OP (2), OP (1), OP (3));
3298 PATTERN (insn
) = gen_cbranchhi4_real_inverted (cmp
, OP (2), OP (1), OP (3));
3303 /* Surprisingly, gcc can generate a comparison of a register with itself, but this
3304 should be handled by the second alternative of the cbranchhi_real pattern. */
3305 if (rtx_equal_p (OP (1), OP (2)))
3307 OP (1) = OP (2) = BC
;
3311 tmp_id
= get_max_insn_count ();
3314 OP (1) = move_to_acc (1, insn
);
3318 /* If we omitted the move of OP1 into the accumulator (because
3319 it was already there from a previous insn), then force the
3320 generation of the move instruction now. We know that we
3321 are about to emit a move into HL via AX, and hence our
3322 optimization to remove the load of OP1 is no longer valid. */
3323 if (tmp_id
== get_max_insn_count ())
3324 force_into_acc (saved_op1
, insn
);
3326 /* We have to copy op2 to HL, but that involves the acc, which
3327 already has a live value. Emit it before those insns. */
3329 first
= next_nonnote_nondebug_insn (prev
);
3331 for (first
= insn
; prev_nonnote_nondebug_insn (first
); first
= prev_nonnote_nondebug_insn (first
))
3333 OP (2) = move_to_hl (2, first
);
3338 /* Like op2, but AX = A * X. */
3340 rl78_alloc_physical_registers_umul (rtx_insn
* insn
)
3342 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
3347 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3348 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3349 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3353 if (recog_data
.constraints
[1][0] == '%'
3354 && is_virtual_register (OP (1))
3355 && !is_virtual_register (OP (2))
3356 && !CONSTANT_P (OP (2)))
3363 OP (0) = move_from_acc (0, insn
);
3365 tmp_id
= get_max_insn_count ();
3368 if (rtx_equal_p (OP (1), OP (2)))
3370 gcc_assert (GET_MODE (OP (2)) == QImode
);
3371 /* The MULU instruction does not support duplicate arguments
3372 but we know that if we copy OP (2) to X it will do so via
3373 A and thus OP (1) will already be loaded into A. */
3374 OP (2) = move_to_x (2, insn
);
3378 OP (1) = move_to_acc (1, insn
);
3382 /* If we omitted the move of OP1 into the accumulator (because
3383 it was already there from a previous insn), then force the
3384 generation of the move instruction now. We know that we
3385 are about to emit a move into HL (or DE) via AX, and hence
3386 our optimization to remove the load of OP1 is no longer valid. */
3387 if (tmp_id
== get_max_insn_count ())
3388 force_into_acc (saved_op1
, insn
);
3390 /* We have to copy op2 to X, but that involves the acc, which
3391 already has a live value. Emit it before those insns. */
3394 first
= next_nonnote_nondebug_insn (prev
);
3396 for (first
= insn
; prev_nonnote_nondebug_insn (first
); first
= prev_nonnote_nondebug_insn (first
))
3398 OP (2) = move_to_x (2, first
);
3404 rl78_alloc_address_registers_macax (rtx_insn
* insn
)
3407 bool replace_in_op0
= false;
3408 bool replace_in_op1
= false;
3412 /* Two different MEMs are not allowed. */
3414 for (op
= 2; op
>= 0; op
--)
3416 if (MEM_P (OP (op
)))
3418 if (op
== 0 && replace_in_op0
)
3420 if (op
== 1 && replace_in_op1
)
3426 /* If we replace a MEM, make sure that we replace it for all
3427 occurrences of the same MEM in the insn. */
3428 replace_in_op0
= (op
> 0 && rtx_equal_p (OP (op
), OP (0)));
3429 replace_in_op1
= (op
> 1 && rtx_equal_p (OP (op
), OP (1)));
3431 OP (op
) = transcode_memory_rtx (OP (op
), HL
, insn
);
3434 && ((GET_CODE (XEXP (OP (op
), 0)) == REG
3435 && REGNO (XEXP (OP (op
), 0)) == SP_REG
)
3436 || (GET_CODE (XEXP (OP (op
), 0)) == PLUS
3437 && REGNO (XEXP (XEXP (OP (op
), 0), 0)) == SP_REG
)))
3439 emit_insn_before (gen_movhi (HL
, gen_rtx_REG (HImode
, SP_REG
)), insn
);
3440 OP (op
) = replace_rtx (OP (op
), gen_rtx_REG (HImode
, SP_REG
), HL
);
3448 OP (op
) = transcode_memory_rtx (OP (op
), DE
, insn
);
3451 OP (op
) = transcode_memory_rtx (OP (op
), BC
, insn
);
3462 rl78_alloc_address_registers_div (rtx_insn
* insn
)
3467 /* Scan all insns and devirtualize them. */
3469 rl78_alloc_physical_registers (void)
3471 /* During most of the compile, gcc is dealing with virtual
3472 registers. At this point, we need to assign physical registers
3473 to the vitual ones, and copy in/out as needed. */
3475 rtx_insn
*insn
, *curr
;
3476 enum attr_valloc valloc_method
;
3478 for (insn
= get_insns (); insn
; insn
= curr
)
3482 curr
= next_nonnote_nondebug_insn (insn
);
3485 && (GET_CODE (PATTERN (insn
)) == SET
3486 || GET_CODE (PATTERN (insn
)) == CALL
)
3487 && INSN_CODE (insn
) == -1)
3489 if (GET_CODE (SET_SRC (PATTERN (insn
))) == ASM_OPERANDS
)
3491 i
= recog (PATTERN (insn
), insn
, 0);
3497 INSN_CODE (insn
) = i
;
3501 cfun
->machine
->virt_insns_ok
= 0;
3502 cfun
->machine
->real_insns_ok
= 1;
3504 clear_content_memory ();
3506 for (insn
= get_insns (); insn
; insn
= curr
)
3510 curr
= insn
? next_nonnote_nondebug_insn (insn
) : NULL
;
3515 clear_content_memory ();
3521 fprintf (dump_file
, "Converting insn %d\n", INSN_UID (insn
));
3523 pattern
= PATTERN (insn
);
3524 if (GET_CODE (pattern
) == PARALLEL
)
3525 pattern
= XVECEXP (pattern
, 0, 0);
3526 if (JUMP_P (insn
) || CALL_P (insn
) || GET_CODE (pattern
) == CALL
)
3527 clear_content_memory ();
3528 if (GET_CODE (pattern
) != SET
3529 && GET_CODE (pattern
) != CALL
)
3531 if (GET_CODE (pattern
) == SET
3532 && GET_CODE (SET_SRC (pattern
)) == ASM_OPERANDS
)
3535 valloc_method
= get_attr_valloc (insn
);
3537 PATTERN (insn
) = copy_rtx_if_shared (PATTERN (insn
));
3539 if (valloc_method
== VALLOC_MACAX
)
3541 record_content (AX
, NULL_RTX
);
3542 record_content (BC
, NULL_RTX
);
3543 record_content (DE
, NULL_RTX
);
3545 else if (valloc_method
== VALLOC_DIVHI
)
3547 record_content (AX
, NULL_RTX
);
3548 record_content (BC
, NULL_RTX
);
3550 else if (valloc_method
== VALLOC_DIVSI
)
3552 record_content (AX
, NULL_RTX
);
3553 record_content (BC
, NULL_RTX
);
3554 record_content (DE
, NULL_RTX
);
3555 record_content (HL
, NULL_RTX
);
3558 if (insn_ok_now (insn
))
3561 INSN_CODE (insn
) = -1;
3563 if (RTX_FRAME_RELATED_P (insn
))
3564 virt_insn_was_frame
= 1;
3566 virt_insn_was_frame
= 0;
3568 switch (valloc_method
)
3571 rl78_alloc_physical_registers_op1 (insn
);
3574 rl78_alloc_physical_registers_op2 (insn
);
3577 rl78_alloc_physical_registers_ro1 (insn
);
3580 rl78_alloc_physical_registers_cmp (insn
);
3583 rl78_alloc_physical_registers_umul (insn
);
3584 record_content (AX
, NULL_RTX
);
3587 /* Macro that clobbers AX. */
3588 rl78_alloc_address_registers_macax (insn
);
3589 record_content (AX
, NULL_RTX
);
3590 record_content (BC
, NULL_RTX
);
3591 record_content (DE
, NULL_RTX
);
3594 rl78_alloc_address_registers_div (insn
);
3595 record_content (AX
, NULL_RTX
);
3596 record_content (BC
, NULL_RTX
);
3597 record_content (DE
, NULL_RTX
);
3598 record_content (HL
, NULL_RTX
);
3601 rl78_alloc_address_registers_div (insn
);
3602 record_content (AX
, NULL_RTX
);
3603 record_content (BC
, NULL_RTX
);
3609 if (JUMP_P (insn
) || CALL_P (insn
) || GET_CODE (pattern
) == CALL
)
3610 clear_content_memory ();
3612 process_postponed_content_update ();
3616 fprintf (stderr
, "\033[0m");
3620 /* Add REG_DEAD notes using DEAD[reg] for rtx S which is part of INSN.
3621 This function scans for uses of registers; the last use (i.e. first
3622 encounter when scanning backwards) triggers a REG_DEAD note if the
3623 reg was previously in DEAD[]. */
3625 rl78_note_reg_uses (char *dead
, rtx s
, rtx insn
)
3634 code
= GET_CODE (s
);
3638 /* Compare registers by number. */
3643 fprintf (dump_file
, "note use reg %d size %d on insn %d\n",
3644 r
, GET_MODE_SIZE (GET_MODE (s
)), INSN_UID (insn
));
3645 print_rtl_single (dump_file
, s
);
3648 add_reg_note (insn
, REG_DEAD
, gen_rtx_REG (GET_MODE (s
), r
));
3649 for (i
= 0; i
< GET_MODE_SIZE (GET_MODE (s
)); i
++)
3653 /* These codes have no constituent expressions
3664 /* These are kept unique for a given value. */
3671 fmt
= GET_RTX_FORMAT (code
);
3673 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3678 for (j
= XVECLEN (s
, i
) - 1; j
>= 0; j
--)
3679 rl78_note_reg_uses (dead
, XVECEXP (s
, i
, j
), insn
);
3681 else if (fmt
[i
] == 'e')
3682 rl78_note_reg_uses (dead
, XEXP (s
, i
), insn
);
3686 /* Like the previous function, but scan for SETs instead. */
3688 rl78_note_reg_set (char *dead
, rtx d
, rtx insn
)
3692 if (GET_CODE (d
) == MEM
)
3693 rl78_note_reg_uses (dead
, XEXP (d
, 0), insn
);
3695 if (GET_CODE (d
) != REG
)
3700 add_reg_note (insn
, REG_UNUSED
, gen_rtx_REG (GET_MODE (d
), r
));
3702 fprintf (dump_file
, "note set reg %d size %d\n", r
, GET_MODE_SIZE (GET_MODE (d
)));
3703 for (i
= 0; i
< GET_MODE_SIZE (GET_MODE (d
)); i
++)
3707 /* This is a rather crude register death pass. Death status is reset
3708 at every jump or call insn. */
3710 rl78_calculate_death_notes (void)
3712 char dead
[FIRST_PSEUDO_REGISTER
];
3716 memset (dead
, 0, sizeof (dead
));
3718 for (insn
= get_last_insn ();
3720 insn
= prev_nonnote_nondebug_insn (insn
))
3724 fprintf (dump_file
, "\n--------------------------------------------------");
3725 fprintf (dump_file
, "\nDead:");
3726 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3728 fprintf (dump_file
, " %s", reg_names
[i
]);
3729 fprintf (dump_file
, "\n");
3730 print_rtl_single (dump_file
, insn
);
3733 switch (GET_CODE (insn
))
3737 if (GET_CODE (p
) == PARALLEL
)
3739 rtx q
= XVECEXP (p
, 0 ,1);
3741 /* This happens with the DIV patterns. */
3742 if (GET_CODE (q
) == SET
)
3746 rl78_note_reg_set (dead
, d
, insn
);
3747 rl78_note_reg_uses (dead
, s
, insn
);
3750 p
= XVECEXP (p
, 0, 0);
3753 switch (GET_CODE (p
))
3758 rl78_note_reg_set (dead
, d
, insn
);
3759 rl78_note_reg_uses (dead
, s
, insn
);
3763 rl78_note_reg_uses (dead
, p
, insn
);
3772 if (INSN_CODE (insn
) == CODE_FOR_rl78_return
)
3774 memset (dead
, 1, sizeof (dead
));
3775 /* We expect a USE just prior to this, which will mark
3776 the actual return registers. The USE will have a
3777 death note, but we aren't going to be modifying it
3782 memset (dead
, 0, sizeof (dead
));
3789 print_rtl_single (dump_file
, insn
);
3793 /* Helper function to reset the origins in RP and the age in AGE for
3796 reset_origins (int *rp
, int *age
)
3799 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3807 set_origin (rtx pat
, rtx_insn
* insn
, int * origins
, int * age
)
3809 rtx src
= SET_SRC (pat
);
3810 rtx dest
= SET_DEST (pat
);
3811 int mb
= GET_MODE_SIZE (GET_MODE (dest
));
3814 if (GET_CODE (dest
) == REG
)
3816 int dr
= REGNO (dest
);
3818 if (GET_CODE (src
) == REG
)
3820 int sr
= REGNO (src
);
3822 int best_age
, best_reg
;
3824 /* See if the copy is not needed. */
3825 for (i
= 0; i
< mb
; i
++)
3826 if (origins
[dr
+ i
] != origins
[sr
+ i
])
3832 fprintf (dump_file
, "deleting because dest already has correct value\n");
3837 if (dr
< 8 || sr
>= 8)
3844 /* See if the copy can be made from another
3845 bank 0 register instead, instead of the
3846 virtual src register. */
3847 for (ar
= 0; ar
< 8; ar
+= mb
)
3851 for (i
= 0; i
< mb
; i
++)
3852 if (origins
[ar
+ i
] != origins
[sr
+ i
])
3855 /* The chip has some reg-reg move limitations. */
3856 if (mb
== 1 && dr
> 3)
3861 if (best_age
== -1 || best_age
> age
[sr
+ i
])
3863 best_age
= age
[sr
+ i
];
3871 /* FIXME: copy debug info too. */
3872 SET_SRC (pat
) = gen_rtx_REG (GET_MODE (src
), best_reg
);
3877 for (i
= 0; i
< mb
; i
++)
3879 origins
[dr
+ i
] = origins
[sr
+ i
];
3880 age
[dr
+ i
] = age
[sr
+ i
] + 1;
3885 /* The destination is computed, its origin is itself. */
3887 fprintf (dump_file
, "resetting origin of r%d for %d byte%s\n",
3888 dr
, mb
, mb
== 1 ? "" : "s");
3890 for (i
= 0; i
< mb
; i
++)
3892 origins
[dr
+ i
] = dr
+ i
;
3897 /* Any registers marked with that reg as an origin are reset. */
3898 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3899 if (origins
[i
] >= dr
&& origins
[i
] < dr
+ mb
)
3906 /* Special case - our MUL patterns uses AX and sometimes BC. */
3907 if (get_attr_valloc (insn
) == VALLOC_MACAX
)
3910 fprintf (dump_file
, "Resetting origin of AX/BC for MUL pattern.\n");
3912 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3913 if (i
<= 3 || origins
[i
] <= 3)
3919 else if (get_attr_valloc (insn
) == VALLOC_DIVHI
)
3922 fprintf (dump_file
, "Resetting origin of AX/DE for DIVHI pattern.\n");
3924 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3929 || origins
[i
] == A_REG
3930 || origins
[i
] == X_REG
3931 || origins
[i
] == D_REG
3932 || origins
[i
] == E_REG
)
3938 else if (get_attr_valloc (insn
) == VALLOC_DIVSI
)
3941 fprintf (dump_file
, "Resetting origin of AX/BC/DE/HL for DIVSI pattern.\n");
3943 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3944 if (i
<= 7 || origins
[i
] <= 7)
3951 if (GET_CODE (src
) == ASHIFT
3952 || GET_CODE (src
) == ASHIFTRT
3953 || GET_CODE (src
) == LSHIFTRT
)
3955 rtx count
= XEXP (src
, 1);
3957 if (GET_CODE (count
) == REG
)
3959 /* Special case - our pattern clobbers the count register. */
3960 int r
= REGNO (count
);
3963 fprintf (dump_file
, "Resetting origin of r%d for shift.\n", r
);
3965 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3966 if (i
== r
|| origins
[i
] == r
)
3975 /* The idea behind this optimization is to look for cases where we
3976 move data from A to B to C, and instead move from A to B, and A to
3977 C. If B is a virtual register or memory, this is a big win on its
3978 own. If B turns out to be unneeded after this, it's a bigger win.
3979 For each register, we try to determine where it's value originally
3980 came from, if it's propogated purely through moves (and not
3981 computes). The ORIGINS[] array has the regno for the "origin" of
3982 the value in the [regno] it's indexed by. */
3984 rl78_propogate_register_origins (void)
3986 int origins
[FIRST_PSEUDO_REGISTER
];
3987 int age
[FIRST_PSEUDO_REGISTER
];
3989 rtx_insn
*insn
, *ninsn
= NULL
;
3992 reset_origins (origins
, age
);
3994 for (insn
= get_insns (); insn
; insn
= ninsn
)
3996 ninsn
= next_nonnote_nondebug_insn (insn
);
4000 fprintf (dump_file
, "\n");
4001 fprintf (dump_file
, "Origins:");
4002 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4003 if (origins
[i
] != i
)
4004 fprintf (dump_file
, " r%d=r%d", i
, origins
[i
]);
4005 fprintf (dump_file
, "\n");
4006 print_rtl_single (dump_file
, insn
);
4009 switch (GET_CODE (insn
))
4015 reset_origins (origins
, age
);
4022 pat
= PATTERN (insn
);
4024 if (GET_CODE (pat
) == PARALLEL
)
4026 rtx clobber
= XVECEXP (pat
, 0, 1);
4027 pat
= XVECEXP (pat
, 0, 0);
4028 if (GET_CODE (clobber
) == CLOBBER
4029 && GET_CODE (XEXP (clobber
, 0)) == REG
)
4031 int cr
= REGNO (XEXP (clobber
, 0));
4032 int mb
= GET_MODE_SIZE (GET_MODE (XEXP (clobber
, 0)));
4034 fprintf (dump_file
, "reset origins of %d regs at %d\n", mb
, cr
);
4035 for (i
= 0; i
< mb
; i
++)
4037 origins
[cr
+ i
] = cr
+ i
;
4041 /* This happens with the DIV patterns. */
4042 else if (GET_CODE (clobber
) == SET
)
4044 set_origin (clobber
, insn
, origins
, age
);
4050 if (GET_CODE (pat
) == SET
)
4052 set_origin (pat
, insn
, origins
, age
);
4054 else if (GET_CODE (pat
) == CLOBBER
4055 && GET_CODE (XEXP (pat
, 0)) == REG
)
4057 if (REG_P (XEXP (pat
, 0)))
4059 unsigned int reg
= REGNO (XEXP (pat
, 0));
4069 /* Remove any SETs where the destination is unneeded. */
4071 rl78_remove_unused_sets (void)
4073 rtx_insn
*insn
, *ninsn
= NULL
;
4076 for (insn
= get_insns (); insn
; insn
= ninsn
)
4078 ninsn
= next_nonnote_nondebug_insn (insn
);
4080 rtx set
= single_set (insn
);
4084 dest
= SET_DEST (set
);
4086 if (GET_CODE (dest
) != REG
|| REGNO (dest
) > 23)
4089 if (find_regno_note (insn
, REG_UNUSED
, REGNO (dest
)))
4092 fprintf (dump_file
, "deleting because the set register is never used.\n");
4098 /* This is the top of the devritualization pass. */
4102 /* split2 only happens when optimizing, but we need all movSIs to be
4107 rl78_alloc_physical_registers ();
4111 fprintf (dump_file
, "\n================DEVIRT:=AFTER=ALLOC=PHYSICAL=REGISTERS================\n");
4112 print_rtl_with_bb (dump_file
, get_insns (), 0);
4115 rl78_propogate_register_origins ();
4116 rl78_calculate_death_notes ();
4120 fprintf (dump_file
, "\n================DEVIRT:=AFTER=PROPOGATION=============================\n");
4121 print_rtl_with_bb (dump_file
, get_insns (), 0);
4122 fprintf (dump_file
, "\n======================================================================\n");
4125 rl78_remove_unused_sets ();
4127 /* The code after devirtualizing has changed so much that at this point
4128 we might as well just rescan everything. Note that
4129 df_rescan_all_insns is not going to help here because it does not
4130 touch the artificial uses and defs. */
4131 df_finish_pass (true);
4133 df_live_add_problem ();
4134 df_scan_alloc (NULL
);
4141 #undef TARGET_RETURN_IN_MEMORY
4142 #define TARGET_RETURN_IN_MEMORY rl78_return_in_memory
4145 rl78_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
4147 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
4148 return (size
== -1 || size
> 8);
4152 #undef TARGET_RTX_COSTS
4153 #define TARGET_RTX_COSTS rl78_rtx_costs
4156 rl78_rtx_costs (rtx x
,
4158 int outer_code ATTRIBUTE_UNUSED
,
4159 int opno ATTRIBUTE_UNUSED
,
4161 bool speed ATTRIBUTE_UNUSED
)
4163 int code
= GET_CODE (x
);
4165 if (code
== IF_THEN_ELSE
)
4167 *total
= COSTS_N_INSNS (10);
4177 *total
= COSTS_N_INSNS (14);
4178 else if (RL78_MUL_G13
)
4179 *total
= COSTS_N_INSNS (29);
4181 *total
= COSTS_N_INSNS (500);
4184 *total
= COSTS_N_INSNS (8);
4189 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4191 switch (INTVAL (XEXP (x
, 1)))
4193 case 0: *total
= COSTS_N_INSNS (0); break;
4194 case 1: *total
= COSTS_N_INSNS (6); break;
4195 case 2: case 3: case 4: case 5: case 6: case 7:
4196 *total
= COSTS_N_INSNS (10); break;
4197 case 8: *total
= COSTS_N_INSNS (6); break;
4198 case 9: case 10: case 11: case 12: case 13: case 14: case 15:
4199 *total
= COSTS_N_INSNS (10); break;
4200 case 16: *total
= COSTS_N_INSNS (3); break;
4201 case 17: case 18: case 19: case 20: case 21: case 22: case 23:
4202 *total
= COSTS_N_INSNS (4); break;
4203 case 24: *total
= COSTS_N_INSNS (4); break;
4204 case 25: case 26: case 27: case 28: case 29: case 30: case 31:
4205 *total
= COSTS_N_INSNS (5); break;
4209 *total
= COSTS_N_INSNS (10+4*16);
4217 static GTY(()) section
* saddr_section
;
4218 static GTY(()) section
* frodata_section
;
4221 rl78_saddr_p (rtx x
)
4227 if (GET_CODE (x
) == PLUS
)
4229 if (GET_CODE (x
) != SYMBOL_REF
)
4233 if (memcmp (c
, "@s.", 3) == 0)
4244 if (GET_CODE (x
) != CONST_INT
)
4247 if ((INTVAL (x
) & 0xFF00) != 0xFF00)
4253 #undef TARGET_STRIP_NAME_ENCODING
4254 #define TARGET_STRIP_NAME_ENCODING rl78_strip_name_encoding
4257 rl78_strip_name_encoding (const char * sym
)
4263 else if (*sym
== '@' && sym
[2] == '.')
4270 /* Like rl78_strip_name_encoding, but does not strip leading asterisks. This
4271 is important if the stripped name is going to be passed to assemble_name()
4272 as that handles asterisk prefixed names in a special manner. */
4275 rl78_strip_nonasm_name_encoding (const char * sym
)
4279 if (*sym
== '@' && sym
[2] == '.')
4288 rl78_attrlist_to_encoding (tree list
, tree decl ATTRIBUTE_UNUSED
)
4292 if (is_attribute_p ("saddr", TREE_PURPOSE (list
)))
4294 list
= TREE_CHAIN (list
);
4300 #define RL78_ATTRIBUTES(decl) \
4301 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
4302 : DECL_ATTRIBUTES (decl) \
4303 ? (DECL_ATTRIBUTES (decl)) \
4304 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
4306 #undef TARGET_ENCODE_SECTION_INFO
4307 #define TARGET_ENCODE_SECTION_INFO rl78_encode_section_info
4310 rl78_encode_section_info (tree decl
, rtx rtl
, int first
)
4313 const char * oldname
;
4318 tree rl78_attributes
;
4323 rtlname
= XEXP (rtl
, 0);
4325 if (GET_CODE (rtlname
) == SYMBOL_REF
)
4326 oldname
= XSTR (rtlname
, 0);
4327 else if (GET_CODE (rtlname
) == MEM
4328 && GET_CODE (XEXP (rtlname
, 0)) == SYMBOL_REF
)
4329 oldname
= XSTR (XEXP (rtlname
, 0), 0);
4333 type
= TREE_TYPE (decl
);
4334 if (type
== error_mark_node
)
4336 if (! DECL_P (decl
))
4338 rl78_attributes
= RL78_ATTRIBUTES (decl
);
4340 encoding
= rl78_attrlist_to_encoding (rl78_attributes
, decl
);
4344 newname
= (char *) alloca (strlen (oldname
) + 4);
4345 sprintf (newname
, "@%c.%s", encoding
, oldname
);
4346 idp
= get_identifier (newname
);
4348 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
4349 SYMBOL_REF_WEAK (XEXP (rtl
, 0)) = DECL_WEAK (decl
);
4350 SET_SYMBOL_REF_DECL (XEXP (rtl
, 0), decl
);
4354 #undef TARGET_ASM_INIT_SECTIONS
4355 #define TARGET_ASM_INIT_SECTIONS rl78_asm_init_sections
4358 rl78_asm_init_sections (void)
4361 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
4362 "\t.section .saddr,\"aw\",@progbits");
4364 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
4365 "\t.section .frodata,\"aw\",@progbits");
4368 #undef TARGET_ASM_SELECT_SECTION
4369 #define TARGET_ASM_SELECT_SECTION rl78_select_section
4372 rl78_select_section (tree decl
,
4374 unsigned HOST_WIDE_INT align
)
4378 switch (TREE_CODE (decl
))
4381 if (!TREE_READONLY (decl
)
4382 || TREE_SIDE_EFFECTS (decl
)
4383 || !DECL_INITIAL (decl
)
4384 || (DECL_INITIAL (decl
) != error_mark_node
4385 && !TREE_CONSTANT (DECL_INITIAL (decl
))))
4389 if (! TREE_CONSTANT (decl
))
4397 if (TREE_CODE (decl
) == VAR_DECL
)
4399 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
4401 if (name
[0] == '@' && name
[2] == '.')
4405 return saddr_section
;
4408 if (TYPE_ADDR_SPACE (TREE_TYPE (decl
)) == ADDR_SPACE_FAR
4411 return frodata_section
;
4416 return TARGET_ES0
? frodata_section
: readonly_data_section
;
4418 switch (categorize_decl_for_section (decl
, reloc
))
4420 case SECCAT_TEXT
: return text_section
;
4421 case SECCAT_DATA
: return data_section
;
4422 case SECCAT_BSS
: return bss_section
;
4423 case SECCAT_RODATA
: return TARGET_ES0
? frodata_section
: readonly_data_section
;
4425 return default_select_section (decl
, reloc
, align
);
4430 rl78_output_labelref (FILE *file
, const char *str
)
4434 str2
= targetm
.strip_name_encoding (str
);
4436 fputs (user_label_prefix
, file
);
4441 rl78_output_aligned_common (FILE *stream
,
4442 tree decl ATTRIBUTE_UNUSED
,
4444 int size
, int align
, int global
)
4446 /* We intentionally don't use rl78_section_tag() here. */
4447 if (name
[0] == '@' && name
[2] == '.')
4449 const char *sec
= 0;
4453 switch_to_section (saddr_section
);
4462 while (align
> BITS_PER_UNIT
)
4467 name2
= targetm
.strip_name_encoding (name
);
4469 fprintf (stream
, "\t.global\t_%s\n", name2
);
4470 fprintf (stream
, "\t.p2align %d\n", p2align
);
4471 fprintf (stream
, "\t.type\t_%s,@object\n", name2
);
4472 fprintf (stream
, "\t.size\t_%s,%d\n", name2
, size
);
4473 fprintf (stream
, "_%s:\n\t.zero\t%d\n", name2
, size
);
4480 fprintf (stream
, "\t.local\t");
4481 assemble_name (stream
, name
);
4482 fprintf (stream
, "\n");
4484 fprintf (stream
, "\t.comm\t");
4485 assemble_name (stream
, name
);
4486 fprintf (stream
, ",%u,%u\n", size
, align
/ BITS_PER_UNIT
);
4489 #undef TARGET_INSERT_ATTRIBUTES
4490 #define TARGET_INSERT_ATTRIBUTES rl78_insert_attributes
4493 rl78_insert_attributes (tree decl
, tree
*attributes ATTRIBUTE_UNUSED
)
4496 && TREE_CODE (decl
) == VAR_DECL
4497 && TREE_READONLY (decl
)
4498 && TREE_ADDRESSABLE (decl
)
4499 && TYPE_ADDR_SPACE (TREE_TYPE (decl
)) == ADDR_SPACE_GENERIC
)
4501 tree type
= TREE_TYPE (decl
);
4502 tree attr
= TYPE_ATTRIBUTES (type
);
4503 int q
= TYPE_QUALS_NO_ADDR_SPACE (type
) | ENCODE_QUAL_ADDR_SPACE (ADDR_SPACE_FAR
);
4505 TREE_TYPE (decl
) = build_type_attribute_qual_variant (type
, attr
, q
);
4509 #undef TARGET_ASM_INTEGER
4510 #define TARGET_ASM_INTEGER rl78_asm_out_integer
4513 rl78_asm_out_integer (rtx x
, unsigned int size
, int aligned_p
)
4515 if (default_assemble_integer (x
, size
, aligned_p
))
4520 assemble_integer_with_op (".long\t", x
);
4527 #undef TARGET_UNWIND_WORD_MODE
4528 #define TARGET_UNWIND_WORD_MODE rl78_unwind_word_mode
4531 rl78_unwind_word_mode (void)
4536 #ifndef USE_COLLECT2
4537 #undef TARGET_ASM_CONSTRUCTOR
4538 #define TARGET_ASM_CONSTRUCTOR rl78_asm_constructor
4539 #undef TARGET_ASM_DESTRUCTOR
4540 #define TARGET_ASM_DESTRUCTOR rl78_asm_destructor
4543 rl78_asm_ctor_dtor (rtx symbol
, int priority
, bool is_ctor
)
4547 if (priority
!= DEFAULT_INIT_PRIORITY
)
4549 /* This section of the function is based upon code copied
4550 from: gcc/varasm.c:get_cdtor_priority_section(). */
4553 sprintf (buf
, "%s.%.5u", is_ctor
? ".ctors" : ".dtors",
4554 MAX_INIT_PRIORITY
- priority
);
4555 sec
= get_section (buf
, 0, NULL
);
4558 sec
= is_ctor
? ctors_section
: dtors_section
;
4560 assemble_addr_to_section (symbol
, sec
);
4564 rl78_asm_constructor (rtx symbol
, int priority
)
4566 rl78_asm_ctor_dtor (symbol
, priority
, true);
4570 rl78_asm_destructor (rtx symbol
, int priority
)
4572 rl78_asm_ctor_dtor (symbol
, priority
, false);
4574 #endif /* ! USE_COLLECT2 */
4576 /* Scan backwards through the insn chain looking to see if the flags
4577 have been set for a comparison of OP against OPERAND. Start with
4578 the insn *before* the current insn. */
4581 rl78_flags_already_set (rtx op
, rtx operand
)
4583 /* We only track the Z flag. */
4584 if (GET_CODE (op
) != EQ
&& GET_CODE (op
) != NE
)
4587 /* This should not happen, but let's be paranoid. */
4588 if (current_output_insn
== NULL_RTX
)
4594 for (insn
= prev_nonnote_nondebug_insn (current_output_insn
);
4596 insn
= prev_nonnote_nondebug_insn (insn
))
4601 if (! INSN_P (insn
))
4604 /* Make sure that the insn can be recognized. */
4605 if (recog_memoized (insn
) == -1)
4608 enum attr_update_Z updated
= get_attr_update_Z (insn
);
4610 rtx set
= single_set (insn
);
4611 bool must_break
= (set
!= NULL_RTX
&& rtx_equal_p (operand
, SET_DEST (set
)));
4617 case UPDATE_Z_CLOBBER
:
4620 case UPDATE_Z_UPDATE_Z
:
4632 /* We have to re-recognize the current insn as the call(s) to
4633 get_attr_update_Z() above will have overwritten the recog_data cache. */
4634 recog_memoized (current_output_insn
);
4635 cleanup_subreg_operands (current_output_insn
);
4636 constrain_operands_cached (current_output_insn
, 1);
4641 #undef TARGET_PREFERRED_RELOAD_CLASS
4642 #define TARGET_PREFERRED_RELOAD_CLASS rl78_preferred_reload_class
4645 rl78_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
4647 if (rclass
== NO_REGS
)
4654 struct gcc_target targetm
= TARGET_INITIALIZER
;
4656 #include "gt-rl78.h"