1 /* Subroutines used for code generation on Renesas RL78 processors.
2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
33 #include "stringpool.h"
38 #include "diagnostic-core.h"
40 #include "stor-layout.h"
43 #include "insn-attr.h"
48 #include "langhooks.h"
49 #include "tree-pass.h"
51 #include "tm-constrs.h" /* for satisfies_constraint_*(). */
54 /* This file should be included last. */
55 #include "target-def.h"
57 static inline bool is_interrupt_func (const_tree decl
);
58 static inline bool is_brk_interrupt_func (const_tree decl
);
59 static void rl78_reorg (void);
60 static const char *rl78_strip_name_encoding (const char *);
61 static const char *rl78_strip_nonasm_name_encoding (const char *);
62 static section
* rl78_select_section (tree
, int, unsigned HOST_WIDE_INT
);
65 /* Debugging statements are tagged with DEBUG0 only so that they can
66 be easily enabled individually, by replacing the '0' with '1' as
71 /* REGISTER_NAMES has the names for individual 8-bit registers, but
72 these have the names we need to use when referring to 16-bit
74 static const char * const word_regnames
[] =
76 "ax", "AX", "bc", "BC", "de", "DE", "hl", "HL",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
79 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
80 "sp", "ap", "psw", "es", "cs"
83 /* used by rl78_addsi3_internal for formatting insns output */
84 static char fmt_buffer
[1024];
86 /* Structure for G13 MDUC registers. */
90 enum machine_mode mode
;
93 struct mduc_reg_type mduc_regs
[] =
103 struct GTY(()) machine_function
105 /* If set, the rest of the fields have been computed. */
107 /* Which register pairs need to be pushed in the prologue. */
108 int need_to_push
[FIRST_PSEUDO_REGISTER
/ 2];
110 /* These fields describe the frame layout... */
112 /* 4 bytes for saved PC */
115 int framesize_locals
;
116 int framesize_outgoing
;
120 /* If set, recog is allowed to match against the "real" patterns. */
122 /* If set, recog is allowed to match against the "virtual" patterns. */
124 /* Set if the current function needs to clean up any trampolines. */
125 int trampolines_used
;
126 /* True if the ES register is used and hence
127 needs to be saved inside interrupt handlers. */
131 /* This is our init_machine_status, as set in
132 rl78_option_override. */
133 static struct machine_function
*
134 rl78_init_machine_status (void)
136 struct machine_function
*m
;
138 m
= ggc_cleared_alloc
<machine_function
> ();
139 m
->virt_insns_ok
= 1;
144 /* This pass converts virtual instructions using virtual registers, to
145 real instructions using real registers. Rather than run it as
146 reorg, we reschedule it before vartrack to help with debugging. */
149 const pass_data pass_data_rl78_devirt
=
153 OPTGROUP_NONE
, /* optinfo_flags */
154 TV_MACH_DEP
, /* tv_id */
155 0, /* properties_required */
156 0, /* properties_provided */
157 0, /* properties_destroyed */
158 0, /* todo_flags_start */
159 0, /* todo_flags_finish */
162 class pass_rl78_devirt
: public rtl_opt_pass
165 pass_rl78_devirt (gcc::context
*ctxt
)
166 : rtl_opt_pass (pass_data_rl78_devirt
, ctxt
)
170 /* opt_pass methods: */
171 virtual unsigned int execute (function
*)
180 make_pass_rl78_devirt (gcc::context
*ctxt
)
182 return new pass_rl78_devirt (ctxt
);
185 /* Redundant move elimination pass. Must be run after the basic block
186 reordering pass for the best effect. */
189 move_elim_pass (void)
191 rtx_insn
*insn
, *ninsn
;
194 for (insn
= get_insns (); insn
; insn
= ninsn
)
198 ninsn
= next_nonnote_nondebug_insn (insn
);
200 if ((set
= single_set (insn
)) == NULL_RTX
)
206 /* If we have two SET insns in a row (without anything
207 between them) and the source of the second one is the
208 destination of the first one, and vice versa, then we
209 can eliminate the second SET. */
211 && rtx_equal_p (SET_DEST (prev
), SET_SRC (set
))
212 && rtx_equal_p (SET_DEST (set
), SET_SRC (prev
))
213 /* ... and none of the operands are volatile. */
214 && ! volatile_refs_p (SET_SRC (prev
))
215 && ! volatile_refs_p (SET_DEST (prev
))
216 && ! volatile_refs_p (SET_SRC (set
))
217 && ! volatile_refs_p (SET_DEST (set
)))
220 fprintf (dump_file
, " Delete insn %d because it is redundant\n",
231 print_rtl_with_bb (dump_file
, get_insns (), TDF_NONE
);
238 const pass_data pass_data_rl78_move_elim
=
241 "move_elim", /* name */
242 OPTGROUP_NONE
, /* optinfo_flags */
243 TV_MACH_DEP
, /* tv_id */
244 0, /* properties_required */
245 0, /* properties_provided */
246 0, /* properties_destroyed */
247 0, /* todo_flags_start */
248 0, /* todo_flags_finish */
251 class pass_rl78_move_elim
: public rtl_opt_pass
254 pass_rl78_move_elim (gcc::context
*ctxt
)
255 : rtl_opt_pass (pass_data_rl78_move_elim
, ctxt
)
259 /* opt_pass methods: */
260 virtual unsigned int execute (function
*) { return move_elim_pass (); }
265 make_pass_rl78_move_elim (gcc::context
*ctxt
)
267 return new pass_rl78_move_elim (ctxt
);
270 #undef TARGET_ASM_FILE_START
271 #define TARGET_ASM_FILE_START rl78_asm_file_start
274 rl78_asm_file_start (void)
280 /* The memory used is 0xffec8 to 0xffedf; real registers are in
281 0xffee0 to 0xffee7. */
282 for (i
= 8; i
< 32; i
++)
283 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", i
, 0xffec0 + i
);
287 for (i
= 0; i
< 8; i
++)
289 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", 8 + i
, 0xffef0 + i
);
290 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", 16 + i
, 0xffee8 + i
);
291 fprintf (asm_out_file
, "r%d\t=\t0x%x\n", 24 + i
, 0xffee0 + i
);
295 opt_pass
*rl78_devirt_pass
= make_pass_rl78_devirt (g
);
296 struct register_pass_info rl78_devirt_info
=
301 PASS_POS_INSERT_BEFORE
304 opt_pass
*rl78_move_elim_pass
= make_pass_rl78_move_elim (g
);
305 struct register_pass_info rl78_move_elim_info
=
310 PASS_POS_INSERT_AFTER
313 register_pass (& rl78_devirt_info
);
314 register_pass (& rl78_move_elim_info
);
318 rl78_output_symbol_ref (FILE * file
, rtx sym
)
320 tree type
= SYMBOL_REF_DECL (sym
);
321 const char *str
= XSTR (sym
, 0);
325 fputs (str
+ 1, file
);
329 str
= rl78_strip_nonasm_name_encoding (str
);
330 if (type
&& TREE_CODE (type
) == FUNCTION_DECL
)
332 fprintf (file
, "%%code(");
333 assemble_name (file
, str
);
337 assemble_name (file
, str
);
341 #undef TARGET_OPTION_OVERRIDE
342 #define TARGET_OPTION_OVERRIDE rl78_option_override
344 #define MUST_SAVE_MDUC_REGISTERS \
345 (TARGET_SAVE_MDUC_REGISTERS \
346 && (is_interrupt_func (NULL_TREE)) && RL78_MUL_G13)
349 rl78_option_override (void)
351 flag_omit_frame_pointer
= 1;
352 flag_no_function_cse
= 1;
353 flag_split_wide_types
= 0;
355 init_machine_status
= rl78_init_machine_status
;
361 for (i
= 24; i
< 32; i
++)
366 && strcmp (lang_hooks
.name
, "GNU C")
367 && strcmp (lang_hooks
.name
, "GNU C11")
368 && strcmp (lang_hooks
.name
, "GNU C17")
369 && strcmp (lang_hooks
.name
, "GNU C23")
370 && strcmp (lang_hooks
.name
, "GNU C89")
371 && strcmp (lang_hooks
.name
, "GNU C99")
372 /* Compiling with -flto results in a language of GNU GIMPLE being used... */
373 && strcmp (lang_hooks
.name
, "GNU GIMPLE"))
374 /* Address spaces are currently only supported by C. */
375 error ("%<-mes0%> can only be used with C");
377 if (TARGET_SAVE_MDUC_REGISTERS
&& !(TARGET_G13
|| RL78_MUL_G13
))
378 warning (0, "mduc registers only saved for G13 target");
380 switch (rl78_cpu_type
)
383 rl78_cpu_type
= CPU_G14
;
384 if (rl78_mul_type
== MUL_UNINIT
)
385 rl78_mul_type
= MUL_NONE
;
389 switch (rl78_mul_type
)
391 case MUL_UNINIT
: rl78_mul_type
= MUL_NONE
; break;
392 case MUL_NONE
: break;
393 case MUL_G13
: error ("%<-mmul=g13%> cannot be used with "
394 "%<-mcpu=g10%>"); break;
395 case MUL_G14
: error ("%<-mmul=g14%> cannot be used with "
396 "%<-mcpu=g10%>"); break;
401 switch (rl78_mul_type
)
403 case MUL_UNINIT
: rl78_mul_type
= MUL_G13
; break;
404 case MUL_NONE
: break;
406 /* The S2 core does not have mul/div instructions. */
407 case MUL_G14
: error ("%<-mmul=g14%> cannot be used with "
408 "%<-mcpu=g13%>"); break;
413 switch (rl78_mul_type
)
415 case MUL_UNINIT
: rl78_mul_type
= MUL_G14
; break;
416 case MUL_NONE
: break;
418 /* The G14 core does not have the hardware multiply peripheral used by the
419 G13 core, hence you cannot use G13 multipliy routines on G14 hardware. */
420 case MUL_G13
: error ("%<-mmul=g13%> cannot be used with "
421 "%<-mcpu=g14%>"); break;
427 /* Most registers are 8 bits. Some are 16 bits because, for example,
428 gcc doesn't like dealing with $FP as a register pair (the second
429 half of $fp is also 2 to keep reload happy wrt register pairs, but
430 no register class includes it). This table maps register numbers
432 static const int register_sizes
[] =
434 1, 1, 1, 1, 1, 1, 1, 1,
435 1, 1, 1, 1, 1, 1, 1, 1,
436 1, 1, 1, 1, 1, 1, 2, 2,
437 1, 1, 1, 1, 1, 1, 1, 1,
441 /* Predicates used in the MD patterns. This one is true when virtual
442 insns may be matched, which typically means before (or during) the
445 rl78_virt_insns_ok (void)
448 return cfun
->machine
->virt_insns_ok
;
452 /* Predicates used in the MD patterns. This one is true when real
453 insns may be matched, which typically means after (or during) the
456 rl78_real_insns_ok (void)
459 return cfun
->machine
->real_insns_ok
;
463 #undef TARGET_HARD_REGNO_NREGS
464 #define TARGET_HARD_REGNO_NREGS rl78_hard_regno_nregs
467 rl78_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
469 int rs
= register_sizes
[regno
];
472 return ((GET_MODE_SIZE (mode
) + rs
- 1) / rs
);
475 #undef TARGET_HARD_REGNO_MODE_OK
476 #define TARGET_HARD_REGNO_MODE_OK rl78_hard_regno_mode_ok
479 rl78_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
481 int s
= GET_MODE_SIZE (mode
);
485 /* These are not to be used by gcc. */
486 if (regno
== 23 || regno
== ES_REG
|| regno
== CS_REG
)
488 /* $fp can always be accessed as a 16-bit value. */
489 if (regno
== FP_REG
&& s
== 2)
493 /* Since a reg-reg move is really a reg-mem move, we must
494 enforce alignment. */
495 if (s
> 1 && (regno
% 2))
500 return (mode
== BImode
);
501 /* All other registers must be accessed in their natural sizes. */
502 if (s
== register_sizes
[regno
])
507 #undef TARGET_MODES_TIEABLE_P
508 #define TARGET_MODES_TIEABLE_P rl78_modes_tieable_p
511 rl78_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
513 return ((GET_MODE_CLASS (mode1
) == MODE_FLOAT
514 || GET_MODE_CLASS (mode1
) == MODE_COMPLEX_FLOAT
)
515 == (GET_MODE_CLASS (mode2
) == MODE_FLOAT
516 || GET_MODE_CLASS (mode2
) == MODE_COMPLEX_FLOAT
));
519 /* Simplify_gen_subreg() doesn't handle memory references the way we
520 need it to below, so we use this function for when we must get a
521 valid subreg in a "natural" state. */
523 rl78_subreg (machine_mode mode
, rtx r
, machine_mode omode
, int byte
)
525 if (GET_CODE (r
) == MEM
)
526 return adjust_address (r
, mode
, byte
);
528 return simplify_gen_subreg (mode
, r
, omode
, byte
);
531 /* Used by movsi. Split SImode moves into two HImode moves, using
532 appropriate patterns for the upper and lower halves of symbols. */
534 rl78_expand_movsi (rtx
*operands
)
536 rtx op00
, op02
, op10
, op12
;
538 op00
= rl78_subreg (HImode
, operands
[0], SImode
, 0);
539 op02
= rl78_subreg (HImode
, operands
[0], SImode
, 2);
540 if (GET_CODE (operands
[1]) == CONST
541 || GET_CODE (operands
[1]) == SYMBOL_REF
)
543 op10
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (0));
544 op10
= gen_rtx_CONST (HImode
, op10
);
545 op12
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (16));
546 op12
= gen_rtx_CONST (HImode
, op12
);
550 op10
= rl78_subreg (HImode
, operands
[1], SImode
, 0);
551 op12
= rl78_subreg (HImode
, operands
[1], SImode
, 2);
554 if (rtx_equal_p (operands
[0], operands
[1]))
556 else if (rtx_equal_p (op00
, op12
))
558 emit_move_insn (op02
, op12
);
559 emit_move_insn (op00
, op10
);
563 emit_move_insn (op00
, op10
);
564 emit_move_insn (op02
, op12
);
568 /* Generate code to move an SImode value. */
570 rl78_split_movsi (rtx
*operands
, machine_mode omode
)
572 rtx op00
, op02
, op10
, op12
;
574 op00
= rl78_subreg (HImode
, operands
[0], omode
, 0);
575 op02
= rl78_subreg (HImode
, operands
[0], omode
, 2);
577 if (GET_CODE (operands
[1]) == CONST
578 || GET_CODE (operands
[1]) == SYMBOL_REF
)
580 op10
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (0));
581 op10
= gen_rtx_CONST (HImode
, op10
);
582 op12
= gen_rtx_ZERO_EXTRACT (HImode
, operands
[1], GEN_INT (16), GEN_INT (16));
583 op12
= gen_rtx_CONST (HImode
, op12
);
587 op10
= rl78_subreg (HImode
, operands
[1], omode
, 0);
588 op12
= rl78_subreg (HImode
, operands
[1], omode
, 2);
591 if (rtx_equal_p (operands
[0], operands
[1]))
593 else if (rtx_equal_p (op00
, op12
))
610 rl78_split_movdi (rtx
*operands
, enum machine_mode omode
)
612 rtx op00
, op04
, op10
, op14
;
613 op00
= rl78_subreg (SImode
, operands
[0], omode
, 0);
614 op04
= rl78_subreg (SImode
, operands
[0], omode
, 4);
615 op10
= rl78_subreg (SImode
, operands
[1], omode
, 0);
616 op14
= rl78_subreg (SImode
, operands
[1], omode
, 4);
617 emit_insn (gen_movsi (op00
, op10
));
618 emit_insn (gen_movsi (op04
, op14
));
621 /* Used by various two-operand expanders which cannot accept all
622 operands in the "far" namespace. Force some such operands into
623 registers so that each pattern has at most one far operand. */
625 rl78_force_nonfar_2 (rtx
*operands
, rtx (*gen
)(rtx
,rtx
))
630 /* FIXME: in the future, be smarter about only doing this if the
631 other operand is also far, assuming the devirtualizer can also
633 if (rl78_far_p (operands
[0]))
635 temp_reg
= operands
[0];
636 operands
[0] = gen_reg_rtx (GET_MODE (operands
[0]));
642 emit_insn (gen (operands
[0], operands
[1]));
644 emit_move_insn (temp_reg
, operands
[0]);
648 /* Likewise, but for three-operand expanders. */
650 rl78_force_nonfar_3 (rtx
*operands
, rtx (*gen
)(rtx
,rtx
,rtx
))
655 /* FIXME: Likewise. */
656 if (rl78_far_p (operands
[1]))
658 rtx temp_reg
= gen_reg_rtx (GET_MODE (operands
[1]));
659 emit_move_insn (temp_reg
, operands
[1]);
660 operands
[1] = temp_reg
;
663 if (rl78_far_p (operands
[0]))
665 temp_reg
= operands
[0];
666 operands
[0] = gen_reg_rtx (GET_MODE (operands
[0]));
672 emit_insn (gen (operands
[0], operands
[1], operands
[2]));
674 emit_move_insn (temp_reg
, operands
[0]);
679 rl78_one_far_p (rtx
*operands
, int n
)
684 for (i
= 0; i
< n
; i
++)
685 if (rl78_far_p (operands
[i
]))
689 else if (rtx_equal_p (operands
[i
], which
))
696 #undef TARGET_CAN_ELIMINATE
697 #define TARGET_CAN_ELIMINATE rl78_can_eliminate
700 rl78_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to ATTRIBUTE_UNUSED
)
705 /* Returns true if the given register needs to be saved by the
708 need_to_save (unsigned int regno
)
710 if (is_interrupt_func (cfun
->decl
))
712 /* We don't know what devirt will need */
716 /* We don't need to save registers that have
717 been reserved for interrupt handlers. */
721 /* If the handler is a non-leaf function then it may call
722 non-interrupt aware routines which will happily clobber
723 any call_used registers, so we have to preserve them.
724 We do not have to worry about the frame pointer register
725 though, as that is handled below. */
726 if (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
) && regno
< 22)
729 /* Otherwise we only have to save a register, call_used
730 or not, if it is used by this handler. */
731 return df_regs_ever_live_p (regno
);
734 if (regno
== FRAME_POINTER_REGNUM
735 && (frame_pointer_needed
|| df_regs_ever_live_p (regno
)))
737 if (fixed_regs
[regno
])
739 if (crtl
->calls_eh_return
)
741 if (df_regs_ever_live_p (regno
)
742 && !call_used_or_fixed_reg_p (regno
))
747 /* We use this to wrap all emitted insns in the prologue. */
751 RTX_FRAME_RELATED_P (x
) = 1;
755 /* Compute all the frame-related fields in our machine_function
758 rl78_compute_frame_info (void)
762 cfun
->machine
->computed
= 1;
763 cfun
->machine
->framesize_regs
= 0;
764 cfun
->machine
->framesize_locals
= get_frame_size ();
765 cfun
->machine
->framesize_outgoing
= crtl
->outgoing_args_size
;
767 for (i
= 0; i
< 16; i
++)
768 if (need_to_save (i
* 2) || need_to_save (i
* 2 + 1))
770 cfun
->machine
->need_to_push
[i
] = 1;
771 cfun
->machine
->framesize_regs
+= 2;
774 cfun
->machine
->need_to_push
[i
] = 0;
776 if ((cfun
->machine
->framesize_locals
+ cfun
->machine
->framesize_outgoing
) & 1)
777 cfun
->machine
->framesize_locals
++;
779 cfun
->machine
->framesize
= (cfun
->machine
->framesize_regs
780 + cfun
->machine
->framesize_locals
781 + cfun
->machine
->framesize_outgoing
);
784 /* Returns true if the provided function has the specified attribute. */
786 has_func_attr (const_tree decl
, const char * func_attr
)
788 if (decl
== NULL_TREE
)
789 decl
= current_function_decl
;
791 return lookup_attribute (func_attr
, DECL_ATTRIBUTES (decl
)) != NULL_TREE
;
794 /* Returns true if the provided function has the "interrupt" attribute. */
796 is_interrupt_func (const_tree decl
)
798 return has_func_attr (decl
, "interrupt") || has_func_attr (decl
, "brk_interrupt");
801 /* Returns true if the provided function has the "brk_interrupt" attribute. */
803 is_brk_interrupt_func (const_tree decl
)
805 return has_func_attr (decl
, "brk_interrupt");
808 /* Check "interrupt" attributes. */
810 rl78_handle_func_attribute (tree
* node
,
812 tree args ATTRIBUTE_UNUSED
,
813 int flags ATTRIBUTE_UNUSED
,
816 gcc_assert (DECL_P (* node
));
818 if (TREE_CODE (* node
) != FUNCTION_DECL
)
820 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
822 * no_add_attrs
= true;
825 /* FIXME: We ought to check that the interrupt and exception
826 handler attributes have been applied to void functions. */
830 /* Check "naked" attributes. */
832 rl78_handle_naked_attribute (tree
* node
,
833 tree name ATTRIBUTE_UNUSED
,
835 int flags ATTRIBUTE_UNUSED
,
838 gcc_assert (DECL_P (* node
));
839 gcc_assert (args
== NULL_TREE
);
841 if (TREE_CODE (* node
) != FUNCTION_DECL
)
843 warning (OPT_Wattributes
, "naked attribute only applies to functions");
844 * no_add_attrs
= true;
847 /* Disable warnings about this function - eg reaching the end without
848 seeing a return statement - because the programmer is doing things
849 that gcc does not know about. */
850 TREE_NO_WARNING (* node
) = 1;
855 /* Check "saddr" attributes. */
857 rl78_handle_saddr_attribute (tree
* node
,
859 tree args ATTRIBUTE_UNUSED
,
860 int flags ATTRIBUTE_UNUSED
,
863 gcc_assert (DECL_P (* node
));
865 if (TREE_CODE (* node
) == FUNCTION_DECL
)
867 warning (OPT_Wattributes
, "%qE attribute doesn%'t apply to functions",
869 * no_add_attrs
= true;
875 /* Check "vector" attribute. */
878 rl78_handle_vector_attribute (tree
* node
,
881 int flags ATTRIBUTE_UNUSED
,
884 gcc_assert (DECL_P (* node
));
885 gcc_assert (args
!= NULL_TREE
);
887 if (TREE_CODE (* node
) != FUNCTION_DECL
)
889 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
891 * no_add_attrs
= true;
897 #undef TARGET_ATTRIBUTE_TABLE
898 #define TARGET_ATTRIBUTE_TABLE rl78_attribute_table
900 /* Table of RL78-specific attributes. */
901 const struct attribute_spec rl78_attribute_table
[] =
903 /* Name, min_len, max_len, decl_req, type_req, fn_type_req,
904 affects_type_identity, handler, exclude. */
905 { "interrupt", 0, -1, true, false, false, false,
906 rl78_handle_func_attribute
, NULL
},
907 { "brk_interrupt", 0, 0, true, false, false, false,
908 rl78_handle_func_attribute
, NULL
},
909 { "naked", 0, 0, true, false, false, false,
910 rl78_handle_naked_attribute
, NULL
},
911 { "saddr", 0, 0, true, false, false, false,
912 rl78_handle_saddr_attribute
, NULL
},
913 { "vector", 1, -1, true, false, false, false,
914 rl78_handle_vector_attribute
, NULL
},
915 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
920 /* Break down an address RTX into its component base/index/addend
921 portions and return TRUE if the address is of a valid form, else
924 characterize_address (rtx x
, rtx
*base
, rtx
*index
, rtx
*addend
)
930 if (GET_CODE (x
) == UNSPEC
931 && XINT (x
, 1) == UNS_ES_ADDR
)
932 x
= XVECEXP (x
, 0, 1);
934 if (GET_CODE (x
) == REG
)
940 /* We sometimes get these without the CONST wrapper */
941 if (GET_CODE (x
) == PLUS
942 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
943 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
949 if (GET_CODE (x
) == PLUS
)
954 if (GET_CODE (*base
) == SUBREG
)
956 if (GET_MODE (*base
) == HImode
957 && GET_MODE (XEXP (*base
, 0)) == SImode
958 && GET_CODE (XEXP (*base
, 0)) == REG
)
960 /* This is a throw-away rtx just to tell everyone
961 else what effective register we're using. */
962 *base
= gen_rtx_REG (HImode
, REGNO (XEXP (*base
, 0)));
966 if (GET_CODE (*base
) != REG
967 && GET_CODE (x
) == REG
)
974 if (GET_CODE (*base
) != REG
)
977 if (GET_CODE (x
) == ZERO_EXTEND
978 && GET_CODE (XEXP (x
, 0)) == REG
)
980 *index
= XEXP (x
, 0);
985 switch (GET_CODE (x
))
988 if (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
989 && GET_CODE (XEXP (x
, 0)) == CONST_INT
)
1000 switch (GET_CODE (XEXP (x
, 0)))
1024 /* Used by the Whb constraint. Match addresses that use HL+B or HL+C
1027 rl78_hl_b_c_addr_p (rtx op
)
1031 if (GET_CODE (op
) != PLUS
)
1035 if (GET_CODE (hl
) == ZERO_EXTEND
)
1041 if (GET_CODE (hl
) != REG
)
1043 if (GET_CODE (bc
) != ZERO_EXTEND
)
1046 if (GET_CODE (bc
) != REG
)
1048 if (REGNO (hl
) != HL_REG
)
1050 if (REGNO (bc
) != B_REG
&& REGNO (bc
) != C_REG
)
1056 #define REG_IS(r, regno) (((r) == (regno)) || ((r) >= FIRST_PSEUDO_REGISTER && !(strict)))
1058 /* Return the appropriate mode for a named address address. */
1060 #undef TARGET_ADDR_SPACE_ADDRESS_MODE
1061 #define TARGET_ADDR_SPACE_ADDRESS_MODE rl78_addr_space_address_mode
1063 static scalar_int_mode
1064 rl78_addr_space_address_mode (addr_space_t addrspace
)
1068 case ADDR_SPACE_GENERIC
:
1070 case ADDR_SPACE_NEAR
:
1072 case ADDR_SPACE_FAR
:
1079 /* Used in various constraints and predicates to match operands in the
1080 "far" address space. */
1087 fprintf (stderr
, "\033[35mrl78_far_p: "); debug_rtx (x
);
1088 fprintf (stderr
, " = %d\033[0m\n", MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
);
1091 /* Not all far addresses are legitimate, because the devirtualizer
1092 can't handle them. */
1093 if (! rl78_as_legitimate_address (GET_MODE (x
), XEXP (x
, 0), false, ADDR_SPACE_FAR
))
1096 return GET_MODE_BITSIZE (rl78_addr_space_address_mode (MEM_ADDR_SPACE (x
))) == 32;
1099 /* Return the appropriate mode for a named address pointer. */
1100 #undef TARGET_ADDR_SPACE_POINTER_MODE
1101 #define TARGET_ADDR_SPACE_POINTER_MODE rl78_addr_space_pointer_mode
1103 static scalar_int_mode
1104 rl78_addr_space_pointer_mode (addr_space_t addrspace
)
1108 case ADDR_SPACE_GENERIC
:
1110 case ADDR_SPACE_NEAR
:
1112 case ADDR_SPACE_FAR
:
1119 /* Returns TRUE for valid addresses. */
1120 #undef TARGET_VALID_POINTER_MODE
1121 #define TARGET_VALID_POINTER_MODE rl78_valid_pointer_mode
1124 rl78_valid_pointer_mode (scalar_int_mode m
)
1126 return (m
== HImode
|| m
== SImode
);
1129 #undef TARGET_LEGITIMATE_CONSTANT_P
1130 #define TARGET_LEGITIMATE_CONSTANT_P rl78_is_legitimate_constant
1133 rl78_is_legitimate_constant (machine_mode mode ATTRIBUTE_UNUSED
, rtx x ATTRIBUTE_UNUSED
)
1139 #define TARGET_LRA_P hook_bool_void_false
1141 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
1142 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P rl78_as_legitimate_address
1145 rl78_as_legitimate_address (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
,
1146 bool strict ATTRIBUTE_UNUSED
,
1147 addr_space_t as ATTRIBUTE_UNUSED
, code_helper
)
1149 rtx base
, index
, addend
;
1150 bool is_far_addr
= false;
1153 as_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (as
));
1155 if (GET_CODE (x
) == UNSPEC
1156 && XINT (x
, 1) == UNS_ES_ADDR
)
1158 x
= XVECEXP (x
, 0, 1);
1162 if (as_bits
== 16 && is_far_addr
)
1165 if (! characterize_address (x
, &base
, &index
, &addend
))
1168 /* We can't extract the high/low portions of a PLUS address
1169 involving a register during devirtualization, so make sure all
1170 such __far addresses do not have addends. This forces GCC to do
1171 the sum separately. */
1172 if (addend
&& base
&& as_bits
== 32 && GET_MODE (base
) == SImode
)
1177 int ir
= REGNO (index
);
1178 int br
= REGNO (base
);
1180 #define OK(test, debug) if (test) { /*fprintf(stderr, "%d: OK %s\n", __LINE__, debug);*/ return true; }
1181 OK (REG_IS (br
, HL_REG
) && REG_IS (ir
, B_REG
), "[hl+b]");
1182 OK (REG_IS (br
, HL_REG
) && REG_IS (ir
, C_REG
), "[hl+c]");
1186 if (strict
&& base
&& GET_CODE (base
) == REG
&& REGNO (base
) >= FIRST_PSEUDO_REGISTER
)
1189 if (! cfun
->machine
->virt_insns_ok
&& base
&& GET_CODE (base
) == REG
1190 && REGNO (base
) >= 8 && REGNO (base
) <= 31)
1196 /* Determine if one named address space is a subset of another. */
1197 #undef TARGET_ADDR_SPACE_SUBSET_P
1198 #define TARGET_ADDR_SPACE_SUBSET_P rl78_addr_space_subset_p
1201 rl78_addr_space_subset_p (addr_space_t subset
, addr_space_t superset
)
1206 subset_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (subset
));
1207 superset_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (superset
));
1209 return (subset_bits
<= superset_bits
);
1212 #undef TARGET_ADDR_SPACE_CONVERT
1213 #define TARGET_ADDR_SPACE_CONVERT rl78_addr_space_convert
1215 /* Convert from one address space to another. */
1217 rl78_addr_space_convert (rtx op
, tree from_type
, tree to_type
)
1219 addr_space_t from_as
= TYPE_ADDR_SPACE (TREE_TYPE (from_type
));
1220 addr_space_t to_as
= TYPE_ADDR_SPACE (TREE_TYPE (to_type
));
1225 to_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (to_as
));
1226 from_bits
= GET_MODE_BITSIZE (rl78_addr_space_address_mode (from_as
));
1228 if (to_bits
< from_bits
)
1231 /* This is unpredictable, as we're truncating off usable address
1234 warning (OPT_Waddress
, "converting far pointer to near pointer");
1235 result
= gen_reg_rtx (HImode
);
1236 if (GET_CODE (op
) == SYMBOL_REF
1237 || (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1238 tmp
= gen_rtx_raw_SUBREG (HImode
, op
, 0);
1240 tmp
= simplify_subreg (HImode
, op
, SImode
, 0);
1241 gcc_assert (tmp
!= NULL_RTX
);
1242 emit_move_insn (result
, tmp
);
1245 else if (to_bits
> from_bits
)
1247 /* This always works. */
1248 result
= gen_reg_rtx (SImode
);
1249 emit_move_insn (rl78_subreg (HImode
, result
, SImode
, 0), op
);
1250 if (TREE_CODE (from_type
) == POINTER_TYPE
1251 && TREE_CODE (TREE_TYPE (from_type
)) == FUNCTION_TYPE
)
1252 emit_move_insn (rl78_subreg (HImode
, result
, SImode
, 2), const0_rtx
);
1254 emit_move_insn (rl78_subreg (HImode
, result
, SImode
, 2), GEN_INT (0x0f));
1262 /* Implements REGNO_MODE_CODE_OK_FOR_BASE_P. */
1264 rl78_regno_mode_code_ok_for_base_p (int regno
, machine_mode mode ATTRIBUTE_UNUSED
,
1265 addr_space_t address_space ATTRIBUTE_UNUSED
,
1266 int outer_code ATTRIBUTE_UNUSED
, int index_code
)
1268 if (regno
<= SP_REG
&& regno
>= 16)
1270 if (index_code
== REG
)
1271 return (regno
== HL_REG
);
1272 if (regno
== C_REG
|| regno
== B_REG
|| regno
== E_REG
|| regno
== L_REG
)
1277 /* Implements MODE_CODE_BASE_REG_CLASS. */
1279 rl78_mode_code_base_reg_class (machine_mode mode ATTRIBUTE_UNUSED
,
1280 addr_space_t address_space ATTRIBUTE_UNUSED
,
1281 int outer_code ATTRIBUTE_UNUSED
,
1282 int index_code ATTRIBUTE_UNUSED
)
1287 /* Typical stack layout should looks like this after the function's prologue:
1292 | | arguments saved | Increasing
1293 | | on the stack | addresses
1294 PARENT arg pointer -> | | /
1295 -------------------------- ---- -------------------
1296 CHILD |ret | return address
1301 frame pointer -> | | /
1309 | | outgoing | Decreasing
1310 | | arguments | addresses
1311 current stack pointer -> | | / |
1312 -------------------------- ---- ------------------ V
1315 /* Implements INITIAL_ELIMINATION_OFFSET. The frame layout is
1316 described in the machine_Function struct definition, above. */
1318 rl78_initial_elimination_offset (int from
, int to
)
1320 int rv
= 0; /* as if arg to arg */
1322 rl78_compute_frame_info ();
1326 case STACK_POINTER_REGNUM
:
1327 rv
+= cfun
->machine
->framesize_outgoing
;
1328 rv
+= cfun
->machine
->framesize_locals
;
1330 case FRAME_POINTER_REGNUM
:
1331 rv
+= cfun
->machine
->framesize_regs
;
1340 case FRAME_POINTER_REGNUM
:
1342 rv
-= cfun
->machine
->framesize_regs
;
1343 case ARG_POINTER_REGNUM
:
1353 rl78_is_naked_func (void)
1355 return (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
);
1358 /* Check if the block uses mul/div insns for G13 target. */
1361 check_mduc_usage (void)
1366 FOR_EACH_BB_FN (bb
, cfun
)
1368 FOR_BB_INSNS (bb
, insn
)
1371 && (get_attr_is_g13_muldiv_insn (insn
) == IS_G13_MULDIV_INSN_YES
))
1378 /* Expand the function prologue (from the prologue pattern). */
1381 rl78_expand_prologue (void)
1384 rtx sp
= gen_rtx_REG (HImode
, STACK_POINTER_REGNUM
);
1385 rtx ax
= gen_rtx_REG (HImode
, AX_REG
);
1388 if (rl78_is_naked_func ())
1391 /* Always re-compute the frame info - the register usage may have changed. */
1392 rl78_compute_frame_info ();
1394 if (MUST_SAVE_MDUC_REGISTERS
&& (!crtl
->is_leaf
|| check_mduc_usage ()))
1395 cfun
->machine
->framesize
+= ARRAY_SIZE (mduc_regs
) * 2;
1397 if (flag_stack_usage_info
)
1398 current_function_static_stack_size
= cfun
->machine
->framesize
;
1400 if (is_interrupt_func (cfun
->decl
) && !TARGET_G10
)
1401 for (i
= 0; i
< 4; i
++)
1402 if (cfun
->machine
->need_to_push
[i
])
1404 /* Select Bank 0 if we are using any registers from Bank 0. */
1405 emit_insn (gen_sel_rb (GEN_INT (0)));
1409 for (i
= 0; i
< 16; i
++)
1410 if (cfun
->machine
->need_to_push
[i
])
1418 emit_move_insn (ax
, gen_rtx_REG (HImode
, reg
));
1424 int need_bank
= i
/4;
1426 if (need_bank
!= rb
)
1428 emit_insn (gen_sel_rb (GEN_INT (need_bank
)));
1433 F (emit_insn (gen_push (gen_rtx_REG (HImode
, reg
))));
1437 emit_insn (gen_sel_rb (GEN_INT (0)));
1439 /* Save ES register inside interrupt functions if it is used. */
1440 if (is_interrupt_func (cfun
->decl
) && cfun
->machine
->uses_es
)
1442 emit_insn (gen_movqi_from_es (gen_rtx_REG (QImode
, A_REG
)));
1443 F (emit_insn (gen_push (ax
)));
1446 /* Save MDUC registers inside interrupt routine. */
1447 if (MUST_SAVE_MDUC_REGISTERS
&& (!crtl
->is_leaf
|| check_mduc_usage ()))
1449 for (unsigned i
= 0; i
< ARRAY_SIZE (mduc_regs
); i
++)
1451 mduc_reg_type
*reg
= mduc_regs
+ i
;
1452 rtx mem_mduc
= gen_rtx_MEM (reg
->mode
, GEN_INT (reg
->address
));
1454 MEM_VOLATILE_P (mem_mduc
) = 1;
1455 if (reg
->mode
== QImode
)
1456 emit_insn (gen_movqi (gen_rtx_REG (QImode
, A_REG
), mem_mduc
));
1458 emit_insn (gen_movhi (gen_rtx_REG (HImode
, AX_REG
), mem_mduc
));
1460 emit_insn (gen_push (gen_rtx_REG (HImode
, AX_REG
)));
1464 if (frame_pointer_needed
)
1466 F (emit_move_insn (ax
, sp
));
1467 F (emit_move_insn (gen_rtx_REG (HImode
, FRAME_POINTER_REGNUM
), ax
));
1470 fs
= cfun
->machine
->framesize_locals
+ cfun
->machine
->framesize_outgoing
;
1473 /* If we need to subtract more than 254*3 then it is faster and
1474 smaller to move SP into AX and perform the subtraction there. */
1479 emit_move_insn (ax
, sp
);
1480 emit_insn (gen_subhi3 (ax
, ax
, GEN_INT (fs
)));
1481 insn
= F (emit_move_insn (sp
, ax
));
1482 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
1483 gen_rtx_SET (sp
, gen_rtx_PLUS (HImode
, sp
,
1490 int fs_byte
= (fs
> 254) ? 254 : fs
;
1492 F (emit_insn (gen_subhi3 (sp
, sp
, GEN_INT (fs_byte
))));
1499 /* Expand the function epilogue (from the epilogue pattern). */
1501 rl78_expand_epilogue (void)
1504 rtx sp
= gen_rtx_REG (HImode
, STACK_POINTER_REGNUM
);
1505 rtx ax
= gen_rtx_REG (HImode
, AX_REG
);
1508 if (rl78_is_naked_func ())
1511 if (frame_pointer_needed
)
1513 emit_move_insn (ax
, gen_rtx_REG (HImode
, FRAME_POINTER_REGNUM
));
1514 emit_move_insn (sp
, ax
);
1518 fs
= cfun
->machine
->framesize_locals
+ cfun
->machine
->framesize_outgoing
;
1521 emit_move_insn (ax
, sp
);
1522 emit_insn (gen_addhi3 (ax
, ax
, GEN_INT (fs
)));
1523 emit_move_insn (sp
, ax
);
1529 int fs_byte
= (fs
> 254) ? 254 : fs
;
1531 emit_insn (gen_addhi3 (sp
, sp
, GEN_INT (fs_byte
)));
1537 /* Restore MDUC registers from interrupt routine. */
1538 if (MUST_SAVE_MDUC_REGISTERS
&& (!crtl
->is_leaf
|| check_mduc_usage ()))
1540 for (int i
= ARRAY_SIZE (mduc_regs
) - 1; i
>= 0; i
--)
1542 mduc_reg_type
*reg
= mduc_regs
+ i
;
1543 rtx mem_mduc
= gen_rtx_MEM (reg
->mode
, GEN_INT (reg
->address
));
1545 emit_insn (gen_pop (gen_rtx_REG (HImode
, AX_REG
)));
1546 MEM_VOLATILE_P (mem_mduc
) = 1;
1547 if (reg
->mode
== QImode
)
1548 emit_insn (gen_movqi (mem_mduc
, gen_rtx_REG (QImode
, A_REG
)));
1550 emit_insn (gen_movhi (mem_mduc
, gen_rtx_REG (HImode
, AX_REG
)));
1554 if (is_interrupt_func (cfun
->decl
) && cfun
->machine
->uses_es
)
1556 emit_insn (gen_pop (gen_rtx_REG (HImode
, AX_REG
)));
1557 emit_insn (gen_movqi_to_es (gen_rtx_REG (QImode
, A_REG
)));
1560 for (i
= 15; i
>= 0; i
--)
1561 if (cfun
->machine
->need_to_push
[i
])
1563 rtx dest
= gen_rtx_REG (HImode
, i
* 2);
1568 emit_insn (gen_pop (dest
));
1571 emit_insn (gen_pop (ax
));
1572 emit_move_insn (dest
, ax
);
1573 /* Generate a USE of the pop'd register so that DCE will not eliminate the move. */
1574 emit_insn (gen_use (dest
));
1579 int need_bank
= i
/ 4;
1581 if (need_bank
!= rb
)
1583 emit_insn (gen_sel_rb (GEN_INT (need_bank
)));
1586 emit_insn (gen_pop (dest
));
1591 emit_insn (gen_sel_rb (GEN_INT (0)));
1593 if (cfun
->machine
->trampolines_used
)
1594 emit_insn (gen_trampoline_uninit ());
1596 if (is_brk_interrupt_func (cfun
->decl
))
1597 emit_jump_insn (gen_brk_interrupt_return ());
1598 else if (is_interrupt_func (cfun
->decl
))
1599 emit_jump_insn (gen_interrupt_return ());
1601 emit_jump_insn (gen_rl78_return ());
1604 /* Likewise, for exception handlers. */
1606 rl78_expand_eh_epilogue (rtx x ATTRIBUTE_UNUSED
)
1608 /* FIXME - replace this with an indirect jump with stack adjust. */
1609 emit_jump_insn (gen_rl78_return ());
1612 #undef TARGET_ASM_FUNCTION_PROLOGUE
1613 #define TARGET_ASM_FUNCTION_PROLOGUE rl78_start_function
1616 add_vector_labels (FILE *file
, const char *aname
)
1620 const char *vname
= "vect";
1624 /* This node is for the vector/interrupt tag itself */
1625 vec_attr
= lookup_attribute (aname
, DECL_ATTRIBUTES (current_function_decl
));
1629 /* Now point it at the first argument */
1630 vec_attr
= TREE_VALUE (vec_attr
);
1632 /* Iterate through the arguments. */
1635 val_attr
= TREE_VALUE (vec_attr
);
1636 switch (TREE_CODE (val_attr
))
1639 s
= TREE_STRING_POINTER (val_attr
);
1640 goto string_id_common
;
1642 case IDENTIFIER_NODE
:
1643 s
= IDENTIFIER_POINTER (val_attr
);
1646 if (strcmp (s
, "$default") == 0)
1648 fprintf (file
, "\t.global\t$tableentry$default$%s\n", vname
);
1649 fprintf (file
, "$tableentry$default$%s:\n", vname
);
1656 vnum
= TREE_INT_CST_LOW (val_attr
);
1658 fprintf (file
, "\t.global\t$tableentry$%d$%s\n", vnum
, vname
);
1659 fprintf (file
, "$tableentry$%d$%s:\n", vnum
, vname
);
1666 vec_attr
= TREE_CHAIN (vec_attr
);
1671 /* We don't use this to actually emit the function prologue. We use
1672 this to insert a comment in the asm file describing the
1675 rl78_start_function (FILE *file
)
1679 add_vector_labels (file
, "interrupt");
1680 add_vector_labels (file
, "vector");
1682 if (cfun
->machine
->framesize
== 0)
1684 fprintf (file
, "\t; start of function\n");
1686 if (cfun
->machine
->framesize_regs
)
1688 fprintf (file
, "\t; push %d:", cfun
->machine
->framesize_regs
);
1689 for (i
= 0; i
< 16; i
++)
1690 if (cfun
->machine
->need_to_push
[i
])
1691 fprintf (file
, " %s", word_regnames
[i
*2]);
1692 fprintf (file
, "\n");
1695 if (frame_pointer_needed
)
1696 fprintf (file
, "\t; $fp points here (r22)\n");
1698 if (cfun
->machine
->framesize_locals
)
1699 fprintf (file
, "\t; locals: %d byte%s\n", cfun
->machine
->framesize_locals
,
1700 cfun
->machine
->framesize_locals
== 1 ? "" : "s");
1702 if (cfun
->machine
->framesize_outgoing
)
1703 fprintf (file
, "\t; outgoing: %d byte%s\n", cfun
->machine
->framesize_outgoing
,
1704 cfun
->machine
->framesize_outgoing
== 1 ? "" : "s");
1706 if (cfun
->machine
->uses_es
)
1707 fprintf (file
, "\t; uses ES register\n");
1709 if (MUST_SAVE_MDUC_REGISTERS
)
1710 fprintf (file
, "\t; preserves MDUC registers\n");
1713 /* Return an RTL describing where a function return value of type RET_TYPE
1716 #undef TARGET_FUNCTION_VALUE
1717 #define TARGET_FUNCTION_VALUE rl78_function_value
1720 rl78_function_value (const_tree ret_type
,
1721 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1722 bool outgoing ATTRIBUTE_UNUSED
)
1724 machine_mode mode
= TYPE_MODE (ret_type
);
1726 return gen_rtx_REG (mode
, 8);
1729 #undef TARGET_PROMOTE_FUNCTION_MODE
1730 #define TARGET_PROMOTE_FUNCTION_MODE rl78_promote_function_mode
1733 rl78_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
1735 int *punsignedp ATTRIBUTE_UNUSED
,
1736 const_tree funtype ATTRIBUTE_UNUSED
, int for_return ATTRIBUTE_UNUSED
)
1741 #undef TARGET_FUNCTION_ARG
1742 #define TARGET_FUNCTION_ARG rl78_function_arg
1745 rl78_function_arg (cumulative_args_t
, const function_arg_info
&)
1750 #undef TARGET_FUNCTION_ARG_ADVANCE
1751 #define TARGET_FUNCTION_ARG_ADVANCE rl78_function_arg_advance
1754 rl78_function_arg_advance (cumulative_args_t cum_v
,
1755 const function_arg_info
&arg
)
1758 CUMULATIVE_ARGS
* cum
= get_cumulative_args (cum_v
);
1760 rounded_size
= arg
.promoted_size_in_bytes ();
1761 if (rounded_size
& 1)
1763 (*cum
) += rounded_size
;
1766 #undef TARGET_FUNCTION_ARG_BOUNDARY
1767 #define TARGET_FUNCTION_ARG_BOUNDARY rl78_function_arg_boundary
1770 rl78_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
1771 const_tree type ATTRIBUTE_UNUSED
)
1776 /* Supported modifier letters:
1778 A - address of a MEM
1779 S - SADDR form of a real register
1780 v - real register corresponding to a virtual register
1781 m - minus - negative of CONST_INT value.
1782 C - inverse of a conditional (NE vs EQ for example)
1783 C - complement of an integer
1784 z - collapsed conditional
1785 s - shift count mod 8
1786 S - shift count mod 16
1787 r - reverse shift count (8-(count mod 8))
1790 h - bottom HI of an SI
1792 q - bottom QI of an HI
1794 e - third QI of an SI (i.e. where the ES register gets values from)
1795 E - fourth QI of an SI (i.e. MSB)
1797 p - Add +0 to a zero-indexed HL based address.
1800 /* Implements the bulk of rl78_print_operand, below. We do it this
1801 way because we need to test for a constant at the top level and
1802 insert the '#', but not test for it anywhere else as we recurse
1803 down into the operand. */
1805 rl78_print_operand_1 (FILE * file
, rtx op
, int letter
)
1809 switch (GET_CODE (op
))
1813 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1816 if (rl78_far_p (op
))
1818 fprintf (file
, "es:");
1819 if (GET_CODE (XEXP (op
, 0)) == UNSPEC
)
1820 op
= gen_rtx_MEM (GET_MODE (op
), XVECEXP (XEXP (op
, 0), 0, 1));
1824 op
= adjust_address (op
, HImode
, 2);
1829 op
= adjust_address (op
, HImode
, 0);
1834 op
= adjust_address (op
, QImode
, 1);
1839 op
= adjust_address (op
, QImode
, 0);
1844 op
= adjust_address (op
, QImode
, 2);
1849 op
= adjust_address (op
, QImode
, 3);
1852 if (CONSTANT_P (XEXP (op
, 0)))
1854 if (!rl78_saddr_p (op
))
1855 fprintf (file
, "!");
1856 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1858 else if (GET_CODE (XEXP (op
, 0)) == PLUS
1859 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
)
1861 if (!rl78_saddr_p (op
))
1862 fprintf (file
, "!");
1863 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1865 else if (GET_CODE (XEXP (op
, 0)) == PLUS
1866 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == REG
1867 && REGNO (XEXP (XEXP (op
, 0), 0)) == 2)
1869 rl78_print_operand_1 (file
, XEXP (XEXP (op
, 0), 1), 'u');
1870 fprintf (file
, "[");
1871 rl78_print_operand_1 (file
, XEXP (XEXP (op
, 0), 0), 0);
1872 if (letter
== 'p' && GET_CODE (XEXP (op
, 0)) == REG
)
1873 fprintf (file
, "+0");
1874 fprintf (file
, "]");
1879 fprintf (file
, "[");
1880 rl78_print_operand_1 (file
, op
, letter
);
1881 if (letter
== 'p' && REG_P (op
) && REGNO (op
) == 6)
1882 fprintf (file
, "+0");
1883 fprintf (file
, "]");
1890 fprintf (file
, "%s", reg_names
[REGNO (op
) | 1]);
1891 else if (letter
== 'H')
1892 fprintf (file
, "%s", reg_names
[REGNO (op
) + 2]);
1893 else if (letter
== 'q')
1894 fprintf (file
, "%s", reg_names
[REGNO (op
) & ~1]);
1895 else if (letter
== 'e')
1896 fprintf (file
, "%s", reg_names
[REGNO (op
) + 2]);
1897 else if (letter
== 'E')
1898 fprintf (file
, "%s", reg_names
[REGNO (op
) + 3]);
1899 else if (letter
== 'S')
1900 fprintf (file
, "0x%x", 0xffef8 + REGNO (op
));
1901 else if (GET_MODE (op
) == HImode
1902 && ! (REGNO (op
) & ~0xfe))
1905 fprintf (file
, "%s", word_regnames
[REGNO (op
) % 8]);
1907 fprintf (file
, "%s", word_regnames
[REGNO (op
)]);
1910 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
1915 fprintf (file
, "%ld", INTVAL (op
) >> 8);
1916 else if (letter
== 'H')
1917 fprintf (file
, "%ld", INTVAL (op
) >> 16);
1918 else if (letter
== 'q')
1919 fprintf (file
, "%ld", INTVAL (op
) & 0xff);
1920 else if (letter
== 'h')
1921 fprintf (file
, "%ld", INTVAL (op
) & 0xffff);
1922 else if (letter
== 'e')
1923 fprintf (file
, "%ld", (INTVAL (op
) >> 16) & 0xff);
1924 else if (letter
== 'B')
1926 int ival
= INTVAL (op
);
1929 if (exact_log2 (ival
) >= 0)
1930 fprintf (file
, "%d", exact_log2 (ival
));
1932 fprintf (file
, "%d", exact_log2 (~ival
& 0xff));
1934 else if (letter
== 'E')
1935 fprintf (file
, "%ld", (INTVAL (op
) >> 24) & 0xff);
1936 else if (letter
== 'm')
1937 fprintf (file
, "%ld", - INTVAL (op
));
1938 else if (letter
== 's')
1939 fprintf (file
, "%ld", INTVAL (op
) % 8);
1940 else if (letter
== 'S')
1941 fprintf (file
, "%ld", INTVAL (op
) % 16);
1942 else if (letter
== 'r')
1943 fprintf (file
, "%ld", 8 - (INTVAL (op
) % 8));
1944 else if (letter
== 'C')
1945 fprintf (file
, "%ld", (INTVAL (op
) ^ 0x8000) & 0xffff);
1947 fprintf (file
, "%ld", INTVAL (op
));
1951 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
1956 int bits
= INTVAL (XEXP (op
, 1));
1957 int ofs
= INTVAL (XEXP (op
, 2));
1958 if (bits
== 16 && ofs
== 0)
1959 fprintf (file
, "%%lo16(");
1960 else if (bits
== 16 && ofs
== 16)
1961 fprintf (file
, "%%hi16(");
1962 else if (bits
== 8 && ofs
== 16)
1963 fprintf (file
, "%%hi8(");
1966 rl78_print_operand_1 (file
, XEXP (op
, 0), 0);
1967 fprintf (file
, ")");
1972 if (GET_CODE (XEXP (op
, 0)) == REG
)
1973 fprintf (file
, "%s", reg_names
[REGNO (XEXP (op
, 0))]);
1975 print_rtl (file
, op
);
1982 fprintf (file
, "%%hi16(");
1988 fprintf (file
, "%%lo16(");
1994 fprintf (file
, "%%hi8(");
1998 if (letter
== 'q' || letter
== 'Q')
1999 output_operand_lossage ("q/Q modifiers invalid for symbol references");
2001 if (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
2003 if (GET_CODE (XEXP (op
, 1)) == SYMBOL_REF
2004 && SYMBOL_REF_DECL (XEXP (op
, 1))
2005 && TREE_CODE (SYMBOL_REF_DECL (XEXP (op
, 1))) == FUNCTION_DECL
)
2007 fprintf (file
, "%%code(");
2008 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op
, 1), 0)));
2009 fprintf (file
, "+");
2010 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
2011 fprintf (file
, ")");
2015 rl78_print_operand_1 (file
, XEXP (op
, 1), letter
);
2016 fprintf (file
, "+");
2017 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
2022 if (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
2023 && SYMBOL_REF_DECL (XEXP (op
, 0))
2024 && TREE_CODE (SYMBOL_REF_DECL (XEXP (op
, 0))) == FUNCTION_DECL
)
2026 fprintf (file
, "%%code(");
2027 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op
, 0), 0)));
2028 fprintf (file
, "+");
2029 rl78_print_operand_1 (file
, XEXP (op
, 1), letter
);
2030 fprintf (file
, ")");
2034 rl78_print_operand_1 (file
, XEXP (op
, 0), letter
);
2035 fprintf (file
, "+");
2036 rl78_print_operand_1 (file
, XEXP (op
, 1), letter
);
2040 fprintf (file
, ")");
2044 if (GET_MODE (op
) == HImode
2045 && SUBREG_BYTE (op
) == 0)
2047 fprintf (file
, "%%lo16(");
2048 rl78_print_operand_1 (file
, SUBREG_REG (op
), 0);
2049 fprintf (file
, ")");
2051 else if (GET_MODE (op
) == HImode
2052 && SUBREG_BYTE (op
) == 2)
2054 fprintf (file
, "%%hi16(");
2055 rl78_print_operand_1 (file
, SUBREG_REG (op
), 0);
2056 fprintf (file
, ")");
2060 fprintf (file
, "(%s)", GET_RTX_NAME (GET_CODE (op
)));
2068 fprintf (file
, "%%hi16(");
2074 fprintf (file
, "%%lo16(");
2080 fprintf (file
, "%%hi8(");
2084 if (letter
== 'q' || letter
== 'Q')
2085 output_operand_lossage ("q/Q modifiers invalid for symbol references");
2087 if (SYMBOL_REF_DECL (op
) && TREE_CODE (SYMBOL_REF_DECL (op
)) == FUNCTION_DECL
)
2089 fprintf (file
, "%%code(");
2090 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (op
, 0)));
2091 fprintf (file
, ")");
2094 assemble_name (file
, rl78_strip_nonasm_name_encoding (XSTR (op
, 0)));
2096 fprintf (file
, ")");
2101 output_asm_label (op
);
2106 fprintf (file
, "#comparison eliminated");
2108 fprintf (file
, letter
== 'C' ? "nc" : "c");
2112 fprintf (file
, "br");
2114 fprintf (file
, letter
== 'C' ? "h" : "nh");
2118 fprintf (file
, "br");
2120 fprintf (file
, letter
== 'C' ? "c" : "nc");
2124 fprintf (file
, "#comparison eliminated");
2126 fprintf (file
, letter
== 'C' ? "nh" : "h");
2130 fprintf (file
, "br");
2132 fprintf (file
, letter
== 'C' ? "nz" : "z");
2136 fprintf (file
, "#comparison eliminated");
2138 fprintf (file
, letter
== 'C' ? "z" : "nz");
2141 /* Note: these assume appropriate adjustments were made so that
2142 unsigned comparisons, which is all this chip has, will
2146 fprintf (file
, "#comparison eliminated");
2148 fprintf (file
, letter
== 'C' ? "nc" : "c");
2152 fprintf (file
, "br");
2154 fprintf (file
, letter
== 'C' ? "h" : "nh");
2158 fprintf (file
, "br");
2160 fprintf (file
, letter
== 'C' ? "c" : "nc");
2164 fprintf (file
, "#comparison eliminated");
2166 fprintf (file
, letter
== 'C' ? "nh" : "h");
2170 fprintf (file
, "(%s)", GET_RTX_NAME (GET_CODE (op
)));
2175 #undef TARGET_PRINT_OPERAND
2176 #define TARGET_PRINT_OPERAND rl78_print_operand
2179 rl78_print_operand (FILE * file
, rtx op
, int letter
)
2181 if (CONSTANT_P (op
) && letter
!= 'u' && letter
!= 's' && letter
!= 'r' && letter
!= 'S' && letter
!= 'B')
2182 fprintf (file
, "#");
2183 rl78_print_operand_1 (file
, op
, letter
);
2186 #undef TARGET_TRAMPOLINE_INIT
2187 #define TARGET_TRAMPOLINE_INIT rl78_trampoline_init
2189 /* Note that the RL78's addressing makes it very difficult to do
2190 trampolines on the stack. So, libgcc has a small pool of
2191 trampolines from which one is allocated to this task. */
2193 rl78_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
2195 rtx mov_addr
, thunk_addr
;
2196 rtx function
= XEXP (DECL_RTL (fndecl
), 0);
2198 mov_addr
= adjust_address (m_tramp
, HImode
, 0);
2199 thunk_addr
= gen_reg_rtx (HImode
);
2201 function
= force_reg (HImode
, function
);
2202 static_chain
= force_reg (HImode
, static_chain
);
2204 emit_insn (gen_trampoline_init (thunk_addr
, function
, static_chain
));
2205 emit_move_insn (mov_addr
, thunk_addr
);
2207 cfun
->machine
->trampolines_used
= 1;
2210 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
2211 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS rl78_trampoline_adjust_address
2214 rl78_trampoline_adjust_address (rtx m_tramp
)
2216 rtx x
= gen_rtx_MEM (HImode
, m_tramp
);
2220 /* Expander for cbranchqi4 and cbranchhi4. RL78 is missing some of
2221 the "normal" compares, specifically, it only has unsigned compares,
2222 so we must synthesize the missing ones. */
2224 rl78_expand_compare (rtx
*operands
)
2226 if (GET_CODE (operands
[2]) == MEM
)
2227 operands
[2] = copy_to_mode_reg (GET_MODE (operands
[2]), operands
[2]);
2232 /* Define this to 1 if you are debugging the peephole optimizers. */
2233 #define DEBUG_PEEP 0
2235 /* Predicate used to enable the peephole2 patterns in rl78-virt.md.
2236 The default "word" size is a byte so we can effectively use all the
2237 registers, but we want to do 16-bit moves whenever possible. This
2238 function determines when such a move is an option. */
2240 rl78_peep_movhi_p (rtx
*operands
)
2245 /* (set (op0) (op1))
2246 (set (op2) (op3)) */
2248 if (! rl78_virt_insns_ok ())
2252 fprintf (stderr
, "\033[33m");
2253 debug_rtx (operands
[0]);
2254 debug_rtx (operands
[1]);
2255 debug_rtx (operands
[2]);
2256 debug_rtx (operands
[3]);
2257 fprintf (stderr
, "\033[0m");
2260 /* You can move a constant to memory as QImode, but not HImode. */
2261 if (GET_CODE (operands
[0]) == MEM
2262 && GET_CODE (operands
[1]) != REG
)
2265 fprintf (stderr
, "no peep: move constant to memory\n");
2270 if (rtx_equal_p (operands
[0], operands
[3]))
2273 fprintf (stderr
, "no peep: overlapping\n");
2278 for (i
= 0; i
< 2; i
++)
2280 if (GET_CODE (operands
[i
]) != GET_CODE (operands
[i
+2]))
2283 fprintf (stderr
, "no peep: different codes\n");
2287 if (GET_MODE (operands
[i
]) != GET_MODE (operands
[i
+2]))
2290 fprintf (stderr
, "no peep: different modes\n");
2295 switch (GET_CODE (operands
[i
]))
2299 if (REGNO (operands
[i
]) + 1 != REGNO (operands
[i
+2])
2300 || GET_MODE (operands
[i
]) != QImode
)
2303 fprintf (stderr
, "no peep: wrong regnos %d %d %d\n",
2304 REGNO (operands
[i
]), REGNO (operands
[i
+2]),
2309 if (! rl78_hard_regno_mode_ok (REGNO (operands
[i
]), HImode
))
2312 fprintf (stderr
, "no peep: reg %d not HI\n", REGNO (operands
[i
]));
2322 if (GET_MODE (operands
[i
]) != QImode
)
2324 if (MEM_ALIGN (operands
[i
]) < 16)
2326 a
= XEXP (operands
[i
], 0);
2327 if (GET_CODE (a
) == CONST
)
2329 if (GET_CODE (a
) == PLUS
)
2331 if (GET_CODE (a
) == CONST_INT
2335 fprintf (stderr
, "no peep: misaligned mem %d\n", i
);
2336 debug_rtx (operands
[i
]);
2340 m
= adjust_address (operands
[i
], QImode
, 1);
2341 if (! rtx_equal_p (m
, operands
[i
+2]))
2344 fprintf (stderr
, "no peep: wrong mem %d\n", i
);
2346 debug_rtx (operands
[i
+2]);
2354 fprintf (stderr
, "no peep: wrong rtx %d\n", i
);
2360 fprintf (stderr
, "\033[32mpeep!\033[0m\n");
2365 /* Likewise, when a peephole is activated, this function helps compute
2366 the new operands. */
2368 rl78_setup_peep_movhi (rtx
*operands
)
2372 for (i
= 0; i
< 2; i
++)
2374 switch (GET_CODE (operands
[i
]))
2377 operands
[i
+4] = gen_rtx_REG (HImode
, REGNO (operands
[i
]));
2381 operands
[i
+4] = GEN_INT ((INTVAL (operands
[i
]) & 0xff) + ((char) INTVAL (operands
[i
+2])) * 256);
2385 operands
[i
+4] = adjust_address (operands
[i
], HImode
, 0);
2395 How Devirtualization works in the RL78 GCC port
2399 The RL78 is an 8-bit port with some 16-bit operations. It has 32
2400 bytes of register space, in four banks, memory-mapped. One bank is
2401 the "selected" bank and holds the registers used for primary
2402 operations. Since the registers are memory mapped, often you can
2403 still refer to the unselected banks via memory accesses.
2407 The GCC port uses bank 0 as the "selected" registers (A, X, BC, etc)
2408 and refers to the other banks via their memory addresses, although
2409 they're treated as regular registers internally. These "virtual"
2410 registers are R8 through R23 (bank3 is reserved for asm-based
2411 interrupt handlers).
2413 There are four machine description files:
2415 rl78.md - common register-independent patterns and definitions
2416 rl78-expand.md - expanders
2417 rl78-virt.md - patterns that match BEFORE devirtualization
2418 rl78-real.md - patterns that match AFTER devirtualization
2420 At least through register allocation and reload, gcc is told that it
2421 can do pretty much anything - but may only use the virtual registers.
2422 GCC cannot properly create the varying addressing modes that the RL78
2423 supports in an efficient way.
2425 Sometime after reload, the RL78 backend "devirtualizes" the RTL. It
2426 uses the "valloc" attribute in rl78-virt.md for determining the rules
2427 by which it will replace virtual registers with real registers (or
2428 not) and how to make up addressing modes. For example, insns tagged
2429 with "ro1" have a single read-only parameter, which may need to be
2430 moved from memory/constant/vreg to a suitable real register. As part
2431 of devirtualization, a flag is toggled, disabling the rl78-virt.md
2432 patterns and enabling the rl78-real.md patterns. The new patterns'
2433 constraints are used to determine the real registers used. NOTE:
2434 patterns in rl78-virt.md essentially ignore the constrains and rely on
2435 predicates, where the rl78-real.md ones essentially ignore the
2436 predicates and rely on the constraints.
2438 The devirtualization pass is scheduled via the pass manager (despite
2439 being called "rl78_reorg") so it can be scheduled prior to var-track
2440 (the idea is to let gdb know about the new registers). Ideally, it
2441 would be scheduled right after pro/epilogue generation, so the
2442 post-reload optimizers could operate on the real registers, but when I
2443 tried that there were some issues building the target libraries.
2445 During devirtualization, a simple register move optimizer is run. It
2446 would be better to run a full CSE/propogation pass on it though, but
2447 that has not yet been attempted.
2450 #define DEBUG_ALLOC 0
2452 #define OP(x) (*recog_data.operand_loc[x])
2454 /* This array is used to hold knowledge about the contents of the
2455 real registers (A ... H), the memory-based registers (r8 ... r31)
2456 and the first NUM_STACK_LOCS words on the stack. We use this to
2457 avoid generating redundant move instructions.
2459 A value in the range 0 .. 31 indicates register A .. r31.
2460 A value in the range 32 .. 63 indicates stack slot (value - 32).
2461 A value of NOT_KNOWN indicates that the contents of that location
2464 #define NUM_STACK_LOCS 32
2465 #define NOT_KNOWN 127
2467 static unsigned char content_memory
[32 + NUM_STACK_LOCS
];
2469 static unsigned char saved_update_index
= NOT_KNOWN
;
2470 static unsigned char saved_update_value
;
2471 static machine_mode saved_update_mode
;
2475 clear_content_memory (void)
2477 memset (content_memory
, NOT_KNOWN
, sizeof content_memory
);
2479 fprintf (dump_file
, " clear content memory\n");
2480 saved_update_index
= NOT_KNOWN
;
2483 /* Convert LOC into an index into the content_memory array.
2484 If LOC cannot be converted, return NOT_KNOWN. */
2486 static unsigned char
2487 get_content_index (rtx loc
)
2491 if (loc
== NULL_RTX
)
2496 if (REGNO (loc
) < 32)
2501 mode
= GET_MODE (loc
);
2503 if (! rl78_stack_based_mem (loc
, mode
))
2506 loc
= XEXP (loc
, 0);
2509 /* loc = MEM (SP) */
2512 /* loc = MEM (PLUS (SP, INT)). */
2513 loc
= XEXP (loc
, 1);
2515 if (INTVAL (loc
) < NUM_STACK_LOCS
)
2516 return 32 + INTVAL (loc
);
2521 /* Return a string describing content INDEX in mode MODE.
2522 WARNING: Can return a pointer to a static buffer. */
2524 get_content_name (unsigned char index
, machine_mode mode
)
2526 static char buffer
[128];
2528 if (index
== NOT_KNOWN
)
2532 sprintf (buffer
, "stack slot %d", index
- 32);
2533 else if (mode
== HImode
)
2534 sprintf (buffer
, "%s%s",
2535 reg_names
[index
+ 1], reg_names
[index
]);
2537 return reg_names
[index
];
2545 display_content_memory (FILE * file
)
2549 fprintf (file
, " Known memory contents:\n");
2551 for (i
= 0; i
< sizeof content_memory
; i
++)
2552 if (content_memory
[i
] != NOT_KNOWN
)
2554 fprintf (file
, " %s contains a copy of ", get_content_name (i
, QImode
));
2555 fprintf (file
, "%s\n", get_content_name (content_memory
[i
], QImode
));
2561 update_content (unsigned char index
, unsigned char val
, machine_mode mode
)
2565 gcc_assert (index
< sizeof content_memory
);
2567 content_memory
[index
] = val
;
2568 if (val
!= NOT_KNOWN
)
2569 content_memory
[val
] = index
;
2571 /* Make the entry in dump_file *before* VAL is increased below. */
2574 fprintf (dump_file
, " %s now contains ", get_content_name (index
, mode
));
2575 if (val
== NOT_KNOWN
)
2576 fprintf (dump_file
, "Unknown\n");
2578 fprintf (dump_file
, "%s and vice versa\n", get_content_name (val
, mode
));
2583 val
= val
== NOT_KNOWN
? val
: val
+ 1;
2585 content_memory
[index
+ 1] = val
;
2586 if (val
!= NOT_KNOWN
)
2588 content_memory
[val
] = index
+ 1;
2593 /* Any other places that had INDEX recorded as their contents are now invalid. */
2594 for (i
= 0; i
< sizeof content_memory
; i
++)
2597 || (val
!= NOT_KNOWN
&& i
== val
))
2604 if (content_memory
[i
] == index
2605 || (val
!= NOT_KNOWN
&& content_memory
[i
] == val
))
2607 content_memory
[i
] = NOT_KNOWN
;
2610 fprintf (dump_file
, " %s cleared\n", get_content_name (i
, mode
));
2613 content_memory
[++ i
] = NOT_KNOWN
;
2618 /* Record that LOC contains VALUE.
2619 For HImode locations record that LOC+1 contains VALUE+1.
2620 If LOC is not a register or stack slot, do nothing.
2621 If VALUE is not a register or stack slot, clear the recorded content. */
2624 record_content (rtx loc
, rtx value
)
2627 unsigned char index
;
2630 if ((index
= get_content_index (loc
)) == NOT_KNOWN
)
2633 val
= get_content_index (value
);
2635 mode
= GET_MODE (loc
);
2642 /* This should not happen when optimizing. */
2644 fprintf (stderr
, "ASSIGNMENT of location to itself detected! [%s]\n",
2645 get_content_name (val
, mode
));
2652 update_content (index
, val
, mode
);
2655 /* Returns TRUE if LOC already contains a copy of VALUE. */
2658 already_contains (rtx loc
, rtx value
)
2660 unsigned char index
;
2663 if ((index
= get_content_index (loc
)) == NOT_KNOWN
)
2666 if ((val
= get_content_index (value
)) == NOT_KNOWN
)
2669 if (content_memory
[index
] != val
)
2672 if (GET_MODE (loc
) == HImode
)
2673 return content_memory
[index
+ 1] == val
+ 1;
2679 rl78_es_addr (rtx addr
)
2681 if (GET_CODE (addr
) == MEM
)
2682 addr
= XEXP (addr
, 0);
2683 if (GET_CODE (addr
) != UNSPEC
)
2685 if (XINT (addr
, 1) != UNS_ES_ADDR
)
2691 rl78_es_base (rtx addr
)
2693 if (GET_CODE (addr
) == MEM
)
2694 addr
= XEXP (addr
, 0);
2695 addr
= XVECEXP (addr
, 0, 1);
2696 if (GET_CODE (addr
) == CONST
2697 && GET_CODE (XEXP (addr
, 0)) == ZERO_EXTRACT
)
2698 addr
= XEXP (XEXP (addr
, 0), 0);
2699 /* Mode doesn't matter here. */
2700 return gen_rtx_MEM (HImode
, addr
);
2703 /* Rescans an insn to see if it's recognized again. This is done
2704 carefully to ensure that all the constraint information is accurate
2705 for the newly matched insn. */
2707 insn_ok_now (rtx_insn
* insn
)
2709 rtx pattern
= PATTERN (insn
);
2712 INSN_CODE (insn
) = -1;
2714 if (recog (pattern
, insn
, 0) > -1)
2716 extract_insn (insn
);
2717 if (constrain_operands (1, get_preferred_alternatives (insn
)))
2720 fprintf (stderr
, "\033[32m");
2722 fprintf (stderr
, "\033[0m");
2724 if (SET_P (pattern
))
2725 record_content (SET_DEST (pattern
), SET_SRC (pattern
));
2727 /* We need to detect far addresses that haven't been
2728 converted to es/lo16 format. */
2729 for (i
=0; i
<recog_data
.n_operands
; i
++)
2730 if (GET_CODE (OP (i
)) == MEM
2731 && GET_MODE (XEXP (OP (i
), 0)) == SImode
2732 && GET_CODE (XEXP (OP (i
), 0)) != UNSPEC
)
2739 /* INSN is not OK as-is. It may not be recognized in real mode or
2740 it might not have satisfied its constraints in real mode. Either
2741 way it will require fixups.
2743 It is vital we always re-recognize at this point as some insns
2744 have fewer operands in real mode than virtual mode. If we do
2745 not re-recognize, then the recog_data will refer to real mode
2746 operands and we may read invalid data. Usually this isn't a
2747 problem, but once in a while the data we read is bogus enough
2748 to cause a segfault or other undesirable behavior. */
2751 /* We need to re-recog the insn with virtual registers to get
2753 INSN_CODE (insn
) = -1;
2754 cfun
->machine
->virt_insns_ok
= 1;
2755 if (recog (pattern
, insn
, 0) > -1)
2757 extract_insn (insn
);
2758 /* In theory this should always be true. */
2759 if (constrain_operands (0, get_preferred_alternatives (insn
)))
2761 cfun
->machine
->virt_insns_ok
= 0;
2767 fprintf (stderr
, "\033[41;30m Unrecognized *virtual* insn \033[0m\n");
2775 #define WORKED fprintf (stderr, "\033[48;5;22m Worked at line %d \033[0m\n", __LINE__)
2776 #define FAILEDSOFAR fprintf (stderr, "\033[48;5;52m FAILED at line %d \033[0m\n", __LINE__)
2777 #define FAILED fprintf (stderr, "\033[48;5;52m FAILED at line %d \033[0m\n", __LINE__), gcc_unreachable ()
2778 #define MAYBE_OK(insn) if (insn_ok_now (insn)) { WORKED; return; } else { FAILEDSOFAR; }
2779 #define MUST_BE_OK(insn) if (insn_ok_now (insn)) { WORKED; return; } FAILED
2781 #define FAILED gcc_unreachable ()
2782 #define MAYBE_OK(insn) if (insn_ok_now (insn)) return;
2783 #define MUST_BE_OK(insn) if (insn_ok_now (insn)) return; FAILED
2786 /* Registers into which we move the contents of virtual registers. */
2787 #define X gen_rtx_REG (QImode, X_REG)
2788 #define A gen_rtx_REG (QImode, A_REG)
2789 #define C gen_rtx_REG (QImode, C_REG)
2790 #define B gen_rtx_REG (QImode, B_REG)
2791 #define E gen_rtx_REG (QImode, E_REG)
2792 #define D gen_rtx_REG (QImode, D_REG)
2793 #define L gen_rtx_REG (QImode, L_REG)
2794 #define H gen_rtx_REG (QImode, H_REG)
2796 #define AX gen_rtx_REG (HImode, AX_REG)
2797 #define BC gen_rtx_REG (HImode, BC_REG)
2798 #define DE gen_rtx_REG (HImode, DE_REG)
2799 #define HL gen_rtx_REG (HImode, HL_REG)
2801 /* Returns TRUE if R is a virtual register. */
2803 is_virtual_register (rtx r
)
2805 return (GET_CODE (r
) == REG
2810 /* In all these alloc routines, we expect the following: the insn
2811 pattern is unshared, the insn was previously recognized and failed
2812 due to predicates or constraints, and the operand data is in
2815 static int virt_insn_was_frame
;
2817 /* Hook for all insns we emit. Re-mark them as FRAME_RELATED if
2820 EM2 (int line ATTRIBUTE_UNUSED
, rtx r
)
2823 fprintf (stderr
, "\033[36m%d: ", line
);
2825 fprintf (stderr
, "\033[0m");
2827 /*SCHED_GROUP_P (r) = 1;*/
2828 if (virt_insn_was_frame
)
2829 RTX_FRAME_RELATED_P (r
) = 1;
2833 #define EM(x) EM2 (__LINE__, x)
2835 /* Return a suitable RTX for the low half of a __far address. */
2837 rl78_lo16 (rtx addr
)
2841 if (GET_CODE (addr
) == SYMBOL_REF
2842 || GET_CODE (addr
) == CONST
)
2844 r
= gen_rtx_ZERO_EXTRACT (HImode
, addr
, GEN_INT (16), GEN_INT (0));
2845 r
= gen_rtx_CONST (HImode
, r
);
2848 r
= rl78_subreg (HImode
, addr
, SImode
, 0);
2850 r
= gen_es_addr (r
);
2851 cfun
->machine
->uses_es
= true;
2856 /* Return a suitable RTX for the high half's lower byte of a __far address. */
2860 if (GET_CODE (addr
) == SYMBOL_REF
2861 || GET_CODE (addr
) == CONST
)
2863 rtx r
= gen_rtx_ZERO_EXTRACT (QImode
, addr
, GEN_INT (8), GEN_INT (16));
2864 r
= gen_rtx_CONST (QImode
, r
);
2867 return rl78_subreg (QImode
, addr
, SImode
, 2);
2871 add_postponed_content_update (rtx to
, rtx value
)
2873 unsigned char index
;
2875 if ((index
= get_content_index (to
)) == NOT_KNOWN
)
2878 gcc_assert (saved_update_index
== NOT_KNOWN
);
2879 saved_update_index
= index
;
2880 saved_update_value
= get_content_index (value
);
2881 saved_update_mode
= GET_MODE (to
);
2885 process_postponed_content_update (void)
2887 if (saved_update_index
!= NOT_KNOWN
)
2889 update_content (saved_update_index
, saved_update_value
, saved_update_mode
);
2890 saved_update_index
= NOT_KNOWN
;
2894 /* Generate and emit a move of (register) FROM into TO. if WHERE is not NULL
2895 then if BEFORE is true then emit the insn before WHERE, otherwise emit it
2896 after WHERE. If TO already contains FROM then do nothing. Returns TO if
2897 BEFORE is true, FROM otherwise. */
2899 gen_and_emit_move (rtx to
, rtx from
, rtx_insn
*where
, bool before
)
2901 machine_mode mode
= GET_MODE (to
);
2903 if (optimize
&& before
&& already_contains (to
, from
))
2906 display_content_memory (stderr
);
2910 fprintf (dump_file
, " Omit move of %s into ",
2911 get_content_name (get_content_index (from
), mode
));
2912 fprintf (dump_file
, "%s as it already contains this value\n",
2913 get_content_name (get_content_index (to
), mode
));
2918 rtx move
= mode
== QImode
? gen_movqi (to
, from
) : gen_movhi (to
, from
);
2922 if (where
== NULL_RTX
)
2925 emit_insn_before (move
, where
);
2928 rtx note
= find_reg_note (where
, REG_EH_REGION
, NULL_RTX
);
2930 /* If necessary move REG_EH_REGION notes forward.
2931 cf. compiling gcc.dg/pr44545.c. */
2932 if (note
!= NULL_RTX
)
2934 add_reg_note (move
, REG_EH_REGION
, XEXP (note
, 0));
2935 remove_note (where
, note
);
2938 emit_insn_after (move
, where
);
2942 record_content (to
, from
);
2944 add_postponed_content_update (to
, from
);
2947 return before
? to
: from
;
2950 /* If M is MEM(REG) or MEM(PLUS(REG,INT)) and REG is virtual then
2951 copy it into NEWBASE and return the updated MEM. Otherwise just
2952 return M. Any needed insns are emitted before BEFORE. */
2954 transcode_memory_rtx (rtx m
, rtx newbase
, rtx_insn
*before
)
2956 rtx base
, index
, addendr
;
2963 if (GET_MODE (XEXP (m
, 0)) == SImode
)
2966 rtx seg
= rl78_hi8 (XEXP (m
, 0));
2970 emit_insn_before (EM (gen_movqi (A
, seg
)), before
);
2971 emit_insn_before (EM (gen_movqi_to_es (A
)), before
);
2974 record_content (A
, NULL_RTX
);
2976 new_m
= gen_rtx_MEM (GET_MODE (m
), rl78_lo16 (XEXP (m
, 0)));
2977 MEM_COPY_ATTRIBUTES (new_m
, m
);
2982 characterize_address (XEXP (m
, 0), & base
, & index
, & addendr
);
2983 gcc_assert (index
== NULL_RTX
);
2985 if (base
== NULL_RTX
)
2988 if (addendr
&& GET_CODE (addendr
) == CONST_INT
)
2989 addend
= INTVAL (addendr
);
2991 gcc_assert (REG_P (base
));
2992 gcc_assert (REG_P (newbase
));
2994 int limit
= 256 - GET_MODE_SIZE (GET_MODE (m
));
2996 if (REGNO (base
) == SP_REG
)
2998 if (addend
>= 0 && addend
<= limit
)
3002 /* BASE should be a virtual register. We copy it to NEWBASE. If
3003 the addend is out of range for DE/HL, we use AX to compute the full
3007 || (addend
> limit
&& REGNO (newbase
) != BC_REG
)
3009 && (GET_CODE (addendr
) != CONST_INT
)
3010 && ((REGNO (newbase
) != BC_REG
))
3016 EM (emit_insn_before (gen_movhi (AX
, base
), before
));
3017 EM (emit_insn_before (gen_addhi3 (AX
, AX
, addendr
), before
));
3018 EM (emit_insn_before (gen_movhi (newbase
, AX
), before
));
3019 record_content (AX
, NULL_RTX
);
3020 record_content (newbase
, NULL_RTX
);
3028 base
= gen_and_emit_move (newbase
, base
, before
, true);
3033 record_content (base
, NULL_RTX
);
3034 base
= gen_rtx_PLUS (HImode
, base
, GEN_INT (addend
));
3038 record_content (base
, NULL_RTX
);
3039 base
= gen_rtx_PLUS (HImode
, base
, addendr
);
3044 m
= change_address (m
, GET_MODE (m
), gen_es_addr (base
));
3045 cfun
->machine
->uses_es
= true;
3048 m
= change_address (m
, GET_MODE (m
), base
);
3052 /* Copy SRC to accumulator (A or AX), placing any generated insns
3053 before BEFORE. Returns accumulator RTX. */
3055 move_to_acc (int opno
, rtx_insn
*before
)
3057 rtx src
= OP (opno
);
3058 machine_mode mode
= GET_MODE (src
);
3060 if (REG_P (src
) && REGNO (src
) < 2)
3063 if (mode
== VOIDmode
)
3064 mode
= recog_data
.operand_mode
[opno
];
3066 return gen_and_emit_move (mode
== QImode
? A
: AX
, src
, before
, true);
3070 force_into_acc (rtx src
, rtx_insn
*before
)
3072 machine_mode mode
= GET_MODE (src
);
3075 if (REG_P (src
) && REGNO (src
) < 2)
3078 move
= mode
== QImode
? gen_movqi (A
, src
) : gen_movhi (AX
, src
);
3082 emit_insn_before (move
, before
);
3083 record_content (AX
, NULL_RTX
);
3086 /* Copy accumulator (A or AX) to DEST, placing any generated insns
3087 after AFTER. Returns accumulator RTX. */
3089 move_from_acc (unsigned int opno
, rtx_insn
*after
)
3091 rtx dest
= OP (opno
);
3092 machine_mode mode
= GET_MODE (dest
);
3094 if (REG_P (dest
) && REGNO (dest
) < 2)
3097 return gen_and_emit_move (dest
, mode
== QImode
? A
: AX
, after
, false);
3100 /* Copy accumulator (A or AX) to REGNO, placing any generated insns
3101 before BEFORE. Returns reg RTX. */
3103 move_acc_to_reg (rtx acc
, int regno
, rtx_insn
*before
)
3105 machine_mode mode
= GET_MODE (acc
);
3108 reg
= gen_rtx_REG (mode
, regno
);
3110 return gen_and_emit_move (reg
, acc
, before
, true);
3113 /* Copy SRC to X, placing any generated insns before BEFORE.
3116 move_to_x (int opno
, rtx_insn
*before
)
3118 rtx src
= OP (opno
);
3119 machine_mode mode
= GET_MODE (src
);
3122 if (mode
== VOIDmode
)
3123 mode
= recog_data
.operand_mode
[opno
];
3124 reg
= (mode
== QImode
) ? X
: AX
;
3126 if (mode
== QImode
|| ! is_virtual_register (OP (opno
)))
3128 OP (opno
) = move_to_acc (opno
, before
);
3129 OP (opno
) = move_acc_to_reg (OP (opno
), X_REG
, before
);
3133 return gen_and_emit_move (reg
, src
, before
, true);
3136 /* Copy OP (opno) to H or HL, placing any generated insns before BEFORE.
3137 Returns H/HL RTX. */
3139 move_to_hl (int opno
, rtx_insn
*before
)
3141 rtx src
= OP (opno
);
3142 machine_mode mode
= GET_MODE (src
);
3145 if (mode
== VOIDmode
)
3146 mode
= recog_data
.operand_mode
[opno
];
3147 reg
= (mode
== QImode
) ? L
: HL
;
3149 if (mode
== QImode
|| ! is_virtual_register (OP (opno
)))
3151 OP (opno
) = move_to_acc (opno
, before
);
3152 OP (opno
) = move_acc_to_reg (OP (opno
), L_REG
, before
);
3156 return gen_and_emit_move (reg
, src
, before
, true);
3159 /* Copy OP (opno) to E or DE, placing any generated insns before BEFORE.
3160 Returns E/DE RTX. */
3162 move_to_de (int opno
, rtx_insn
*before
)
3164 rtx src
= OP (opno
);
3165 machine_mode mode
= GET_MODE (src
);
3168 if (mode
== VOIDmode
)
3169 mode
= recog_data
.operand_mode
[opno
];
3171 reg
= (mode
== QImode
) ? E
: DE
;
3173 if (mode
== QImode
|| ! is_virtual_register (OP (opno
)))
3175 OP (opno
) = move_to_acc (opno
, before
);
3176 OP (opno
) = move_acc_to_reg (OP (opno
), E_REG
, before
);
3180 gen_and_emit_move (reg
, src
, before
, true);
3186 /* Devirtualize an insn of the form (SET (op) (unop (op))). */
3188 rl78_alloc_physical_registers_op1 (rtx_insn
* insn
)
3190 /* op[0] = func op[1] */
3192 /* We first try using A as the destination, then copying it
3194 if (rtx_equal_p (OP (0), OP (1)))
3197 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3201 /* If necessary, load the operands into BC and HL.
3202 Check to see if we already have OP (0) in HL
3203 and if so, swap the order.
3205 It is tempting to perform this optimization when OP(0) does
3206 not hold a MEM, but this leads to bigger code in general.
3207 The problem is that if OP(1) holds a MEM then swapping it
3208 into BC means a BC-relative load is used and these are 3
3209 bytes long vs 1 byte for an HL load. */
3211 && already_contains (HL
, XEXP (OP (0), 0)))
3213 OP (0) = transcode_memory_rtx (OP (0), HL
, insn
);
3214 OP (1) = transcode_memory_rtx (OP (1), BC
, insn
);
3218 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3219 OP (1) = transcode_memory_rtx (OP (1), HL
, insn
);
3225 OP (0) = move_from_acc (0, insn
);
3229 /* Try copying the src to acc first, then. This is for, for
3230 example, ZERO_EXTEND or NOT. */
3231 OP (1) = move_to_acc (1, insn
);
3236 /* Returns true if operand OPNUM contains a constraint of type CONSTRAINT.
3237 Assumes that the current insn has already been recognised and hence the
3238 constraint data has been filled in. */
3240 has_constraint (unsigned int opnum
, enum constraint_num constraint
)
3242 const char * p
= recog_data
.constraints
[opnum
];
3244 /* No constraints means anything is accepted. */
3245 if (p
== NULL
|| *p
== 0 || *p
== ',')
3254 len
= CONSTRAINT_LEN (c
, p
);
3255 gcc_assert (len
> 0);
3263 if (lookup_constraint (p
) == constraint
)
3271 /* Devirtualize an insn of the form (SET (op) (binop (op) (op))). */
3273 rl78_alloc_physical_registers_op2 (rtx_insn
* insn
)
3281 if (rtx_equal_p (OP (0), OP (1)))
3286 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3287 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3292 OP (1) = transcode_memory_rtx (OP (1), HL
, insn
);
3293 OP (2) = transcode_memory_rtx (OP (2), DE
, insn
);
3296 else if (rtx_equal_p (OP (0), OP (2)))
3298 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3300 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3304 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3305 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3306 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3311 prev
= prev_nonnote_nondebug_insn (insn
);
3312 if (recog_data
.constraints
[1][0] == '%'
3313 && is_virtual_register (OP (1))
3314 && ! is_virtual_register (OP (2))
3315 && ! CONSTANT_P (OP (2)))
3322 /* Make a note of whether (H)L is being used. It matters
3323 because if OP (2) also needs reloading, then we must take
3324 care not to corrupt HL. */
3325 hl_used
= reg_mentioned_p (L
, OP (0)) || reg_mentioned_p (L
, OP (1));
3327 /* If HL is not currently being used and dest == op1 then there are
3328 some possible optimizations available by reloading one of the
3329 operands into HL, before trying to use the accumulator. */
3332 && rtx_equal_p (OP (0), OP (1)))
3334 /* If op0 is a Ws1 type memory address then switching the base
3335 address register to HL might allow us to perform an in-memory
3336 operation. (eg for the INCW instruction).
3338 FIXME: Adding the move into HL is costly if this optimization is not
3339 going to work, so for now, make sure that we know that the new insn will
3340 match the requirements of the addhi3_real pattern. Really we ought to
3341 generate a candidate sequence, test that, and then install it if the
3342 results are good. */
3343 if (satisfies_constraint_Ws1 (OP (0))
3344 && has_constraint (0, CONSTRAINT_Wh1
)
3345 && (satisfies_constraint_K (OP (2)) || satisfies_constraint_L (OP (2))))
3347 rtx base
, index
, addend
, newbase
;
3349 characterize_address (XEXP (OP (0), 0), & base
, & index
, & addend
);
3350 gcc_assert (index
== NULL_RTX
);
3351 gcc_assert (REG_P (base
) && REGNO (base
) == SP_REG
);
3353 /* Ws1 addressing allows an offset of 0, Wh1 addressing requires a non-zero offset. */
3354 if (addend
!= NULL_RTX
)
3356 newbase
= gen_and_emit_move (HL
, base
, insn
, true);
3357 record_content (newbase
, NULL_RTX
);
3358 newbase
= gen_rtx_PLUS (HImode
, newbase
, addend
);
3360 OP (0) = OP (1) = change_address (OP (0), VOIDmode
, newbase
);
3362 /* We do not want to fail here as this means that
3363 we have inserted useless insns into the stream. */
3367 else if (REG_P (OP (0))
3368 && satisfies_constraint_Ws1 (OP (2))
3369 && has_constraint (2, CONSTRAINT_Wh1
))
3371 rtx base
, index
, addend
, newbase
;
3373 characterize_address (XEXP (OP (2), 0), & base
, & index
, & addend
);
3374 gcc_assert (index
== NULL_RTX
);
3375 gcc_assert (REG_P (base
) && REGNO (base
) == SP_REG
);
3377 /* Ws1 addressing allows an offset of 0, Wh1 addressing requires a non-zero offset. */
3378 if (addend
!= NULL_RTX
)
3380 gen_and_emit_move (HL
, base
, insn
, true);
3382 if (REGNO (OP (0)) != X_REG
)
3384 OP (1) = move_to_acc (1, insn
);
3385 OP (0) = move_from_acc (0, insn
);
3388 record_content (HL
, NULL_RTX
);
3389 newbase
= gen_rtx_PLUS (HImode
, HL
, addend
);
3391 OP (2) = change_address (OP (2), VOIDmode
, newbase
);
3393 /* We do not want to fail here as this means that
3394 we have inserted useless insns into the stream. */
3400 OP (0) = move_from_acc (0, insn
);
3402 tmp_id
= get_max_insn_count ();
3405 if (rtx_equal_p (OP (1), OP (2)))
3406 OP (2) = OP (1) = move_to_acc (1, insn
);
3408 OP (1) = move_to_acc (1, insn
);
3412 /* If we omitted the move of OP1 into the accumulator (because
3413 it was already there from a previous insn), then force the
3414 generation of the move instruction now. We know that we
3415 are about to emit a move into HL (or DE) via AX, and hence
3416 our optimization to remove the load of OP1 is no longer valid. */
3417 if (tmp_id
== get_max_insn_count ())
3418 force_into_acc (saved_op1
, insn
);
3420 /* We have to copy op2 to HL (or DE), but that involves AX, which
3421 already has a live value. Emit it before those insns. */
3424 first
= next_nonnote_nondebug_insn (prev
);
3426 for (first
= insn
; prev_nonnote_nondebug_insn (first
); first
= prev_nonnote_nondebug_insn (first
))
3429 OP (2) = hl_used
? move_to_de (2, first
) : move_to_hl (2, first
);
3434 /* Devirtualize an insn of the form SET (PC) (MEM/REG). */
3436 rl78_alloc_physical_registers_ro1 (rtx_insn
* insn
)
3438 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3442 OP (0) = move_to_acc (0, insn
);
3447 /* Devirtualize a compare insn. */
3449 rl78_alloc_physical_registers_cmp (rtx_insn
* insn
)
3453 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
3456 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3457 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3459 /* HI compares have to have OP (1) in AX, but QI
3460 compares do not, so it is worth checking here. */
3463 /* For an HImode compare, OP (1) must always be in AX.
3464 But if OP (1) is a REG (and not AX), then we can avoid
3465 a reload of OP (1) if we reload OP (2) into AX and invert
3468 && REGNO (OP (1)) != AX_REG
3469 && GET_MODE (OP (1)) == HImode
3472 rtx cmp
= XEXP (SET_SRC (PATTERN (insn
)), 0);
3474 OP (2) = move_to_acc (2, insn
);
3476 switch (GET_CODE (cmp
))
3481 case LTU
: cmp
= gen_rtx_GTU (HImode
, OP (2), OP (1)); break;
3482 case GTU
: cmp
= gen_rtx_LTU (HImode
, OP (2), OP (1)); break;
3483 case LEU
: cmp
= gen_rtx_GEU (HImode
, OP (2), OP (1)); break;
3484 case GEU
: cmp
= gen_rtx_LEU (HImode
, OP (2), OP (1)); break;
3497 if (GET_CODE (cmp
) == EQ
|| GET_CODE (cmp
) == NE
)
3498 PATTERN (insn
) = gen_cbranchhi4_real (cmp
, OP (2), OP (1), OP (3));
3500 PATTERN (insn
) = gen_cbranchhi4_real_inverted (cmp
, OP (2), OP (1), OP (3));
3505 /* Surprisingly, gcc can generate a comparison of a register with itself, but this
3506 should be handled by the second alternative of the cbranchhi_real pattern. */
3507 if (rtx_equal_p (OP (1), OP (2)))
3509 OP (1) = OP (2) = BC
;
3513 tmp_id
= get_max_insn_count ();
3516 OP (1) = move_to_acc (1, insn
);
3520 /* If we omitted the move of OP1 into the accumulator (because
3521 it was already there from a previous insn), then force the
3522 generation of the move instruction now. We know that we
3523 are about to emit a move into HL via AX, and hence our
3524 optimization to remove the load of OP1 is no longer valid. */
3525 if (tmp_id
== get_max_insn_count ())
3526 force_into_acc (saved_op1
, insn
);
3528 /* We have to copy op2 to HL, but that involves the acc, which
3529 already has a live value. Emit it before those insns. */
3531 first
= next_nonnote_nondebug_insn (prev
);
3533 for (first
= insn
; prev_nonnote_nondebug_insn (first
); first
= prev_nonnote_nondebug_insn (first
))
3535 OP (2) = move_to_hl (2, first
);
3540 /* Like op2, but AX = A * X. */
3542 rl78_alloc_physical_registers_umul (rtx_insn
* insn
)
3544 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
3549 OP (0) = transcode_memory_rtx (OP (0), BC
, insn
);
3550 OP (1) = transcode_memory_rtx (OP (1), DE
, insn
);
3551 OP (2) = transcode_memory_rtx (OP (2), HL
, insn
);
3555 if (recog_data
.constraints
[1][0] == '%'
3556 && is_virtual_register (OP (1))
3557 && !is_virtual_register (OP (2))
3558 && !CONSTANT_P (OP (2)))
3565 OP (0) = move_from_acc (0, insn
);
3567 tmp_id
= get_max_insn_count ();
3570 if (rtx_equal_p (OP (1), OP (2)))
3572 gcc_assert (GET_MODE (OP (2)) == QImode
);
3573 /* The MULU instruction does not support duplicate arguments
3574 but we know that if we copy OP (2) to X it will do so via
3575 A and thus OP (1) will already be loaded into A. */
3576 OP (2) = move_to_x (2, insn
);
3580 OP (1) = move_to_acc (1, insn
);
3584 /* If we omitted the move of OP1 into the accumulator (because
3585 it was already there from a previous insn), then force the
3586 generation of the move instruction now. We know that we
3587 are about to emit a move into HL (or DE) via AX, and hence
3588 our optimization to remove the load of OP1 is no longer valid. */
3589 if (tmp_id
== get_max_insn_count ())
3590 force_into_acc (saved_op1
, insn
);
3592 /* We have to copy op2 to X, but that involves the acc, which
3593 already has a live value. Emit it before those insns. */
3596 first
= next_nonnote_nondebug_insn (prev
);
3598 for (first
= insn
; prev_nonnote_nondebug_insn (first
); first
= prev_nonnote_nondebug_insn (first
))
3600 OP (2) = move_to_x (2, first
);
3606 rl78_alloc_address_registers_macax (rtx_insn
* insn
)
3609 bool replace_in_op0
= false;
3610 bool replace_in_op1
= false;
3614 /* Two different MEMs are not allowed. */
3616 for (op
= 2; op
>= 0; op
--)
3618 if (MEM_P (OP (op
)))
3620 if (op
== 0 && replace_in_op0
)
3622 if (op
== 1 && replace_in_op1
)
3628 /* If we replace a MEM, make sure that we replace it for all
3629 occurrences of the same MEM in the insn. */
3630 replace_in_op0
= (op
> 0 && rtx_equal_p (OP (op
), OP (0)));
3631 replace_in_op1
= (op
> 1 && rtx_equal_p (OP (op
), OP (1)));
3633 OP (op
) = transcode_memory_rtx (OP (op
), HL
, insn
);
3636 && ((GET_CODE (XEXP (OP (op
), 0)) == REG
3637 && REGNO (XEXP (OP (op
), 0)) == SP_REG
)
3638 || (GET_CODE (XEXP (OP (op
), 0)) == PLUS
3639 && REGNO (XEXP (XEXP (OP (op
), 0), 0)) == SP_REG
)))
3641 emit_insn_before (gen_movhi (HL
, gen_rtx_REG (HImode
, SP_REG
)), insn
);
3642 OP (op
) = replace_rtx (OP (op
), gen_rtx_REG (HImode
, SP_REG
), HL
);
3650 OP (op
) = transcode_memory_rtx (OP (op
), DE
, insn
);
3653 OP (op
) = transcode_memory_rtx (OP (op
), BC
, insn
);
3664 rl78_alloc_address_registers_div (rtx_insn
* insn
)
3669 /* Scan all insns and devirtualize them. */
3671 rl78_alloc_physical_registers (void)
3673 /* During most of the compile, gcc is dealing with virtual
3674 registers. At this point, we need to assign physical registers
3675 to the vitual ones, and copy in/out as needed. */
3677 rtx_insn
*insn
, *curr
;
3678 enum attr_valloc valloc_method
;
3680 for (insn
= get_insns (); insn
; insn
= curr
)
3684 curr
= next_nonnote_nondebug_insn (insn
);
3687 && (GET_CODE (PATTERN (insn
)) == SET
3688 || GET_CODE (PATTERN (insn
)) == CALL
)
3689 && INSN_CODE (insn
) == -1)
3691 if (GET_CODE (SET_SRC (PATTERN (insn
))) == ASM_OPERANDS
)
3693 i
= recog (PATTERN (insn
), insn
, 0);
3699 INSN_CODE (insn
) = i
;
3703 cfun
->machine
->virt_insns_ok
= 0;
3704 cfun
->machine
->real_insns_ok
= 1;
3706 clear_content_memory ();
3708 for (insn
= get_insns (); insn
; insn
= curr
)
3712 curr
= insn
? next_nonnote_nondebug_insn (insn
) : NULL
;
3717 clear_content_memory ();
3723 fprintf (dump_file
, "Converting insn %d\n", INSN_UID (insn
));
3725 pattern
= PATTERN (insn
);
3726 if (GET_CODE (pattern
) == PARALLEL
)
3727 pattern
= XVECEXP (pattern
, 0, 0);
3728 if (JUMP_P (insn
) || CALL_P (insn
) || GET_CODE (pattern
) == CALL
)
3729 clear_content_memory ();
3730 if (GET_CODE (pattern
) != SET
3731 && GET_CODE (pattern
) != CALL
)
3733 if (GET_CODE (pattern
) == SET
3734 && GET_CODE (SET_SRC (pattern
)) == ASM_OPERANDS
)
3737 valloc_method
= get_attr_valloc (insn
);
3739 PATTERN (insn
) = copy_rtx_if_shared (PATTERN (insn
));
3741 if (valloc_method
== VALLOC_MACAX
)
3743 record_content (AX
, NULL_RTX
);
3744 record_content (BC
, NULL_RTX
);
3745 record_content (DE
, NULL_RTX
);
3747 else if (valloc_method
== VALLOC_DIVHI
)
3749 record_content (AX
, NULL_RTX
);
3750 record_content (BC
, NULL_RTX
);
3752 else if (valloc_method
== VALLOC_DIVSI
)
3754 record_content (AX
, NULL_RTX
);
3755 record_content (BC
, NULL_RTX
);
3756 record_content (DE
, NULL_RTX
);
3757 record_content (HL
, NULL_RTX
);
3760 if (insn_ok_now (insn
))
3763 INSN_CODE (insn
) = -1;
3765 if (RTX_FRAME_RELATED_P (insn
))
3766 virt_insn_was_frame
= 1;
3768 virt_insn_was_frame
= 0;
3770 switch (valloc_method
)
3773 rl78_alloc_physical_registers_op1 (insn
);
3776 rl78_alloc_physical_registers_op2 (insn
);
3779 rl78_alloc_physical_registers_ro1 (insn
);
3782 rl78_alloc_physical_registers_cmp (insn
);
3785 rl78_alloc_physical_registers_umul (insn
);
3786 record_content (AX
, NULL_RTX
);
3789 /* Macro that clobbers AX. */
3790 rl78_alloc_address_registers_macax (insn
);
3791 record_content (AX
, NULL_RTX
);
3792 record_content (BC
, NULL_RTX
);
3793 record_content (DE
, NULL_RTX
);
3796 rl78_alloc_address_registers_div (insn
);
3797 record_content (AX
, NULL_RTX
);
3798 record_content (BC
, NULL_RTX
);
3799 record_content (DE
, NULL_RTX
);
3800 record_content (HL
, NULL_RTX
);
3803 rl78_alloc_address_registers_div (insn
);
3804 record_content (AX
, NULL_RTX
);
3805 record_content (BC
, NULL_RTX
);
3811 if (JUMP_P (insn
) || CALL_P (insn
) || GET_CODE (pattern
) == CALL
)
3812 clear_content_memory ();
3814 process_postponed_content_update ();
3818 fprintf (stderr
, "\033[0m");
3822 /* Add REG_DEAD notes using DEAD[reg] for rtx S which is part of INSN.
3823 This function scans for uses of registers; the last use (i.e. first
3824 encounter when scanning backwards) triggers a REG_DEAD note if the
3825 reg was previously in DEAD[]. */
3827 rl78_note_reg_uses (char *dead
, rtx s
, rtx insn
)
3836 code
= GET_CODE (s
);
3840 /* Compare registers by number. */
3845 fprintf (dump_file
, "note use reg %d size %d on insn %d\n",
3846 r
, GET_MODE_SIZE (GET_MODE (s
)), INSN_UID (insn
));
3847 print_rtl_single (dump_file
, s
);
3850 add_reg_note (insn
, REG_DEAD
, gen_rtx_REG (GET_MODE (s
), r
));
3851 for (i
= 0; i
< GET_MODE_SIZE (GET_MODE (s
)); i
++)
3855 /* These codes have no constituent expressions
3865 /* These are kept unique for a given value. */
3872 fmt
= GET_RTX_FORMAT (code
);
3874 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3879 for (j
= XVECLEN (s
, i
) - 1; j
>= 0; j
--)
3880 rl78_note_reg_uses (dead
, XVECEXP (s
, i
, j
), insn
);
3882 else if (fmt
[i
] == 'e')
3883 rl78_note_reg_uses (dead
, XEXP (s
, i
), insn
);
3887 /* Like the previous function, but scan for SETs instead. */
3889 rl78_note_reg_set (char *dead
, rtx d
, rtx insn
)
3893 if (GET_CODE (d
) == MEM
)
3894 rl78_note_reg_uses (dead
, XEXP (d
, 0), insn
);
3896 if (GET_CODE (d
) != REG
)
3899 /* Do not mark the reg unused unless all QImode parts of it are dead. */
3902 for (i
= 0; i
< GET_MODE_SIZE (GET_MODE (d
)); i
++)
3906 add_reg_note (insn
, REG_UNUSED
, gen_rtx_REG (GET_MODE (d
), r
));
3908 fprintf (dump_file
, "note set reg %d size %d\n", r
, GET_MODE_SIZE (GET_MODE (d
)));
3909 for (i
= 0; i
< GET_MODE_SIZE (GET_MODE (d
)); i
++)
3913 /* This is a rather crude register death pass. Death status is reset
3914 at every jump or call insn. */
3916 rl78_calculate_death_notes (void)
3918 char dead
[FIRST_PSEUDO_REGISTER
];
3923 memset (dead
, 0, sizeof (dead
));
3925 for (insn
= get_last_insn ();
3927 insn
= prev_nonnote_nondebug_insn (insn
))
3931 fprintf (dump_file
, "\n--------------------------------------------------");
3932 fprintf (dump_file
, "\nDead:");
3933 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3935 fprintf (dump_file
, " %s", reg_names
[i
]);
3936 fprintf (dump_file
, "\n");
3937 print_rtl_single (dump_file
, insn
);
3940 switch (GET_CODE (insn
))
3944 if (GET_CODE (p
) == PARALLEL
)
3946 rtx q
= XVECEXP (p
, 0 ,1);
3948 /* This happens with the DIV patterns. */
3949 if (GET_CODE (q
) == SET
)
3953 rl78_note_reg_set (dead
, d
, insn
);
3954 rl78_note_reg_uses (dead
, s
, insn
);
3957 p
= XVECEXP (p
, 0, 0);
3960 switch (GET_CODE (p
))
3965 rl78_note_reg_set (dead
, d
, insn
);
3966 rl78_note_reg_uses (dead
, s
, insn
);
3970 rl78_note_reg_uses (dead
, p
, insn
);
3979 if (INSN_CODE (insn
) == CODE_FOR_rl78_return
)
3981 memset (dead
, 1, sizeof (dead
));
3982 /* We expect a USE just prior to this, which will mark
3983 the actual return registers. The USE will have a
3984 death note, but we aren't going to be modifying it
3990 memset (dead
, 0, sizeof (dead
));
3997 print_rtl_single (dump_file
, insn
);
4001 /* Helper function to reset the origins in RP and the age in AGE for
4004 reset_origins (int *rp
, int *age
)
4007 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4015 set_origin (rtx pat
, rtx_insn
* insn
, int * origins
, int * age
)
4017 rtx src
= SET_SRC (pat
);
4018 rtx dest
= SET_DEST (pat
);
4019 int mb
= GET_MODE_SIZE (GET_MODE (dest
));
4022 if (GET_CODE (dest
) == REG
)
4024 int dr
= REGNO (dest
);
4026 if (GET_CODE (src
) == REG
)
4028 int sr
= REGNO (src
);
4030 int best_age
, best_reg
;
4032 /* See if the copy is not needed. */
4033 for (i
= 0; i
< mb
; i
++)
4034 if (origins
[dr
+ i
] != origins
[sr
+ i
])
4040 fprintf (dump_file
, "deleting because dest already has correct value\n");
4045 if (dr
< 8 || sr
>= 8)
4052 /* See if the copy can be made from another
4053 bank 0 register instead, instead of the
4054 virtual src register. */
4055 for (ar
= 0; ar
< 8; ar
+= mb
)
4059 for (i
= 0; i
< mb
; i
++)
4060 if (origins
[ar
+ i
] != origins
[sr
+ i
])
4063 /* The chip has some reg-reg move limitations. */
4064 if (mb
== 1 && dr
> 3)
4069 if (best_age
== -1 || best_age
> age
[sr
+ i
])
4071 best_age
= age
[sr
+ i
];
4079 /* FIXME: copy debug info too. */
4080 SET_SRC (pat
) = gen_rtx_REG (GET_MODE (src
), best_reg
);
4085 for (i
= 0; i
< mb
; i
++)
4087 origins
[dr
+ i
] = origins
[sr
+ i
];
4088 age
[dr
+ i
] = age
[sr
+ i
] + 1;
4093 /* The destination is computed, its origin is itself. */
4095 fprintf (dump_file
, "resetting origin of r%d for %d byte%s\n",
4096 dr
, mb
, mb
== 1 ? "" : "s");
4098 for (i
= 0; i
< mb
; i
++)
4100 origins
[dr
+ i
] = dr
+ i
;
4105 /* Any registers marked with that reg as an origin are reset. */
4106 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4107 if (origins
[i
] >= dr
&& origins
[i
] < dr
+ mb
)
4114 /* Special case - our MUL patterns uses AX and sometimes BC. */
4115 if (get_attr_valloc (insn
) == VALLOC_MACAX
)
4118 fprintf (dump_file
, "Resetting origin of AX/BC for MUL pattern.\n");
4120 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4121 if (i
<= 3 || origins
[i
] <= 3)
4127 else if (get_attr_valloc (insn
) == VALLOC_DIVHI
)
4130 fprintf (dump_file
, "Resetting origin of AX/DE for DIVHI pattern.\n");
4132 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4137 || origins
[i
] == A_REG
4138 || origins
[i
] == X_REG
4139 || origins
[i
] == D_REG
4140 || origins
[i
] == E_REG
)
4146 else if (get_attr_valloc (insn
) == VALLOC_DIVSI
)
4149 fprintf (dump_file
, "Resetting origin of AX/BC/DE/HL for DIVSI pattern.\n");
4151 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4152 if (i
<= 7 || origins
[i
] <= 7)
4159 if (GET_CODE (src
) == ASHIFT
4160 || GET_CODE (src
) == ASHIFTRT
4161 || GET_CODE (src
) == LSHIFTRT
)
4163 rtx count
= XEXP (src
, 1);
4165 if (GET_CODE (count
) == REG
)
4167 /* Special case - our pattern clobbers the count register. */
4168 int r
= REGNO (count
);
4171 fprintf (dump_file
, "Resetting origin of r%d for shift.\n", r
);
4173 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4174 if (i
== r
|| origins
[i
] == r
)
4183 /* The idea behind this optimization is to look for cases where we
4184 move data from A to B to C, and instead move from A to B, and A to
4185 C. If B is a virtual register or memory, this is a big win on its
4186 own. If B turns out to be unneeded after this, it's a bigger win.
4187 For each register, we try to determine where it's value originally
4188 came from, if it's propogated purely through moves (and not
4189 computes). The ORIGINS[] array has the regno for the "origin" of
4190 the value in the [regno] it's indexed by. */
4192 rl78_propogate_register_origins (void)
4194 int origins
[FIRST_PSEUDO_REGISTER
];
4195 int age
[FIRST_PSEUDO_REGISTER
];
4197 rtx_insn
*insn
, *ninsn
= NULL
;
4200 reset_origins (origins
, age
);
4202 for (insn
= get_insns (); insn
; insn
= ninsn
)
4204 ninsn
= next_nonnote_nondebug_insn (insn
);
4208 fprintf (dump_file
, "\n");
4209 fprintf (dump_file
, "Origins:");
4210 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4211 if (origins
[i
] != i
)
4212 fprintf (dump_file
, " r%d=r%d", i
, origins
[i
]);
4213 fprintf (dump_file
, "\n");
4214 print_rtl_single (dump_file
, insn
);
4217 switch (GET_CODE (insn
))
4223 reset_origins (origins
, age
);
4230 pat
= PATTERN (insn
);
4232 if (GET_CODE (pat
) == PARALLEL
)
4234 rtx clobber
= XVECEXP (pat
, 0, 1);
4235 pat
= XVECEXP (pat
, 0, 0);
4236 if (GET_CODE (clobber
) == CLOBBER
4237 && GET_CODE (XEXP (clobber
, 0)) == REG
)
4239 int cr
= REGNO (XEXP (clobber
, 0));
4240 int mb
= GET_MODE_SIZE (GET_MODE (XEXP (clobber
, 0)));
4242 fprintf (dump_file
, "reset origins of %d regs at %d\n", mb
, cr
);
4243 for (i
= 0; i
< mb
; i
++)
4245 origins
[cr
+ i
] = cr
+ i
;
4249 /* This happens with the DIV patterns. */
4250 else if (GET_CODE (clobber
) == SET
)
4252 set_origin (clobber
, insn
, origins
, age
);
4258 if (GET_CODE (pat
) == SET
)
4260 set_origin (pat
, insn
, origins
, age
);
4262 else if (GET_CODE (pat
) == CLOBBER
4263 && GET_CODE (XEXP (pat
, 0)) == REG
)
4265 if (REG_P (XEXP (pat
, 0)))
4267 unsigned int reg
= REGNO (XEXP (pat
, 0));
4277 /* Remove any SETs where the destination is unneeded. */
4279 rl78_remove_unused_sets (void)
4281 rtx_insn
*insn
, *ninsn
= NULL
;
4284 for (insn
= get_insns (); insn
; insn
= ninsn
)
4286 ninsn
= next_nonnote_nondebug_insn (insn
);
4288 rtx set
= single_set (insn
);
4292 dest
= SET_DEST (set
);
4294 if (GET_CODE (dest
) != REG
|| REGNO (dest
) > 23)
4297 if (find_regno_note (insn
, REG_UNUSED
, REGNO (dest
)))
4300 fprintf (dump_file
, "deleting because the set register is never used.\n");
4306 /* This is the top of the devritualization pass. */
4310 /* split2 only happens when optimizing, but we need all movSIs to be
4315 rl78_alloc_physical_registers ();
4319 fprintf (dump_file
, "\n================DEVIRT:=AFTER=ALLOC=PHYSICAL=REGISTERS================\n");
4320 print_rtl_with_bb (dump_file
, get_insns (), TDF_NONE
);
4323 rl78_propogate_register_origins ();
4324 rl78_calculate_death_notes ();
4328 fprintf (dump_file
, "\n================DEVIRT:=AFTER=PROPOGATION=============================\n");
4329 print_rtl_with_bb (dump_file
, get_insns (), TDF_NONE
);
4330 fprintf (dump_file
, "\n======================================================================\n");
4333 rl78_remove_unused_sets ();
4335 /* The code after devirtualizing has changed so much that at this point
4336 we might as well just rescan everything. Note that
4337 df_rescan_all_insns is not going to help here because it does not
4338 touch the artificial uses and defs. */
4339 df_finish_pass (true);
4341 df_live_add_problem ();
4342 df_scan_alloc (NULL
);
4349 #undef TARGET_RETURN_IN_MEMORY
4350 #define TARGET_RETURN_IN_MEMORY rl78_return_in_memory
4353 rl78_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
4355 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
4356 return (size
== -1 || size
> 8);
4360 #undef TARGET_RTX_COSTS
4361 #define TARGET_RTX_COSTS rl78_rtx_costs
4364 rl78_rtx_costs (rtx x
,
4366 int outer_code ATTRIBUTE_UNUSED
,
4367 int opno ATTRIBUTE_UNUSED
,
4369 bool speed ATTRIBUTE_UNUSED
)
4371 int code
= GET_CODE (x
);
4373 if (code
== IF_THEN_ELSE
)
4375 *total
= COSTS_N_INSNS (10);
4381 if (code
== MULT
&& ! speed
)
4383 * total
= COSTS_N_INSNS (8);
4395 /* If we are compiling for space then we do not want to use the
4396 inline SImode multiplication patterns or shift sequences.
4397 The cost is not set to 1 or 5 however as we have to allow for
4398 the possibility that we might be converting a leaf function
4399 into a non-leaf function. (There is no way to tell here).
4400 A value of 13 seems to be a reasonable compromise for the
4402 * total
= COSTS_N_INSNS (13);
4403 else if (RL78_MUL_G14
)
4404 *total
= COSTS_N_INSNS (14);
4405 else if (RL78_MUL_G13
)
4406 *total
= COSTS_N_INSNS (29);
4408 *total
= COSTS_N_INSNS (500);
4412 *total
= COSTS_N_INSNS (8);
4418 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4420 switch (INTVAL (XEXP (x
, 1)))
4422 case 0: *total
= COSTS_N_INSNS (0); break;
4423 case 1: *total
= COSTS_N_INSNS (6); break;
4424 case 2: case 3: case 4: case 5: case 6: case 7:
4425 *total
= COSTS_N_INSNS (10); break;
4426 case 8: *total
= COSTS_N_INSNS (6); break;
4427 case 9: case 10: case 11: case 12: case 13: case 14: case 15:
4428 *total
= COSTS_N_INSNS (10); break;
4429 case 16: *total
= COSTS_N_INSNS (3); break;
4430 case 17: case 18: case 19: case 20: case 21: case 22: case 23:
4431 *total
= COSTS_N_INSNS (4); break;
4432 case 24: *total
= COSTS_N_INSNS (4); break;
4433 case 25: case 26: case 27: case 28: case 29: case 30: case 31:
4434 *total
= COSTS_N_INSNS (5); break;
4438 *total
= COSTS_N_INSNS (10+4*16);
4449 static GTY(()) section
* saddr_section
;
4450 static GTY(()) section
* frodata_section
;
4453 rl78_saddr_p (rtx x
)
4459 if (GET_CODE (x
) == PLUS
)
4461 if (GET_CODE (x
) != SYMBOL_REF
)
4465 if (memcmp (c
, "@s.", 3) == 0)
4476 if (GET_CODE (x
) != CONST_INT
)
4479 if ((INTVAL (x
) & 0xFF00) != 0xFF00)
4485 #undef TARGET_STRIP_NAME_ENCODING
4486 #define TARGET_STRIP_NAME_ENCODING rl78_strip_name_encoding
4489 rl78_strip_name_encoding (const char * sym
)
4495 else if (*sym
== '@' && sym
[2] == '.')
4502 /* Like rl78_strip_name_encoding, but does not strip leading asterisks. This
4503 is important if the stripped name is going to be passed to assemble_name()
4504 as that handles asterisk prefixed names in a special manner. */
4507 rl78_strip_nonasm_name_encoding (const char * sym
)
4511 if (*sym
== '@' && sym
[2] == '.')
4520 rl78_attrlist_to_encoding (tree list
, tree decl ATTRIBUTE_UNUSED
)
4524 if (is_attribute_p ("saddr", TREE_PURPOSE (list
)))
4526 list
= TREE_CHAIN (list
);
4532 #define RL78_ATTRIBUTES(decl) \
4533 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
4534 : DECL_ATTRIBUTES (decl) \
4535 ? (DECL_ATTRIBUTES (decl)) \
4536 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
4538 #undef TARGET_ENCODE_SECTION_INFO
4539 #define TARGET_ENCODE_SECTION_INFO rl78_encode_section_info
4542 rl78_encode_section_info (tree decl
, rtx rtl
, int first
)
4545 const char * oldname
;
4550 tree rl78_attributes
;
4555 rtlname
= XEXP (rtl
, 0);
4557 if (GET_CODE (rtlname
) == SYMBOL_REF
)
4558 oldname
= XSTR (rtlname
, 0);
4559 else if (GET_CODE (rtlname
) == MEM
4560 && GET_CODE (XEXP (rtlname
, 0)) == SYMBOL_REF
)
4561 oldname
= XSTR (XEXP (rtlname
, 0), 0);
4565 type
= TREE_TYPE (decl
);
4566 if (type
== error_mark_node
)
4568 if (! DECL_P (decl
))
4570 rl78_attributes
= RL78_ATTRIBUTES (decl
);
4572 encoding
= rl78_attrlist_to_encoding (rl78_attributes
, decl
);
4576 newname
= (char *) alloca (strlen (oldname
) + 4);
4577 sprintf (newname
, "@%c.%s", encoding
, oldname
);
4578 idp
= get_identifier (newname
);
4580 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
4581 SYMBOL_REF_WEAK (XEXP (rtl
, 0)) = DECL_WEAK (decl
);
4582 SET_SYMBOL_REF_DECL (XEXP (rtl
, 0), decl
);
4586 #undef TARGET_ASM_INIT_SECTIONS
4587 #define TARGET_ASM_INIT_SECTIONS rl78_asm_init_sections
4590 rl78_asm_init_sections (void)
4593 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
4594 "\t.section .saddr,\"aw\",@progbits");
4596 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
4597 "\t.section .frodata,\"aw\",@progbits");
4600 #undef TARGET_ASM_SELECT_SECTION
4601 #define TARGET_ASM_SELECT_SECTION rl78_select_section
4604 rl78_select_section (tree decl
,
4606 unsigned HOST_WIDE_INT align
)
4610 switch (TREE_CODE (decl
))
4613 if (!TREE_READONLY (decl
)
4614 || TREE_SIDE_EFFECTS (decl
)
4615 || !DECL_INITIAL (decl
)
4616 || (DECL_INITIAL (decl
) != error_mark_node
4617 && !TREE_CONSTANT (DECL_INITIAL (decl
))))
4621 if (! TREE_CONSTANT (decl
))
4629 if (TREE_CODE (decl
) == VAR_DECL
)
4631 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
4633 if (name
[0] == '@' && name
[2] == '.')
4637 return saddr_section
;
4640 if (TYPE_ADDR_SPACE (TREE_TYPE (decl
)) == ADDR_SPACE_FAR
4643 return frodata_section
;
4648 return TARGET_ES0
? frodata_section
: readonly_data_section
;
4650 switch (categorize_decl_for_section (decl
, reloc
))
4652 case SECCAT_TEXT
: return text_section
;
4653 case SECCAT_DATA
: return data_section
;
4654 case SECCAT_BSS
: return bss_section
;
4655 case SECCAT_RODATA
: return TARGET_ES0
? frodata_section
: readonly_data_section
;
4657 return default_select_section (decl
, reloc
, align
);
4662 rl78_output_labelref (FILE *file
, const char *str
)
4666 str2
= targetm
.strip_name_encoding (str
);
4668 fputs (user_label_prefix
, file
);
4673 rl78_output_aligned_common (FILE *stream
,
4674 tree decl ATTRIBUTE_UNUSED
,
4676 int size
, int align
, int global
)
4678 /* We intentionally don't use rl78_section_tag() here. */
4679 if (name
[0] == '@' && name
[2] == '.')
4681 const char *sec
= 0;
4685 switch_to_section (saddr_section
);
4694 while (align
> BITS_PER_UNIT
)
4699 name2
= targetm
.strip_name_encoding (name
);
4701 fprintf (stream
, "\t.global\t_%s\n", name2
);
4702 fprintf (stream
, "\t.p2align %d\n", p2align
);
4703 fprintf (stream
, "\t.type\t_%s,@object\n", name2
);
4704 fprintf (stream
, "\t.size\t_%s,%d\n", name2
, size
);
4705 fprintf (stream
, "_%s:\n\t.zero\t%d\n", name2
, size
);
4712 fprintf (stream
, "\t.local\t");
4713 assemble_name (stream
, name
);
4714 fprintf (stream
, "\n");
4716 fprintf (stream
, "\t.comm\t");
4717 assemble_name (stream
, name
);
4718 fprintf (stream
, ",%u,%u\n", size
, align
/ BITS_PER_UNIT
);
4721 #undef TARGET_INSERT_ATTRIBUTES
4722 #define TARGET_INSERT_ATTRIBUTES rl78_insert_attributes
4725 rl78_insert_attributes (tree decl
, tree
*attributes ATTRIBUTE_UNUSED
)
4729 && TREE_READONLY (decl
)
4730 && TREE_ADDRESSABLE (decl
)
4731 && TYPE_ADDR_SPACE (TREE_TYPE (decl
)) == ADDR_SPACE_GENERIC
)
4733 tree type
= TREE_TYPE (decl
);
4734 tree attr
= TYPE_ATTRIBUTES (type
);
4735 int q
= TYPE_QUALS_NO_ADDR_SPACE (type
) | ENCODE_QUAL_ADDR_SPACE (ADDR_SPACE_FAR
);
4737 TREE_TYPE (decl
) = build_type_attribute_qual_variant (type
, attr
, q
);
4741 #undef TARGET_ASM_INTEGER
4742 #define TARGET_ASM_INTEGER rl78_asm_out_integer
4745 rl78_asm_out_integer (rtx x
, unsigned int size
, int aligned_p
)
4747 if (default_assemble_integer (x
, size
, aligned_p
))
4752 assemble_integer_with_op (".long\t", x
);
4759 #undef TARGET_UNWIND_WORD_MODE
4760 #define TARGET_UNWIND_WORD_MODE rl78_unwind_word_mode
4762 static scalar_int_mode
4763 rl78_unwind_word_mode (void)
4768 #ifndef USE_COLLECT2
4769 #undef TARGET_ASM_CONSTRUCTOR
4770 #define TARGET_ASM_CONSTRUCTOR rl78_asm_constructor
4771 #undef TARGET_ASM_DESTRUCTOR
4772 #define TARGET_ASM_DESTRUCTOR rl78_asm_destructor
4775 rl78_asm_ctor_dtor (rtx symbol
, int priority
, bool is_ctor
)
4779 if (priority
!= DEFAULT_INIT_PRIORITY
)
4781 /* This section of the function is based upon code copied
4782 from: gcc/varasm.cc:get_cdtor_priority_section(). */
4785 sprintf (buf
, "%s.%.5u", is_ctor
? ".ctors" : ".dtors",
4786 MAX_INIT_PRIORITY
- priority
);
4787 sec
= get_section (buf
, 0, NULL
);
4790 sec
= is_ctor
? ctors_section
: dtors_section
;
4792 assemble_addr_to_section (symbol
, sec
);
4796 rl78_asm_constructor (rtx symbol
, int priority
)
4798 rl78_asm_ctor_dtor (symbol
, priority
, true);
4802 rl78_asm_destructor (rtx symbol
, int priority
)
4804 rl78_asm_ctor_dtor (symbol
, priority
, false);
4806 #endif /* ! USE_COLLECT2 */
4808 /* Scan backwards through the insn chain looking to see if the flags
4809 have been set for a comparison of OP against OPERAND. Start with
4810 the insn *before* the current insn. */
4813 rl78_flags_already_set (rtx op
, rtx operand
)
4815 /* We only track the Z flag. */
4816 if (GET_CODE (op
) != EQ
&& GET_CODE (op
) != NE
)
4819 /* This should not happen, but let's be paranoid. */
4820 if (current_output_insn
== NULL_RTX
)
4826 for (insn
= prev_nonnote_nondebug_insn (current_output_insn
);
4828 insn
= prev_nonnote_nondebug_insn (insn
))
4833 if (! INSN_P (insn
))
4836 /* Make sure that the insn can be recognized. */
4837 if (recog_memoized (insn
) == -1)
4840 enum attr_update_Z updated
= get_attr_update_Z (insn
);
4842 rtx set
= single_set (insn
);
4843 bool must_break
= (set
!= NULL_RTX
&& rtx_equal_p (operand
, SET_DEST (set
)));
4849 case UPDATE_Z_CLOBBER
:
4852 case UPDATE_Z_UPDATE_Z
:
4864 /* We have to re-recognize the current insn as the call(s) to
4865 get_attr_update_Z() above will have overwritten the recog_data cache. */
4866 recog_memoized (current_output_insn
);
4867 cleanup_subreg_operands (current_output_insn
);
4868 constrain_operands_cached (current_output_insn
, 1);
4874 rl78_addsi3_internal (rtx
* operands
, unsigned int alternative
)
4876 const char *addH2
= "addw ax, %H2\n\t";
4878 /* If we are adding in a constant symbolic address when -mes0
4879 is active then we know that the address must be <64K and
4880 that it is invalid to access anything above 64K relative to
4881 this address. So we can skip adding in the high bytes. */
4883 && GET_CODE (operands
[2]) == SYMBOL_REF
4884 && VAR_P (SYMBOL_REF_DECL (operands
[2]))
4885 && TREE_READONLY (SYMBOL_REF_DECL (operands
[2]))
4886 && ! TREE_SIDE_EFFECTS (SYMBOL_REF_DECL (operands
[2])))
4887 return "movw ax, %h1\n\taddw ax, %h2\n\tmovw %h0, ax";
4889 if(CONST_INT_P(operands
[2]))
4891 if((INTVAL(operands
[2]) & 0xFFFF0000) == 0)
4895 else if((INTVAL(operands
[2]) & 0xFFFF0000) == 0x00010000)
4897 addH2
= "incw ax\n\t";
4899 else if((INTVAL(operands
[2]) & 0xFFFF0000) == 0xFFFF0000)
4901 addH2
= "decw ax\n\t";
4905 switch (alternative
)
4909 snprintf(fmt_buffer
, sizeof(fmt_buffer
),
4910 "movw ax, %%h1\n\taddw ax, %%h2\n\tmovw %%h0, ax\n\tmovw ax, %%H1\n\tsknc\n\tincw ax\n\t%smovw %%H0,ax", addH2
);
4913 snprintf(fmt_buffer
, sizeof(fmt_buffer
),
4914 "movw ax, %%h1\n\taddw ax, %%h2\n\tmovw bc, ax\n\tmovw ax, %%H1\n\tsknc\n\tincw ax\n\t%smovw %%H0, ax\n\tmovw ax, bc\n\tmovw %%h0, ax", addH2
);
4924 rl78_emit_libcall (const char *name
, enum rtx_code code
,
4925 enum machine_mode dmode
, enum machine_mode smode
,
4926 int noperands
, rtx
*operands
)
4934 libcall
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4939 ret
= emit_library_call_value (libcall
, NULL_RTX
, LCT_CONST
,
4940 dmode
, operands
[1], smode
);
4941 equiv
= gen_rtx_fmt_e (code
, dmode
, operands
[1]);
4945 ret
= emit_library_call_value (libcall
, NULL_RTX
,
4947 operands
[1], smode
, operands
[2],
4949 equiv
= gen_rtx_fmt_ee (code
, dmode
, operands
[1], operands
[2]);
4956 insns
= get_insns ();
4958 emit_libcall_block (insns
, operands
[0], ret
, equiv
);
4963 #undef TARGET_PREFERRED_RELOAD_CLASS
4964 #define TARGET_PREFERRED_RELOAD_CLASS rl78_preferred_reload_class
4967 rl78_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
4969 if (rclass
== NO_REGS
)
4976 struct gcc_target targetm
= TARGET_INITIALIZER
;
4978 #include "gt-rl78.h"