gcc/config/rl78/rl78.h

   1 /* GCC backend definitions for the Renesas RL78 processor.
   2    Copyright (C) 2011-2013 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20 \f
  21
  22 #define RL78_MUL_NONE   (rl78_mul_type == MUL_NONE)
  23 #define RL78_MUL_RL78   (rl78_mul_type == MUL_RL78)
  24 #define RL78_MUL_G13    (rl78_mul_type == MUL_G13)
  25
  26 #define TARGET_CPU_CPP_BUILTINS()               \
  27   do                                            \
  28     {                                           \
  29       builtin_define ("__RL78__");              \
  30       builtin_assert ("cpu=RL78");              \
  31       if (RL78_MUL_RL78)                        \
  32         builtin_define ("__RL78_MUL_RL78__");   \
  33       if (RL78_MUL_G13)                         \
  34         builtin_define ("__RL78_MUL_G13__");    \
  35       if (TARGET_G10)                           \
  36         builtin_define ("__RL78_G10__");        \
  37     }                                           \
  38   while (0)
  39
  40 #undef  STARTFILE_SPEC
  41 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
  42
  43 #undef  ENDFILE_SPEC
  44 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  45
  46 #undef  ASM_SPEC
  47 #define ASM_SPEC "\
  48 %{mrelax:-relax} \
  49 %{mg10} \
  50 "
  51
  52 #undef  LINK_SPEC
  53 #define LINK_SPEC "\
  54 %{mrelax:-relax} \
  55 "
  56
  57 #undef  LIB_SPEC
  58 #define LIB_SPEC "                                      \
  59 --start-group                                           \
  60 -lc                                                     \
  61 -lsim                                                   \
  62 %{fprofile-arcs|fprofile-generate|coverage:-lgcov}      \
  63 --end-group                                             \
  64 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}}         \
  65 "
  66 \f
  67
  68 #define BITS_BIG_ENDIAN                 0
  69 #define BYTES_BIG_ENDIAN                0
  70 #define WORDS_BIG_ENDIAN                0
  71
  72 #ifdef IN_LIBGCC2
  73 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits).  */
  74 #define UNITS_PER_WORD                  4
  75 /* We have a problem with libgcc2.  It only defines two versions of
  76    each function, one for "int" and one for "long long".  Ie it assumes
  77    that "sizeof (int) == sizeof (long)".  For the RL78 this is not true
  78    and we need a third set of functions.  We explicitly define
  79    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
  80    to get the SI and DI versions from the libgcc2.c sources, and we
  81    provide our own set of HI functions, which is why this
  82    definition is surrounded by #ifndef..#endif.  */
  83 #ifndef LIBGCC2_UNITS_PER_WORD
  84 #define LIBGCC2_UNITS_PER_WORD          4
  85 #endif
  86 #else
  87 /* Actual width of a word, in units (bytes).  */
  88 #define UNITS_PER_WORD                  1
  89 #endif
  90
  91 #define SHORT_TYPE_SIZE                 16
  92 #define INT_TYPE_SIZE                   16
  93 #define LONG_TYPE_SIZE                  32
  94 #define LONG_LONG_TYPE_SIZE             64
  95
  96 #define FLOAT_TYPE_SIZE                 32
  97 #define DOUBLE_TYPE_SIZE                32 /*64*/
  98 #define LONG_DOUBLE_TYPE_SIZE           64 /*DOUBLE_TYPE_SIZE*/
  99
 100 #define LIBGCC2_HAS_DF_MODE             1
 101 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE   64
 102
 103 #define DEFAULT_SIGNED_CHAR             0
 104
 105 #define STRICT_ALIGNMENT                1
 106 #define FUNCTION_BOUNDARY               8
 107 #define BIGGEST_ALIGNMENT               16
 108 #define STACK_BOUNDARY                  16
 109 #define PARM_BOUNDARY                   16
 110
 111 #define STACK_GROWS_DOWNWARD            1
 112 #define FRAME_GROWS_DOWNWARD            1
 113 #define FIRST_PARM_OFFSET(FNDECL)       0
 114
 115 #define MAX_REGS_PER_ADDRESS            1
 116
 117 #define Pmode                           HImode
 118 #define POINTER_SIZE                    16
 119 #undef  SIZE_TYPE
 120 #define SIZE_TYPE                       "unsigned int"
 121 #undef  PTRDIFF_TYPE
 122 #define PTRDIFF_TYPE                    "int"
 123 #undef  WCHAR_TYPE
 124 #define WCHAR_TYPE                      "long int"
 125 #undef  WCHAR_TYPE_SIZE
 126 #define WCHAR_TYPE_SIZE                 BITS_PER_WORD
 127 #define POINTERS_EXTEND_UNSIGNED        1
 128 #define FUNCTION_MODE                   HImode
 129 #define CASE_VECTOR_MODE                Pmode
 130 #define WORD_REGISTER_OPERATIONS        0
 131 #define HAS_LONG_COND_BRANCH            0
 132 #define HAS_LONG_UNCOND_BRANCH          0
 133
 134 #define MOVE_MAX                        2
 135 #define STARTING_FRAME_OFFSET           0
 136
 137 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)   1
 138
 139 #define ADDR_SPACE_FAR  1
 140
 141 #define HAVE_PRE_DECCREMENT             0
 142 #define HAVE_POST_INCREMENT             0
 143
 144 #define MOVE_RATIO(SPEED)               ((SPEED) ? 24 : 16)
 145 #define SLOW_BYTE_ACCESS                0
 146
 147 #define STORE_FLAG_VALUE                1
 148 #define LOAD_EXTEND_OP(MODE)            ZERO_EXTEND
 149 #define SHORT_IMMEDIATES_SIGN_EXTEND    0
 150 \f
 151
 152 /* The RL78 has four register banks.  Normal operation uses RB0 as
 153    real registers, RB1 and RB2 as "virtual" registers (because we know
 154    they'll be there, and not used as variables), and RB3 is reserved
 155    for interrupt handlers.  The virtual registers are accessed as
 156    SADDRs:
 157
 158    FFEE0-FFEE7 RB0
 159    FFEE8-FFEEF RB1
 160    FFEF0-FFEF7 RB2
 161    FFEF8-FFEFF RB3
 162 */
 163 #define REGISTER_NAMES                                          \
 164   {                                                             \
 165     "x", "a", "c", "b", "e", "d", "l", "h",                     \
 166     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",       \
 167     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",     \
 168     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",     \
 169       "sp", "ap", "psw", "es", "cs"                             \
 170   }
 171
 172 #define ADDITIONAL_REGISTER_NAMES       \
 173 {                                       \
 174 { "ax", 0 }, \
 175 { "bc", 2 }, \
 176 { "de", 4 }, \
 177 { "hl", 6 }, \
 178 { "rp0", 0 }, \
 179 { "rp1", 2 }, \
 180 { "rp2", 4 }, \
 181 { "rp3", 6 }, \
 182 { "r0", 0 }, \
 183 { "r1", 1 }, \
 184 { "r2", 2 }, \
 185 { "r3", 3 }, \
 186 { "r4", 4 }, \
 187 { "r5", 5 }, \
 188 { "r6", 6 }, \
 189 { "r7", 7 }, \
 190 }
 191
 192 enum reg_class
 193 {
 194   NO_REGS,                      /* No registers in set.  */
 195   XREG,
 196   AREG,
 197   AXREG,
 198   CREG,
 199   BREG,
 200   BCREG,
 201   EREG,
 202   DREG,
 203   DEREG,
 204   LREG,
 205   HREG,
 206   HLREG,
 207   IDX_REGS,
 208   QI_REGS,
 209   SPREG,
 210   R8W_REGS,
 211   R10W_REGS,
 212   INT_REGS,
 213   V_REGS,                       /* Virtual registers.  */
 214   GR_REGS,                      /* Integer registers.  */
 215   PSWREG,
 216   ALL_REGS,                     /* All registers.  */
 217   LIM_REG_CLASSES               /* Max value + 1.  */
 218 };
 219
 220 #define REG_CLASS_NAMES                                 \
 221 {                                                       \
 222   "NO_REGS",                                            \
 223   "XREG",                                               \
 224   "AREG",                                               \
 225   "AXREG",                                              \
 226   "CREG",                                               \
 227   "BREG",                                               \
 228   "BCREG",                                              \
 229   "EREG",                                               \
 230   "DREG",                                               \
 231   "DEREG",                                              \
 232   "LREG",                                               \
 233   "HREG",                                               \
 234   "HLREG",                                              \
 235   "IDX_REGS",                                           \
 236   "QI_REGS",                                            \
 237   "SPREG",                                              \
 238   "R8W_REGS",                                           \
 239   "R10W_REGS",                                          \
 240   "INT_REGS",                                           \
 241   "V_REGS",                                             \
 242   "GR_REGS",                                            \
 243   "PSWREG",                                             \
 244   "ALL_REGS"                                            \
 245 }
 246
 247 #define REG_CLASS_CONTENTS                              \
 248 {                                                       \
 249   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 250   { 0x00000001, 0x00000000 }, \
 251   { 0x00000002, 0x00000000 }, \
 252   { 0x00000003, 0x00000000 }, \
 253   { 0x00000004, 0x00000000 }, \
 254   { 0x00000008, 0x00000000 }, \
 255   { 0x0000000c, 0x00000000 }, \
 256   { 0x00000010, 0x00000000 }, \
 257   { 0x00000020, 0x00000000 }, \
 258   { 0x00000030, 0x00000000 }, \
 259   { 0x00000040, 0x00000000 }, \
 260   { 0x00000080, 0x00000000 }, \
 261   { 0x000000c0, 0x00000000 }, \
 262   { 0x0000000c, 0x00000000 },   /* B and C - index regs.  */    \
 263   { 0x000000ff, 0x00000000 },   /* all real registers.  */      \
 264   { 0x00000000, 0x00000001 },   /* SP */                        \
 265   { 0x00000300, 0x00000000 },   /* R8 - HImode */               \
 266   { 0x00000c00, 0x00000000 },   /* R10 - HImode */              \
 267   { 0xff000000, 0x00000000 },   /* INT - HImode */              \
 268   { 0xff7fff00, 0x00000000 },   /* Virtual registers.  */       \
 269   { 0xff7fffff, 0x00000002 },   /* General registers.  */       \
 270   { 0x04000000, 0x00000004 },   /* PSW.  */     \
 271   { 0xff7fffff, 0x0000001f }    /* All registers.  */           \
 272 }
 273
 274 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 275 #define N_REG_CLASSES                   (int) LIM_REG_CLASSES
 276 #define CLASS_MAX_NREGS(CLASS, MODE)    ((GET_MODE_SIZE (MODE) \
 277                                           + UNITS_PER_WORD - 1) \
 278                                          / UNITS_PER_WORD)
 279
 280 #define GENERAL_REGS                    GR_REGS
 281 #define BASE_REG_CLASS                  V_REGS
 282 #define INDEX_REG_CLASS                 V_REGS
 283
 284 #define FIRST_PSEUDO_REGISTER           37
 285
 286 #define REGNO_REG_CLASS(REGNO)          ((REGNO) < FIRST_PSEUDO_REGISTER \
 287                                          ? GR_REGS : NO_REGS)
 288
 289 #define FRAME_POINTER_REGNUM            22
 290 #define STACK_POINTER_REGNUM            32
 291 #define ARG_POINTER_REGNUM              33
 292 #define CC_REGNUM                       34
 293 #define FUNC_RETURN_REGNUM              8
 294 #define STATIC_CHAIN_REGNUM             14
 295
 296 /* Trampolines are implemented with a separate data stack.  The memory
 297    on stack only holds the function pointer for the chosen stub.
 298  */
 299
 300 #define TRAMPOLINE_SIZE                 4
 301 #define TRAMPOLINE_ALIGNMENT            16
 302
 303 #define ELIMINABLE_REGS                                 \
 304 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },        \
 305  { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM },        \
 306  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
 307
 308 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)    \
 309   (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
 310
 311
 312 #define FUNCTION_ARG_REGNO_P(N)         0
 313 #define FUNCTION_VALUE_REGNO_P(N)       ((N) == 8)
 314 #define DEFAULT_PCC_STRUCT_RETURN       0
 315
 316 #define FIXED_REGISTERS                                 \
 317 {                                                       \
 318   1,1,1,1, 1,1,1,1,                                     \
 319   0,0,0,0, 0,0,0,0,                                     \
 320   0,0,0,0, 0,0,1,1,                                     \
 321   1,1,1,1, 1,1,1,1,                                     \
 322   0, 1, 0, 1, 1                                         \
 323 }
 324
 325 #define CALL_USED_REGISTERS                             \
 326 {                                                       \
 327   1,1,1,1, 1,1,1,1,                                     \
 328   1,1,1,1, 1,1,1,1,                                     \
 329   0,0,0,0, 0,0,1,1,                                     \
 330   1,1,1,1, 1,1,1,1,                                     \
 331   0, 1, 1, 1, 1                                         \
 332 }
 333
 334 #define LIBCALL_VALUE(MODE)                             \
 335   gen_rtx_REG ((MODE),                                  \
 336                FUNC_RETURN_REGNUM)
 337
 338 /* Order of allocation of registers.  */
 339
 340 #define REG_ALLOC_ORDER                                 \
 341   { 8, 9, 10, 11, 12, 13, 14, 15,                       \
 342     16, 17, 18, 19, 20, 21, 22, 23,                     \
 343     0, 1, 6, 7, 2, 3, 4, 5,                             \
 344     24, 25, 26, 27, 28, 29, 30, 31,                     \
 345     32, 33, 34                                          \
 346 }
 347
 348 #define REGNO_IN_RANGE(REGNO, MIN, MAX)                 \
 349   (IN_RANGE ((REGNO), (MIN), (MAX))                     \
 350    || (reg_renumber != NULL                             \
 351        && reg_renumber[(REGNO)] >= (MIN)                \
 352        && reg_renumber[(REGNO)] <= (MAX)))
 353
 354 #ifdef REG_OK_STRICT
 355 #define REGNO_OK_FOR_BASE_P(regno)      REGNO_IN_RANGE (regno, 16, 31)
 356 #else
 357 #define REGNO_OK_FOR_BASE_P(regno)      1
 358 #endif
 359
 360 #define REGNO_OK_FOR_INDEX_P(regno)     REGNO_OK_FOR_BASE_P (regno)
 361
 362 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
 363   rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
 364
 365 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
 366   rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
 367
 368 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR)                               \
 369   ((COUNT) == 0                                                         \
 370    ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
 371    : NULL_RTX)
 372
 373 #define INCOMING_RETURN_ADDR_RTX        gen_rtx_MEM (Pmode, stack_pointer_rtx)
 374
 375 #define ACCUMULATE_OUTGOING_ARGS        1
 376
 377 typedef unsigned int CUMULATIVE_ARGS;
 378
 379 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 380   (CUM) = 0
 381
 382 \f
 383 /* FIXME */
 384 #define NO_PROFILE_COUNTERS     1
 385 #define PROFILE_BEFORE_PROLOGUE 1
 386
 387 #define FUNCTION_PROFILER(FILE, LABELNO)        \
 388     fprintf (FILE, "\tbsr\t__mcount\n");
 389 \f
 390
 391 #define HARD_REGNO_NREGS(REGNO, MODE)            \
 392   rl78_hard_regno_nregs (REGNO, MODE)
 393
 394 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 395   rl78_hard_regno_mode_ok (REGNO, MODE)
 396
 397 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 398   (   (   GET_MODE_CLASS (MODE1) == MODE_FLOAT                  \
 399        || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)         \
 400    == (   GET_MODE_CLASS (MODE2) == MODE_FLOAT                  \
 401        || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 402 \f
 403
 404 #define TEXT_SECTION_ASM_OP ".text"
 405 #define DATA_SECTION_ASM_OP ".data"
 406 #define BSS_SECTION_ASM_OP ".bss"
 407 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
 408 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
 409
 410 #define ASM_COMMENT_START       " ;"
 411 #define ASM_APP_ON              ""
 412 #define ASM_APP_OFF             ""
 413 #define LOCAL_LABEL_PREFIX      ".L"
 414 #undef  USER_LABEL_PREFIX
 415 #define USER_LABEL_PREFIX       "_"
 416
 417 #define GLOBAL_ASM_OP           "\t.global\t"
 418
 419 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
 420   fprintf (FILE, "\t.long .L%d\n", VALUE)
 421
 422 /* This is how to output an element of a case-vector that is relative.
 423    Note: The local label referenced by the "3b" below is emitted by
 424    the tablejump insn.  */
 425
 426 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
 427   fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
 428
 429
 430 #define ASM_OUTPUT_ALIGN(STREAM, LOG)           \
 431   do                                            \
 432     {                                           \
 433       if ((LOG) == 0)                           \
 434         break;                                  \
 435       fprintf (STREAM, "\t.balign %d\n", 1 << (LOG));   \
 436     }                                           \
 437   while (0)
 438
 439 /* For PIC put jump tables into the text section so that the offsets that
 440    they contain are always computed between two same-section symbols.  */
 441 #define JUMP_TABLES_IN_TEXT_SECTION     (flag_pic)
 442 \f
 443 /* This is a version of REG_P that also returns TRUE for SUBREGs.  */
 444 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
 445
 446 /* Like REG_P except that this macro is true for SET expressions.  */
 447 #define SET_P(rtl)    (GET_CODE (rtl) == SET)
 448 \f
 449 #undef  PREFERRED_DEBUGGING_TYPE
 450 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 451
 452 #undef  DWARF2_ADDR_SIZE
 453 #define DWARF2_ADDR_SIZE                        4
 454
 455 #define DWARF2_ASM_LINE_DEBUG_INFO              1
 456
 457 #define EXIT_IGNORE_STACK                       0
 458 #define INCOMING_FRAME_SP_OFFSET                4
 459 \f
 460
 461 #define BRANCH_COST(SPEED,PREDICT)       1
 462 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
 463
 464 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
 465 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
 466
 467 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
 468
 469 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH.  */
 470 #define DWARF2_UNWIND_INFO 0
 471
 472 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()